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| Rev 1268 | Rev 1321 | ||
|---|---|---|---|
| Line 135... | Line 135... | ||
| 135 | return 0; |
135 | return 0; |
| 136 | } |
136 | } |
| Line 137... | Line 137... | ||
| 137 | 137 | ||
| 138 | void rv370_pcie_gart_disable(struct radeon_device *rdev) |
138 | void rv370_pcie_gart_disable(struct radeon_device *rdev) |
| 139 | { |
139 | { |
| - | 140 | u32 tmp; |
|
| Line 140... | Line 141... | ||
| 140 | uint32_t tmp; |
141 | int r; |
| 141 | 142 | ||
| 142 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
143 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
| 143 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
144 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
| Line 1190... | Line 1191... | ||
| 1190 | 1191 | ||
| 1191 | static int r300_startup(struct radeon_device *rdev) |
1192 | static int r300_startup(struct radeon_device *rdev) |
| 1192 | { |
1193 | { |
| Line -... | Line 1194... | ||
| - | 1194 | int r; |
|
| - | 1195 | ||
| - | 1196 | /* set common regs */ |
|
| 1193 | int r; |
1197 | r100_set_common_regs(rdev); |
| 1194 | 1198 | /* program mc */ |
|
| 1195 | r300_mc_program(rdev); |
1199 | r300_mc_program(rdev); |
| 1196 | /* Resume clock */ |
1200 | /* Resume clock */ |
| 1197 | r300_clock_startup(rdev); |
1201 | r300_clock_startup(rdev); |
| Line 1202... | Line 1206... | ||
| 1202 | if (rdev->flags & RADEON_IS_PCIE) { |
1206 | if (rdev->flags & RADEON_IS_PCIE) { |
| 1203 | r = rv370_pcie_gart_enable(rdev); |
1207 | r = rv370_pcie_gart_enable(rdev); |
| 1204 | if (r) |
1208 | if (r) |
| 1205 | return r; |
1209 | return r; |
| 1206 | } |
1210 | } |
| - | 1211 | ||
| - | 1212 | if (rdev->family == CHIP_R300 || |
|
| - | 1213 | rdev->family == CHIP_R350 || |
|
| - | 1214 | rdev->family == CHIP_RV350) |
|
| - | 1215 | r100_enable_bm(rdev); |
|
| - | 1216 | ||
| 1207 | if (rdev->flags & RADEON_IS_PCI) { |
1217 | if (rdev->flags & RADEON_IS_PCI) { |
| 1208 | r = r100_pci_gart_enable(rdev); |
1218 | r = r100_pci_gart_enable(rdev); |
| 1209 | if (r) |
1219 | if (r) |
| 1210 | return r; |
1220 | return r; |
| 1211 | } |
1221 | } |
| 1212 | /* Enable IRQ */ |
1222 | /* Enable IRQ */ |
| 1213 | // rdev->irq.sw_int = true; |
- | |
| 1214 | // r100_irq_set(rdev); |
1223 | // r100_irq_set(rdev); |
| 1215 | /* 1M ring buffer */ |
1224 | /* 1M ring buffer */ |
| 1216 | // r = r100_cp_init(rdev, 1024 * 1024); |
1225 | // r = r100_cp_init(rdev, 1024 * 1024); |
| 1217 | // if (r) { |
1226 | // if (r) { |
| 1218 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
1227 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| Line 1263... | Line 1272... | ||
| 1263 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
1272 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 1264 | RREG32(R_000E40_RBBM_STATUS), |
1273 | RREG32(R_000E40_RBBM_STATUS), |
| 1265 | RREG32(R_0007C0_CP_STAT)); |
1274 | RREG32(R_0007C0_CP_STAT)); |
| 1266 | } |
1275 | } |
| 1267 | /* check if cards are posted or not */ |
1276 | /* check if cards are posted or not */ |
| 1268 | if (!radeon_card_posted(rdev) && rdev->bios) { |
1277 | if (radeon_boot_test_post_card(rdev) == false) |
| 1269 | DRM_INFO("GPU not posted. posting now...\n"); |
- | |
| 1270 | radeon_combios_asic_init(rdev->ddev); |
1278 | return -EINVAL; |
| 1271 | } |
- | |
| 1272 | /* Set asic errata */ |
1279 | /* Set asic errata */ |
| 1273 | r300_errata(rdev); |
1280 | r300_errata(rdev); |
| 1274 | /* Initialize clocks */ |
1281 | /* Initialize clocks */ |
| 1275 | radeon_get_clock_info(rdev->ddev); |
1282 | radeon_get_clock_info(rdev->ddev); |
| 1276 | /* Get vram informations */ |
1283 | /* Get vram informations */ |