Rev 1246 | Rev 1321 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 1246 | Rev 1268 | ||
---|---|---|---|
Line 111... | Line 111... | ||
111 | return r; |
111 | return r; |
112 | /* discard memory request outside of configured range */ |
112 | /* discard memory request outside of configured range */ |
113 | tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
113 | tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
114 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
114 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
115 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location); |
115 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location); |
116 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096; |
116 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE; |
117 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); |
117 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); |
118 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); |
118 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); |
119 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); |
119 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); |
120 | table_addr = rdev->gart.table_addr; |
120 | table_addr = rdev->gart.table_addr; |
121 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); |
121 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); |