Rev 2005 | Rev 5078 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 2005 | Rev 2997 | ||
---|---|---|---|
Line 23... | Line 23... | ||
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #include "drmP.h" |
28 | #include |
29 | #include "drm.h" |
- | |
30 | #include "radeon_drm.h" |
29 | #include |
31 | #include "radeon_reg.h" |
30 | #include "radeon_reg.h" |
32 | #include "radeon.h" |
31 | #include "radeon.h" |
33 | #include "radeon_asic.h" |
32 | #include "radeon_asic.h" |
Line 34... | Line 33... | ||
34 | 33 | ||
Line 85... | Line 84... | ||
85 | #endif |
84 | #endif |
Line 86... | Line 85... | ||
86 | 85 | ||
87 | int r200_copy_dma(struct radeon_device *rdev, |
86 | int r200_copy_dma(struct radeon_device *rdev, |
88 | uint64_t src_offset, |
87 | uint64_t src_offset, |
89 | uint64_t dst_offset, |
88 | uint64_t dst_offset, |
90 | unsigned num_pages, |
89 | unsigned num_gpu_pages, |
91 | struct radeon_fence *fence) |
90 | struct radeon_fence **fence) |
- | 91 | { |
|
92 | { |
92 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
93 | uint32_t size; |
93 | uint32_t size; |
94 | uint32_t cur_size; |
94 | uint32_t cur_size; |
95 | int i, num_loops; |
95 | int i, num_loops; |
Line 96... | Line 96... | ||
96 | int r = 0; |
96 | int r = 0; |
97 | 97 | ||
98 | /* radeon pitch is /64 */ |
98 | /* radeon pitch is /64 */ |
99 | size = num_pages << PAGE_SHIFT; |
99 | size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT; |
100 | num_loops = DIV_ROUND_UP(size, 0x1FFFFF); |
100 | num_loops = DIV_ROUND_UP(size, 0x1FFFFF); |
101 | r = radeon_ring_lock(rdev, num_loops * 4 + 64); |
101 | r = radeon_ring_lock(rdev, ring, num_loops * 4 + 64); |
102 | if (r) { |
102 | if (r) { |
103 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
103 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
104 | return r; |
104 | return r; |
105 | } |
105 | } |
106 | /* Must wait for 2D idle & clean before DMA or hangs might happen */ |
106 | /* Must wait for 2D idle & clean before DMA or hangs might happen */ |
107 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
107 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
108 | radeon_ring_write(rdev, (1 << 16)); |
108 | radeon_ring_write(ring, (1 << 16)); |
109 | for (i = 0; i < num_loops; i++) { |
109 | for (i = 0; i < num_loops; i++) { |
110 | cur_size = size; |
110 | cur_size = size; |
111 | if (cur_size > 0x1FFFFF) { |
111 | if (cur_size > 0x1FFFFF) { |
112 | cur_size = 0x1FFFFF; |
112 | cur_size = 0x1FFFFF; |
113 | } |
113 | } |
114 | size -= cur_size; |
114 | size -= cur_size; |
115 | radeon_ring_write(rdev, PACKET0(0x720, 2)); |
115 | radeon_ring_write(ring, PACKET0(0x720, 2)); |
116 | radeon_ring_write(rdev, src_offset); |
116 | radeon_ring_write(ring, src_offset); |
117 | radeon_ring_write(rdev, dst_offset); |
117 | radeon_ring_write(ring, dst_offset); |
118 | radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); |
118 | radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30)); |
119 | src_offset += cur_size; |
119 | src_offset += cur_size; |
120 | dst_offset += cur_size; |
120 | dst_offset += cur_size; |
121 | } |
121 | } |
122 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
122 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
123 | radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); |
123 | radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE); |
124 | if (fence) { |
124 | if (fence) { |
125 | r = radeon_fence_emit(rdev, fence); |
125 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
126 | } |
126 | } |
127 | radeon_ring_unlock_commit(rdev); |
127 | radeon_ring_unlock_commit(rdev, ring); |
128 | return r; |
128 | return r; |
Line 129... | Line 129... | ||
129 | } |
129 | } |
Line 154... | Line 154... | ||
154 | int i; |
154 | int i; |
155 | int face; |
155 | int face; |
156 | u32 tile_flags = 0; |
156 | u32 tile_flags = 0; |
157 | u32 idx_value; |
157 | u32 idx_value; |
Line 158... | Line 158... | ||
158 | 158 | ||
159 | ib = p->ib->ptr; |
159 | ib = p->ib.ptr; |
160 | track = (struct r100_cs_track *)p->track; |
160 | track = (struct r100_cs_track *)p->track; |
161 | idx_value = radeon_get_ib_value(p, idx); |
161 | idx_value = radeon_get_ib_value(p, idx); |
162 | switch (reg) { |
162 | switch (reg) { |
163 | case RADEON_CRTC_GUI_TRIG_VLINE: |
163 | case RADEON_CRTC_GUI_TRIG_VLINE: |
Line 215... | Line 215... | ||
215 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
215 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
216 | idx, reg); |
216 | idx, reg); |
217 | r100_cs_dump_packet(p, pkt); |
217 | r100_cs_dump_packet(p, pkt); |
218 | return r; |
218 | return r; |
219 | } |
219 | } |
- | 220 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
|
- | 221 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
|
- | 222 | tile_flags |= R200_TXO_MACRO_TILE; |
|
- | 223 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
|
- | 224 | tile_flags |= R200_TXO_MICRO_TILE; |
|
- | 225 | ||
- | 226 | tmp = idx_value & ~(0x7 << 2); |
|
- | 227 | tmp |= tile_flags; |
|
- | 228 | ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); |
|
- | 229 | } else |
|
220 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
230 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
221 | track->textures[i].robj = reloc->robj; |
231 | track->textures[i].robj = reloc->robj; |
222 | track->tex_dirty = true; |
232 | track->tex_dirty = true; |
223 | break; |
233 | break; |
224 | case R200_PP_CUBIC_OFFSET_F1_0: |
234 | case R200_PP_CUBIC_OFFSET_F1_0: |
Line 277... | Line 287... | ||
277 | idx, reg); |
287 | idx, reg); |
278 | r100_cs_dump_packet(p, pkt); |
288 | r100_cs_dump_packet(p, pkt); |
279 | return r; |
289 | return r; |
280 | } |
290 | } |
Line -... | Line 291... | ||
- | 291 | ||
281 | 292 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
|
282 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
293 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
283 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
294 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
284 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
295 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
Line 285... | Line 296... | ||
285 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
296 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
286 | 297 | ||
287 | tmp = idx_value & ~(0x7 << 16); |
298 | tmp = idx_value & ~(0x7 << 16); |
- | 299 | tmp |= tile_flags; |
|
- | 300 | ib[idx] = tmp; |
|
Line 288... | Line 301... | ||
288 | tmp |= tile_flags; |
301 | } else |
289 | ib[idx] = tmp; |
302 | ib[idx] = idx_value; |
290 | 303 | ||
291 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
304 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |