WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/r200.c



 
int r200_packet0_check(struct radeon_cs_parser *p,
		       struct radeon_cs_packet *pkt,
		       unsigned idx, unsigned reg)
 
{
	struct radeon_cs_reloc *reloc;
	struct r100_cs_track *track;
	volatile uint32_t *ib;
	uint32_t tmp;
	int r;
	int i;
	int face;
	u32 tile_flags = 0;

	u32 idx_value;
 
 
 
	ib = p->ib->ptr;
	track = (struct r100_cs_track *)p->track;
	idx_value = radeon_get_ib_value(p, idx);
	switch (reg) {
	case RADEON_CRTC_GUI_TRIG_VLINE:
		r = r100_cs_packet_parse_vline(p);

				  idx, reg);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		track->zb.robj = reloc->robj;
		track->zb.offset = idx_value;
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		break;
	case RADEON_RB3D_COLOROFFSET:
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		track->cb[0].robj = reloc->robj;
		track->cb[0].offset = idx_value;
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		break;
	case R200_PP_TXOFFSET_0:
	case R200_PP_TXOFFSET_1:
	case R200_PP_TXOFFSET_2:
	case R200_PP_TXOFFSET_3:

			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		track->textures[i].robj = reloc->robj;
		break;
	case R200_PP_CUBIC_OFFSET_F1_0:
	case R200_PP_CUBIC_OFFSET_F2_0:
	case R200_PP_CUBIC_OFFSET_F3_0:

			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		track->textures[i].cube_info[face - 1].offset = idx_value;
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		track->textures[i].cube_info[face - 1].robj = reloc->robj;
		break;
	case RADEON_RE_WIDTH_HEIGHT:
		track->maxy = ((idx_value >> 16) & 0x7FF);
		break;
	case RADEON_RB3D_COLORPITCH:
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",

		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
			tile_flags |= RADEON_COLOR_TILE_ENABLE;
		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
			tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;

 
		tmp = idx_value & ~(0x7 << 16);
		tmp |= tile_flags;

		ib[idx] = tmp;
 
		track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
		break;
	case RADEON_RB3D_DEPTHPITCH:
		track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
		break;
	case RADEON_RB3D_CNTL:
		switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
		case 7:
		case 8:
		case 9:

		case 6:
			track->cb[0].cpp = 4;
			break;
		default:
			DRM_ERROR("Invalid color buffer format (%d) !\n",
				  ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
			return -EINVAL;
		}
		if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {
			DRM_ERROR("No support for depth xy offset in kms\n");
			return -EINVAL;
		}

 
		track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
		break;
	case RADEON_RB3D_ZSTENCILCNTL:
		switch (idx_value & 0xf) {
		case 0:
			track->zb.cpp = 2;
			break;
		case 2:

			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		break;
	case RADEON_PP_CNTL:
		{
			uint32_t temp = idx_value >> 4;
			for (i = 0; i < track->num_texture; i++)
				track->textures[i].enabled = !!(temp & (1 << i));
		}
		break;
	case RADEON_SE_VF_CNTL:
		track->vap_vf_cntl = idx_value;
		break;
	case 0x210c:
		/* VAP_VF_MAX_VTX_INDX */
		track->max_indx = idx_value & 0x00FFFFFFUL;
		break;
	case R200_SE_VTX_FMT_0:
		track->vtx_size = r200_get_vtx_size_0(idx_value);
		break;
	case R200_SE_VTX_FMT_1:
		track->vtx_size += r200_get_vtx_size_1(idx_value);
		break;
	case R200_PP_TXSIZE_0:
	case R200_PP_TXSIZE_1:
	case R200_PP_TXSIZE_2:
	case R200_PP_TXSIZE_3:
	case R200_PP_TXSIZE_4:
	case R200_PP_TXSIZE_5:
		i = (reg - R200_PP_TXSIZE_0) / 32;
		track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
		track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
		break;
	case R200_PP_TXPITCH_0:
	case R200_PP_TXPITCH_1:
	case R200_PP_TXPITCH_2:
	case R200_PP_TXPITCH_3:
	case R200_PP_TXPITCH_4:
	case R200_PP_TXPITCH_5:
		i = (reg - R200_PP_TXPITCH_0) / 32;
		track->textures[i].pitch = idx_value + 32;
		break;
	case R200_PP_TXFILTER_0:
	case R200_PP_TXFILTER_1:
	case R200_PP_TXFILTER_2:
	case R200_PP_TXFILTER_3:
	case R200_PP_TXFILTER_4:
	case R200_PP_TXFILTER_5:
		i = (reg - R200_PP_TXFILTER_0) / 32;
		track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
						 >> R200_MAX_MIP_LEVEL_SHIFT);
		tmp = (idx_value >> 23) & 0x7;
		if (tmp == 2 || tmp == 6)
			track->textures[i].roundup_w = false;
		tmp = (idx_value >> 27) & 0x7;
		if (tmp == 2 || tmp == 6)
			track->textures[i].roundup_h = false;
		break;
	case R200_PP_TXMULTI_CTL_0:
	case R200_PP_TXMULTI_CTL_1:

	case R200_PP_TXFORMAT_X_2:
	case R200_PP_TXFORMAT_X_3:
	case R200_PP_TXFORMAT_X_4:
	case R200_PP_TXFORMAT_X_5:
		i = (reg - R200_PP_TXFORMAT_X_0) / 32;
		track->textures[i].txdepth = idx_value & 0x7;
		tmp = (idx_value >> 16) & 0x3;
		/* 2D, 3D, CUBE */
		switch (tmp) {
		case 0:
		case 5:
		case 6:

	case R200_PP_TXFORMAT_2:
	case R200_PP_TXFORMAT_3:
	case R200_PP_TXFORMAT_4:
	case R200_PP_TXFORMAT_5:
		i = (reg - R200_PP_TXFORMAT_0) / 32;
		if (idx_value & R200_TXFORMAT_NON_POWER2) {
			track->textures[i].use_pitch = 1;
		} else {
			track->textures[i].use_pitch = 0;
			track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
			track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
		}
		switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
		case R200_TXFORMAT_I8:
		case R200_TXFORMAT_RGB332:
		case R200_TXFORMAT_Y8:
			track->textures[i].cpp = 1;
			break;

		case R200_TXFORMAT_DXT23:
		case R200_TXFORMAT_DXT45:
			track->textures[i].cpp = 4;
			break;
		}
		track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
		track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
		break;
	case R200_PP_CUBIC_FACES_0:
	case R200_PP_CUBIC_FACES_1:
	case R200_PP_CUBIC_FACES_2:
	case R200_PP_CUBIC_FACES_3:
	case R200_PP_CUBIC_FACES_4:
	case R200_PP_CUBIC_FACES_5:
		tmp = idx_value;
		i = (reg - R200_PP_CUBIC_FACES_0) / 32;
		for (face = 0; face < 4; face++) {
			track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
			track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
		}

	}
	return 0;
}
#endif

 
void r200_set_safe_registers(struct radeon_device *rdev)
{
	rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
 
	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);

Rev 1179	Rev 1221
Line 95...	Line 95...
95		95
96	int r200_packet0_check(struct radeon_cs_parser *p,	96	int r200_packet0_check(struct radeon_cs_parser *p,
97	struct radeon_cs_packet *pkt,	97	struct radeon_cs_packet *pkt,
98	unsigned idx, unsigned reg)	98	unsigned idx, unsigned reg)
99	{	-
100	struct radeon_cs_chunk *ib_chunk;	99	{
101	struct radeon_cs_reloc *reloc;	100	struct radeon_cs_reloc *reloc;
102	struct r100_cs_track *track;	101	struct r100_cs_track *track;
103	volatile uint32_t *ib;	102	volatile uint32_t *ib;
104	uint32_t tmp;	103	uint32_t tmp;
105	int r;	104	int r;
106	int i;	105	int i;
107	int face;	106	int face;
-		107	u32 tile_flags = 0;
Line 108...	Line 108...
108	u32 tile_flags = 0;	108	u32 idx_value;
109		-
110	ib = p->ib->ptr;	109
111	ib_chunk = &p->chunks[p->chunk_ib_idx];	-
-		110	ib = p->ib->ptr;
112	track = (struct r100_cs_track *)p->track;	111	track = (struct r100_cs_track *)p->track;
113		112	idx_value = radeon_get_ib_value(p, idx);
114	switch (reg) {	113	switch (reg) {
115	case RADEON_CRTC_GUI_TRIG_VLINE:	114	case RADEON_CRTC_GUI_TRIG_VLINE:
116	r = r100_cs_packet_parse_vline(p);	115	r = r100_cs_packet_parse_vline(p);
Line 136...	Line 135...
136	idx, reg);	135	idx, reg);
137	r100_cs_dump_packet(p, pkt);	136	r100_cs_dump_packet(p, pkt);
138	return r;	137	return r;
139	}	138	}
140	track->zb.robj = reloc->robj;	139	track->zb.robj = reloc->robj;
141	track->zb.offset = ib_chunk->kdata[idx];	140	track->zb.offset = idx_value;
142	ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);	141	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
143	break;	142	break;
144	case RADEON_RB3D_COLOROFFSET:	143	case RADEON_RB3D_COLOROFFSET:
145	r = r100_cs_packet_next_reloc(p, &reloc);	144	r = r100_cs_packet_next_reloc(p, &reloc);
146	if (r) {	145	if (r) {
147	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	146	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
148	idx, reg);	147	idx, reg);
149	r100_cs_dump_packet(p, pkt);	148	r100_cs_dump_packet(p, pkt);
150	return r;	149	return r;
151	}	150	}
152	track->cb[0].robj = reloc->robj;	151	track->cb[0].robj = reloc->robj;
153	track->cb[0].offset = ib_chunk->kdata[idx];	152	track->cb[0].offset = idx_value;
154	ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);	153	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
155	break;	154	break;
156	case R200_PP_TXOFFSET_0:	155	case R200_PP_TXOFFSET_0:
157	case R200_PP_TXOFFSET_1:	156	case R200_PP_TXOFFSET_1:
158	case R200_PP_TXOFFSET_2:	157	case R200_PP_TXOFFSET_2:
159	case R200_PP_TXOFFSET_3:	158	case R200_PP_TXOFFSET_3:
Line 165...	Line 164...
165	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	164	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
166	idx, reg);	165	idx, reg);
167	r100_cs_dump_packet(p, pkt);	166	r100_cs_dump_packet(p, pkt);
168	return r;	167	return r;
169	}	168	}
170	ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);	169	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
171	track->textures[i].robj = reloc->robj;	170	track->textures[i].robj = reloc->robj;
172	break;	171	break;
173	case R200_PP_CUBIC_OFFSET_F1_0:	172	case R200_PP_CUBIC_OFFSET_F1_0:
174	case R200_PP_CUBIC_OFFSET_F2_0:	173	case R200_PP_CUBIC_OFFSET_F2_0:
175	case R200_PP_CUBIC_OFFSET_F3_0:	174	case R200_PP_CUBIC_OFFSET_F3_0:
Line 207...	Line 206...
207	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	206	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
208	idx, reg);	207	idx, reg);
209	r100_cs_dump_packet(p, pkt);	208	r100_cs_dump_packet(p, pkt);
210	return r;	209	return r;
211	}	210	}
212	track->textures[i].cube_info[face - 1].offset = ib_chunk->kdata[idx];	211	track->textures[i].cube_info[face - 1].offset = idx_value;
213	ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);	212	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
214	track->textures[i].cube_info[face - 1].robj = reloc->robj;	213	track->textures[i].cube_info[face - 1].robj = reloc->robj;
215	break;	214	break;
216	case RADEON_RE_WIDTH_HEIGHT:	215	case RADEON_RE_WIDTH_HEIGHT:
217	track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF);	216	track->maxy = ((idx_value >> 16) & 0x7FF);
218	break;	217	break;
219	case RADEON_RB3D_COLORPITCH:	218	case RADEON_RB3D_COLORPITCH:
220	r = r100_cs_packet_next_reloc(p, &reloc);	219	r = r100_cs_packet_next_reloc(p, &reloc);
221	if (r) {	220	if (r) {
222	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	221	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
Line 228...	Line 227...
228	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)	227	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
229	tile_flags \|= RADEON_COLOR_TILE_ENABLE;	228	tile_flags \|= RADEON_COLOR_TILE_ENABLE;
230	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)	229	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
231	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;	230	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;
Line 232...	Line 231...
232		231
233	tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);	232	tmp = idx_value & ~(0x7 << 16);
234	tmp \|= tile_flags;	233	tmp \|= tile_flags;
Line 235...	Line 234...
235	ib[idx] = tmp;	234	ib[idx] = tmp;
236		235
237	track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK;	236	track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
238	break;	237	break;
239	case RADEON_RB3D_DEPTHPITCH:	238	case RADEON_RB3D_DEPTHPITCH:
240	track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK;	239	track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
241	break;	240	break;
242	case RADEON_RB3D_CNTL:	241	case RADEON_RB3D_CNTL:
243	switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {	242	switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
244	case 7:	243	case 7:
245	case 8:	244	case 8:
246	case 9:	245	case 9:
Line 256...	Line 255...
256	case 6:	255	case 6:
257	track->cb[0].cpp = 4;	256	track->cb[0].cpp = 4;
258	break;	257	break;
259	default:	258	default:
260	DRM_ERROR("Invalid color buffer format (%d) !\n",	259	DRM_ERROR("Invalid color buffer format (%d) !\n",
261	((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));	260	((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
262	return -EINVAL;	261	return -EINVAL;
263	}	262	}
264	if (ib_chunk->kdata[idx] & RADEON_DEPTHXY_OFFSET_ENABLE) {	263	if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {
265	DRM_ERROR("No support for depth xy offset in kms\n");	264	DRM_ERROR("No support for depth xy offset in kms\n");
266	return -EINVAL;	265	return -EINVAL;
267	}	266	}
Line 268...	Line 267...
268		267
269	track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE);	268	track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
270	break;	269	break;
271	case RADEON_RB3D_ZSTENCILCNTL:	270	case RADEON_RB3D_ZSTENCILCNTL:
272	switch (ib_chunk->kdata[idx] & 0xf) {	271	switch (idx_value & 0xf) {
273	case 0:	272	case 0:
274	track->zb.cpp = 2;	273	track->zb.cpp = 2;
275	break;	274	break;
276	case 2:	275	case 2:
Line 291...	Line 290...
291	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",	290	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
292	idx, reg);	291	idx, reg);
293	r100_cs_dump_packet(p, pkt);	292	r100_cs_dump_packet(p, pkt);
294	return r;	293	return r;
295	}	294	}
296	ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);	295	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
297	break;	296	break;
298	case RADEON_PP_CNTL:	297	case RADEON_PP_CNTL:
299	{	298	{
300	uint32_t temp = ib_chunk->kdata[idx] >> 4;	299	uint32_t temp = idx_value >> 4;
301	for (i = 0; i < track->num_texture; i++)	300	for (i = 0; i < track->num_texture; i++)
302	track->textures[i].enabled = !!(temp & (1 << i));	301	track->textures[i].enabled = !!(temp & (1 << i));
303	}	302	}
304	break;	303	break;
305	case RADEON_SE_VF_CNTL:	304	case RADEON_SE_VF_CNTL:
306	track->vap_vf_cntl = ib_chunk->kdata[idx];	305	track->vap_vf_cntl = idx_value;
307	break;	306	break;
308	case 0x210c:	307	case 0x210c:
309	/* VAP_VF_MAX_VTX_INDX */	308	/* VAP_VF_MAX_VTX_INDX */
310	track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL;	309	track->max_indx = idx_value & 0x00FFFFFFUL;
311	break;	310	break;
312	case R200_SE_VTX_FMT_0:	311	case R200_SE_VTX_FMT_0:
313	track->vtx_size = r200_get_vtx_size_0(ib_chunk->kdata[idx]);	312	track->vtx_size = r200_get_vtx_size_0(idx_value);
314	break;	313	break;
315	case R200_SE_VTX_FMT_1:	314	case R200_SE_VTX_FMT_1:
316	track->vtx_size += r200_get_vtx_size_1(ib_chunk->kdata[idx]);	315	track->vtx_size += r200_get_vtx_size_1(idx_value);
317	break;	316	break;
318	case R200_PP_TXSIZE_0:	317	case R200_PP_TXSIZE_0:
319	case R200_PP_TXSIZE_1:	318	case R200_PP_TXSIZE_1:
320	case R200_PP_TXSIZE_2:	319	case R200_PP_TXSIZE_2:
321	case R200_PP_TXSIZE_3:	320	case R200_PP_TXSIZE_3:
322	case R200_PP_TXSIZE_4:	321	case R200_PP_TXSIZE_4:
323	case R200_PP_TXSIZE_5:	322	case R200_PP_TXSIZE_5:
324	i = (reg - R200_PP_TXSIZE_0) / 32;	323	i = (reg - R200_PP_TXSIZE_0) / 32;
325	track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1;	324	track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
326	track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;	325	track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
327	break;	326	break;
328	case R200_PP_TXPITCH_0:	327	case R200_PP_TXPITCH_0:
329	case R200_PP_TXPITCH_1:	328	case R200_PP_TXPITCH_1:
330	case R200_PP_TXPITCH_2:	329	case R200_PP_TXPITCH_2:
331	case R200_PP_TXPITCH_3:	330	case R200_PP_TXPITCH_3:
332	case R200_PP_TXPITCH_4:	331	case R200_PP_TXPITCH_4:
333	case R200_PP_TXPITCH_5:	332	case R200_PP_TXPITCH_5:
334	i = (reg - R200_PP_TXPITCH_0) / 32;	333	i = (reg - R200_PP_TXPITCH_0) / 32;
335	track->textures[i].pitch = ib_chunk->kdata[idx] + 32;	334	track->textures[i].pitch = idx_value + 32;
336	break;	335	break;
337	case R200_PP_TXFILTER_0:	336	case R200_PP_TXFILTER_0:
338	case R200_PP_TXFILTER_1:	337	case R200_PP_TXFILTER_1:
339	case R200_PP_TXFILTER_2:	338	case R200_PP_TXFILTER_2:
340	case R200_PP_TXFILTER_3:	339	case R200_PP_TXFILTER_3:
341	case R200_PP_TXFILTER_4:	340	case R200_PP_TXFILTER_4:
342	case R200_PP_TXFILTER_5:	341	case R200_PP_TXFILTER_5:
343	i = (reg - R200_PP_TXFILTER_0) / 32;	342	i = (reg - R200_PP_TXFILTER_0) / 32;
344	track->textures[i].num_levels = ((ib_chunk->kdata[idx] & R200_MAX_MIP_LEVEL_MASK)	343	track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
345	>> R200_MAX_MIP_LEVEL_SHIFT);	344	>> R200_MAX_MIP_LEVEL_SHIFT);
346	tmp = (ib_chunk->kdata[idx] >> 23) & 0x7;	345	tmp = (idx_value >> 23) & 0x7;
347	if (tmp == 2 \|\| tmp == 6)	346	if (tmp == 2 \|\| tmp == 6)
348	track->textures[i].roundup_w = false;	347	track->textures[i].roundup_w = false;
349	tmp = (ib_chunk->kdata[idx] >> 27) & 0x7;	348	tmp = (idx_value >> 27) & 0x7;
350	if (tmp == 2 \|\| tmp == 6)	349	if (tmp == 2 \|\| tmp == 6)
351	track->textures[i].roundup_h = false;	350	track->textures[i].roundup_h = false;
352	break;	351	break;
353	case R200_PP_TXMULTI_CTL_0:	352	case R200_PP_TXMULTI_CTL_0:
354	case R200_PP_TXMULTI_CTL_1:	353	case R200_PP_TXMULTI_CTL_1:
Line 363...	Line 362...
363	case R200_PP_TXFORMAT_X_2:	362	case R200_PP_TXFORMAT_X_2:
364	case R200_PP_TXFORMAT_X_3:	363	case R200_PP_TXFORMAT_X_3:
365	case R200_PP_TXFORMAT_X_4:	364	case R200_PP_TXFORMAT_X_4:
366	case R200_PP_TXFORMAT_X_5:	365	case R200_PP_TXFORMAT_X_5:
367	i = (reg - R200_PP_TXFORMAT_X_0) / 32;	366	i = (reg - R200_PP_TXFORMAT_X_0) / 32;
368	track->textures[i].txdepth = ib_chunk->kdata[idx] & 0x7;	367	track->textures[i].txdepth = idx_value & 0x7;
369	tmp = (ib_chunk->kdata[idx] >> 16) & 0x3;	368	tmp = (idx_value >> 16) & 0x3;
370	/* 2D, 3D, CUBE */	369	/* 2D, 3D, CUBE */
371	switch (tmp) {	370	switch (tmp) {
372	case 0:	371	case 0:
373	case 5:	372	case 5:
374	case 6:	373	case 6:
Line 388...	Line 387...
388	case R200_PP_TXFORMAT_2:	387	case R200_PP_TXFORMAT_2:
389	case R200_PP_TXFORMAT_3:	388	case R200_PP_TXFORMAT_3:
390	case R200_PP_TXFORMAT_4:	389	case R200_PP_TXFORMAT_4:
391	case R200_PP_TXFORMAT_5:	390	case R200_PP_TXFORMAT_5:
392	i = (reg - R200_PP_TXFORMAT_0) / 32;	391	i = (reg - R200_PP_TXFORMAT_0) / 32;
393	if (ib_chunk->kdata[idx] & R200_TXFORMAT_NON_POWER2) {	392	if (idx_value & R200_TXFORMAT_NON_POWER2) {
394	track->textures[i].use_pitch = 1;	393	track->textures[i].use_pitch = 1;
395	} else {	394	} else {
396	track->textures[i].use_pitch = 0;	395	track->textures[i].use_pitch = 0;
397	track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);	396	track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
398	track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);	397	track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
399	}	398	}
400	switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) {	399	switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
401	case R200_TXFORMAT_I8:	400	case R200_TXFORMAT_I8:
402	case R200_TXFORMAT_RGB332:	401	case R200_TXFORMAT_RGB332:
403	case R200_TXFORMAT_Y8:	402	case R200_TXFORMAT_Y8:
404	track->textures[i].cpp = 1;	403	track->textures[i].cpp = 1;
405	break;	404	break;
Line 423...	Line 422...
423	case R200_TXFORMAT_DXT23:	422	case R200_TXFORMAT_DXT23:
424	case R200_TXFORMAT_DXT45:	423	case R200_TXFORMAT_DXT45:
425	track->textures[i].cpp = 4;	424	track->textures[i].cpp = 4;
426	break;	425	break;
427	}	426	}
428	track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf);	427	track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
429	track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf);	428	track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
430	break;	429	break;
431	case R200_PP_CUBIC_FACES_0:	430	case R200_PP_CUBIC_FACES_0:
432	case R200_PP_CUBIC_FACES_1:	431	case R200_PP_CUBIC_FACES_1:
433	case R200_PP_CUBIC_FACES_2:	432	case R200_PP_CUBIC_FACES_2:
434	case R200_PP_CUBIC_FACES_3:	433	case R200_PP_CUBIC_FACES_3:
435	case R200_PP_CUBIC_FACES_4:	434	case R200_PP_CUBIC_FACES_4:
436	case R200_PP_CUBIC_FACES_5:	435	case R200_PP_CUBIC_FACES_5:
437	tmp = ib_chunk->kdata[idx];	436	tmp = idx_value;
438	i = (reg - R200_PP_CUBIC_FACES_0) / 32;	437	i = (reg - R200_PP_CUBIC_FACES_0) / 32;
439	for (face = 0; face < 4; face++) {	438	for (face = 0; face < 4; face++) {
440	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);	439	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
441	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);	440	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
442	}	441	}
Line 448...	Line 447...
448	}	447	}
449	return 0;	448	return 0;
450	}	449	}
451	#endif	450	#endif
Line 452...	Line 451...
452		451
453	int r200_init(struct radeon_device *rdev)	452	void r200_set_safe_registers(struct radeon_device *rdev)
454	{	453	{
455	rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;	454	rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
456	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);	-
457	return 0;	455	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r200.c – Rev 1179 → 1221