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Rev 1221 Rev 1963
Line 46... Line 46...
46 
#define		PACKET3_NOP			0x10
 46 
#define		PACKET3_NOP			0x10
47 
#define		PACKET3_3D_DRAW_VBUF		0x28
 47 
#define		PACKET3_3D_DRAW_VBUF		0x28
48 
#define		PACKET3_3D_DRAW_IMMD		0x29
 48 
#define		PACKET3_3D_DRAW_IMMD		0x29
49 
#define		PACKET3_3D_DRAW_INDX		0x2A
 49 
#define		PACKET3_3D_DRAW_INDX		0x2A
50 
#define		PACKET3_3D_LOAD_VBPNTR		0x2F
 50 
#define		PACKET3_3D_LOAD_VBPNTR		0x2F
- 
 
 51 
#define		PACKET3_3D_CLEAR_ZMASK		0x32
51 
#define		PACKET3_INDX_BUFFER		0x33
 52 
#define		PACKET3_INDX_BUFFER		0x33
52 
#define		PACKET3_3D_DRAW_VBUF_2		0x34
 53 
#define		PACKET3_3D_DRAW_VBUF_2		0x34
53 
#define		PACKET3_3D_DRAW_IMMD_2		0x35
 54 
#define		PACKET3_3D_DRAW_IMMD_2		0x35
54 
#define		PACKET3_3D_DRAW_INDX_2		0x36
 55 
#define		PACKET3_3D_DRAW_INDX_2		0x36
- 
 
 56 
#define		PACKET3_3D_CLEAR_HIZ		0x37
55 
#define		PACKET3_BITBLT_MULTI		0x9B
 57 
#define		PACKET3_BITBLT_MULTI		0x9B
Line 56... Line 58...
56 
 
 58 
 
57 
#define PACKET0(reg, n)	(CP_PACKET0 |					\
 59 
#define PACKET0(reg, n)	(CP_PACKET0 |					\
58 
			 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |	\
 60 
			 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |	\
Line 72... Line 74...
72 
#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
 74 
#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
73 
#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
 75 
#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
74 
#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
 76 
#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
Line 75... Line 77...
75 
 
 77 
 
- 
 
 78 
/* Registers */
- 
 
 79 
#define R_0000F0_RBBM_SOFT_RESET                     0x0000F0
- 
 
 80 
#define   S_0000F0_SOFT_RESET_CP(x)                    (((x) & 0x1) << 0)
- 
 
 81 
#define   G_0000F0_SOFT_RESET_CP(x)                    (((x) >> 0) & 0x1)
- 
 
 82 
#define   C_0000F0_SOFT_RESET_CP                       0xFFFFFFFE
- 
 
 83 
#define   S_0000F0_SOFT_RESET_HI(x)                    (((x) & 0x1) << 1)
- 
 
 84 
#define   G_0000F0_SOFT_RESET_HI(x)                    (((x) >> 1) & 0x1)
- 
 
 85 
#define   C_0000F0_SOFT_RESET_HI                       0xFFFFFFFD
- 
 
 86 
#define   S_0000F0_SOFT_RESET_SE(x)                    (((x) & 0x1) << 2)
- 
 
 87 
#define   G_0000F0_SOFT_RESET_SE(x)                    (((x) >> 2) & 0x1)
- 
 
 88 
#define   C_0000F0_SOFT_RESET_SE                       0xFFFFFFFB
- 
 
 89 
#define   S_0000F0_SOFT_RESET_RE(x)                    (((x) & 0x1) << 3)
- 
 
 90 
#define   G_0000F0_SOFT_RESET_RE(x)                    (((x) >> 3) & 0x1)
- 
 
 91 
#define   C_0000F0_SOFT_RESET_RE                       0xFFFFFFF7
- 
 
 92 
#define   S_0000F0_SOFT_RESET_PP(x)                    (((x) & 0x1) << 4)
- 
 
 93 
#define   G_0000F0_SOFT_RESET_PP(x)                    (((x) >> 4) & 0x1)
- 
 
 94 
#define   C_0000F0_SOFT_RESET_PP                       0xFFFFFFEF
- 
 
 95 
#define   S_0000F0_SOFT_RESET_E2(x)                    (((x) & 0x1) << 5)
- 
 
 96 
#define   G_0000F0_SOFT_RESET_E2(x)                    (((x) >> 5) & 0x1)
- 
 
 97 
#define   C_0000F0_SOFT_RESET_E2                       0xFFFFFFDF
- 
 
 98 
#define   S_0000F0_SOFT_RESET_RB(x)                    (((x) & 0x1) << 6)
- 
 
 99 
#define   G_0000F0_SOFT_RESET_RB(x)                    (((x) >> 6) & 0x1)
- 
 
 100 
#define   C_0000F0_SOFT_RESET_RB                       0xFFFFFFBF
- 
 
 101 
#define   S_0000F0_SOFT_RESET_HDP(x)                   (((x) & 0x1) << 7)
- 
 
 102 
#define   G_0000F0_SOFT_RESET_HDP(x)                   (((x) >> 7) & 0x1)
- 
 
 103 
#define   C_0000F0_SOFT_RESET_HDP                      0xFFFFFF7F
- 
 
 104 
#define   S_0000F0_SOFT_RESET_MC(x)                    (((x) & 0x1) << 8)
- 
 
 105 
#define   G_0000F0_SOFT_RESET_MC(x)                    (((x) >> 8) & 0x1)
- 
 
 106 
#define   C_0000F0_SOFT_RESET_MC                       0xFFFFFEFF
- 
 
 107 
#define   S_0000F0_SOFT_RESET_AIC(x)                   (((x) & 0x1) << 9)
- 
 
 108 
#define   G_0000F0_SOFT_RESET_AIC(x)                   (((x) >> 9) & 0x1)
- 
 
 109 
#define   C_0000F0_SOFT_RESET_AIC                      0xFFFFFDFF
- 
 
 110 
#define   S_0000F0_SOFT_RESET_VIP(x)                   (((x) & 0x1) << 10)
- 
 
 111 
#define   G_0000F0_SOFT_RESET_VIP(x)                   (((x) >> 10) & 0x1)
- 
 
 112 
#define   C_0000F0_SOFT_RESET_VIP                      0xFFFFFBFF
- 
 
 113 
#define   S_0000F0_SOFT_RESET_DISP(x)                  (((x) & 0x1) << 11)
- 
 
 114 
#define   G_0000F0_SOFT_RESET_DISP(x)                  (((x) >> 11) & 0x1)
- 
 
 115 
#define   C_0000F0_SOFT_RESET_DISP                     0xFFFFF7FF
- 
 
 116 
#define   S_0000F0_SOFT_RESET_CG(x)                    (((x) & 0x1) << 12)
- 
 
 117 
#define   G_0000F0_SOFT_RESET_CG(x)                    (((x) >> 12) & 0x1)
- 
 
 118 
#define   C_0000F0_SOFT_RESET_CG                       0xFFFFEFFF
- 
 
 119 
#define R_000030_BUS_CNTL                            0x000030
- 
 
 120 
#define   S_000030_BUS_DBL_RESYNC(x)                   (((x) & 0x1) << 0)
- 
 
 121 
#define   G_000030_BUS_DBL_RESYNC(x)                   (((x) >> 0) & 0x1)
- 
 
 122 
#define   C_000030_BUS_DBL_RESYNC                      0xFFFFFFFE
- 
 
 123 
#define   S_000030_BUS_MSTR_RESET(x)                   (((x) & 0x1) << 1)
- 
 
 124 
#define   G_000030_BUS_MSTR_RESET(x)                   (((x) >> 1) & 0x1)
- 
 
 125 
#define   C_000030_BUS_MSTR_RESET                      0xFFFFFFFD
- 
 
 126 
#define   S_000030_BUS_FLUSH_BUF(x)                    (((x) & 0x1) << 2)
- 
 
 127 
#define   G_000030_BUS_FLUSH_BUF(x)                    (((x) >> 2) & 0x1)
- 
 
 128 
#define   C_000030_BUS_FLUSH_BUF                       0xFFFFFFFB
- 
 
 129 
#define   S_000030_BUS_STOP_REQ_DIS(x)                 (((x) & 0x1) << 3)
- 
 
 130 
#define   G_000030_BUS_STOP_REQ_DIS(x)                 (((x) >> 3) & 0x1)
- 
 
 131 
#define   C_000030_BUS_STOP_REQ_DIS                    0xFFFFFFF7
- 
 
 132 
#define   S_000030_BUS_PM4_READ_COMBINE_EN(x)          (((x) & 0x1) << 4)
- 
 
 133 
#define   G_000030_BUS_PM4_READ_COMBINE_EN(x)          (((x) >> 4) & 0x1)
- 
 
 134 
#define   C_000030_BUS_PM4_READ_COMBINE_EN             0xFFFFFFEF
- 
 
 135 
#define   S_000030_BUS_WRT_COMBINE_EN(x)               (((x) & 0x1) << 5)
- 
 
 136 
#define   G_000030_BUS_WRT_COMBINE_EN(x)               (((x) >> 5) & 0x1)
- 
 
 137 
#define   C_000030_BUS_WRT_COMBINE_EN                  0xFFFFFFDF
- 
 
 138 
#define   S_000030_BUS_MASTER_DIS(x)                   (((x) & 0x1) << 6)
- 
 
 139 
#define   G_000030_BUS_MASTER_DIS(x)                   (((x) >> 6) & 0x1)
- 
 
 140 
#define   C_000030_BUS_MASTER_DIS                      0xFFFFFFBF
- 
 
 141 
#define   S_000030_BIOS_ROM_WRT_EN(x)                  (((x) & 0x1) << 7)
- 
 
 142 
#define   G_000030_BIOS_ROM_WRT_EN(x)                  (((x) >> 7) & 0x1)
- 
 
 143 
#define   C_000030_BIOS_ROM_WRT_EN                     0xFFFFFF7F
- 
 
 144 
#define   S_000030_BM_DAC_CRIPPLE(x)                   (((x) & 0x1) << 8)
- 
 
 145 
#define   G_000030_BM_DAC_CRIPPLE(x)                   (((x) >> 8) & 0x1)
- 
 
 146 
#define   C_000030_BM_DAC_CRIPPLE                      0xFFFFFEFF
- 
 
 147 
#define   S_000030_BUS_NON_PM4_READ_COMBINE_EN(x)      (((x) & 0x1) << 9)
- 
 
 148 
#define   G_000030_BUS_NON_PM4_READ_COMBINE_EN(x)      (((x) >> 9) & 0x1)
- 
 
 149 
#define   C_000030_BUS_NON_PM4_READ_COMBINE_EN         0xFFFFFDFF
- 
 
 150 
#define   S_000030_BUS_XFERD_DISCARD_EN(x)             (((x) & 0x1) << 10)
- 
 
 151 
#define   G_000030_BUS_XFERD_DISCARD_EN(x)             (((x) >> 10) & 0x1)
- 
 
 152 
#define   C_000030_BUS_XFERD_DISCARD_EN                0xFFFFFBFF
- 
 
 153 
#define   S_000030_BUS_SGL_READ_DISABLE(x)             (((x) & 0x1) << 11)
- 
 
 154 
#define   G_000030_BUS_SGL_READ_DISABLE(x)             (((x) >> 11) & 0x1)
- 
 
 155 
#define   C_000030_BUS_SGL_READ_DISABLE                0xFFFFF7FF
- 
 
 156 
#define   S_000030_BIOS_DIS_ROM(x)                     (((x) & 0x1) << 12)
- 
 
 157 
#define   G_000030_BIOS_DIS_ROM(x)                     (((x) >> 12) & 0x1)
- 
 
 158 
#define   C_000030_BIOS_DIS_ROM                        0xFFFFEFFF
- 
 
 159 
#define   S_000030_BUS_PCI_READ_RETRY_EN(x)            (((x) & 0x1) << 13)
- 
 
 160 
#define   G_000030_BUS_PCI_READ_RETRY_EN(x)            (((x) >> 13) & 0x1)
- 
 
 161 
#define   C_000030_BUS_PCI_READ_RETRY_EN               0xFFFFDFFF
- 
 
 162 
#define   S_000030_BUS_AGP_AD_STEPPING_EN(x)           (((x) & 0x1) << 14)
- 
 
 163 
#define   G_000030_BUS_AGP_AD_STEPPING_EN(x)           (((x) >> 14) & 0x1)
- 
 
 164 
#define   C_000030_BUS_AGP_AD_STEPPING_EN              0xFFFFBFFF
- 
 
 165 
#define   S_000030_BUS_PCI_WRT_RETRY_EN(x)             (((x) & 0x1) << 15)
- 
 
 166 
#define   G_000030_BUS_PCI_WRT_RETRY_EN(x)             (((x) >> 15) & 0x1)
- 
 
 167 
#define   C_000030_BUS_PCI_WRT_RETRY_EN                0xFFFF7FFF
- 
 
 168 
#define   S_000030_BUS_RETRY_WS(x)                     (((x) & 0xF) << 16)
- 
 
 169 
#define   G_000030_BUS_RETRY_WS(x)                     (((x) >> 16) & 0xF)
- 
 
 170 
#define   C_000030_BUS_RETRY_WS                        0xFFF0FFFF
- 
 
 171 
#define   S_000030_BUS_MSTR_RD_MULT(x)                 (((x) & 0x1) << 20)
- 
 
 172 
#define   G_000030_BUS_MSTR_RD_MULT(x)                 (((x) >> 20) & 0x1)
- 
 
 173 
#define   C_000030_BUS_MSTR_RD_MULT                    0xFFEFFFFF
- 
 
 174 
#define   S_000030_BUS_MSTR_RD_LINE(x)                 (((x) & 0x1) << 21)
- 
 
 175 
#define   G_000030_BUS_MSTR_RD_LINE(x)                 (((x) >> 21) & 0x1)
- 
 
 176 
#define   C_000030_BUS_MSTR_RD_LINE                    0xFFDFFFFF
- 
 
 177 
#define   S_000030_BUS_SUSPEND(x)                      (((x) & 0x1) << 22)
- 
 
 178 
#define   G_000030_BUS_SUSPEND(x)                      (((x) >> 22) & 0x1)
- 
 
 179 
#define   C_000030_BUS_SUSPEND                         0xFFBFFFFF
- 
 
 180 
#define   S_000030_LAT_16X(x)                          (((x) & 0x1) << 23)
- 
 
 181 
#define   G_000030_LAT_16X(x)                          (((x) >> 23) & 0x1)
- 
 
 182 
#define   C_000030_LAT_16X                             0xFF7FFFFF
- 
 
 183 
#define   S_000030_BUS_RD_DISCARD_EN(x)                (((x) & 0x1) << 24)
- 
 
 184 
#define   G_000030_BUS_RD_DISCARD_EN(x)                (((x) >> 24) & 0x1)
- 
 
 185 
#define   C_000030_BUS_RD_DISCARD_EN                   0xFEFFFFFF
- 
 
 186 
#define   S_000030_ENFRCWRDY(x)                        (((x) & 0x1) << 25)
- 
 
 187 
#define   G_000030_ENFRCWRDY(x)                        (((x) >> 25) & 0x1)
- 
 
 188 
#define   C_000030_ENFRCWRDY                           0xFDFFFFFF
- 
 
 189 
#define   S_000030_BUS_MSTR_WS(x)                      (((x) & 0x1) << 26)
- 
 
 190 
#define   G_000030_BUS_MSTR_WS(x)                      (((x) >> 26) & 0x1)
- 
 
 191 
#define   C_000030_BUS_MSTR_WS                         0xFBFFFFFF
- 
 
 192 
#define   S_000030_BUS_PARKING_DIS(x)                  (((x) & 0x1) << 27)
- 
 
 193 
#define   G_000030_BUS_PARKING_DIS(x)                  (((x) >> 27) & 0x1)
- 
 
 194 
#define   C_000030_BUS_PARKING_DIS                     0xF7FFFFFF
- 
 
 195 
#define   S_000030_BUS_MSTR_DISCONNECT_EN(x)           (((x) & 0x1) << 28)
- 
 
 196 
#define   G_000030_BUS_MSTR_DISCONNECT_EN(x)           (((x) >> 28) & 0x1)
- 
 
 197 
#define   C_000030_BUS_MSTR_DISCONNECT_EN              0xEFFFFFFF
- 
 
 198 
#define   S_000030_SERR_EN(x)                          (((x) & 0x1) << 29)
- 
 
 199 
#define   G_000030_SERR_EN(x)                          (((x) >> 29) & 0x1)
- 
 
 200 
#define   C_000030_SERR_EN                             0xDFFFFFFF
- 
 
 201 
#define   S_000030_BUS_READ_BURST(x)                   (((x) & 0x1) << 30)
- 
 
 202 
#define   G_000030_BUS_READ_BURST(x)                   (((x) >> 30) & 0x1)
- 
 
 203 
#define   C_000030_BUS_READ_BURST                      0xBFFFFFFF
- 
 
 204 
#define   S_000030_BUS_RDY_READ_DLY(x)                 (((x) & 0x1) << 31)
- 
 
 205 
#define   G_000030_BUS_RDY_READ_DLY(x)                 (((x) >> 31) & 0x1)
76 
/* Registers */
 206 
#define   C_000030_BUS_RDY_READ_DLY                    0x7FFFFFFF
77 
#define R_000040_GEN_INT_CNTL                        0x000040
 207 
#define R_000040_GEN_INT_CNTL                        0x000040
78 
#define   S_000040_CRTC_VBLANK(x)                      (((x) & 0x1) << 0)
 208 
#define   S_000040_CRTC_VBLANK(x)                      (((x) & 0x1) << 0)
79 
#define   G_000040_CRTC_VBLANK(x)                      (((x) >> 0) & 0x1)
 209 
#define   G_000040_CRTC_VBLANK(x)                      (((x) >> 0) & 0x1)
80 
#define   C_000040_CRTC_VBLANK                         0xFFFFFFFE
 210 
#define   C_000040_CRTC_VBLANK                         0xFFFFFFFE
Line 419... Line 549...
419 
#define   G_000360_CUR2_OFFSET(x)                      (((x) >> 0) & 0x7FFFFFF)
 549 
#define   G_000360_CUR2_OFFSET(x)                      (((x) >> 0) & 0x7FFFFFF)
420 
#define   C_000360_CUR2_OFFSET                         0xF8000000
 550 
#define   C_000360_CUR2_OFFSET                         0xF8000000
421 
#define   S_000360_CUR2_LOCK(x)                        (((x) & 0x1) << 31)
 551 
#define   S_000360_CUR2_LOCK(x)                        (((x) & 0x1) << 31)
422 
#define   G_000360_CUR2_LOCK(x)                        (((x) >> 31) & 0x1)
 552 
#define   G_000360_CUR2_LOCK(x)                        (((x) >> 31) & 0x1)
423 
#define   C_000360_CUR2_LOCK                           0x7FFFFFFF
 553 
#define   C_000360_CUR2_LOCK                           0x7FFFFFFF
424 
#define R_0003C2_GENMO_WT                            0x0003C0
 554 
#define R_0003C2_GENMO_WT                            0x0003C2
425 
#define   S_0003C2_GENMO_MONO_ADDRESS_B(x)             (((x) & 0x1) << 0)
 555 
#define   S_0003C2_GENMO_MONO_ADDRESS_B(x)             (((x) & 0x1) << 0)
426 
#define   G_0003C2_GENMO_MONO_ADDRESS_B(x)             (((x) >> 0) & 0x1)
 556 
#define   G_0003C2_GENMO_MONO_ADDRESS_B(x)             (((x) >> 0) & 0x1)
427 
#define   C_0003C2_GENMO_MONO_ADDRESS_B                0xFE
 557 
#define   C_0003C2_GENMO_MONO_ADDRESS_B                0xFE
428 
#define   S_0003C2_VGA_RAM_EN(x)                       (((x) & 0x1) << 1)
 558 
#define   S_0003C2_VGA_RAM_EN(x)                       (((x) & 0x1) << 1)
429 
#define   G_0003C2_VGA_RAM_EN(x)                       (((x) >> 1) & 0x1)
 559 
#define   G_0003C2_VGA_RAM_EN(x)                       (((x) >> 1) & 0x1)
Line 708... Line 838...
708 
#define   C_00000D_FORCE_TDM                           0xF7FFFFFF
 838 
#define   C_00000D_FORCE_TDM                           0xF7FFFFFF
709 
#define   S_00000D_FORCE_RB(x)                         (((x) & 0x1) << 28)
 839 
#define   S_00000D_FORCE_RB(x)                         (((x) & 0x1) << 28)
710 
#define   G_00000D_FORCE_RB(x)                         (((x) >> 28) & 0x1)
 840 
#define   G_00000D_FORCE_RB(x)                         (((x) >> 28) & 0x1)
711 
#define   C_00000D_FORCE_RB                            0xEFFFFFFF
 841 
#define   C_00000D_FORCE_RB                            0xEFFFFFFF
Line -... Line 842...
- 
 
 842 
 
- 
 
 843 
/* PLL regs */
- 
 
 844 
#define SCLK_CNTL                                      0xd
- 
 
 845 
#define   FORCE_HDP                                    (1 << 17)
- 
 
 846 
#define CLK_PWRMGT_CNTL                                0x14
- 
 
 847 
#define   GLOBAL_PMAN_EN                               (1 << 10)
- 
 
 848 
#define   DISP_PM                                      (1 << 20)
- 
 
 849 
#define PLL_PWRMGT_CNTL                                0x15
- 
 
 850 
#define   MPLL_TURNOFF                                 (1 << 0)
- 
 
 851 
#define   SPLL_TURNOFF                                 (1 << 1)
- 
 
 852 
#define   PPLL_TURNOFF                                 (1 << 2)
- 
 
 853 
#define   P2PLL_TURNOFF                                (1 << 3)
- 
 
 854 
#define   TVPLL_TURNOFF                                (1 << 4)
- 
 
 855 
#define   MOBILE_SU                                    (1 << 16)
- 
 
 856 
#define   SU_SCLK_USE_BCLK                             (1 << 17)
- 
 
 857 
#define SCLK_CNTL2                                     0x1e
- 
 
 858 
#define   REDUCED_SPEED_SCLK_MODE                      (1 << 16)
- 
 
 859 
#define   REDUCED_SPEED_SCLK_SEL(x)                    ((x) << 17)
- 
 
 860 
#define MCLK_MISC                                      0x1f
- 
 
 861 
#define   EN_MCLK_TRISTATE_IN_SUSPEND                  (1 << 18)
- 
 
 862 
#define SCLK_MORE_CNTL                                 0x35
- 
 
 863 
#define   REDUCED_SPEED_SCLK_EN                        (1 << 16)
- 
 
 864 
#define   IO_CG_VOLTAGE_DROP                           (1 << 17)
- 
 
 865 
#define   VOLTAGE_DELAY_SEL(x)                         ((x) << 20)
- 
 
 866 
#define   VOLTAGE_DROP_SYNC                            (1 << 19)
- 
 
 867 
 
- 
 
 868 
/* mmreg */
- 
 
 869 
#define DISP_PWR_MAN                                   0xd08
- 
 
 870 
#define   DISP_D3_GRPH_RST                             (1 << 18)
- 
 
 871 
#define   DISP_D3_SUBPIC_RST                           (1 << 19)
- 
 
 872 
#define   DISP_D3_OV0_RST                              (1 << 20)
- 
 
 873 
#define   DISP_D1D2_GRPH_RST                           (1 << 21)
- 
 
 874 
#define   DISP_D1D2_SUBPIC_RST                         (1 << 22)
- 
 
 875 
#define   DISP_D1D2_OV0_RST                            (1 << 23)
- 
 
 876 
#define   DISP_DVO_ENABLE_RST                          (1 << 24)
- 
 
 877 
#define   TV_ENABLE_RST                                (1 << 25)
Line 712... Line 878...
712 
 
 878 
#define   AUTO_PWRUP_EN                                (1 << 26)