WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/r100.c

 	 * wait for another frame.
 	 */
 	while (r100_is_in_vblank(rdev, crtc)) {
 		if (i++ % 100 == 0) {
 			if (!r100_is_counter_moving(rdev, crtc))
-					break;
+				break;
-			}
+		}
+	}
 	while (!r100_is_in_vblank(rdev, crtc)) {
 		if (i++ % 100 == 0) {
 			if (!r100_is_counter_moving(rdev, crtc))
-					break;
+				break;
+		}
+	}
+}
+	}
 	/* Initialize common gart structure */
 	r = radeon_gart_init(rdev);
 	if (r)
 		return r;
-    rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
+	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
+	rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
 	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 	return radeon_gart_table_ram_alloc(rdev);
+}
 	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 	WREG32(RADEON_AIC_LO_ADDR, 0);
 	WREG32(RADEON_AIC_HI_ADDR, 0);
+}
+uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
+{
+	return addr;
+}
 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
-			    uint64_t addr, uint32_t flags)
+			    uint64_t entry)
+{
 	u32 *gtt = rdev->gart.ptr;
-	gtt[i] = cpu_to_le32(lower_32_bits(addr));
+	gtt[i] = cpu_to_le32(lower_32_bits(entry));
+}
 void r100_pci_gart_fini(struct radeon_device *rdev)
 {
 	radeon_gart_fini(rdev);
-		r100_pci_gart_disable(rdev);
+	r100_pci_gart_disable(rdev);
 	radeon_gart_table_ram_free(rdev);
+}
+	}
 	if (rdev->irq.hpd[1]) {
 		tmp |= RADEON_FP2_DETECT_MASK;
+	}
 	WREG32(RADEON_GEN_INT_CNTL, tmp);
+	/* read back to post the write */
+	RREG32(RADEON_GEN_INT_CNTL);
 	return 0;
+}
 void r100_irq_disable(struct radeon_device *rdev)
 			radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
+		}
 		/* Vertical blank interrupts */
 		if (status & RADEON_CRTC_VBLANK_STAT) {
 			if (rdev->irq.crtc_vblank_int[0]) {
-//				drm_handle_vblank(rdev->ddev, 0);
+				drm_handle_vblank(rdev->ddev, 0);
 				rdev->pm.vblank_sync = true;
-//				wake_up(&rdev->irq.vblank_queue);
+				wake_up(&rdev->irq.vblank_queue);
+			}
-//			if (rdev->irq.pflip[0])
+			if (atomic_read(&rdev->irq.pflip[0]))
-//				radeon_crtc_handle_flip(rdev, 0);
+				radeon_crtc_handle_vblank(rdev, 0);
+		}
 		if (status & RADEON_CRTC2_VBLANK_STAT) {
 			if (rdev->irq.crtc_vblank_int[1]) {
-//				drm_handle_vblank(rdev->ddev, 1);
+				drm_handle_vblank(rdev->ddev, 1);
 				rdev->pm.vblank_sync = true;
-//				wake_up(&rdev->irq.vblank_queue);
+				wake_up(&rdev->irq.vblank_queue);
+			}
-//			if (rdev->irq.pflip[1])
+			if (atomic_read(&rdev->irq.pflip[1]))
-//				radeon_crtc_handle_flip(rdev, 1);
+				radeon_crtc_handle_vblank(rdev, 1);
+		}
 		if (status & RADEON_FP_DETECT_STAT) {
 			queue_hotplug = true;
 			DRM_DEBUG("HPD1\n");
+		}
 	BUG();
 	return false;
+}
 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
-		   uint64_t src_offset,
+				    uint64_t src_offset,
-		   uint64_t dst_offset,
+				    uint64_t dst_offset,
-		   unsigned num_gpu_pages,
+				    unsigned num_gpu_pages,
 				    struct reservation_object *resv)
+{
 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 	struct radeon_fence *fence;
 		   (rdev->family == CHIP_R580) ||
 		   (rdev->family == CHIP_RV560) ||
 		   (rdev->family == CHIP_RV570)) {
 		DRM_INFO("Loading R500 Microcode\n");
 		fw_name = FIRMWARE_R520;
-		}
+	}
 	err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
-   if (err) {
+	if (err) {
-       printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
+		printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
-              fw_name);
+		       fw_name);
 	} else if (rdev->me_fw->size % 8) {
 		printk(KERN_ERR
 		       "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 		       rdev->me_fw->size, fw_name);
 	ib = p->ib.ptr;
 	track = (struct r100_cs_track *)p->track;
 	idx_value = radeon_get_ib_value(p, idx);
-		switch (reg) {
+	switch (reg) {
-		case RADEON_CRTC_GUI_TRIG_VLINE:
+	case RADEON_CRTC_GUI_TRIG_VLINE:
-			r = r100_cs_packet_parse_vline(p);
+		r = r100_cs_packet_parse_vline(p);
-			if (r) {
+		if (r) {
-				DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
-						idx, reg);
+				  idx, reg);
 			radeon_cs_dump_packet(p, pkt);
-				return r;
+			return r;
+		}
-			break;
+		break;
 		/* FIXME: only allow PACKET3 blit? easier to check for out of
 		 * range access */
-		case RADEON_DST_PITCH_OFFSET:
+	case RADEON_DST_PITCH_OFFSET:
-		case RADEON_SRC_PITCH_OFFSET:
+	case RADEON_SRC_PITCH_OFFSET:
 		r = r100_reloc_pitch_offset(p, pkt, idx, reg);
 		if (r)
 			return r;
 		break;
 	case RADEON_RB3D_DEPTHOFFSET:
 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
-			if (r) {
+		if (r) {
-				DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
-					  idx, reg);
+				  idx, reg);
 			radeon_cs_dump_packet(p, pkt);
-				return r;
+			return r;
+		}
 		track->zb.robj = reloc->robj;
 		track->zb.offset = idx_value;
 		track->zb_dirty = true;
 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
-			break;
+		break;
-		case RADEON_RB3D_COLOROFFSET:
+	case RADEON_RB3D_COLOROFFSET:
 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 		if (r) {
 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 		track->cb[0].robj = reloc->robj;
 		track->cb[0].offset = idx_value;
 		track->cb_dirty = true;
 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
 		break;
-		case RADEON_PP_TXOFFSET_0:
+	case RADEON_PP_TXOFFSET_0:
-		case RADEON_PP_TXOFFSET_1:
+	case RADEON_PP_TXOFFSET_1:
-		case RADEON_PP_TXOFFSET_2:
+	case RADEON_PP_TXOFFSET_2:
 		i = (reg - RADEON_PP_TXOFFSET_0) / 24;
 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 		if (r) {
 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 				  idx, reg);
 		if (r) {
 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 				  idx, reg);
 			radeon_cs_dump_packet(p, pkt);
 			return r;
-			}
+		}
 		track->textures[1].cube_info[i].offset = idx_value;
 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
 		track->textures[1].cube_info[i].robj = reloc->robj;
 		track->tex_dirty = true;
 		break;
 	case RADEON_PP_CUBIC_OFFSET_T2_2:
 	case RADEON_PP_CUBIC_OFFSET_T2_3:
 	case RADEON_PP_CUBIC_OFFSET_T2_4:
 		i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
-			if (r) {
+		if (r) {
-				DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
-					  idx, reg);
+				  idx, reg);
 			radeon_cs_dump_packet(p, pkt);
-				return r;
+			return r;
-			}
+		}
 		track->textures[2].cube_info[i].offset = idx_value;
 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
 		track->textures[2].cube_info[i].robj = reloc->robj;
 		track->tex_dirty = true;
 		break;
 	case RADEON_RE_WIDTH_HEIGHT:
 		track->maxy = ((idx_value >> 16) & 0x7FF);
 		track->cb_dirty = true;
 		track->zb_dirty = true;
-			break;
+		break;
-		case RADEON_RB3D_COLORPITCH:
+	case RADEON_RB3D_COLORPITCH:
 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
-			if (r) {
+		if (r) {
-				DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
-					  idx, reg);
+				  idx, reg);
 			radeon_cs_dump_packet(p, pkt);
-				return r;
+			return r;
-			}
+		}
 		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
 			if (reloc->tiling_flags & RADEON_TILING_MACRO)
 				tile_flags |= RADEON_COLOR_TILE_ENABLE;
 			if (reloc->tiling_flags & RADEON_TILING_MICRO)
 				tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
-		tmp = idx_value & ~(0x7 << 16);
+			tmp = idx_value & ~(0x7 << 16);
 			tmp |= tile_flags;
 			ib[idx] = tmp;
 		} else
 			break;
 		default:
 			break;
+		}
 		track->zb_dirty = true;
-			break;
+		break;
-		case RADEON_RB3D_ZPASS_ADDR:
+	case RADEON_RB3D_ZPASS_ADDR:
 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
-			if (r) {
+		if (r) {
-				DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
-					  idx, reg);
+				  idx, reg);
 			radeon_cs_dump_packet(p, pkt);
-				return r;
+			return r;
-			}
+		}
 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
-			break;
+		break;
 	case RADEON_PP_CNTL:
+		{
 			uint32_t temp = idx_value >> 4;
 			for (i = 0; i < track->num_texture; i++)
 				track->textures[i].enabled = !!(temp & (1 << i));
 			track->tex_dirty = true;
+		}
-			break;
+		break;
 	case RADEON_SE_VF_CNTL:
 		track->vap_vf_cntl = idx_value;
 		break;
 	case RADEON_SE_VTX_FMT:
 		track->vtx_size = r100_get_vtx_size(idx_value);
 	track = (struct r100_cs_track *)p->track;
 	switch (pkt->opcode) {
 	case PACKET3_3D_LOAD_VBPNTR:
 		r = r100_packet3_load_vbpntr(p, pkt, idx);
 		if (r)
-				return r;
+			return r;
 		break;
 	case PACKET3_INDX_BUFFER:
 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 		if (r) {
 			DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
 			return r;
+		}
 		p->idx += pkt.count + 2;
 		switch (pkt.type) {
 		case RADEON_PACKET_TYPE0:
-				if (p->rdev->family >= CHIP_R200)
+			if (p->rdev->family >= CHIP_R200)
-					r = r100_cs_parse_packet0(p, &pkt,
+				r = r100_cs_parse_packet0(p, &pkt,
-								  p->rdev->config.r100.reg_safe_bm,
+					p->rdev->config.r100.reg_safe_bm,
-								  p->rdev->config.r100.reg_safe_bm_size,
+					p->rdev->config.r100.reg_safe_bm_size,
-								  &r200_packet0_check);
+					&r200_packet0_check);
-				else
+			else
-					r = r100_cs_parse_packet0(p, &pkt,
+				r = r100_cs_parse_packet0(p, &pkt,
-								  p->rdev->config.r100.reg_safe_bm,
+					p->rdev->config.r100.reg_safe_bm,
-								  p->rdev->config.r100.reg_safe_bm_size,
+					p->rdev->config.r100.reg_safe_bm_size,
-								  &r100_packet0_check);
+					&r100_packet0_check);
-				break;
+			break;
 		case RADEON_PACKET_TYPE2:
-				break;
+			break;
 		case RADEON_PACKET_TYPE3:
-				r = r100_packet3_check(p, &pkt);
+			r = r100_packet3_check(p, &pkt);
-				break;
+			break;
-			default:
+		default:
-				DRM_ERROR("Unknown packet type %d !\n",
+			DRM_ERROR("Unknown packet type %d !\n",
-					  pkt.type);
+				  pkt.type);
-				return -EINVAL;
+			return -EINVAL;
+		}
 		if (r)
 			return r;
 	} while (p->idx < p->chunk_ib->length_dw);
 	return 0;
 	rbbm_status = RREG32(R_000E40_RBBM_STATUS);
 	if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
 		radeon_ring_lockup_update(rdev, ring);
 		return false;
+	}
 	return radeon_ring_test_lockup(rdev, ring);
+}
 		 */
 		if (rdev->mc.real_vram_size == 0) {
 			rdev->mc.real_vram_size = 8192 * 1024;
 			WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
+		}
-		 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
+		/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
 		 * Novell bug 204882 + along with lots of ubuntu ones
 		 */
 		if (rdev->mc.aper_size > config_aper_size)
 			config_aper_size = rdev->mc.aper_size;
  * Indirect registers accessor
  */
 void r100_pll_errata_after_index(struct radeon_device *rdev)
+{
 	if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
-	(void)RREG32(RADEON_CLOCK_CNTL_DATA);
+		(void)RREG32(RADEON_CLOCK_CNTL_DATA);
-	(void)RREG32(RADEON_CRTC_GEN_CNTL);
+		(void)RREG32(RADEON_CRTC_GEN_CNTL);
+	}
+}
 static void r100_pll_errata_after_data(struct radeon_device *rdev)
 	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
 	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
 	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
 	seq_printf(m, "%u dwords in ring\n", count);
 	if (ring->ready) {
-	for (j = 0; j <= count; j++) {
+		for (j = 0; j <= count; j++) {
-		i = (rdp + j) & ring->ptr_mask;
+			i = (rdp + j) & ring->ptr_mask;
-		seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
+			seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
-	}
+		}
+	}
 	return 0;
+}
 	struct drm_display_mode *mode1 = NULL;
 	struct drm_display_mode *mode2 = NULL;
 	uint32_t pixel_bytes1 = 0;
 	uint32_t pixel_bytes2 = 0;
+	/* Guess line buffer size to be 8192 pixels */
+	u32 lb_size = 8192;
 	if (!rdev->mode_info.mode_config_initialized)
 		return;
 	radeon_update_display_priority(rdev);
 	if (rdev->mode_info.crtcs[0]->base.enabled) {
 		mode1 = &rdev->mode_info.crtcs[0]->base.mode;
 		pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8;
 	}
 	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
-	if (rdev->mode_info.crtcs[1]->base.enabled) {
+		if (rdev->mode_info.crtcs[1]->base.enabled) {
-		mode2 = &rdev->mode_info.crtcs[1]->base.mode;
+			mode2 = &rdev->mode_info.crtcs[1]->base.mode;
 			pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8;
+		}
+	}
+		}
 		DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
 			  (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
+	}
+	/* Save number of lines the linebuffer leads before the scanout */
+	if (mode1)
+	    rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
+	if (mode2)
 	    rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
+}
 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
+	}
 	r100_irq_set(rdev);
 	rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 	/* 1M ring buffer */
-   r = r100_cp_init(rdev, 1024 * 1024);
+	r = r100_cp_init(rdev, 1024 * 1024);
-   if (r) {
+	if (r) {
 		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
-       return r;
+		return r;
+	}
 	r = radeon_ib_pool_init(rdev);
 	if (r) {
 		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 		return r;
+	}
+	return 0;
+}
+void r100_fini(struct radeon_device *rdev)
+{
+	radeon_pm_fini(rdev);
+	r100_cp_fini(rdev);
+	radeon_wb_fini(rdev);
+	radeon_ib_pool_fini(rdev);
+	radeon_gem_fini(rdev);
+	if (rdev->flags & RADEON_IS_PCI)
+		r100_pci_gart_fini(rdev);
+	radeon_agp_fini(rdev);
+	radeon_irq_kms_fini(rdev);
+	radeon_fence_driver_fini(rdev);
+	radeon_bo_fini(rdev);
+	radeon_atombios_fini(rdev);
 	kfree(rdev->bios);
-	return 0;
+	rdev->bios = NULL;
+}
 /*
 	rdev->accel_working = true;
 	r = r100_startup(rdev);
 	if (r) {
 		/* Somethings want wront with the accel init stop accel */
 		dev_err(rdev->dev, "Disabling GPU acceleration\n");
+		r100_cp_fini(rdev);
+		radeon_wb_fini(rdev);
+		radeon_ib_pool_fini(rdev);
+		radeon_irq_kms_fini(rdev);
 		if (rdev->flags & RADEON_IS_PCI)
 			r100_pci_gart_fini(rdev);
 		rdev->accel_working = false;
+	}
 	return 0;
+}
+uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
+{
+	unsigned long flags;
+	uint32_t ret;
+	spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
+	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
+	ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
+	spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
+	return ret;
+}
+void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
+	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
+	writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
+	spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
+}
 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
+{
 	if (reg < rdev->rio_mem_size)
 		return ioread32(rdev->rio_mem + reg);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r100.c – Rev 5271 → 6104