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Rev 3120 Rev 3192
Line 389... Line 389...
389 
int r100_irq_process(struct radeon_device *rdev)
 389 
int r100_irq_process(struct radeon_device *rdev)
390 
{
 390 
{
391 
	uint32_t status, msi_rearm;
 391 
	uint32_t status, msi_rearm;
392 
	bool queue_hotplug = false;
 392 
	bool queue_hotplug = false;
Line 393... Line -...
393 
 
 - 
 
394 
 
 393 
 
395 
	status = r100_irq_ack(rdev);
 394 
	status = r100_irq_ack(rdev);
396 
	if (!status) {
 395 
	if (!status) {
397 
		return IRQ_NONE;
 396 
		return IRQ_NONE;
398 
	}
 397 
	}
Line 802... Line 801...
802 
	if (r) {
 801 
	if (r) {
803 
		DRM_ERROR("radeon: cp isn't working (%d).\n", r);
 802 
		DRM_ERROR("radeon: cp isn't working (%d).\n", r);
804 
		return r;
 803 
		return r;
805 
	}
 804 
	}
806 
	ring->ready = true;
 805 
	ring->ready = true;
807 
//	radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 806 
	radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
- 
 
 807 
 
- 
 
 808 
	if (!ring->rptr_save_reg /* not resuming from suspend */
- 
 
 809 
	    && radeon_ring_supports_scratch_reg(rdev, ring)) {
- 
 
 810 
		r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
- 
 
 811 
		if (r) {
- 
 
 812 
			DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
- 
 
 813 
			ring->rptr_save_reg = 0;
- 
 
 814 
		}
- 
 
 815 
	}
808 
	return 0;
 816 
	return 0;
809 
}
 817 
}
Line 810... Line 818...
810 
 
 818 
 
811 
void r100_cp_fini(struct radeon_device *rdev)
 819 
void r100_cp_fini(struct radeon_device *rdev)
812 
{
 820 
{
813 
	if (r100_cp_wait_for_idle(rdev)) {
 821 
	if (r100_cp_wait_for_idle(rdev)) {
814 
		DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
 822 
		DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
815 
	}
 823 
	}
816 
	/* Disable ring */
 824 
	/* Disable ring */
- 
 
 825 
	r100_cp_disable(rdev);
817 
	r100_cp_disable(rdev);
 826 
	radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
818 
	radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
 827 
	radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
819 
	DRM_INFO("radeon: cp finalized\n");
 828 
	DRM_INFO("radeon: cp finalized\n");
Line 820... Line 829...
820 
}
 829 
}
821 
 
 830 
 
822 
void r100_cp_disable(struct radeon_device *rdev)
 831 
void r100_cp_disable(struct radeon_device *rdev)
823 
{
 832 
{
824 
	/* Disable ring */
 833 
	/* Disable ring */
825 
//	radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 834 
	radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
826 
	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
 835 
	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
827 
	WREG32(RADEON_CP_CSQ_MODE, 0);
 836 
	WREG32(RADEON_CP_CSQ_MODE, 0);
828 
	WREG32(RADEON_CP_CSQ_CNTL, 0);
 837 
	WREG32(RADEON_CP_CSQ_CNTL, 0);
Line 3706... Line 3715...
3706 
		rdev->accel_working = false;
 3715 
		rdev->accel_working = false;
3707 
	}
 3716 
	}
3708 
	return 0;
 3717 
	return 0;
3709 
}
 3718 
}
Line 3710... Line 3719...
3710 
 
 3719 
 
- 
 
 3720 
uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
3711 
uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
 3721 
		      bool always_indirect)
3712 
{
 3722 
{
3713 
	if (reg < rdev->rmmio_size)
 3723 
	if (reg < rdev->rmmio_size && !always_indirect)
3714 
		return readl(((void __iomem *)rdev->rmmio) + reg);
 3724 
		return readl(((void __iomem *)rdev->rmmio) + reg);
- 
 
 3725 
	else {
- 
 
 3726 
		unsigned long flags;
- 
 
 3727 
		uint32_t ret;
- 
 
 3728 
 
3715 
	else {
 3729 
		spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
3716 
		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 3730 
		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
- 
 
 3731 
		ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
- 
 
 3732 
		spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
- 
 
 3733 
 
3717 
		return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 3734 
		return ret;
3718 
	}
 3735 
	}
Line 3719... Line 3736...
3719 
}
 3736 
}
- 
 
 3737 
 
3720 
 
 3738 
void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
3721 
void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 3739 
		  bool always_indirect)
3722 
{
 3740 
{
3723 
	if (reg < rdev->rmmio_size)
 3741 
	if (reg < rdev->rmmio_size && !always_indirect)
- 
 
 3742 
		writel(v, ((void __iomem *)rdev->rmmio) + reg);
- 
 
 3743 
	else {
- 
 
 3744 
		unsigned long flags;
3724 
		writel(v, ((void __iomem *)rdev->rmmio) + reg);
 3745 
 
3725 
	else {
 3746 
		spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
- 
 
 3747 
		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
3726 
		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 3748 
		writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
3727 
		writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 3749 
		spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
Line 3728... Line 3750...
3728 
	}
 3750 
	}
3729 
}
 3751 
}