Rev 1321 | Rev 1404 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 1321 | Rev 1403 | ||
---|---|---|---|
Line 118... | Line 118... | ||
118 | 118 | ||
119 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
119 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
120 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
120 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
121 | switch (radeon_connector->hpd.hpd) { |
121 | switch (radeon_connector->hpd.hpd) { |
122 | case RADEON_HPD_1: |
122 | case RADEON_HPD_1: |
123 | rdev->irq.hpd[0] = true; |
123 | // rdev->irq.hpd[0] = true; |
124 | break; |
124 | break; |
125 | case RADEON_HPD_2: |
125 | case RADEON_HPD_2: |
126 | rdev->irq.hpd[1] = true; |
126 | // rdev->irq.hpd[1] = true; |
127 | break; |
127 | break; |
128 | default: |
128 | default: |
129 | break; |
129 | break; |
130 | } |
130 | } |
- | 131 | } |
|
131 | } |
132 | // if (rdev->irq.installed) |
132 | r100_irq_set(rdev); |
133 | // r100_irq_set(rdev); |
Line 133... | Line 134... | ||
133 | } |
134 | } |
134 | 135 | ||
135 | void r100_hpd_fini(struct radeon_device *rdev) |
136 | void r100_hpd_fini(struct radeon_device *rdev) |
Line 139... | Line 140... | ||
139 | 140 | ||
140 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
141 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
141 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
142 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
142 | switch (radeon_connector->hpd.hpd) { |
143 | switch (radeon_connector->hpd.hpd) { |
143 | case RADEON_HPD_1: |
144 | case RADEON_HPD_1: |
144 | rdev->irq.hpd[0] = false; |
145 | // rdev->irq.hpd[0] = false; |
145 | break; |
146 | break; |
146 | case RADEON_HPD_2: |
147 | case RADEON_HPD_2: |
147 | rdev->irq.hpd[1] = false; |
148 | // rdev->irq.hpd[1] = false; |
148 | break; |
149 | break; |
149 | default: |
150 | default: |
150 | break; |
151 | break; |
151 | } |
152 | } |
Line 261... | Line 262... | ||
261 | } |
262 | } |
262 | return irqs & irq_mask; |
263 | return irqs & irq_mask; |
263 | } |
264 | } |
Line -... | Line 265... | ||
- | 265 | ||
- | 266 | ||
- | 267 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) |
|
- | 268 | { |
|
- | 269 | if (crtc == 0) |
|
- | 270 | return RREG32(RADEON_CRTC_CRNT_FRAME); |
|
- | 271 | else |
|
Line 264... | Line 272... | ||
264 | 272 | return RREG32(RADEON_CRTC2_CRNT_FRAME); |
|
265 | 273 | } |
|
266 | 274 | ||
267 | void r100_fence_ring_emit(struct radeon_device *rdev, |
275 | void r100_fence_ring_emit(struct radeon_device *rdev, |
268 | struct radeon_fence *fence) |
276 | struct radeon_fence *fence) |
269 | { |
277 | { |
270 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
278 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
271 | * for enough space (today caller are ib schedule and buffer move) */ |
279 | * for enough space (today caller are ib schedule and buffer move) */ |
- | 280 | /* Wait until IDLE & CLEAN */ |
|
- | 281 | radeon_ring_write(rdev, PACKET0(0x1720, 0)); |
|
- | 282 | radeon_ring_write(rdev, (1 << 16) | (1 << 17)); |
|
- | 283 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
|
- | 284 | radeon_ring_write(rdev, rdev->config.r100.hdp_cntl | |
|
272 | /* Wait until IDLE & CLEAN */ |
285 | RADEON_HDP_READ_BUFFER_INVALIDATE); |
273 | radeon_ring_write(rdev, PACKET0(0x1720, 0)); |
286 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
274 | radeon_ring_write(rdev, (1 << 16) | (1 << 17)); |
287 | radeon_ring_write(rdev, rdev->config.r100.hdp_cntl); |
275 | /* Emit fence sequence & fire IRQ */ |
288 | /* Emit fence sequence & fire IRQ */ |
276 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); |
289 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); |
Line 517... | Line 530... | ||
517 | rdev->me_fw = NULL; |
530 | rdev->me_fw = NULL; |
518 | } |
531 | } |
519 | return err; |
532 | return err; |
520 | } |
533 | } |
Line 521... | Line -... | ||
521 | - | ||
522 | static inline __u32 __swab32(__u32 x) |
- | |
523 | { |
- | |
524 | asm("bswapl %0" : |
- | |
525 | "=&r" (x) |
- | |
526 | :"r" (x)); |
- | |
527 | return x; |
- | |
528 | } |
- | |
529 | - | ||
530 | static inline __u32 be32_to_cpup(const __be32 *p) |
- | |
531 | { |
- | |
532 | return __swab32(*(__u32 *)p); |
- | |
533 | } |
- | |
Line 534... | Line 534... | ||
534 | 534 | ||
535 | 535 | ||
536 | static void r100_cp_load_microcode(struct radeon_device *rdev) |
536 | static void r100_cp_load_microcode(struct radeon_device *rdev) |
537 | { |
537 | { |
Line 1306... | Line 1306... | ||
1306 | case RADEON_TXFORMAT_ARGB1555: |
1306 | case RADEON_TXFORMAT_ARGB1555: |
1307 | case RADEON_TXFORMAT_RGB565: |
1307 | case RADEON_TXFORMAT_RGB565: |
1308 | case RADEON_TXFORMAT_ARGB4444: |
1308 | case RADEON_TXFORMAT_ARGB4444: |
1309 | case RADEON_TXFORMAT_VYUY422: |
1309 | case RADEON_TXFORMAT_VYUY422: |
1310 | case RADEON_TXFORMAT_YVYU422: |
1310 | case RADEON_TXFORMAT_YVYU422: |
1311 | case RADEON_TXFORMAT_DXT1: |
- | |
1312 | case RADEON_TXFORMAT_SHADOW16: |
1311 | case RADEON_TXFORMAT_SHADOW16: |
1313 | case RADEON_TXFORMAT_LDUDV655: |
1312 | case RADEON_TXFORMAT_LDUDV655: |
1314 | case RADEON_TXFORMAT_DUDV88: |
1313 | case RADEON_TXFORMAT_DUDV88: |
1315 | track->textures[i].cpp = 2; |
1314 | track->textures[i].cpp = 2; |
1316 | break; |
1315 | break; |
1317 | case RADEON_TXFORMAT_ARGB8888: |
1316 | case RADEON_TXFORMAT_ARGB8888: |
1318 | case RADEON_TXFORMAT_RGBA8888: |
1317 | case RADEON_TXFORMAT_RGBA8888: |
1319 | case RADEON_TXFORMAT_DXT23: |
- | |
1320 | case RADEON_TXFORMAT_DXT45: |
- | |
1321 | case RADEON_TXFORMAT_SHADOW32: |
1318 | case RADEON_TXFORMAT_SHADOW32: |
1322 | case RADEON_TXFORMAT_LDUDUV8888: |
1319 | case RADEON_TXFORMAT_LDUDUV8888: |
1323 | track->textures[i].cpp = 4; |
1320 | track->textures[i].cpp = 4; |
1324 | break; |
1321 | break; |
- | 1322 | case RADEON_TXFORMAT_DXT1: |
|
- | 1323 | track->textures[i].cpp = 1; |
|
- | 1324 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
|
- | 1325 | break; |
|
- | 1326 | case RADEON_TXFORMAT_DXT23: |
|
- | 1327 | case RADEON_TXFORMAT_DXT45: |
|
- | 1328 | track->textures[i].cpp = 1; |
|
- | 1329 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; |
|
- | 1330 | break; |
|
1325 | } |
1331 | } |
1326 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
1332 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
1327 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
1333 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
1328 | break; |
1334 | break; |
1329 | case RADEON_PP_CUBIC_FACES_0: |
1335 | case RADEON_PP_CUBIC_FACES_0: |
Line 1419... | Line 1425... | ||
1419 | case PACKET3_3D_DRAW_IMMD: |
1425 | case PACKET3_3D_DRAW_IMMD: |
1420 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
1426 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
1421 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1427 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1422 | return -EINVAL; |
1428 | return -EINVAL; |
1423 | } |
1429 | } |
- | 1430 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); |
|
1424 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1431 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1425 | track->immd_dwords = pkt->count - 1; |
1432 | track->immd_dwords = pkt->count - 1; |
1426 | r = r100_cs_track_check(p->rdev, track); |
1433 | r = r100_cs_track_check(p->rdev, track); |
1427 | if (r) |
1434 | if (r) |
1428 | return r; |
1435 | return r; |
Line 1640... | Line 1647... | ||
1640 | { |
1647 | { |
1641 | /* TODO: anythings to do here ? pipes ? */ |
1648 | /* TODO: anythings to do here ? pipes ? */ |
1642 | r100_hdp_reset(rdev); |
1649 | r100_hdp_reset(rdev); |
1643 | } |
1650 | } |
Line 1644... | Line -... | ||
1644 | - | ||
1645 | void r100_hdp_flush(struct radeon_device *rdev) |
- | |
1646 | { |
- | |
1647 | u32 tmp; |
- | |
1648 | tmp = RREG32(RADEON_HOST_PATH_CNTL); |
- | |
1649 | tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE; |
- | |
1650 | WREG32(RADEON_HOST_PATH_CNTL, tmp); |
- | |
1651 | } |
- | |
1652 | 1651 | ||
1653 | void r100_hdp_reset(struct radeon_device *rdev) |
1652 | void r100_hdp_reset(struct radeon_device *rdev) |
1654 | { |
1653 | { |
Line 1655... | Line 1654... | ||
1655 | uint32_t tmp; |
1654 | uint32_t tmp; |
Line 2846... | Line 2845... | ||
2846 | rdev->mc.vram_location = tmp << 16; |
2845 | rdev->mc.vram_location = tmp << 16; |
2847 | } |
2846 | } |
2848 | if (rdev->flags & RADEON_IS_AGP) { |
2847 | if (rdev->flags & RADEON_IS_AGP) { |
2849 | r = radeon_agp_init(rdev); |
2848 | r = radeon_agp_init(rdev); |
2850 | if (r) { |
2849 | if (r) { |
2851 | printk(KERN_WARNING "[drm] Disabling AGP\n"); |
- | |
2852 | rdev->flags &= ~RADEON_IS_AGP; |
2850 | radeon_agp_disable(rdev); |
2853 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
- | |
2854 | } else { |
2851 | } else { |
2855 | rdev->mc.gtt_location = rdev->mc.agp_base; |
2852 | rdev->mc.gtt_location = rdev->mc.agp_base; |
2856 | } |
2853 | } |
2857 | } |
2854 | } |
2858 | r = radeon_mc_setup(rdev); |
2855 | r = radeon_mc_setup(rdev); |
Line 2899... | Line 2896... | ||
2899 | return -EINVAL; |
2896 | return -EINVAL; |
2900 | /* Set asic errata */ |
2897 | /* Set asic errata */ |
2901 | r100_errata(rdev); |
2898 | r100_errata(rdev); |
2902 | /* Initialize clocks */ |
2899 | /* Initialize clocks */ |
2903 | radeon_get_clock_info(rdev->ddev); |
2900 | radeon_get_clock_info(rdev->ddev); |
- | 2901 | /* Initialize power management */ |
|
- | 2902 | radeon_pm_init(rdev); |
|
2904 | /* Get vram informations */ |
2903 | /* Get vram informations */ |
2905 | r100_vram_info(rdev); |
2904 | r100_vram_info(rdev); |
2906 | /* Initialize memory controller (also test AGP) */ |
2905 | /* Initialize memory controller (also test AGP) */ |
2907 | r = r100_mc_init(rdev); |
2906 | r = r100_mc_init(rdev); |
2908 | dbgprintf("mc vram location %x\n", rdev->mc.vram_location); |
2907 | dbgprintf("mc vram location %x\n", rdev->mc.vram_location); |