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int r100_mc_wait_for_idle(struct radeon_device *rdev);

int r100_mc_wait_for_idle(struct radeon_device *rdev);

void r100_gpu_wait_for_vsync(struct radeon_device *rdev);

void r100_gpu_wait_for_vsync(struct radeon_device *rdev);

void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);

void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);

int r100_debugfs_mc_info_init(struct radeon_device *rdev);

int r100_debugfs_mc_info_init(struct radeon_device *rdev);

#if 0

/*

/*

 * PCI GART

 * PCI GART

 */

 */

void r100_pci_gart_tlb_flush(struct radeon_device *rdev)

void r100_pci_gart_tlb_flush(struct radeon_device *rdev)

	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);

	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);

	WREG32(RADEON_AIC_LO_ADDR, 0);

	WREG32(RADEON_AIC_LO_ADDR, 0);

	WREG32(RADEON_AIC_HI_ADDR, 0);

	WREG32(RADEON_AIC_HI_ADDR, 0);

}

}

int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)

int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)

{

{

	if (i < 0 || i > rdev->gart.num_gpu_pages) {

	if (i < 0 || i > rdev->gart.num_gpu_pages) {

		return -EINVAL;

		return -EINVAL;

void r100_mc_disable_clients(struct radeon_device *rdev)

void r100_mc_disable_clients(struct radeon_device *rdev)

{

{

	uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;

	uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;

//   }

	}

	/* stop display and memory access */

	/* stop display and memory access */

	ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);

	ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);

void r100_mc_setup(struct radeon_device *rdev)

void r100_mc_setup(struct radeon_device *rdev)

{

{

	uint32_t tmp;

	uint32_t tmp;

	int r;

	int r;

	}

//   }

	/* Write VRAM size in case we are limiting it */

	/* Write VRAM size in case we are limiting it */

	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);

	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);

	tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;

	tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;

	tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);

	tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);

int r100_mc_init(struct radeon_device *rdev)

int r100_mc_init(struct radeon_device *rdev)

{

{

		DRM_ERROR("Failed to register debugfs file for RBBM !\n");

//       DRM_ERROR("Failed to register debugfs file for RBBM !\n");

	}

//   }

}

}

void r100_mc_fini(struct radeon_device *rdev)

void r100_mc_fini(struct radeon_device *rdev)

{

{

	radeon_gart_fini(rdev);

//   radeon_gart_fini(rdev);

}

/*

/*

 * Fence emission

 * Fence emission

 */

 */

	radeon_ring_write(rdev, fence->seq);

	radeon_ring_write(rdev, fence->seq);

	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));

	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));

	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);

	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);

}

}

#if 0

/*

/*

 * Writeback

 * Writeback

 */

 */

int r100_wb_init(struct radeon_device *rdev)

int r100_wb_init(struct radeon_device *rdev)

		rdev->wb.wb_obj = NULL;

		rdev->wb.wb_obj = NULL;

	}

	}

}

}

#if 0

int r100_copy_blit(struct radeon_device *rdev,

int r100_copy_blit(struct radeon_device *rdev,

		   uint64_t src_offset,

		   uint64_t src_offset,

		   uint64_t dst_offset,

		   uint64_t dst_offset,

	}

	}

	radeon_ring_unlock_commit(rdev);

	radeon_ring_unlock_commit(rdev);

	return r;

	return r;

}

}

#endif

/*

/*

 * CP

 * CP

			  RADEON_ISYNC_WAIT_IDLEGUI |

			  RADEON_ISYNC_WAIT_IDLEGUI |

			  RADEON_ISYNC_CPSCRATCH_IDLEGUI);

			  RADEON_ISYNC_CPSCRATCH_IDLEGUI);

	radeon_ring_unlock_commit(rdev);

	radeon_ring_unlock_commit(rdev);

}

}

static void r100_cp_load_microcode(struct radeon_device *rdev)

static void r100_cp_load_microcode(struct radeon_device *rdev)

{

{

    dbgprintf("%s\n",__FUNCTION__);

	int i;

	if (r100_gui_wait_for_idle(rdev)) {

	if (r100_gui_wait_for_idle(rdev)) {

		printk(KERN_WARNING "Failed to wait GUI idle while "

		printk(KERN_WARNING "Failed to wait GUI idle while "

	}

	}

	rdev->cp.ready = true;

	rdev->cp.ready = true;

	return 0;

	return 0;

}

}

#if 0

void r100_cp_fini(struct radeon_device *rdev)

void r100_cp_fini(struct radeon_device *rdev)

{

{

		printk(KERN_WARNING "Failed to wait GUI idle while "

		printk(KERN_WARNING "Failed to wait GUI idle while "

		       "programming pipes. Bad things might happen.\n");

		       "programming pipes. Bad things might happen.\n");

	}

	}

}

}

#endif

int r100_cp_reset(struct radeon_device *rdev)

int r100_cp_reset(struct radeon_device *rdev)

{

{

		}

		}

	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);

	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);

	return 0;

	return 0;

}

}

#endif

/*

/*

 * Global GPU functions

 * Global GPU functions

	    rdev->family == CHIP_RS200) {

	    rdev->family == CHIP_RS200) {

		rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;

		rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;

	}

	}

}

}

#endif

	tmp = RREG32(RADEON_RBBM_STATUS);

	tmp = RREG32(RADEON_RBBM_STATUS);

	DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);

	DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);

	return -1;

	return -1;

}

}

int r100_gpu_reset(struct radeon_device *rdev)

int r100_gpu_reset(struct radeon_device *rdev)

{

{

	uint32_t status;

	uint32_t status;

	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);

	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);

	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);

	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);

#endif

}

/*

/*

 * Indirect registers accessor

 * Indirect registers accessor

 */

 */