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Rev 3764 | Rev 5078 | ||
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Line 126... | Line 126... | ||
126 | #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) |
126 | #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) |
127 | #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) |
127 | #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) |
128 | #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) |
128 | #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) |
129 | #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) |
129 | #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) |
130 | #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) |
130 | #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) |
- | 131 | #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) |
|
131 | #define VM_CONTEXT1_CNTL 0x1414 |
132 | #define VM_CONTEXT1_CNTL 0x1414 |
132 | #define VM_CONTEXT0_CNTL2 0x1430 |
133 | #define VM_CONTEXT0_CNTL2 0x1430 |
133 | #define VM_CONTEXT1_CNTL2 0x1434 |
134 | #define VM_CONTEXT1_CNTL2 0x1434 |
134 | #define VM_INVALIDATE_REQUEST 0x1478 |
135 | #define VM_INVALIDATE_REQUEST 0x1478 |
135 | #define VM_INVALIDATE_RESPONSE 0x147c |
136 | #define VM_INVALIDATE_RESPONSE 0x147c |
- | 137 | #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC |
|
- | 138 | #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC |
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- | 139 | #define PROTECTIONS_MASK (0xf << 0) |
|
- | 140 | #define PROTECTIONS_SHIFT 0 |
|
- | 141 | /* bit 0: range |
|
- | 142 | * bit 2: pde0 |
|
- | 143 | * bit 3: valid |
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- | 144 | * bit 4: read |
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- | 145 | * bit 5: write |
|
- | 146 | */ |
|
- | 147 | #define MEMORY_CLIENT_ID_MASK (0xff << 12) |
|
- | 148 | #define MEMORY_CLIENT_ID_SHIFT 12 |
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- | 149 | #define MEMORY_CLIENT_RW_MASK (1 << 24) |
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- | 150 | #define MEMORY_CLIENT_RW_SHIFT 24 |
|
- | 151 | #define FAULT_VMID_MASK (0x7 << 25) |
|
- | 152 | #define FAULT_VMID_SHIFT 25 |
|
136 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 |
153 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 |
137 | #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c |
154 | #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c |
138 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C |
155 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C |
139 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C |
156 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C |
140 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C |
157 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C |
Line 487... | Line 504... | ||
487 | 504 | ||
488 | #define VGT_EVENT_INITIATOR 0x28a90 |
505 | #define VGT_EVENT_INITIATOR 0x28a90 |
489 | # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) |
506 | # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) |
Line -... | Line 507... | ||
- | 507 | # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) |
|
- | 508 | ||
- | 509 | /* TN SMU registers */ |
|
- | 510 | #define TN_CURRENT_GNB_TEMP 0x1F390 |
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- | 511 | ||
- | 512 | /* pm registers */ |
|
- | 513 | #define SMC_MSG 0x20c |
|
- | 514 | #define HOST_SMC_MSG(x) ((x) << 0) |
|
- | 515 | #define HOST_SMC_MSG_MASK (0xff << 0) |
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- | 516 | #define HOST_SMC_MSG_SHIFT 0 |
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- | 517 | #define HOST_SMC_RESP(x) ((x) << 8) |
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- | 518 | #define HOST_SMC_RESP_MASK (0xff << 8) |
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- | 519 | #define HOST_SMC_RESP_SHIFT 8 |
|
- | 520 | #define SMC_HOST_MSG(x) ((x) << 16) |
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- | 521 | #define SMC_HOST_MSG_MASK (0xff << 16) |
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- | 522 | #define SMC_HOST_MSG_SHIFT 16 |
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- | 523 | #define SMC_HOST_RESP(x) ((x) << 24) |
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- | 524 | #define SMC_HOST_RESP_MASK (0xff << 24) |
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- | 525 | #define SMC_HOST_RESP_SHIFT 24 |
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- | 526 | ||
- | 527 | #define CG_SPLL_FUNC_CNTL 0x600 |
|
- | 528 | #define SPLL_RESET (1 << 0) |
|
- | 529 | #define SPLL_SLEEP (1 << 1) |
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- | 530 | #define SPLL_BYPASS_EN (1 << 3) |
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- | 531 | #define SPLL_REF_DIV(x) ((x) << 4) |
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- | 532 | #define SPLL_REF_DIV_MASK (0x3f << 4) |
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- | 533 | #define SPLL_PDIV_A(x) ((x) << 20) |
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- | 534 | #define SPLL_PDIV_A_MASK (0x7f << 20) |
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- | 535 | #define SPLL_PDIV_A_SHIFT 20 |
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- | 536 | #define CG_SPLL_FUNC_CNTL_2 0x604 |
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- | 537 | #define SCLK_MUX_SEL(x) ((x) << 0) |
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- | 538 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) |
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- | 539 | #define CG_SPLL_FUNC_CNTL_3 0x608 |
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- | 540 | #define SPLL_FB_DIV(x) ((x) << 0) |
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- | 541 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) |
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- | 542 | #define SPLL_FB_DIV_SHIFT 0 |
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- | 543 | #define SPLL_DITHEN (1 << 28) |
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- | 544 | ||
- | 545 | #define MPLL_CNTL_MODE 0x61c |
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- | 546 | # define SS_SSEN (1 << 24) |
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- | 547 | # define SS_DSMODE_EN (1 << 25) |
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- | 548 | ||
- | 549 | #define MPLL_AD_FUNC_CNTL 0x624 |
|
- | 550 | #define CLKF(x) ((x) << 0) |
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- | 551 | #define CLKF_MASK (0x7f << 0) |
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- | 552 | #define CLKR(x) ((x) << 7) |
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- | 553 | #define CLKR_MASK (0x1f << 7) |
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- | 554 | #define CLKFRAC(x) ((x) << 12) |
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- | 555 | #define CLKFRAC_MASK (0x1f << 12) |
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- | 556 | #define YCLK_POST_DIV(x) ((x) << 17) |
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- | 557 | #define YCLK_POST_DIV_MASK (3 << 17) |
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- | 558 | #define IBIAS(x) ((x) << 20) |
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- | 559 | #define IBIAS_MASK (0x3ff << 20) |
|
- | 560 | #define RESET (1 << 30) |
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- | 561 | #define PDNB (1 << 31) |
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- | 562 | #define MPLL_AD_FUNC_CNTL_2 0x628 |
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- | 563 | #define BYPASS (1 << 19) |
|
- | 564 | #define BIAS_GEN_PDNB (1 << 24) |
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- | 565 | #define RESET_EN (1 << 25) |
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- | 566 | #define VCO_MODE (1 << 29) |
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- | 567 | #define MPLL_DQ_FUNC_CNTL 0x62c |
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- | 568 | #define MPLL_DQ_FUNC_CNTL_2 0x630 |
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- | 569 | ||
- | 570 | #define GENERAL_PWRMGT 0x63c |
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- | 571 | # define GLOBAL_PWRMGT_EN (1 << 0) |
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- | 572 | # define STATIC_PM_EN (1 << 1) |
|
- | 573 | # define THERMAL_PROTECTION_DIS (1 << 2) |
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- | 574 | # define THERMAL_PROTECTION_TYPE (1 << 3) |
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- | 575 | # define ENABLE_GEN2PCIE (1 << 4) |
|
- | 576 | # define ENABLE_GEN2XSP (1 << 5) |
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- | 577 | # define SW_SMIO_INDEX(x) ((x) << 6) |
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- | 578 | # define SW_SMIO_INDEX_MASK (3 << 6) |
|
- | 579 | # define SW_SMIO_INDEX_SHIFT 6 |
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- | 580 | # define LOW_VOLT_D2_ACPI (1 << 8) |
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- | 581 | # define LOW_VOLT_D3_ACPI (1 << 9) |
|
- | 582 | # define VOLT_PWRMGT_EN (1 << 10) |
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- | 583 | # define BACKBIAS_PAD_EN (1 << 18) |
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- | 584 | # define BACKBIAS_VALUE (1 << 19) |
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- | 585 | # define DYN_SPREAD_SPECTRUM_EN (1 << 23) |
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- | 586 | # define AC_DC_SW (1 << 24) |
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- | 587 | ||
- | 588 | #define SCLK_PWRMGT_CNTL 0x644 |
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- | 589 | # define SCLK_PWRMGT_OFF (1 << 0) |
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- | 590 | # define SCLK_LOW_D1 (1 << 1) |
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- | 591 | # define FIR_RESET (1 << 4) |
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- | 592 | # define FIR_FORCE_TREND_SEL (1 << 5) |
|
- | 593 | # define FIR_TREND_MODE (1 << 6) |
|
- | 594 | # define DYN_GFX_CLK_OFF_EN (1 << 7) |
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- | 595 | # define GFX_CLK_FORCE_ON (1 << 8) |
|
- | 596 | # define GFX_CLK_REQUEST_OFF (1 << 9) |
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- | 597 | # define GFX_CLK_FORCE_OFF (1 << 10) |
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- | 598 | # define GFX_CLK_OFF_ACPI_D1 (1 << 11) |
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- | 599 | # define GFX_CLK_OFF_ACPI_D2 (1 << 12) |
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- | 600 | # define GFX_CLK_OFF_ACPI_D3 (1 << 13) |
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- | 601 | # define DYN_LIGHT_SLEEP_EN (1 << 14) |
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- | 602 | #define MCLK_PWRMGT_CNTL 0x648 |
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- | 603 | # define DLL_SPEED(x) ((x) << 0) |
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- | 604 | # define DLL_SPEED_MASK (0x1f << 0) |
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- | 605 | # define MPLL_PWRMGT_OFF (1 << 5) |
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- | 606 | # define DLL_READY (1 << 6) |
|
- | 607 | # define MC_INT_CNTL (1 << 7) |
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- | 608 | # define MRDCKA0_PDNB (1 << 8) |
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- | 609 | # define MRDCKA1_PDNB (1 << 9) |
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- | 610 | # define MRDCKB0_PDNB (1 << 10) |
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- | 611 | # define MRDCKB1_PDNB (1 << 11) |
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- | 612 | # define MRDCKC0_PDNB (1 << 12) |
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- | 613 | # define MRDCKC1_PDNB (1 << 13) |
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- | 614 | # define MRDCKD0_PDNB (1 << 14) |
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- | 615 | # define MRDCKD1_PDNB (1 << 15) |
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- | 616 | # define MRDCKA0_RESET (1 << 16) |
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- | 617 | # define MRDCKA1_RESET (1 << 17) |
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- | 618 | # define MRDCKB0_RESET (1 << 18) |
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- | 619 | # define MRDCKB1_RESET (1 << 19) |
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- | 620 | # define MRDCKC0_RESET (1 << 20) |
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- | 621 | # define MRDCKC1_RESET (1 << 21) |
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- | 622 | # define MRDCKD0_RESET (1 << 22) |
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- | 623 | # define MRDCKD1_RESET (1 << 23) |
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- | 624 | # define DLL_READY_READ (1 << 24) |
|
- | 625 | # define USE_DISPLAY_GAP (1 << 25) |
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- | 626 | # define USE_DISPLAY_URGENT_NORMAL (1 << 26) |
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- | 627 | # define MPLL_TURNOFF_D2 (1 << 28) |
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- | 628 | #define DLL_CNTL 0x64c |
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- | 629 | # define MRDCKA0_BYPASS (1 << 24) |
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- | 630 | # define MRDCKA1_BYPASS (1 << 25) |
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- | 631 | # define MRDCKB0_BYPASS (1 << 26) |
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- | 632 | # define MRDCKB1_BYPASS (1 << 27) |
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- | 633 | # define MRDCKC0_BYPASS (1 << 28) |
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- | 634 | # define MRDCKC1_BYPASS (1 << 29) |
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- | 635 | # define MRDCKD0_BYPASS (1 << 30) |
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- | 636 | # define MRDCKD1_BYPASS (1 << 31) |
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- | 637 | ||
- | 638 | #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c |
|
- | 639 | # define CURRENT_STATE_INDEX_MASK (0xf << 4) |
|
- | 640 | # define CURRENT_STATE_INDEX_SHIFT 4 |
|
- | 641 | ||
- | 642 | #define CG_AT 0x6d4 |
|
- | 643 | # define CG_R(x) ((x) << 0) |
|
- | 644 | # define CG_R_MASK (0xffff << 0) |
|
- | 645 | # define CG_L(x) ((x) << 16) |
|
- | 646 | # define CG_L_MASK (0xffff << 16) |
|
- | 647 | ||
- | 648 | #define CG_BIF_REQ_AND_RSP 0x7f4 |
|
- | 649 | #define CG_CLIENT_REQ(x) ((x) << 0) |
|
- | 650 | #define CG_CLIENT_REQ_MASK (0xff << 0) |
|
- | 651 | #define CG_CLIENT_REQ_SHIFT 0 |
|
- | 652 | #define CG_CLIENT_RESP(x) ((x) << 8) |
|
- | 653 | #define CG_CLIENT_RESP_MASK (0xff << 8) |
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- | 654 | #define CG_CLIENT_RESP_SHIFT 8 |
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- | 655 | #define CLIENT_CG_REQ(x) ((x) << 16) |
|
- | 656 | #define CLIENT_CG_REQ_MASK (0xff << 16) |
|
- | 657 | #define CLIENT_CG_REQ_SHIFT 16 |
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- | 658 | #define CLIENT_CG_RESP(x) ((x) << 24) |
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- | 659 | #define CLIENT_CG_RESP_MASK (0xff << 24) |
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- | 660 | #define CLIENT_CG_RESP_SHIFT 24 |
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- | 661 | ||
- | 662 | #define CG_SPLL_SPREAD_SPECTRUM 0x790 |
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- | 663 | #define SSEN (1 << 0) |
|
- | 664 | #define CLK_S(x) ((x) << 4) |
|
- | 665 | #define CLK_S_MASK (0xfff << 4) |
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- | 666 | #define CLK_S_SHIFT 4 |
|
- | 667 | #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 |
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- | 668 | #define CLK_V(x) ((x) << 0) |
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- | 669 | #define CLK_V_MASK (0x3ffffff << 0) |
|
- | 670 | #define CLK_V_SHIFT 0 |
|
- | 671 | ||
- | 672 | #define SMC_SCRATCH0 0x81c |
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- | 673 | ||
- | 674 | #define CG_SPLL_FUNC_CNTL_4 0x850 |
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- | 675 | ||
- | 676 | #define MPLL_SS1 0x85c |
|
- | 677 | #define CLKV(x) ((x) << 0) |
|
- | 678 | #define CLKV_MASK (0x3ffffff << 0) |
|
- | 679 | #define MPLL_SS2 0x860 |
|
- | 680 | #define CLKS(x) ((x) << 0) |
|
- | 681 | #define CLKS_MASK (0xfff << 0) |
|
- | 682 | ||
- | 683 | #define CG_CAC_CTRL 0x88c |
|
- | 684 | #define TID_CNT(x) ((x) << 0) |
|
- | 685 | #define TID_CNT_MASK (0x3fff << 0) |
|
- | 686 | #define TID_UNIT(x) ((x) << 14) |
|
- | 687 | #define TID_UNIT_MASK (0xf << 14) |
|
- | 688 | ||
- | 689 | #define CG_IND_ADDR 0x8f8 |
|
- | 690 | #define CG_IND_DATA 0x8fc |
|
- | 691 | /* CGIND regs */ |
|
- | 692 | #define CG_CGTT_LOCAL_0 0x00 |
|
- | 693 | #define CG_CGTT_LOCAL_1 0x01 |
|
- | 694 | ||
- | 695 | #define MC_CG_CONFIG 0x25bc |
|
- | 696 | #define MCDW_WR_ENABLE (1 << 0) |
|
- | 697 | #define MCDX_WR_ENABLE (1 << 1) |
|
- | 698 | #define MCDY_WR_ENABLE (1 << 2) |
|
- | 699 | #define MCDZ_WR_ENABLE (1 << 3) |
|
- | 700 | #define MC_RD_ENABLE(x) ((x) << 4) |
|
- | 701 | #define MC_RD_ENABLE_MASK (3 << 4) |
|
- | 702 | #define INDEX(x) ((x) << 6) |
|
- | 703 | #define INDEX_MASK (0xfff << 6) |
|
- | 704 | #define INDEX_SHIFT 6 |
|
- | 705 | ||
- | 706 | #define MC_ARB_CAC_CNTL 0x2750 |
|
- | 707 | #define ENABLE (1 << 0) |
|
- | 708 | #define READ_WEIGHT(x) ((x) << 1) |
|
- | 709 | #define READ_WEIGHT_MASK (0x3f << 1) |
|
- | 710 | #define READ_WEIGHT_SHIFT 1 |
|
- | 711 | #define WRITE_WEIGHT(x) ((x) << 7) |
|
- | 712 | #define WRITE_WEIGHT_MASK (0x3f << 7) |
|
- | 713 | #define WRITE_WEIGHT_SHIFT 7 |
|
- | 714 | #define ALLOW_OVERFLOW (1 << 13) |
|
- | 715 | ||
- | 716 | #define MC_ARB_DRAM_TIMING 0x2774 |
|
- | 717 | #define MC_ARB_DRAM_TIMING2 0x2778 |
|
- | 718 | ||
- | 719 | #define MC_ARB_RFSH_RATE 0x27b0 |
|
- | 720 | #define POWERMODE0(x) ((x) << 0) |
|
- | 721 | #define POWERMODE0_MASK (0xff << 0) |
|
- | 722 | #define POWERMODE0_SHIFT 0 |
|
- | 723 | #define POWERMODE1(x) ((x) << 8) |
|
- | 724 | #define POWERMODE1_MASK (0xff << 8) |
|
- | 725 | #define POWERMODE1_SHIFT 8 |
|
- | 726 | #define POWERMODE2(x) ((x) << 16) |
|
- | 727 | #define POWERMODE2_MASK (0xff << 16) |
|
- | 728 | #define POWERMODE2_SHIFT 16 |
|
- | 729 | #define POWERMODE3(x) ((x) << 24) |
|
- | 730 | #define POWERMODE3_MASK (0xff << 24) |
|
- | 731 | #define POWERMODE3_SHIFT 24 |
|
- | 732 | ||
- | 733 | #define MC_ARB_CG 0x27e8 |
|
- | 734 | #define CG_ARB_REQ(x) ((x) << 0) |
|
- | 735 | #define CG_ARB_REQ_MASK (0xff << 0) |
|
- | 736 | #define CG_ARB_REQ_SHIFT 0 |
|
- | 737 | #define CG_ARB_RESP(x) ((x) << 8) |
|
- | 738 | #define CG_ARB_RESP_MASK (0xff << 8) |
|
- | 739 | #define CG_ARB_RESP_SHIFT 8 |
|
- | 740 | #define ARB_CG_REQ(x) ((x) << 16) |
|
- | 741 | #define ARB_CG_REQ_MASK (0xff << 16) |
|
- | 742 | #define ARB_CG_REQ_SHIFT 16 |
|
- | 743 | #define ARB_CG_RESP(x) ((x) << 24) |
|
- | 744 | #define ARB_CG_RESP_MASK (0xff << 24) |
|
- | 745 | #define ARB_CG_RESP_SHIFT 24 |
|
- | 746 | ||
- | 747 | #define MC_ARB_DRAM_TIMING_1 0x27f0 |
|
- | 748 | #define MC_ARB_DRAM_TIMING_2 0x27f4 |
|
- | 749 | #define MC_ARB_DRAM_TIMING_3 0x27f8 |
|
- | 750 | #define MC_ARB_DRAM_TIMING2_1 0x27fc |
|
- | 751 | #define MC_ARB_DRAM_TIMING2_2 0x2800 |
|
- | 752 | #define MC_ARB_DRAM_TIMING2_3 0x2804 |
|
- | 753 | #define MC_ARB_BURST_TIME 0x2808 |
|
- | 754 | #define STATE0(x) ((x) << 0) |
|
- | 755 | #define STATE0_MASK (0x1f << 0) |
|
- | 756 | #define STATE0_SHIFT 0 |
|
- | 757 | #define STATE1(x) ((x) << 5) |
|
- | 758 | #define STATE1_MASK (0x1f << 5) |
|
- | 759 | #define STATE1_SHIFT 5 |
|
- | 760 | #define STATE2(x) ((x) << 10) |
|
- | 761 | #define STATE2_MASK (0x1f << 10) |
|
- | 762 | #define STATE2_SHIFT 10 |
|
- | 763 | #define STATE3(x) ((x) << 15) |
|
- | 764 | #define STATE3_MASK (0x1f << 15) |
|
- | 765 | #define STATE3_SHIFT 15 |
|
- | 766 | ||
- | 767 | #define MC_CG_DATAPORT 0x2884 |
|
- | 768 | ||
- | 769 | #define MC_SEQ_RAS_TIMING 0x28a0 |
|
- | 770 | #define MC_SEQ_CAS_TIMING 0x28a4 |
|
- | 771 | #define MC_SEQ_MISC_TIMING 0x28a8 |
|
- | 772 | #define MC_SEQ_MISC_TIMING2 0x28ac |
|
- | 773 | #define MC_SEQ_PMG_TIMING 0x28b0 |
|
- | 774 | #define MC_SEQ_RD_CTL_D0 0x28b4 |
|
- | 775 | #define MC_SEQ_RD_CTL_D1 0x28b8 |
|
- | 776 | #define MC_SEQ_WR_CTL_D0 0x28bc |
|
- | 777 | #define MC_SEQ_WR_CTL_D1 0x28c0 |
|
- | 778 | ||
- | 779 | #define MC_SEQ_MISC0 0x2a00 |
|
- | 780 | #define MC_SEQ_MISC0_GDDR5_SHIFT 28 |
|
- | 781 | #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 |
|
- | 782 | #define MC_SEQ_MISC0_GDDR5_VALUE 5 |
|
- | 783 | #define MC_SEQ_MISC1 0x2a04 |
|
- | 784 | #define MC_SEQ_RESERVE_M 0x2a08 |
|
- | 785 | #define MC_PMG_CMD_EMRS 0x2a0c |
|
- | 786 | ||
- | 787 | #define MC_SEQ_MISC3 0x2a2c |
|
- | 788 | ||
- | 789 | #define MC_SEQ_MISC5 0x2a54 |
|
- | 790 | #define MC_SEQ_MISC6 0x2a58 |
|
- | 791 | ||
- | 792 | #define MC_SEQ_MISC7 0x2a64 |
|
- | 793 | ||
- | 794 | #define MC_SEQ_RAS_TIMING_LP 0x2a6c |
|
- | 795 | #define MC_SEQ_CAS_TIMING_LP 0x2a70 |
|
- | 796 | #define MC_SEQ_MISC_TIMING_LP 0x2a74 |
|
- | 797 | #define MC_SEQ_MISC_TIMING2_LP 0x2a78 |
|
- | 798 | #define MC_SEQ_WR_CTL_D0_LP 0x2a7c |
|
- | 799 | #define MC_SEQ_WR_CTL_D1_LP 0x2a80 |
|
- | 800 | #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 |
|
- | 801 | #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 |
|
- | 802 | ||
- | 803 | #define MC_PMG_CMD_MRS 0x2aac |
|
- | 804 | ||
- | 805 | #define MC_SEQ_RD_CTL_D0_LP 0x2b1c |
|
- | 806 | #define MC_SEQ_RD_CTL_D1_LP 0x2b20 |
|
- | 807 | ||
- | 808 | #define MC_PMG_CMD_MRS1 0x2b44 |
|
- | 809 | #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 |
|
- | 810 | #define MC_SEQ_PMG_TIMING_LP 0x2b4c |
|
- | 811 | ||
- | 812 | #define MC_PMG_CMD_MRS2 0x2b5c |
|
- | 813 | #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 |
|
- | 814 | ||
- | 815 | #define LB_SYNC_RESET_SEL 0x6b28 |
|
- | 816 | #define LB_SYNC_RESET_SEL_MASK (3 << 0) |
|
- | 817 | #define LB_SYNC_RESET_SEL_SHIFT 0 |
|
- | 818 | ||
- | 819 | #define DC_STUTTER_CNTL 0x6b30 |
|
- | 820 | #define DC_STUTTER_ENABLE_A (1 << 0) |
|
- | 821 | #define DC_STUTTER_ENABLE_B (1 << 1) |
|
- | 822 | ||
- | 823 | #define SQ_CAC_THRESHOLD 0x8e4c |
|
- | 824 | #define VSP(x) ((x) << 0) |
|
- | 825 | #define VSP_MASK (0xff << 0) |
|
- | 826 | #define VSP_SHIFT 0 |
|
- | 827 | #define VSP0(x) ((x) << 8) |
|
- | 828 | #define VSP0_MASK (0xff << 8) |
|
- | 829 | #define VSP0_SHIFT 8 |
|
- | 830 | #define GPR(x) ((x) << 16) |
|
- | 831 | #define GPR_MASK (0xff << 16) |
|
- | 832 | #define GPR_SHIFT 16 |
|
- | 833 | ||
- | 834 | #define SQ_POWER_THROTTLE 0x8e58 |
|
- | 835 | #define MIN_POWER(x) ((x) << 0) |
|
- | 836 | #define MIN_POWER_MASK (0x3fff << 0) |
|
- | 837 | #define MIN_POWER_SHIFT 0 |
|
- | 838 | #define MAX_POWER(x) ((x) << 16) |
|
- | 839 | #define MAX_POWER_MASK (0x3fff << 16) |
|
- | 840 | #define MAX_POWER_SHIFT 0 |
|
- | 841 | #define SQ_POWER_THROTTLE2 0x8e5c |
|
- | 842 | #define MAX_POWER_DELTA(x) ((x) << 0) |
|
- | 843 | #define MAX_POWER_DELTA_MASK (0x3fff << 0) |
|
- | 844 | #define MAX_POWER_DELTA_SHIFT 0 |
|
- | 845 | #define STI_SIZE(x) ((x) << 16) |
|
- | 846 | #define STI_SIZE_MASK (0x3ff << 16) |
|
- | 847 | #define STI_SIZE_SHIFT 16 |
|
- | 848 | #define LTI_RATIO(x) ((x) << 27) |
|
- | 849 | #define LTI_RATIO_MASK (0xf << 27) |
|
- | 850 | #define LTI_RATIO_SHIFT 27 |
|
- | 851 | ||
- | 852 | /* CG indirect registers */ |
|
- | 853 | #define CG_CAC_REGION_1_WEIGHT_0 0x83 |
|
- | 854 | #define WEIGHT_TCP_SIG0(x) ((x) << 0) |
|
- | 855 | #define WEIGHT_TCP_SIG0_MASK (0x3f << 0) |
|
- | 856 | #define WEIGHT_TCP_SIG0_SHIFT 0 |
|
- | 857 | #define WEIGHT_TCP_SIG1(x) ((x) << 6) |
|
- | 858 | #define WEIGHT_TCP_SIG1_MASK (0x3f << 6) |
|
- | 859 | #define WEIGHT_TCP_SIG1_SHIFT 6 |
|
- | 860 | #define WEIGHT_TA_SIG(x) ((x) << 12) |
|
- | 861 | #define WEIGHT_TA_SIG_MASK (0x3f << 12) |
|
- | 862 | #define WEIGHT_TA_SIG_SHIFT 12 |
|
- | 863 | #define CG_CAC_REGION_1_WEIGHT_1 0x84 |
|
- | 864 | #define WEIGHT_TCC_EN0(x) ((x) << 0) |
|
- | 865 | #define WEIGHT_TCC_EN0_MASK (0x3f << 0) |
|
- | 866 | #define WEIGHT_TCC_EN0_SHIFT 0 |
|
- | 867 | #define WEIGHT_TCC_EN1(x) ((x) << 6) |
|
- | 868 | #define WEIGHT_TCC_EN1_MASK (0x3f << 6) |
|
- | 869 | #define WEIGHT_TCC_EN1_SHIFT 6 |
|
- | 870 | #define WEIGHT_TCC_EN2(x) ((x) << 12) |
|
- | 871 | #define WEIGHT_TCC_EN2_MASK (0x3f << 12) |
|
- | 872 | #define WEIGHT_TCC_EN2_SHIFT 12 |
|
- | 873 | #define WEIGHT_TCC_EN3(x) ((x) << 18) |
|
- | 874 | #define WEIGHT_TCC_EN3_MASK (0x3f << 18) |
|
- | 875 | #define WEIGHT_TCC_EN3_SHIFT 18 |
|
- | 876 | #define CG_CAC_REGION_2_WEIGHT_0 0x85 |
|
- | 877 | #define WEIGHT_CB_EN0(x) ((x) << 0) |
|
- | 878 | #define WEIGHT_CB_EN0_MASK (0x3f << 0) |
|
- | 879 | #define WEIGHT_CB_EN0_SHIFT 0 |
|
- | 880 | #define WEIGHT_CB_EN1(x) ((x) << 6) |
|
- | 881 | #define WEIGHT_CB_EN1_MASK (0x3f << 6) |
|
- | 882 | #define WEIGHT_CB_EN1_SHIFT 6 |
|
- | 883 | #define WEIGHT_CB_EN2(x) ((x) << 12) |
|
- | 884 | #define WEIGHT_CB_EN2_MASK (0x3f << 12) |
|
- | 885 | #define WEIGHT_CB_EN2_SHIFT 12 |
|
- | 886 | #define WEIGHT_CB_EN3(x) ((x) << 18) |
|
- | 887 | #define WEIGHT_CB_EN3_MASK (0x3f << 18) |
|
- | 888 | #define WEIGHT_CB_EN3_SHIFT 18 |
|
- | 889 | #define CG_CAC_REGION_2_WEIGHT_1 0x86 |
|
- | 890 | #define WEIGHT_DB_SIG0(x) ((x) << 0) |
|
- | 891 | #define WEIGHT_DB_SIG0_MASK (0x3f << 0) |
|
- | 892 | #define WEIGHT_DB_SIG0_SHIFT 0 |
|
- | 893 | #define WEIGHT_DB_SIG1(x) ((x) << 6) |
|
- | 894 | #define WEIGHT_DB_SIG1_MASK (0x3f << 6) |
|
- | 895 | #define WEIGHT_DB_SIG1_SHIFT 6 |
|
- | 896 | #define WEIGHT_DB_SIG2(x) ((x) << 12) |
|
- | 897 | #define WEIGHT_DB_SIG2_MASK (0x3f << 12) |
|
- | 898 | #define WEIGHT_DB_SIG2_SHIFT 12 |
|
- | 899 | #define WEIGHT_DB_SIG3(x) ((x) << 18) |
|
- | 900 | #define WEIGHT_DB_SIG3_MASK (0x3f << 18) |
|
- | 901 | #define WEIGHT_DB_SIG3_SHIFT 18 |
|
- | 902 | #define CG_CAC_REGION_2_WEIGHT_2 0x87 |
|
- | 903 | #define WEIGHT_SXM_SIG0(x) ((x) << 0) |
|
- | 904 | #define WEIGHT_SXM_SIG0_MASK (0x3f << 0) |
|
- | 905 | #define WEIGHT_SXM_SIG0_SHIFT 0 |
|
- | 906 | #define WEIGHT_SXM_SIG1(x) ((x) << 6) |
|
- | 907 | #define WEIGHT_SXM_SIG1_MASK (0x3f << 6) |
|
- | 908 | #define WEIGHT_SXM_SIG1_SHIFT 6 |
|
- | 909 | #define WEIGHT_SXM_SIG2(x) ((x) << 12) |
|
- | 910 | #define WEIGHT_SXM_SIG2_MASK (0x3f << 12) |
|
- | 911 | #define WEIGHT_SXM_SIG2_SHIFT 12 |
|
- | 912 | #define WEIGHT_SXS_SIG0(x) ((x) << 18) |
|
- | 913 | #define WEIGHT_SXS_SIG0_MASK (0x3f << 18) |
|
- | 914 | #define WEIGHT_SXS_SIG0_SHIFT 18 |
|
- | 915 | #define WEIGHT_SXS_SIG1(x) ((x) << 24) |
|
- | 916 | #define WEIGHT_SXS_SIG1_MASK (0x3f << 24) |
|
- | 917 | #define WEIGHT_SXS_SIG1_SHIFT 24 |
|
- | 918 | #define CG_CAC_REGION_3_WEIGHT_0 0x88 |
|
- | 919 | #define WEIGHT_XBR_0(x) ((x) << 0) |
|
- | 920 | #define WEIGHT_XBR_0_MASK (0x3f << 0) |
|
- | 921 | #define WEIGHT_XBR_0_SHIFT 0 |
|
- | 922 | #define WEIGHT_XBR_1(x) ((x) << 6) |
|
- | 923 | #define WEIGHT_XBR_1_MASK (0x3f << 6) |
|
- | 924 | #define WEIGHT_XBR_1_SHIFT 6 |
|
- | 925 | #define WEIGHT_XBR_2(x) ((x) << 12) |
|
- | 926 | #define WEIGHT_XBR_2_MASK (0x3f << 12) |
|
- | 927 | #define WEIGHT_XBR_2_SHIFT 12 |
|
- | 928 | #define WEIGHT_SPI_SIG0(x) ((x) << 18) |
|
- | 929 | #define WEIGHT_SPI_SIG0_MASK (0x3f << 18) |
|
- | 930 | #define WEIGHT_SPI_SIG0_SHIFT 18 |
|
- | 931 | #define CG_CAC_REGION_3_WEIGHT_1 0x89 |
|
- | 932 | #define WEIGHT_SPI_SIG1(x) ((x) << 0) |
|
- | 933 | #define WEIGHT_SPI_SIG1_MASK (0x3f << 0) |
|
- | 934 | #define WEIGHT_SPI_SIG1_SHIFT 0 |
|
- | 935 | #define WEIGHT_SPI_SIG2(x) ((x) << 6) |
|
- | 936 | #define WEIGHT_SPI_SIG2_MASK (0x3f << 6) |
|
- | 937 | #define WEIGHT_SPI_SIG2_SHIFT 6 |
|
- | 938 | #define WEIGHT_SPI_SIG3(x) ((x) << 12) |
|
- | 939 | #define WEIGHT_SPI_SIG3_MASK (0x3f << 12) |
|
- | 940 | #define WEIGHT_SPI_SIG3_SHIFT 12 |
|
- | 941 | #define WEIGHT_SPI_SIG4(x) ((x) << 18) |
|
- | 942 | #define WEIGHT_SPI_SIG4_MASK (0x3f << 18) |
|
- | 943 | #define WEIGHT_SPI_SIG4_SHIFT 18 |
|
- | 944 | #define WEIGHT_SPI_SIG5(x) ((x) << 24) |
|
- | 945 | #define WEIGHT_SPI_SIG5_MASK (0x3f << 24) |
|
- | 946 | #define WEIGHT_SPI_SIG5_SHIFT 24 |
|
- | 947 | #define CG_CAC_REGION_4_WEIGHT_0 0x8a |
|
- | 948 | #define WEIGHT_LDS_SIG0(x) ((x) << 0) |
|
- | 949 | #define WEIGHT_LDS_SIG0_MASK (0x3f << 0) |
|
- | 950 | #define WEIGHT_LDS_SIG0_SHIFT 0 |
|
- | 951 | #define WEIGHT_LDS_SIG1(x) ((x) << 6) |
|
- | 952 | #define WEIGHT_LDS_SIG1_MASK (0x3f << 6) |
|
- | 953 | #define WEIGHT_LDS_SIG1_SHIFT 6 |
|
- | 954 | #define WEIGHT_SC(x) ((x) << 24) |
|
- | 955 | #define WEIGHT_SC_MASK (0x3f << 24) |
|
- | 956 | #define WEIGHT_SC_SHIFT 24 |
|
- | 957 | #define CG_CAC_REGION_4_WEIGHT_1 0x8b |
|
- | 958 | #define WEIGHT_BIF(x) ((x) << 0) |
|
- | 959 | #define WEIGHT_BIF_MASK (0x3f << 0) |
|
- | 960 | #define WEIGHT_BIF_SHIFT 0 |
|
- | 961 | #define WEIGHT_CP(x) ((x) << 6) |
|
- | 962 | #define WEIGHT_CP_MASK (0x3f << 6) |
|
- | 963 | #define WEIGHT_CP_SHIFT 6 |
|
- | 964 | #define WEIGHT_PA_SIG0(x) ((x) << 12) |
|
- | 965 | #define WEIGHT_PA_SIG0_MASK (0x3f << 12) |
|
- | 966 | #define WEIGHT_PA_SIG0_SHIFT 12 |
|
- | 967 | #define WEIGHT_PA_SIG1(x) ((x) << 18) |
|
- | 968 | #define WEIGHT_PA_SIG1_MASK (0x3f << 18) |
|
- | 969 | #define WEIGHT_PA_SIG1_SHIFT 18 |
|
- | 970 | #define WEIGHT_VGT_SIG0(x) ((x) << 24) |
|
- | 971 | #define WEIGHT_VGT_SIG0_MASK (0x3f << 24) |
|
- | 972 | #define WEIGHT_VGT_SIG0_SHIFT 24 |
|
- | 973 | #define CG_CAC_REGION_4_WEIGHT_2 0x8c |
|
- | 974 | #define WEIGHT_VGT_SIG1(x) ((x) << 0) |
|
- | 975 | #define WEIGHT_VGT_SIG1_MASK (0x3f << 0) |
|
- | 976 | #define WEIGHT_VGT_SIG1_SHIFT 0 |
|
- | 977 | #define WEIGHT_VGT_SIG2(x) ((x) << 6) |
|
- | 978 | #define WEIGHT_VGT_SIG2_MASK (0x3f << 6) |
|
- | 979 | #define WEIGHT_VGT_SIG2_SHIFT 6 |
|
- | 980 | #define WEIGHT_DC_SIG0(x) ((x) << 12) |
|
- | 981 | #define WEIGHT_DC_SIG0_MASK (0x3f << 12) |
|
- | 982 | #define WEIGHT_DC_SIG0_SHIFT 12 |
|
- | 983 | #define WEIGHT_DC_SIG1(x) ((x) << 18) |
|
- | 984 | #define WEIGHT_DC_SIG1_MASK (0x3f << 18) |
|
- | 985 | #define WEIGHT_DC_SIG1_SHIFT 18 |
|
- | 986 | #define WEIGHT_DC_SIG2(x) ((x) << 24) |
|
- | 987 | #define WEIGHT_DC_SIG2_MASK (0x3f << 24) |
|
- | 988 | #define WEIGHT_DC_SIG2_SHIFT 24 |
|
- | 989 | #define CG_CAC_REGION_4_WEIGHT_3 0x8d |
|
- | 990 | #define WEIGHT_DC_SIG3(x) ((x) << 0) |
|
- | 991 | #define WEIGHT_DC_SIG3_MASK (0x3f << 0) |
|
- | 992 | #define WEIGHT_DC_SIG3_SHIFT 0 |
|
- | 993 | #define WEIGHT_UVD_SIG0(x) ((x) << 6) |
|
- | 994 | #define WEIGHT_UVD_SIG0_MASK (0x3f << 6) |
|
- | 995 | #define WEIGHT_UVD_SIG0_SHIFT 6 |
|
- | 996 | #define WEIGHT_UVD_SIG1(x) ((x) << 12) |
|
- | 997 | #define WEIGHT_UVD_SIG1_MASK (0x3f << 12) |
|
- | 998 | #define WEIGHT_UVD_SIG1_SHIFT 12 |
|
- | 999 | #define WEIGHT_SPARE0(x) ((x) << 18) |
|
- | 1000 | #define WEIGHT_SPARE0_MASK (0x3f << 18) |
|
- | 1001 | #define WEIGHT_SPARE0_SHIFT 18 |
|
- | 1002 | #define WEIGHT_SPARE1(x) ((x) << 24) |
|
- | 1003 | #define WEIGHT_SPARE1_MASK (0x3f << 24) |
|
- | 1004 | #define WEIGHT_SPARE1_SHIFT 24 |
|
- | 1005 | #define CG_CAC_REGION_5_WEIGHT_0 0x8e |
|
- | 1006 | #define WEIGHT_SQ_VSP(x) ((x) << 0) |
|
- | 1007 | #define WEIGHT_SQ_VSP_MASK (0x3fff << 0) |
|
- | 1008 | #define WEIGHT_SQ_VSP_SHIFT 0 |
|
- | 1009 | #define WEIGHT_SQ_VSP0(x) ((x) << 14) |
|
- | 1010 | #define WEIGHT_SQ_VSP0_MASK (0x3fff << 14) |
|
- | 1011 | #define WEIGHT_SQ_VSP0_SHIFT 14 |
|
- | 1012 | #define CG_CAC_REGION_4_OVERRIDE_4 0xab |
|
- | 1013 | #define OVR_MODE_SPARE_0(x) ((x) << 16) |
|
- | 1014 | #define OVR_MODE_SPARE_0_MASK (0x1 << 16) |
|
- | 1015 | #define OVR_MODE_SPARE_0_SHIFT 16 |
|
- | 1016 | #define OVR_VAL_SPARE_0(x) ((x) << 17) |
|
- | 1017 | #define OVR_VAL_SPARE_0_MASK (0x1 << 17) |
|
- | 1018 | #define OVR_VAL_SPARE_0_SHIFT 17 |
|
- | 1019 | #define OVR_MODE_SPARE_1(x) ((x) << 18) |
|
- | 1020 | #define OVR_MODE_SPARE_1_MASK (0x3f << 18) |
|
- | 1021 | #define OVR_MODE_SPARE_1_SHIFT 18 |
|
- | 1022 | #define OVR_VAL_SPARE_1(x) ((x) << 19) |
|
- | 1023 | #define OVR_VAL_SPARE_1_MASK (0x3f << 19) |
|
- | 1024 | #define OVR_VAL_SPARE_1_SHIFT 19 |
|
- | 1025 | #define CG_CAC_REGION_5_WEIGHT_1 0xb7 |
|
- | 1026 | #define WEIGHT_SQ_GPR(x) ((x) << 0) |
|
- | 1027 | #define WEIGHT_SQ_GPR_MASK (0x3fff << 0) |
|
- | 1028 | #define WEIGHT_SQ_GPR_SHIFT 0 |
|
- | 1029 | #define WEIGHT_SQ_LDS(x) ((x) << 14) |
|
- | 1030 | #define WEIGHT_SQ_LDS_MASK (0x3fff << 14) |
|
- | 1031 | #define WEIGHT_SQ_LDS_SHIFT 14 |
|
- | 1032 | ||
- | 1033 | /* PCIE link stuff */ |
|
- | 1034 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
|
- | 1035 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ |
|
- | 1036 | # define LC_LINK_WIDTH_SHIFT 0 |
|
- | 1037 | # define LC_LINK_WIDTH_MASK 0x7 |
|
- | 1038 | # define LC_LINK_WIDTH_X0 0 |
|
- | 1039 | # define LC_LINK_WIDTH_X1 1 |
|
- | 1040 | # define LC_LINK_WIDTH_X2 2 |
|
- | 1041 | # define LC_LINK_WIDTH_X4 3 |
|
- | 1042 | # define LC_LINK_WIDTH_X8 4 |
|
- | 1043 | # define LC_LINK_WIDTH_X16 6 |
|
- | 1044 | # define LC_LINK_WIDTH_RD_SHIFT 4 |
|
- | 1045 | # define LC_LINK_WIDTH_RD_MASK 0x70 |
|
- | 1046 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) |
|
- | 1047 | # define LC_RECONFIG_NOW (1 << 8) |
|
- | 1048 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) |
|
- | 1049 | # define LC_RENEGOTIATE_EN (1 << 10) |
|
- | 1050 | # define LC_SHORT_RECONFIG_EN (1 << 11) |
|
- | 1051 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) |
|
- | 1052 | # define LC_UPCONFIGURE_DIS (1 << 13) |
|
- | 1053 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
|
- | 1054 | # define LC_GEN2_EN_STRAP (1 << 0) |
|
- | 1055 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) |
|
- | 1056 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) |
|
- | 1057 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) |
|
- | 1058 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) |
|
- | 1059 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 |
|
- | 1060 | # define LC_CURRENT_DATA_RATE (1 << 11) |
|
- | 1061 | # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) |
|
- | 1062 | # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) |
|
- | 1063 | # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 |
|
- | 1064 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
|
- | 1065 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) |
|
- | 1066 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) |
|
- | 1067 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) |
|
- | 1068 | #define MM_CFGREGS_CNTL 0x544c |
|
- | 1069 | # define MM_WR_TO_CFG_EN (1 << 3) |
|
- | 1070 | #define LINK_CNTL2 0x88 /* F0 */ |
|
- | 1071 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
|
490 | # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) |
1072 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
491 | 1073 | ||
492 | /* |
1074 | /* |
493 | * UVD |
1075 | * UVD |
494 | */ |
1076 | */ |
Line 571... | Line 1153... | ||
571 | # define PACKET3_TC_ACTION_ENA (1 << 23) |
1153 | # define PACKET3_TC_ACTION_ENA (1 << 23) |
572 | # define PACKET3_CB_ACTION_ENA (1 << 25) |
1154 | # define PACKET3_CB_ACTION_ENA (1 << 25) |
573 | # define PACKET3_DB_ACTION_ENA (1 << 26) |
1155 | # define PACKET3_DB_ACTION_ENA (1 << 26) |
574 | # define PACKET3_SH_ACTION_ENA (1 << 27) |
1156 | # define PACKET3_SH_ACTION_ENA (1 << 27) |
575 | # define PACKET3_SX_ACTION_ENA (1 << 28) |
1157 | # define PACKET3_SX_ACTION_ENA (1 << 28) |
- | 1158 | # define PACKET3_ENGINE_ME (1 << 31) |
|
576 | #define PACKET3_ME_INITIALIZE 0x44 |
1159 | #define PACKET3_ME_INITIALIZE 0x44 |
577 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) |
1160 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) |
578 | #define PACKET3_COND_WRITE 0x45 |
1161 | #define PACKET3_COND_WRITE 0x45 |
579 | #define PACKET3_EVENT_WRITE 0x46 |
1162 | #define PACKET3_EVENT_WRITE 0x46 |
580 | #define EVENT_TYPE(x) ((x) << 0) |
1163 | #define EVENT_TYPE(x) ((x) << 0) |