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Rev 3192 Rev 3764
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#define CAYMAN_GB_ADDR_CONFIG_GOLDEN       0x02011003
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#define CAYMAN_GB_ADDR_CONFIG_GOLDEN       0x02011003
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#define ARUBA_GB_ADDR_CONFIG_GOLDEN        0x12010001
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#define ARUBA_GB_ADDR_CONFIG_GOLDEN        0x12010001
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#define DMIF_ADDR_CONFIG  				0xBD4
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/* DCE6 only */
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#define DMIF_ADDR_CALC  				0xC00
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#define DMIF_ADDR_CONFIG  				0xBD4
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#define	SRBM_GFX_CNTL				        0x0E44
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#define	SRBM_GFX_CNTL				        0x0E44
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#define		RINGID(x)					(((x) & 0x3) << 0)
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#define		RINGID(x)					(((x) & 0x3) << 0)
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#define		VMID(x)						(((x) & 0x7) << 0)
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#define	SRBM_STATUS				        0x0E50
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#define		RLC_RQ_PENDING 				(1 << 3)
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#define		GRBM_RQ_PENDING 			(1 << 5)
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#define		VMC_BUSY 				(1 << 8)
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#define		MCB_BUSY 				(1 << 9)
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#define		MCB_NON_DISPLAY_BUSY 			(1 << 10)
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#define		MCC_BUSY 				(1 << 11)
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#define		MCD_BUSY 				(1 << 12)
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#define		SEM_BUSY 				(1 << 14)
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#define		VMID(x)						(((x) & 0x7) << 0)
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#define		RLC_BUSY 				(1 << 15)
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#define	SRBM_STATUS				        0x0E50
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#define		IH_BUSY 				(1 << 17)
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#define	SRBM_SOFT_RESET				        0x0E60
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#define	SRBM_SOFT_RESET				        0x0E60
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#define		SOFT_RESET_DMA				(1 << 20)
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#define		SOFT_RESET_DMA				(1 << 20)
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#define		SOFT_RESET_TST				(1 << 21)
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#define		SOFT_RESET_TST				(1 << 21)
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#define		SOFT_RESET_REGBB		       	(1 << 22)
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#define		SOFT_RESET_REGBB			(1 << 22)
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#define		SOFT_RESET_ORB				(1 << 23)
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#define		SOFT_RESET_ORB				(1 << 23)
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#define	SRBM_STATUS2				        0x0EC4
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#define		DMA_BUSY 				(1 << 5)
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#define		DMA1_BUSY 				(1 << 6)
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#define VM_CONTEXT0_REQUEST_RESPONSE			0x1470
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#define VM_CONTEXT0_REQUEST_RESPONSE			0x1470
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#define		REQUEST_TYPE(x)					(((x) & 0xf) << 0)
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#define		REQUEST_TYPE(x)					(((x) & 0xf) << 0)
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#define		RESPONSE_TYPE_MASK				0x000000F0
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#define		RESPONSE_TYPE_MASK				0x000000F0
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#define		RESPONSE_TYPE_SHIFT				4
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#define		RESPONSE_TYPE_SHIFT				4
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#define VGT_EVENT_INITIATOR                             0x28a90
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#define VGT_EVENT_INITIATOR                             0x28a90
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#       define CACHE_FLUSH_AND_INV_EVENT_TS                     (0x14 << 0)
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#       define CACHE_FLUSH_AND_INV_EVENT_TS                     (0x14 << 0)
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#       define CACHE_FLUSH_AND_INV_EVENT                        (0x16 << 0)
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#       define CACHE_FLUSH_AND_INV_EVENT                        (0x16 << 0)
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/*
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 * UVD
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 */
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#define UVD_SEMA_ADDR_LOW				0xEF00
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#define UVD_SEMA_ADDR_HIGH				0xEF04
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#define UVD_SEMA_CMD					0xEF08
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#define UVD_UDEC_ADDR_CONFIG				0xEF4C
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#define UVD_UDEC_DB_ADDR_CONFIG				0xEF50
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#define UVD_UDEC_DBW_ADDR_CONFIG			0xEF54
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#define UVD_RBC_RB_RPTR					0xF690
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#define UVD_RBC_RB_WPTR					0xF694
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/*
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/*
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 * PM4
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 * PM4
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 */
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#define	PACKET_TYPE0	0
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#define	PACKET_TYPE1	1
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#define	PACKET_TYPE2	2
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#define	PACKET_TYPE3	3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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 */
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#define PACKET0(reg, n)	((PACKET_TYPE0 << 30) |				\
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#define PACKET0(reg, n)	((RADEON_PACKET_TYPE0 << 30) |			\
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			 (((reg) >> 2) & 0xFFFF) |			\
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			 (((reg) >> 2) & 0xFFFF) |			\
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			 ((n) & 0x3FFF) << 16)
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			 ((n) & 0x3FFF) << 16)
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#define CP_PACKET2			0x80000000
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#define CP_PACKET2			0x80000000
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#define		PACKET2_PAD_SHIFT		0
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#define		PACKET2_PAD_SHIFT		0
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#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
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#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
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#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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#define PACKET3(op, n)	((PACKET_TYPE3 << 30) |				\
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#define PACKET3(op, n)	((RADEON_PACKET_TYPE3 << 30) |			\
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			 (((op) & 0xFF) << 8) |				\
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			 (((op) & 0xFF) << 8) |				\
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#define DMA_IB_PACKET(cmd, vmid, n)	((((cmd) & 0xF) << 28) |	\
 683 
#define DMA_IB_PACKET(cmd, vmid, n)	((((cmd) & 0xF) << 28) |	\
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					 (((vmid) & 0xF) << 20) |	\
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					 (((vmid) & 0xF) << 20) |	\
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					 (((n) & 0xFFFFF) << 0))
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 686 
 
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 687 
#define DMA_PTE_PDE_PACKET(n)		((2 << 28) |			\
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					 (1 << 26) |			\
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					 (1 << 21) |			\
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					 (((n) & 0xFFFFF) << 0))
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					 (((n) & 0xFFFFF) << 0))
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 691 
 
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/* async DMA Packet types */
 692 
/* async DMA Packet types */
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#define	DMA_PACKET_WRITE				  0x2
 693 
#define	DMA_PACKET_WRITE				  0x2
668 
#define	DMA_PACKET_COPY					  0x3
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#define	DMA_PACKET_COPY					  0x3