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Rev 5271 | Rev 6104 | ||
---|---|---|---|
Line 3860... | Line 3860... | ||
3860 | struct radeon_ps *new_ps = &eg_pi->requested_rps; |
3860 | struct radeon_ps *new_ps = &eg_pi->requested_rps; |
Line 3861... | Line 3861... | ||
3861 | 3861 | ||
3862 | ni_update_current_ps(rdev, new_ps); |
3862 | ni_update_current_ps(rdev, new_ps); |
Line -... | Line 3863... | ||
- | 3863 | } |
|
3863 | } |
3864 | |
3864 | 3865 | #if 0 |
|
3865 | void ni_dpm_reset_asic(struct radeon_device *rdev) |
3866 | void ni_dpm_reset_asic(struct radeon_device *rdev) |
3866 | { |
3867 | { |
3867 | ni_restrict_performance_levels_before_switch(rdev); |
3868 | ni_restrict_performance_levels_before_switch(rdev); |
- | 3869 | rv770_set_boot_state(rdev); |
|
Line 3868... | Line 3870... | ||
3868 | rv770_set_boot_state(rdev); |
3870 | } |
3869 | } |
3871 | #endif |
3870 | 3872 | ||
3871 | union power_info { |
3873 | union power_info { |
Line 4315... | Line 4317... | ||
4315 | seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u\n", |
4317 | seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u\n", |
4316 | current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci); |
4318 | current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci); |
4317 | } |
4319 | } |
4318 | } |
4320 | } |
Line -... | Line 4321... | ||
- | 4321 | ||
- | 4322 | u32 ni_dpm_get_current_sclk(struct radeon_device *rdev) |
|
- | 4323 | { |
|
- | 4324 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
|
- | 4325 | struct radeon_ps *rps = &eg_pi->current_rps; |
|
- | 4326 | struct ni_ps *ps = ni_get_ps(rps); |
|
- | 4327 | struct rv7xx_pl *pl; |
|
- | 4328 | u32 current_index = |
|
- | 4329 | (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> |
|
- | 4330 | CURRENT_STATE_INDEX_SHIFT; |
|
- | 4331 | ||
- | 4332 | if (current_index >= ps->performance_level_count) { |
|
- | 4333 | return 0; |
|
- | 4334 | } else { |
|
- | 4335 | pl = &ps->performance_levels[current_index]; |
|
- | 4336 | return pl->sclk; |
|
- | 4337 | } |
|
- | 4338 | } |
|
- | 4339 | ||
- | 4340 | u32 ni_dpm_get_current_mclk(struct radeon_device *rdev) |
|
- | 4341 | { |
|
- | 4342 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
|
- | 4343 | struct radeon_ps *rps = &eg_pi->current_rps; |
|
- | 4344 | struct ni_ps *ps = ni_get_ps(rps); |
|
- | 4345 | struct rv7xx_pl *pl; |
|
- | 4346 | u32 current_index = |
|
- | 4347 | (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> |
|
- | 4348 | CURRENT_STATE_INDEX_SHIFT; |
|
- | 4349 | ||
- | 4350 | if (current_index >= ps->performance_level_count) { |
|
- | 4351 | return 0; |
|
- | 4352 | } else { |
|
- | 4353 | pl = &ps->performance_levels[current_index]; |
|
- | 4354 | return pl->mclk; |
|
- | 4355 | } |
|
- | 4356 | } |
|
4319 | 4357 | ||
4320 | u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low) |
4358 | u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low) |
4321 | { |
4359 | { |
4322 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
4360 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |