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| Rev 3192 | Rev 3764 | ||
|---|---|---|---|
| Line 32... | Line 32... | ||
| 32 | #include "nid.h" |
32 | #include "nid.h" |
| 33 | #include "atom.h" |
33 | #include "atom.h" |
| 34 | #include "ni_reg.h" |
34 | #include "ni_reg.h" |
| 35 | #include "cayman_blit_shaders.h" |
35 | #include "cayman_blit_shaders.h" |
| Line -... | Line 36... | ||
| - | 36 | ||
| - | 37 | extern bool evergreen_is_display_hung(struct radeon_device *rdev); |
|
| 36 | 38 | extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev); |
|
| 37 | extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); |
39 | extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); |
| 38 | extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); |
40 | extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); |
| 39 | extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
41 | extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
| 40 | extern void evergreen_mc_program(struct radeon_device *rdev); |
42 | extern void evergreen_mc_program(struct radeon_device *rdev); |
| Line 74... | Line 76... | ||
| 74 | MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); |
76 | MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); |
| 75 | MODULE_FIRMWARE("radeon/ARUBA_pfp.bin"); |
77 | MODULE_FIRMWARE("radeon/ARUBA_pfp.bin"); |
| 76 | MODULE_FIRMWARE("radeon/ARUBA_me.bin"); |
78 | MODULE_FIRMWARE("radeon/ARUBA_me.bin"); |
| 77 | MODULE_FIRMWARE("radeon/ARUBA_rlc.bin"); |
79 | MODULE_FIRMWARE("radeon/ARUBA_rlc.bin"); |
| Line -... | Line 80... | ||
| - | 80 | ||
| - | 81 | ||
| - | 82 | static const u32 cayman_golden_registers2[] = |
|
| - | 83 | { |
|
| - | 84 | 0x3e5c, 0xffffffff, 0x00000000, |
|
| - | 85 | 0x3e48, 0xffffffff, 0x00000000, |
|
| - | 86 | 0x3e4c, 0xffffffff, 0x00000000, |
|
| - | 87 | 0x3e64, 0xffffffff, 0x00000000, |
|
| - | 88 | 0x3e50, 0xffffffff, 0x00000000, |
|
| - | 89 | 0x3e60, 0xffffffff, 0x00000000 |
|
| - | 90 | }; |
|
| - | 91 | ||
| - | 92 | static const u32 cayman_golden_registers[] = |
|
| - | 93 | { |
|
| - | 94 | 0x5eb4, 0xffffffff, 0x00000002, |
|
| - | 95 | 0x5e78, 0x8f311ff1, 0x001000f0, |
|
| - | 96 | 0x3f90, 0xffff0000, 0xff000000, |
|
| - | 97 | 0x9148, 0xffff0000, 0xff000000, |
|
| - | 98 | 0x3f94, 0xffff0000, 0xff000000, |
|
| - | 99 | 0x914c, 0xffff0000, 0xff000000, |
|
| - | 100 | 0xc78, 0x00000080, 0x00000080, |
|
| - | 101 | 0xbd4, 0x70073777, 0x00011003, |
|
| - | 102 | 0xd02c, 0xbfffff1f, 0x08421000, |
|
| - | 103 | 0xd0b8, 0x73773777, 0x02011003, |
|
| - | 104 | 0x5bc0, 0x00200000, 0x50100000, |
|
| - | 105 | 0x98f8, 0x33773777, 0x02011003, |
|
| - | 106 | 0x98fc, 0xffffffff, 0x76541032, |
|
| - | 107 | 0x7030, 0x31000311, 0x00000011, |
|
| - | 108 | 0x2f48, 0x33773777, 0x42010001, |
|
| - | 109 | 0x6b28, 0x00000010, 0x00000012, |
|
| - | 110 | 0x7728, 0x00000010, 0x00000012, |
|
| - | 111 | 0x10328, 0x00000010, 0x00000012, |
|
| - | 112 | 0x10f28, 0x00000010, 0x00000012, |
|
| - | 113 | 0x11b28, 0x00000010, 0x00000012, |
|
| - | 114 | 0x12728, 0x00000010, 0x00000012, |
|
| - | 115 | 0x240c, 0x000007ff, 0x00000000, |
|
| - | 116 | 0x8a14, 0xf000001f, 0x00000007, |
|
| - | 117 | 0x8b24, 0x3fff3fff, 0x00ff0fff, |
|
| - | 118 | 0x8b10, 0x0000ff0f, 0x00000000, |
|
| - | 119 | 0x28a4c, 0x07ffffff, 0x06000000, |
|
| - | 120 | 0x10c, 0x00000001, 0x00010003, |
|
| - | 121 | 0xa02c, 0xffffffff, 0x0000009b, |
|
| - | 122 | 0x913c, 0x0000010f, 0x01000100, |
|
| - | 123 | 0x8c04, 0xf8ff00ff, 0x40600060, |
|
| - | 124 | 0x28350, 0x00000f01, 0x00000000, |
|
| - | 125 | 0x9508, 0x3700001f, 0x00000002, |
|
| - | 126 | 0x960c, 0xffffffff, 0x54763210, |
|
| - | 127 | 0x88c4, 0x001f3ae3, 0x00000082, |
|
| - | 128 | 0x88d0, 0xffffffff, 0x0f40df40, |
|
| - | 129 | 0x88d4, 0x0000001f, 0x00000010, |
|
| - | 130 | 0x8974, 0xffffffff, 0x00000000 |
|
| - | 131 | }; |
|
| - | 132 | ||
| - | 133 | static const u32 dvst_golden_registers2[] = |
|
| - | 134 | { |
|
| - | 135 | 0x8f8, 0xffffffff, 0, |
|
| - | 136 | 0x8fc, 0x00380000, 0, |
|
| - | 137 | 0x8f8, 0xffffffff, 1, |
|
| - | 138 | 0x8fc, 0x0e000000, 0 |
|
| - | 139 | }; |
|
| - | 140 | ||
| - | 141 | static const u32 dvst_golden_registers[] = |
|
| - | 142 | { |
|
| - | 143 | 0x690, 0x3fff3fff, 0x20c00033, |
|
| - | 144 | 0x918c, 0x0fff0fff, 0x00010006, |
|
| - | 145 | 0x91a8, 0x0fff0fff, 0x00010006, |
|
| - | 146 | 0x9150, 0xffffdfff, 0x6e944040, |
|
| - | 147 | 0x917c, 0x0fff0fff, 0x00030002, |
|
| - | 148 | 0x9198, 0x0fff0fff, 0x00030002, |
|
| - | 149 | 0x915c, 0x0fff0fff, 0x00010000, |
|
| - | 150 | 0x3f90, 0xffff0001, 0xff000000, |
|
| - | 151 | 0x9178, 0x0fff0fff, 0x00070000, |
|
| - | 152 | 0x9194, 0x0fff0fff, 0x00070000, |
|
| - | 153 | 0x9148, 0xffff0001, 0xff000000, |
|
| - | 154 | 0x9190, 0x0fff0fff, 0x00090008, |
|
| - | 155 | 0x91ac, 0x0fff0fff, 0x00090008, |
|
| - | 156 | 0x3f94, 0xffff0000, 0xff000000, |
|
| - | 157 | 0x914c, 0xffff0000, 0xff000000, |
|
| - | 158 | 0x929c, 0x00000fff, 0x00000001, |
|
| - | 159 | 0x55e4, 0xff607fff, 0xfc000100, |
|
| - | 160 | 0x8a18, 0xff000fff, 0x00000100, |
|
| - | 161 | 0x8b28, 0xff000fff, 0x00000100, |
|
| - | 162 | 0x9144, 0xfffc0fff, 0x00000100, |
|
| - | 163 | 0x6ed8, 0x00010101, 0x00010000, |
|
| - | 164 | 0x9830, 0xffffffff, 0x00000000, |
|
| - | 165 | 0x9834, 0xf00fffff, 0x00000400, |
|
| - | 166 | 0x9838, 0xfffffffe, 0x00000000, |
|
| - | 167 | 0xd0c0, 0xff000fff, 0x00000100, |
|
| - | 168 | 0xd02c, 0xbfffff1f, 0x08421000, |
|
| - | 169 | 0xd0b8, 0x73773777, 0x12010001, |
|
| - | 170 | 0x5bb0, 0x000000f0, 0x00000070, |
|
| - | 171 | 0x98f8, 0x73773777, 0x12010001, |
|
| - | 172 | 0x98fc, 0xffffffff, 0x00000010, |
|
| - | 173 | 0x9b7c, 0x00ff0000, 0x00fc0000, |
|
| - | 174 | 0x8030, 0x00001f0f, 0x0000100a, |
|
| - | 175 | 0x2f48, 0x73773777, 0x12010001, |
|
| - | 176 | 0x2408, 0x00030000, 0x000c007f, |
|
| - | 177 | 0x8a14, 0xf000003f, 0x00000007, |
|
| - | 178 | 0x8b24, 0x3fff3fff, 0x00ff0fff, |
|
| - | 179 | 0x8b10, 0x0000ff0f, 0x00000000, |
|
| - | 180 | 0x28a4c, 0x07ffffff, 0x06000000, |
|
| - | 181 | 0x4d8, 0x00000fff, 0x00000100, |
|
| - | 182 | 0xa008, 0xffffffff, 0x00010000, |
|
| - | 183 | 0x913c, 0xffff03ff, 0x01000100, |
|
| - | 184 | 0x8c00, 0x000000ff, 0x00000003, |
|
| - | 185 | 0x8c04, 0xf8ff00ff, 0x40600060, |
|
| - | 186 | 0x8cf0, 0x1fff1fff, 0x08e00410, |
|
| - | 187 | 0x28350, 0x00000f01, 0x00000000, |
|
| - | 188 | 0x9508, 0xf700071f, 0x00000002, |
|
| - | 189 | 0x960c, 0xffffffff, 0x54763210, |
|
| - | 190 | 0x20ef8, 0x01ff01ff, 0x00000002, |
|
| - | 191 | 0x20e98, 0xfffffbff, 0x00200000, |
|
| - | 192 | 0x2015c, 0xffffffff, 0x00000f40, |
|
| - | 193 | 0x88c4, 0x001f3ae3, 0x00000082, |
|
| - | 194 | 0x8978, 0x3fffffff, 0x04050140, |
|
| - | 195 | 0x88d4, 0x0000001f, 0x00000010, |
|
| - | 196 | 0x8974, 0xffffffff, 0x00000000 |
|
| - | 197 | }; |
|
| - | 198 | ||
| - | 199 | static const u32 scrapper_golden_registers[] = |
|
| - | 200 | { |
|
| - | 201 | 0x690, 0x3fff3fff, 0x20c00033, |
|
| - | 202 | 0x918c, 0x0fff0fff, 0x00010006, |
|
| - | 203 | 0x918c, 0x0fff0fff, 0x00010006, |
|
| - | 204 | 0x91a8, 0x0fff0fff, 0x00010006, |
|
| - | 205 | 0x91a8, 0x0fff0fff, 0x00010006, |
|
| - | 206 | 0x9150, 0xffffdfff, 0x6e944040, |
|
| - | 207 | 0x9150, 0xffffdfff, 0x6e944040, |
|
| - | 208 | 0x917c, 0x0fff0fff, 0x00030002, |
|
| - | 209 | 0x917c, 0x0fff0fff, 0x00030002, |
|
| - | 210 | 0x9198, 0x0fff0fff, 0x00030002, |
|
| - | 211 | 0x9198, 0x0fff0fff, 0x00030002, |
|
| - | 212 | 0x915c, 0x0fff0fff, 0x00010000, |
|
| - | 213 | 0x915c, 0x0fff0fff, 0x00010000, |
|
| - | 214 | 0x3f90, 0xffff0001, 0xff000000, |
|
| - | 215 | 0x3f90, 0xffff0001, 0xff000000, |
|
| - | 216 | 0x9178, 0x0fff0fff, 0x00070000, |
|
| - | 217 | 0x9178, 0x0fff0fff, 0x00070000, |
|
| - | 218 | 0x9194, 0x0fff0fff, 0x00070000, |
|
| - | 219 | 0x9194, 0x0fff0fff, 0x00070000, |
|
| - | 220 | 0x9148, 0xffff0001, 0xff000000, |
|
| - | 221 | 0x9148, 0xffff0001, 0xff000000, |
|
| - | 222 | 0x9190, 0x0fff0fff, 0x00090008, |
|
| - | 223 | 0x9190, 0x0fff0fff, 0x00090008, |
|
| - | 224 | 0x91ac, 0x0fff0fff, 0x00090008, |
|
| - | 225 | 0x91ac, 0x0fff0fff, 0x00090008, |
|
| - | 226 | 0x3f94, 0xffff0000, 0xff000000, |
|
| - | 227 | 0x3f94, 0xffff0000, 0xff000000, |
|
| - | 228 | 0x914c, 0xffff0000, 0xff000000, |
|
| - | 229 | 0x914c, 0xffff0000, 0xff000000, |
|
| - | 230 | 0x929c, 0x00000fff, 0x00000001, |
|
| - | 231 | 0x929c, 0x00000fff, 0x00000001, |
|
| - | 232 | 0x55e4, 0xff607fff, 0xfc000100, |
|
| - | 233 | 0x8a18, 0xff000fff, 0x00000100, |
|
| - | 234 | 0x8a18, 0xff000fff, 0x00000100, |
|
| - | 235 | 0x8b28, 0xff000fff, 0x00000100, |
|
| - | 236 | 0x8b28, 0xff000fff, 0x00000100, |
|
| - | 237 | 0x9144, 0xfffc0fff, 0x00000100, |
|
| - | 238 | 0x9144, 0xfffc0fff, 0x00000100, |
|
| - | 239 | 0x6ed8, 0x00010101, 0x00010000, |
|
| - | 240 | 0x9830, 0xffffffff, 0x00000000, |
|
| - | 241 | 0x9830, 0xffffffff, 0x00000000, |
|
| - | 242 | 0x9834, 0xf00fffff, 0x00000400, |
|
| - | 243 | 0x9834, 0xf00fffff, 0x00000400, |
|
| - | 244 | 0x9838, 0xfffffffe, 0x00000000, |
|
| - | 245 | 0x9838, 0xfffffffe, 0x00000000, |
|
| - | 246 | 0xd0c0, 0xff000fff, 0x00000100, |
|
| - | 247 | 0xd02c, 0xbfffff1f, 0x08421000, |
|
| - | 248 | 0xd02c, 0xbfffff1f, 0x08421000, |
|
| - | 249 | 0xd0b8, 0x73773777, 0x12010001, |
|
| - | 250 | 0xd0b8, 0x73773777, 0x12010001, |
|
| - | 251 | 0x5bb0, 0x000000f0, 0x00000070, |
|
| - | 252 | 0x98f8, 0x73773777, 0x12010001, |
|
| - | 253 | 0x98f8, 0x73773777, 0x12010001, |
|
| - | 254 | 0x98fc, 0xffffffff, 0x00000010, |
|
| - | 255 | 0x98fc, 0xffffffff, 0x00000010, |
|
| - | 256 | 0x9b7c, 0x00ff0000, 0x00fc0000, |
|
| - | 257 | 0x9b7c, 0x00ff0000, 0x00fc0000, |
|
| - | 258 | 0x8030, 0x00001f0f, 0x0000100a, |
|
| - | 259 | 0x8030, 0x00001f0f, 0x0000100a, |
|
| - | 260 | 0x2f48, 0x73773777, 0x12010001, |
|
| - | 261 | 0x2f48, 0x73773777, 0x12010001, |
|
| - | 262 | 0x2408, 0x00030000, 0x000c007f, |
|
| - | 263 | 0x8a14, 0xf000003f, 0x00000007, |
|
| - | 264 | 0x8a14, 0xf000003f, 0x00000007, |
|
| - | 265 | 0x8b24, 0x3fff3fff, 0x00ff0fff, |
|
| - | 266 | 0x8b24, 0x3fff3fff, 0x00ff0fff, |
|
| - | 267 | 0x8b10, 0x0000ff0f, 0x00000000, |
|
| - | 268 | 0x8b10, 0x0000ff0f, 0x00000000, |
|
| - | 269 | 0x28a4c, 0x07ffffff, 0x06000000, |
|
| - | 270 | 0x28a4c, 0x07ffffff, 0x06000000, |
|
| - | 271 | 0x4d8, 0x00000fff, 0x00000100, |
|
| - | 272 | 0x4d8, 0x00000fff, 0x00000100, |
|
| - | 273 | 0xa008, 0xffffffff, 0x00010000, |
|
| - | 274 | 0xa008, 0xffffffff, 0x00010000, |
|
| - | 275 | 0x913c, 0xffff03ff, 0x01000100, |
|
| - | 276 | 0x913c, 0xffff03ff, 0x01000100, |
|
| - | 277 | 0x90e8, 0x001fffff, 0x010400c0, |
|
| - | 278 | 0x8c00, 0x000000ff, 0x00000003, |
|
| - | 279 | 0x8c00, 0x000000ff, 0x00000003, |
|
| - | 280 | 0x8c04, 0xf8ff00ff, 0x40600060, |
|
| - | 281 | 0x8c04, 0xf8ff00ff, 0x40600060, |
|
| - | 282 | 0x8c30, 0x0000000f, 0x00040005, |
|
| - | 283 | 0x8cf0, 0x1fff1fff, 0x08e00410, |
|
| - | 284 | 0x8cf0, 0x1fff1fff, 0x08e00410, |
|
| - | 285 | 0x900c, 0x00ffffff, 0x0017071f, |
|
| - | 286 | 0x28350, 0x00000f01, 0x00000000, |
|
| - | 287 | 0x28350, 0x00000f01, 0x00000000, |
|
| - | 288 | 0x9508, 0xf700071f, 0x00000002, |
|
| - | 289 | 0x9508, 0xf700071f, 0x00000002, |
|
| - | 290 | 0x9688, 0x00300000, 0x0017000f, |
|
| - | 291 | 0x960c, 0xffffffff, 0x54763210, |
|
| - | 292 | 0x960c, 0xffffffff, 0x54763210, |
|
| - | 293 | 0x20ef8, 0x01ff01ff, 0x00000002, |
|
| - | 294 | 0x20e98, 0xfffffbff, 0x00200000, |
|
| - | 295 | 0x2015c, 0xffffffff, 0x00000f40, |
|
| - | 296 | 0x88c4, 0x001f3ae3, 0x00000082, |
|
| - | 297 | 0x88c4, 0x001f3ae3, 0x00000082, |
|
| - | 298 | 0x8978, 0x3fffffff, 0x04050140, |
|
| - | 299 | 0x8978, 0x3fffffff, 0x04050140, |
|
| - | 300 | 0x88d4, 0x0000001f, 0x00000010, |
|
| - | 301 | 0x88d4, 0x0000001f, 0x00000010, |
|
| - | 302 | 0x8974, 0xffffffff, 0x00000000, |
|
| - | 303 | 0x8974, 0xffffffff, 0x00000000 |
|
| - | 304 | }; |
|
| - | 305 | ||
| - | 306 | static void ni_init_golden_registers(struct radeon_device *rdev) |
|
| - | 307 | { |
|
| - | 308 | switch (rdev->family) { |
|
| - | 309 | case CHIP_CAYMAN: |
|
| - | 310 | radeon_program_register_sequence(rdev, |
|
| - | 311 | cayman_golden_registers, |
|
| - | 312 | (const u32)ARRAY_SIZE(cayman_golden_registers)); |
|
| - | 313 | radeon_program_register_sequence(rdev, |
|
| - | 314 | cayman_golden_registers2, |
|
| - | 315 | (const u32)ARRAY_SIZE(cayman_golden_registers2)); |
|
| - | 316 | break; |
|
| - | 317 | case CHIP_ARUBA: |
|
| - | 318 | if ((rdev->pdev->device == 0x9900) || |
|
| - | 319 | (rdev->pdev->device == 0x9901) || |
|
| - | 320 | (rdev->pdev->device == 0x9903) || |
|
| - | 321 | (rdev->pdev->device == 0x9904) || |
|
| - | 322 | (rdev->pdev->device == 0x9905) || |
|
| - | 323 | (rdev->pdev->device == 0x9906) || |
|
| - | 324 | (rdev->pdev->device == 0x9907) || |
|
| - | 325 | (rdev->pdev->device == 0x9908) || |
|
| - | 326 | (rdev->pdev->device == 0x9909) || |
|
| - | 327 | (rdev->pdev->device == 0x990A) || |
|
| - | 328 | (rdev->pdev->device == 0x990B) || |
|
| - | 329 | (rdev->pdev->device == 0x990C) || |
|
| - | 330 | (rdev->pdev->device == 0x990D) || |
|
| - | 331 | (rdev->pdev->device == 0x990E) || |
|
| - | 332 | (rdev->pdev->device == 0x990F) || |
|
| - | 333 | (rdev->pdev->device == 0x9910) || |
|
| - | 334 | (rdev->pdev->device == 0x9913) || |
|
| - | 335 | (rdev->pdev->device == 0x9917) || |
|
| - | 336 | (rdev->pdev->device == 0x9918)) { |
|
| - | 337 | radeon_program_register_sequence(rdev, |
|
| - | 338 | dvst_golden_registers, |
|
| - | 339 | (const u32)ARRAY_SIZE(dvst_golden_registers)); |
|
| - | 340 | radeon_program_register_sequence(rdev, |
|
| - | 341 | dvst_golden_registers2, |
|
| - | 342 | (const u32)ARRAY_SIZE(dvst_golden_registers2)); |
|
| - | 343 | } else { |
|
| - | 344 | radeon_program_register_sequence(rdev, |
|
| - | 345 | scrapper_golden_registers, |
|
| - | 346 | (const u32)ARRAY_SIZE(scrapper_golden_registers)); |
|
| - | 347 | radeon_program_register_sequence(rdev, |
|
| - | 348 | dvst_golden_registers2, |
|
| - | 349 | (const u32)ARRAY_SIZE(dvst_golden_registers2)); |
|
| - | 350 | } |
|
| - | 351 | break; |
|
| - | 352 | default: |
|
| - | 353 | break; |
|
| - | 354 | } |
|
| - | 355 | } |
|
| 78 | 356 | ||
| Line 79... | Line 357... | ||
| 79 | #define BTC_IO_MC_REGS_SIZE 29 |
357 | #define BTC_IO_MC_REGS_SIZE 29 |
| 80 | 358 | ||
| 81 | static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
359 | static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
| Line 464... | Line 742... | ||
| 464 | (rdev->pdev->device == 0x9905) || |
742 | (rdev->pdev->device == 0x9905) || |
| 465 | (rdev->pdev->device == 0x9906) || |
743 | (rdev->pdev->device == 0x9906) || |
| 466 | (rdev->pdev->device == 0x9907) || |
744 | (rdev->pdev->device == 0x9907) || |
| 467 | (rdev->pdev->device == 0x9908) || |
745 | (rdev->pdev->device == 0x9908) || |
| 468 | (rdev->pdev->device == 0x9909) || |
746 | (rdev->pdev->device == 0x9909) || |
| - | 747 | (rdev->pdev->device == 0x990B) || |
|
| - | 748 | (rdev->pdev->device == 0x990C) || |
|
| - | 749 | (rdev->pdev->device == 0x990F) || |
|
| 469 | (rdev->pdev->device == 0x9910) || |
750 | (rdev->pdev->device == 0x9910) || |
| - | 751 | (rdev->pdev->device == 0x9917) || |
|
| - | 752 | (rdev->pdev->device == 0x9999) || |
|
| 470 | (rdev->pdev->device == 0x9917)) { |
753 | (rdev->pdev->device == 0x999C)) { |
| 471 | rdev->config.cayman.max_simds_per_se = 6; |
754 | rdev->config.cayman.max_simds_per_se = 6; |
| 472 | rdev->config.cayman.max_backends_per_se = 2; |
755 | rdev->config.cayman.max_backends_per_se = 2; |
| 473 | } else if ((rdev->pdev->device == 0x9903) || |
756 | } else if ((rdev->pdev->device == 0x9903) || |
| 474 | (rdev->pdev->device == 0x9904) || |
757 | (rdev->pdev->device == 0x9904) || |
| 475 | (rdev->pdev->device == 0x990A) || |
758 | (rdev->pdev->device == 0x990A) || |
| - | 759 | (rdev->pdev->device == 0x990D) || |
|
| - | 760 | (rdev->pdev->device == 0x990E) || |
|
| 476 | (rdev->pdev->device == 0x9913) || |
761 | (rdev->pdev->device == 0x9913) || |
| - | 762 | (rdev->pdev->device == 0x9918) || |
|
| 477 | (rdev->pdev->device == 0x9918)) { |
763 | (rdev->pdev->device == 0x999D)) { |
| 478 | rdev->config.cayman.max_simds_per_se = 4; |
764 | rdev->config.cayman.max_simds_per_se = 4; |
| 479 | rdev->config.cayman.max_backends_per_se = 2; |
765 | rdev->config.cayman.max_backends_per_se = 2; |
| 480 | } else if ((rdev->pdev->device == 0x9919) || |
766 | } else if ((rdev->pdev->device == 0x9919) || |
| 481 | (rdev->pdev->device == 0x9990) || |
767 | (rdev->pdev->device == 0x9990) || |
| 482 | (rdev->pdev->device == 0x9991) || |
768 | (rdev->pdev->device == 0x9991) || |
| 483 | (rdev->pdev->device == 0x9994) || |
769 | (rdev->pdev->device == 0x9994) || |
| - | 770 | (rdev->pdev->device == 0x9995) || |
|
| - | 771 | (rdev->pdev->device == 0x9996) || |
|
| - | 772 | (rdev->pdev->device == 0x999A) || |
|
| 484 | (rdev->pdev->device == 0x99A0)) { |
773 | (rdev->pdev->device == 0x99A0)) { |
| 485 | rdev->config.cayman.max_simds_per_se = 3; |
774 | rdev->config.cayman.max_simds_per_se = 3; |
| 486 | rdev->config.cayman.max_backends_per_se = 1; |
775 | rdev->config.cayman.max_backends_per_se = 1; |
| 487 | } else { |
776 | } else { |
| 488 | rdev->config.cayman.max_simds_per_se = 2; |
777 | rdev->config.cayman.max_simds_per_se = 2; |
| Line 602... | Line 891... | ||
| 602 | tmp <<= 4; |
891 | tmp <<= 4; |
| 603 | tmp |= rb_disable_bitmap; |
892 | tmp |= rb_disable_bitmap; |
| 604 | } |
893 | } |
| 605 | /* enabled rb are just the one not disabled :) */ |
894 | /* enabled rb are just the one not disabled :) */ |
| 606 | disabled_rb_mask = tmp; |
895 | disabled_rb_mask = tmp; |
| - | 896 | tmp = 0; |
|
| - | 897 | for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++) |
|
| - | 898 | tmp |= (1 << i); |
|
| - | 899 | /* if all the backends are disabled, fix it up here */ |
|
| - | 900 | if ((disabled_rb_mask & tmp) == tmp) { |
|
| - | 901 | for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++) |
|
| - | 902 | disabled_rb_mask &= ~(1 << i); |
|
| - | 903 | } |
|
| Line 607... | Line 904... | ||
| 607 | 904 | ||
| 608 | WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); |
905 | WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); |
| Line 609... | Line 906... | ||
| 609 | WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); |
906 | WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); |
| 610 | 907 | ||
| - | 908 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
|
| - | 909 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
|
| 611 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
910 | if (ASIC_IS_DCE6(rdev)) |
| 612 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
911 | WREG32(DMIF_ADDR_CALC, gb_addr_config); |
| 613 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
912 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
| - | 913 | WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); |
|
| - | 914 | WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); |
|
| - | 915 | WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); |
|
| 614 | WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); |
916 | WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); |
| - | 917 | WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); |
|
| - | 918 | ||
| - | 919 | if ((rdev->config.cayman.max_backends_per_se == 1) && |
|
| - | 920 | (rdev->flags & RADEON_IS_IGP)) { |
|
| - | 921 | if ((disabled_rb_mask & 3) == 1) { |
|
| - | 922 | /* RB0 disabled, RB1 enabled */ |
|
| - | 923 | tmp = 0x11111111; |
|
| - | 924 | } else { |
|
| - | 925 | /* RB1 disabled, RB0 enabled */ |
|
| - | 926 | tmp = 0x00000000; |
|
| 615 | WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); |
927 | } |
| 616 | 928 | } else { |
|
| 617 | tmp = gb_addr_config & NUM_PIPES_MASK; |
929 | tmp = gb_addr_config & NUM_PIPES_MASK; |
| 618 | tmp = r6xx_remap_render_backend(rdev, tmp, |
930 | tmp = r6xx_remap_render_backend(rdev, tmp, |
| 619 | rdev->config.cayman.max_backends_per_se * |
931 | rdev->config.cayman.max_backends_per_se * |
| - | 932 | rdev->config.cayman.max_shader_engines, |
|
| 620 | rdev->config.cayman.max_shader_engines, |
933 | CAYMAN_MAX_BACKENDS, disabled_rb_mask); |
| Line 621... | Line 934... | ||
| 621 | CAYMAN_MAX_BACKENDS, disabled_rb_mask); |
934 | } |
| 622 | WREG32(GB_BACKEND_MAP, tmp); |
935 | WREG32(GB_BACKEND_MAP, tmp); |
| 623 | 936 | ||
| Line 900... | Line 1213... | ||
| 900 | radeon_ring_write(ring, 0xFFFFFFFF); |
1213 | radeon_ring_write(ring, 0xFFFFFFFF); |
| 901 | radeon_ring_write(ring, 0); |
1214 | radeon_ring_write(ring, 0); |
| 902 | radeon_ring_write(ring, 10); /* poll interval */ |
1215 | radeon_ring_write(ring, 10); /* poll interval */ |
| 903 | } |
1216 | } |
| Line -... | Line 1217... | ||
| - | 1217 | ||
| - | 1218 | void cayman_uvd_semaphore_emit(struct radeon_device *rdev, |
|
| - | 1219 | struct radeon_ring *ring, |
|
| - | 1220 | struct radeon_semaphore *semaphore, |
|
| - | 1221 | bool emit_wait) |
|
| - | 1222 | { |
|
| - | 1223 | uint64_t addr = semaphore->gpu_addr; |
|
| - | 1224 | ||
| - | 1225 | radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); |
|
| - | 1226 | radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); |
|
| - | 1227 | ||
| - | 1228 | radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); |
|
| - | 1229 | radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); |
|
| - | 1230 | ||
| - | 1231 | radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); |
|
| - | 1232 | radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); |
|
| - | 1233 | } |
|
| 904 | 1234 | ||
| 905 | static void cayman_cp_enable(struct radeon_device *rdev, bool enable) |
1235 | static void cayman_cp_enable(struct radeon_device *rdev, bool enable) |
| 906 | { |
1236 | { |
| 907 | if (enable) |
1237 | if (enable) |
| 908 | WREG32(CP_ME_CNTL, 0); |
1238 | WREG32(CP_ME_CNTL, 0); |
| Line 1200... | Line 1530... | ||
| 1200 | * Returns 0 for success, error for failure. |
1530 | * Returns 0 for success, error for failure. |
| 1201 | */ |
1531 | */ |
| 1202 | int cayman_dma_resume(struct radeon_device *rdev) |
1532 | int cayman_dma_resume(struct radeon_device *rdev) |
| 1203 | { |
1533 | { |
| 1204 | struct radeon_ring *ring; |
1534 | struct radeon_ring *ring; |
| 1205 | u32 rb_cntl, dma_cntl; |
1535 | u32 rb_cntl, dma_cntl, ib_cntl; |
| 1206 | u32 rb_bufsz; |
1536 | u32 rb_bufsz; |
| 1207 | u32 reg_offset, wb_offset; |
1537 | u32 reg_offset, wb_offset; |
| 1208 | int i, r; |
1538 | int i, r; |
| Line 1209... | Line 1539... | ||
| 1209 | 1539 | ||
| Line 1249... | Line 1579... | ||
| 1249 | rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; |
1579 | rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; |
| Line 1250... | Line 1580... | ||
| 1250 | 1580 | ||
| Line 1251... | Line 1581... | ||
| 1251 | WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8); |
1581 | WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8); |
| - | 1582 | ||
| - | 1583 | /* enable DMA IBs */ |
|
| - | 1584 | ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE; |
|
| - | 1585 | #ifdef __BIG_ENDIAN |
|
| 1252 | 1586 | ib_cntl |= DMA_IB_SWAP_ENABLE; |
|
| Line 1253... | Line 1587... | ||
| 1253 | /* enable DMA IBs */ |
1587 | #endif |
| 1254 | WREG32(DMA_IB_CNTL + reg_offset, DMA_IB_ENABLE | CMD_VMID_FORCE); |
1588 | WREG32(DMA_IB_CNTL + reg_offset, ib_cntl); |
| 1255 | 1589 | ||
| Line 1290... | Line 1624... | ||
| 1290 | cayman_dma_stop(rdev); |
1624 | cayman_dma_stop(rdev); |
| 1291 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); |
1625 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); |
| 1292 | radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); |
1626 | radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); |
| 1293 | } |
1627 | } |
| Line 1294... | Line 1628... | ||
| 1294 | 1628 | ||
| 1295 | static void cayman_gpu_soft_reset_gfx(struct radeon_device *rdev) |
1629 | static u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev) |
| 1296 | { |
1630 | { |
| - | 1631 | u32 reset_mask = 0; |
|
| Line -... | Line 1632... | ||
| - | 1632 | u32 tmp; |
|
| 1297 | u32 grbm_reset = 0; |
1633 | |
| - | 1634 | /* GRBM_STATUS */ |
|
| - | 1635 | tmp = RREG32(GRBM_STATUS); |
|
| - | 1636 | if (tmp & (PA_BUSY | SC_BUSY | |
|
| - | 1637 | SH_BUSY | SX_BUSY | |
|
| - | 1638 | TA_BUSY | VGT_BUSY | |
|
| - | 1639 | DB_BUSY | CB_BUSY | |
|
| 1298 | 1640 | GDS_BUSY | SPI_BUSY | |
|
| Line 1299... | Line -... | ||
| 1299 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) |
- | |
| 1300 | return; |
- | |
| 1301 | - | ||
| 1302 | dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n", |
- | |
| 1303 | RREG32(GRBM_STATUS)); |
1641 | IA_BUSY | IA_BUSY_NO_DMA)) |
| 1304 | dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n", |
- | |
| 1305 | RREG32(GRBM_STATUS_SE0)); |
- | |
| 1306 | dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n", |
- | |
| 1307 | RREG32(GRBM_STATUS_SE1)); |
- | |
| 1308 | dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n", |
1642 | reset_mask |= RADEON_RESET_GFX; |
| 1309 | RREG32(SRBM_STATUS)); |
- | |
| 1310 | dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", |
1643 | |
| 1311 | RREG32(CP_STALLED_STAT1)); |
- | |
| 1312 | dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", |
- | |
| 1313 | RREG32(CP_STALLED_STAT2)); |
- | |
| 1314 | dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", |
- | |
| Line 1315... | Line 1644... | ||
| 1315 | RREG32(CP_BUSY_STAT)); |
1644 | if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING | |
| 1316 | dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", |
1645 | CP_BUSY | CP_COHERENCY_BUSY)) |
| Line 1317... | Line -... | ||
| 1317 | RREG32(CP_STAT)); |
- | |
| 1318 | - | ||
| 1319 | /* Disable CP parsing/prefetching */ |
- | |
| 1320 | WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); |
- | |
| 1321 | 1646 | reset_mask |= RADEON_RESET_CP; |
|
| 1322 | /* reset all the gfx blocks */ |
- | |
| 1323 | grbm_reset = (SOFT_RESET_CP | |
- | |
| 1324 | SOFT_RESET_CB | |
1647 | |
| 1325 | SOFT_RESET_DB | |
- | |
| 1326 | SOFT_RESET_GDS | |
- | |
| 1327 | SOFT_RESET_PA | |
- | |
| 1328 | SOFT_RESET_SC | |
1648 | if (tmp & GRBM_EE_BUSY) |
| 1329 | SOFT_RESET_SPI | |
- | |
| 1330 | SOFT_RESET_SH | |
1649 | reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; |
| Line 1331... | Line -... | ||
| 1331 | SOFT_RESET_SX | |
- | |
| 1332 | SOFT_RESET_TC | |
1650 | |
| 1333 | SOFT_RESET_TA | |
1651 | /* DMA_STATUS_REG 0 */ |
| 1334 | SOFT_RESET_VGT | |
- | |
| 1335 | SOFT_RESET_IA); |
1652 | tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); |
| 1336 | 1653 | if (!(tmp & DMA_IDLE)) |
|
| Line 1337... | Line -... | ||
| 1337 | dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); |
- | |
| 1338 | WREG32(GRBM_SOFT_RESET, grbm_reset); |
1654 | reset_mask |= RADEON_RESET_DMA; |
| 1339 | (void)RREG32(GRBM_SOFT_RESET); |
- | |
| 1340 | udelay(50); |
- | |
| 1341 | WREG32(GRBM_SOFT_RESET, 0); |
- | |
| 1342 | (void)RREG32(GRBM_SOFT_RESET); |
1655 | |
| 1343 | - | ||
| 1344 | dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n", |
1656 | /* DMA_STATUS_REG 1 */ |
| 1345 | RREG32(GRBM_STATUS)); |
- | |
| 1346 | dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n", |
- | |
| 1347 | RREG32(GRBM_STATUS_SE0)); |
- | |
| 1348 | dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n", |
1657 | tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); |
| 1349 | RREG32(GRBM_STATUS_SE1)); |
- | |
| 1350 | dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n", |
- | |
| 1351 | RREG32(SRBM_STATUS)); |
- | |
| 1352 | dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", |
- | |
| Line 1353... | Line -... | ||
| 1353 | RREG32(CP_STALLED_STAT1)); |
- | |
| - | 1658 | if (!(tmp & DMA_IDLE)) |
|
| - | 1659 | reset_mask |= RADEON_RESET_DMA1; |
|
| Line -... | Line 1660... | ||
| - | 1660 | ||
| - | 1661 | /* SRBM_STATUS2 */ |
|
| 1354 | dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", |
1662 | tmp = RREG32(SRBM_STATUS2); |
| 1355 | RREG32(CP_STALLED_STAT2)); |
- | |
| 1356 | dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", |
1663 | if (tmp & DMA_BUSY) |
| Line 1357... | Line 1664... | ||
| 1357 | RREG32(CP_BUSY_STAT)); |
1664 | reset_mask |= RADEON_RESET_DMA; |
| 1358 | dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", |
1665 | |
| Line 1359... | Line 1666... | ||
| 1359 | RREG32(CP_STAT)); |
1666 | if (tmp & DMA1_BUSY) |
| 1360 | 1667 | reset_mask |= RADEON_RESET_DMA1; |
|
| Line 1361... | Line -... | ||
| 1361 | } |
- | |
| 1362 | - | ||
| 1363 | static void cayman_gpu_soft_reset_dma(struct radeon_device *rdev) |
1668 | |
| 1364 | { |
1669 | /* SRBM_STATUS */ |
| Line 1365... | Line -... | ||
| 1365 | u32 tmp; |
- | |
| 1366 | - | ||
| 1367 | if (RREG32(DMA_STATUS_REG) & DMA_IDLE) |
1670 | tmp = RREG32(SRBM_STATUS); |
| 1368 | return; |
1671 | if (tmp & (RLC_RQ_PENDING | RLC_BUSY)) |
| Line 1369... | Line 1672... | ||
| 1369 | 1672 | reset_mask |= RADEON_RESET_RLC; |
|
| 1370 | dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", |
1673 | |
| 1371 | RREG32(DMA_STATUS_REG)); |
1674 | if (tmp & IH_BUSY) |
| - | 1675 | reset_mask |= RADEON_RESET_IH; |
|
| 1372 | 1676 | ||
| 1373 | /* dma0 */ |
1677 | if (tmp & SEM_BUSY) |
| Line 1374... | Line 1678... | ||
| 1374 | tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); |
1678 | reset_mask |= RADEON_RESET_SEM; |
| 1375 | tmp &= ~DMA_RB_ENABLE; |
1679 | |
| - | 1680 | if (tmp & GRBM_RQ_PENDING) |
|
| - | 1681 | reset_mask |= RADEON_RESET_GRBM; |
|
| Line -... | Line 1682... | ||
| - | 1682 | ||
| - | 1683 | if (tmp & VMC_BUSY) |
|
| - | 1684 | reset_mask |= RADEON_RESET_VMC; |
|
| - | 1685 | ||
| 1376 | WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); |
1686 | if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY | |
| Line -... | Line 1687... | ||
| - | 1687 | MCC_BUSY | MCD_BUSY)) |
|
| - | 1688 | reset_mask |= RADEON_RESET_MC; |
|
| - | 1689 | ||
| 1377 | 1690 | if (evergreen_is_display_hung(rdev)) |
|
| 1378 | /* dma1 */ |
1691 | reset_mask |= RADEON_RESET_DISPLAY; |
| 1379 | tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); |
1692 | |
| - | 1693 | /* VM_L2_STATUS */ |
|
| - | 1694 | tmp = RREG32(VM_L2_STATUS); |
|
| Line 1380... | Line 1695... | ||
| 1380 | tmp &= ~DMA_RB_ENABLE; |
1695 | if (tmp & L2_BUSY) |
| 1381 | WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); |
1696 | reset_mask |= RADEON_RESET_VMC; |
| Line 1382... | Line 1697... | ||
| 1382 | 1697 | ||
| Line -... | Line 1698... | ||
| - | 1698 | /* Skip MC reset as it's mostly likely not hung, just busy */ |
|
| 1383 | /* Reset dma */ |
1699 | if (reset_mask & RADEON_RESET_MC) { |
| 1384 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1); |
1700 | DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); |
| 1385 | RREG32(SRBM_SOFT_RESET); |
1701 | reset_mask &= ~RADEON_RESET_MC; |
| 1386 | udelay(50); |
1702 | } |
| 1387 | WREG32(SRBM_SOFT_RESET, 0); |
1703 | |
| 1388 | 1704 | return reset_mask; |
|
| 1389 | dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", |
1705 | } |
| 1390 | RREG32(DMA_STATUS_REG)); |
1706 | |
| Line -... | Line 1707... | ||
| - | 1707 | static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) |
|
| - | 1708 | { |
|
| - | 1709 | struct evergreen_mc_save save; |
|
| - | 1710 | u32 grbm_soft_reset = 0, srbm_soft_reset = 0; |
|
| - | 1711 | u32 tmp; |
|
| - | 1712 | ||
| - | 1713 | if (reset_mask == 0) |
|
| - | 1714 | return; |
|
| - | 1715 | ||
| - | 1716 | dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); |
|
| - | 1717 | ||
| - | 1718 | evergreen_print_gpu_status_regs(rdev); |
|
| - | 1719 | dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", |
|
| - | 1720 | RREG32(0x14F8)); |
|
| - | 1721 | dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", |
|
| - | 1722 | RREG32(0x14D8)); |
|
| - | 1723 | dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", |
|
| - | 1724 | RREG32(0x14FC)); |
|
| - | 1725 | dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", |
|
| 1391 | 1726 | RREG32(0x14DC)); |
|
| 1392 | } |
1727 | |
| 1393 | 1728 | /* Disable CP parsing/prefetching */ |
|
| 1394 | static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) |
1729 | WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); |
| Line 1395... | Line 1730... | ||
| 1395 | { |
1730 | |
| 1396 | struct evergreen_mc_save save; |
1731 | if (reset_mask & RADEON_RESET_DMA) { |
| - | 1732 | /* dma0 */ |
|
| - | 1733 | tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); |
|
| - | 1734 | tmp &= ~DMA_RB_ENABLE; |
|
| - | 1735 | WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); |
|
| - | 1736 | } |
|
| - | 1737 | ||
| - | 1738 | if (reset_mask & RADEON_RESET_DMA1) { |
|
| - | 1739 | /* dma1 */ |
|
| - | 1740 | tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); |
|
| - | 1741 | tmp &= ~DMA_RB_ENABLE; |
|
| - | 1742 | WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); |
|
| - | 1743 | } |
|
| - | 1744 | ||
| - | 1745 | udelay(50); |
|
| - | 1746 | ||
| - | 1747 | evergreen_mc_stop(rdev, &save); |
|
| - | 1748 | if (evergreen_mc_wait_for_idle(rdev)) { |
|
| - | 1749 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
|
| Line 1397... | Line 1750... | ||
| 1397 | 1750 | } |
|
| - | 1751 | ||
| - | 1752 | if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { |
|
| - | 1753 | grbm_soft_reset = SOFT_RESET_CB | |
|
| - | 1754 | SOFT_RESET_DB | |
|
| - | 1755 | SOFT_RESET_GDS | |
|
| - | 1756 | SOFT_RESET_PA | |
|
| - | 1757 | SOFT_RESET_SC | |
|
| - | 1758 | SOFT_RESET_SPI | |
|
| - | 1759 | SOFT_RESET_SH | |
|
| - | 1760 | SOFT_RESET_SX | |
|
| - | 1761 | SOFT_RESET_TC | |
|
| - | 1762 | SOFT_RESET_TA | |
|
| - | 1763 | SOFT_RESET_VGT | |
|
| - | 1764 | SOFT_RESET_IA; |
|
| - | 1765 | } |
|
| - | 1766 | ||
| - | 1767 | if (reset_mask & RADEON_RESET_CP) { |
|
| - | 1768 | grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT; |
|
| - | 1769 | ||
| - | 1770 | srbm_soft_reset |= SOFT_RESET_GRBM; |
|
| - | 1771 | } |
|
| - | 1772 | ||
| - | 1773 | if (reset_mask & RADEON_RESET_DMA) |
|
| - | 1774 | srbm_soft_reset |= SOFT_RESET_DMA; |
|
| - | 1775 | ||
| - | 1776 | if (reset_mask & RADEON_RESET_DMA1) |
|
| - | 1777 | srbm_soft_reset |= SOFT_RESET_DMA1; |
|
| - | 1778 | ||
| - | 1779 | if (reset_mask & RADEON_RESET_DISPLAY) |
|
| - | 1780 | srbm_soft_reset |= SOFT_RESET_DC; |
|
| 1398 | if (reset_mask == 0) |
1781 | |
| - | 1782 | if (reset_mask & RADEON_RESET_RLC) |
|
| - | 1783 | srbm_soft_reset |= SOFT_RESET_RLC; |
|
| - | 1784 | ||
| - | 1785 | if (reset_mask & RADEON_RESET_SEM) |
|
| - | 1786 | srbm_soft_reset |= SOFT_RESET_SEM; |
|
| - | 1787 | ||
| - | 1788 | if (reset_mask & RADEON_RESET_IH) |
|
| - | 1789 | srbm_soft_reset |= SOFT_RESET_IH; |
|
| - | 1790 | ||
| - | 1791 | if (reset_mask & RADEON_RESET_GRBM) |
|
| - | 1792 | srbm_soft_reset |= SOFT_RESET_GRBM; |
|
| - | 1793 | ||
| - | 1794 | if (reset_mask & RADEON_RESET_VMC) |
|
| - | 1795 | srbm_soft_reset |= SOFT_RESET_VMC; |
|
| - | 1796 | ||
| - | 1797 | if (!(rdev->flags & RADEON_IS_IGP)) { |
|
| - | 1798 | if (reset_mask & RADEON_RESET_MC) |
|
| - | 1799 | srbm_soft_reset |= SOFT_RESET_MC; |
|
| - | 1800 | } |
|
| - | 1801 | ||
| - | 1802 | if (grbm_soft_reset) { |
|
| - | 1803 | tmp = RREG32(GRBM_SOFT_RESET); |
|
| - | 1804 | tmp |= grbm_soft_reset; |
|
| - | 1805 | dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); |
|
| Line 1399... | Line 1806... | ||
| 1399 | return 0; |
1806 | WREG32(GRBM_SOFT_RESET, tmp); |
| 1400 | 1807 | tmp = RREG32(GRBM_SOFT_RESET); |
|
| Line 1401... | Line 1808... | ||
| 1401 | dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); |
1808 | |
| 1402 | 1809 | udelay(50); |
|
| - | 1810 | ||
| - | 1811 | tmp &= ~grbm_soft_reset; |
|
| 1403 | dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", |
1812 | WREG32(GRBM_SOFT_RESET, tmp); |
| Line 1404... | Line 1813... | ||
| 1404 | RREG32(0x14F8)); |
1813 | tmp = RREG32(GRBM_SOFT_RESET); |
| 1405 | dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", |
1814 | } |
| - | 1815 | ||
| - | 1816 | if (srbm_soft_reset) { |
|
| - | 1817 | tmp = RREG32(SRBM_SOFT_RESET); |
|
| - | 1818 | tmp |= srbm_soft_reset; |
|
| - | 1819 | dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); |
|
| - | 1820 | WREG32(SRBM_SOFT_RESET, tmp); |
|
| - | 1821 | tmp = RREG32(SRBM_SOFT_RESET); |
|
| 1406 | RREG32(0x14D8)); |
1822 | |
| - | 1823 | udelay(50); |
|
| - | 1824 | ||
| - | 1825 | tmp &= ~srbm_soft_reset; |
|
| - | 1826 | WREG32(SRBM_SOFT_RESET, tmp); |
|
| - | 1827 | tmp = RREG32(SRBM_SOFT_RESET); |
|
| - | 1828 | } |
|
| - | 1829 | ||
| - | 1830 | /* Wait a little for things to settle down */ |
|
| - | 1831 | udelay(50); |
|
| - | 1832 | ||
| - | 1833 | evergreen_mc_resume(rdev, &save); |
|
| - | 1834 | udelay(50); |
|
| - | 1835 | ||
| - | 1836 | evergreen_print_gpu_status_regs(rdev); |
|
| - | 1837 | } |
|
| - | 1838 | ||
| - | 1839 | int cayman_asic_reset(struct radeon_device *rdev) |
|
| - | 1840 | { |
|
| - | 1841 | u32 reset_mask; |
|
| - | 1842 | ||
| - | 1843 | reset_mask = cayman_gpu_check_soft_reset(rdev); |
|
| - | 1844 | ||
| - | 1845 | if (reset_mask) |
|
| 1407 | dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", |
1846 | r600_set_bios_scratch_engine_hung(rdev, true); |
| 1408 | RREG32(0x14FC)); |
1847 | |
| - | 1848 | cayman_gpu_soft_reset(rdev, reset_mask); |
|
| - | 1849 | ||
| - | 1850 | reset_mask = cayman_gpu_check_soft_reset(rdev); |
|
| - | 1851 | ||
| - | 1852 | if (!reset_mask) |
|
| - | 1853 | r600_set_bios_scratch_engine_hung(rdev, false); |
|
| 1409 | dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", |
1854 | |
| Line 1410... | Line 1855... | ||
| 1410 | RREG32(0x14DC)); |
1855 | return 0; |
| 1411 | 1856 | } |
|
| 1412 | evergreen_mc_stop(rdev, &save); |
1857 | |
| 1413 | if (evergreen_mc_wait_for_idle(rdev)) { |
1858 | /** |
| 1414 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
1859 | * cayman_gfx_is_lockup - Check if the GFX engine is locked up |
| 1415 | } |
1860 | * |
| 1416 | 1861 | * @rdev: radeon_device pointer |
|
| 1417 | if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) |
1862 | * @ring: radeon_ring structure holding ring information |
| 1418 | cayman_gpu_soft_reset_gfx(rdev); |
1863 | * |
| 1419 | 1864 | * Check if the GFX engine is locked up. |
|
| 1420 | if (reset_mask & RADEON_RESET_DMA) |
1865 | * Returns true if the engine appears to be locked up, false if not. |
| - | 1866 | */ |
|
| 1421 | cayman_gpu_soft_reset_dma(rdev); |
1867 | bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
| Line 1422... | Line 1868... | ||
| 1422 | 1868 | { |
|
| 1423 | /* Wait a little for things to settle down */ |
1869 | u32 reset_mask = cayman_gpu_check_soft_reset(rdev); |
| 1424 | udelay(50); |
1870 | |
| 1425 | 1871 | if (!(reset_mask & (RADEON_RESET_GFX | |
|
| - | 1872 | RADEON_RESET_COMPUTE | |
|
| 1426 | evergreen_mc_resume(rdev, &save); |
1873 | RADEON_RESET_CP))) { |
| 1427 | return 0; |
1874 | radeon_ring_lockup_update(ring); |
| 1428 | } |
1875 | return false; |
| 1429 | 1876 | } |
|
| 1430 | int cayman_asic_reset(struct radeon_device *rdev) |
1877 | /* force CP activities */ |
| 1431 | { |
1878 | radeon_ring_force_activity(rdev, ring); |
| Line 1527... | Line 1974... | ||
| 1527 | if (r) { |
1974 | if (r) { |
| 1528 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
1975 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
| 1529 | return r; |
1976 | return r; |
| 1530 | } |
1977 | } |
| Line -... | Line 1978... | ||
| - | 1978 | ||
| - | 1979 | // r = rv770_uvd_resume(rdev); |
|
| - | 1980 | // if (!r) { |
|
| - | 1981 | // r = radeon_fence_driver_start_ring(rdev, |
|
| - | 1982 | // R600_RING_TYPE_UVD_INDEX); |
|
| - | 1983 | // if (r) |
|
| - | 1984 | // dev_err(rdev->dev, "UVD fences init error (%d).\n", r); |
|
| - | 1985 | // } |
|
| - | 1986 | // if (r) |
|
| - | 1987 | // rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; |
|
| 1531 | 1988 | ||
| 1532 | r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); |
1989 | r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); |
| 1533 | if (r) { |
1990 | if (r) { |
| 1534 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
1991 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
| 1535 | return r; |
1992 | return r; |
| Line 1552... | Line 2009... | ||
| 1552 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
2009 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
| 1553 | return r; |
2010 | return r; |
| 1554 | } |
2011 | } |
| Line 1555... | Line 2012... | ||
| 1555 | 2012 | ||
| - | 2013 | /* Enable IRQ */ |
|
| - | 2014 | if (!rdev->irq.installed) { |
|
| - | 2015 | r = radeon_irq_kms_init(rdev); |
|
| - | 2016 | if (r) |
|
| - | 2017 | return r; |
|
| - | 2018 | } |
|
| 1556 | /* Enable IRQ */ |
2019 | |
| 1557 | r = r600_irq_init(rdev); |
2020 | r = r600_irq_init(rdev); |
| 1558 | if (r) { |
2021 | if (r) { |
| 1559 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
2022 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
| 1560 | // radeon_irq_kms_fini(rdev); |
2023 | // radeon_irq_kms_fini(rdev); |
| Line 1593... | Line 2056... | ||
| 1593 | 2056 | ||
| 1594 | r = cayman_dma_resume(rdev); |
2057 | r = cayman_dma_resume(rdev); |
| 1595 | if (r) |
2058 | if (r) |
| Line -... | Line 2059... | ||
| - | 2059 | return r; |
|
| - | 2060 | ||
| - | 2061 | ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
|
| - | 2062 | if (ring->ring_size) { |
|
| - | 2063 | r = radeon_ring_init(rdev, ring, ring->ring_size, |
|
| - | 2064 | R600_WB_UVD_RPTR_OFFSET, |
|
| - | 2065 | UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, |
|
| - | 2066 | 0, 0xfffff, RADEON_CP_PACKET2); |
|
| - | 2067 | if (!r) |
|
| - | 2068 | r = r600_uvd_init(rdev); |
|
| - | 2069 | if (r) |
|
| - | 2070 | DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); |
|
| 1596 | return r; |
2071 | } |
| 1597 | 2072 | ||
| 1598 | r = radeon_ib_pool_init(rdev); |
2073 | r = radeon_ib_pool_init(rdev); |
| 1599 | if (r) { |
2074 | if (r) { |
| 1600 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
2075 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| - | 2076 | return r; |
|
| - | 2077 | } |
|
| - | 2078 | ||
| - | 2079 | r = radeon_vm_manager_init(rdev); |
|
| - | 2080 | if (r) { |
|
| - | 2081 | dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); |
|
| - | 2082 | return r; |
|
| - | 2083 | } |
|
| 1601 | return r; |
2084 | |
| 1602 | } |
2085 | |
| Line 1639... | Line 2122... | ||
| 1639 | return -EINVAL; |
2122 | return -EINVAL; |
| 1640 | } |
2123 | } |
| 1641 | DRM_INFO("GPU not posted. posting now...\n"); |
2124 | DRM_INFO("GPU not posted. posting now...\n"); |
| 1642 | atom_asic_init(rdev->mode_info.atom_context); |
2125 | atom_asic_init(rdev->mode_info.atom_context); |
| 1643 | } |
2126 | } |
| - | 2127 | /* init golden registers */ |
|
| - | 2128 | ni_init_golden_registers(rdev); |
|
| 1644 | /* Initialize scratch registers */ |
2129 | /* Initialize scratch registers */ |
| 1645 | r600_scratch_init(rdev); |
2130 | r600_scratch_init(rdev); |
| 1646 | /* Initialize surface registers */ |
2131 | /* Initialize surface registers */ |
| 1647 | radeon_surface_init(rdev); |
2132 | radeon_surface_init(rdev); |
| 1648 | /* Initialize clocks */ |
2133 | /* Initialize clocks */ |
| Line 1658... | Line 2143... | ||
| 1658 | /* Memory manager */ |
2143 | /* Memory manager */ |
| 1659 | r = radeon_bo_init(rdev); |
2144 | r = radeon_bo_init(rdev); |
| 1660 | if (r) |
2145 | if (r) |
| 1661 | return r; |
2146 | return r; |
| Line 1662... | Line -... | ||
| 1662 | - | ||
| 1663 | r = radeon_irq_kms_init(rdev); |
- | |
| 1664 | if (r) |
- | |
| 1665 | return r; |
- | |
| 1666 | 2147 | ||
| 1667 | ring->ring_obj = NULL; |
2148 | ring->ring_obj = NULL; |
| Line 1668... | Line 2149... | ||
| 1668 | r600_ring_init(rdev, ring, 1024 * 1024); |
2149 | r600_ring_init(rdev, ring, 1024 * 1024); |
| 1669 | 2150 | ||
| Line 1673... | Line 2154... | ||
| 1673 | 2154 | ||
| 1674 | ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; |
2155 | ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; |
| 1675 | ring->ring_obj = NULL; |
2156 | ring->ring_obj = NULL; |
| Line -... | Line 2157... | ||
| - | 2157 | r600_ring_init(rdev, ring, 64 * 1024); |
|
| - | 2158 | ||
| - | 2159 | // r = radeon_uvd_init(rdev); |
|
| - | 2160 | // if (!r) { |
|
| - | 2161 | // ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
|
| - | 2162 | // ring->ring_obj = NULL; |
|
| - | 2163 | // r600_ring_init(rdev, ring, 4096); |
|
| 1676 | r600_ring_init(rdev, ring, 64 * 1024); |
2164 | // } |
| 1677 | 2165 | ||
| Line 1678... | Line 2166... | ||
| 1678 | rdev->ih.ring_obj = NULL; |
2166 | rdev->ih.ring_obj = NULL; |
| 1679 | r600_ih_ring_init(rdev, 64 * 1024); |
2167 | r600_ih_ring_init(rdev, 64 * 1024); |
| Line 1746... | Line 2234... | ||
| 1746 | 2234 | ||
| 1747 | /** |
2235 | /** |
| 1748 | * cayman_vm_set_page - update the page tables using the CP |
2236 | * cayman_vm_set_page - update the page tables using the CP |
| 1749 | * |
2237 | * |
| - | 2238 | * @rdev: radeon_device pointer |
|
| 1750 | * @rdev: radeon_device pointer |
2239 | * @ib: indirect buffer to fill with commands |
| 1751 | * @pe: addr of the page entry |
2240 | * @pe: addr of the page entry |
| 1752 | * @addr: dst addr to write into pe |
2241 | * @addr: dst addr to write into pe |
| 1753 | * @count: number of page entries to update |
2242 | * @count: number of page entries to update |
| 1754 | * @incr: increase next addr by incr bytes |
2243 | * @incr: increase next addr by incr bytes |
| 1755 | * @flags: access flags |
2244 | * @flags: access flags |
| 1756 | * |
2245 | * |
| 1757 | * Update the page tables using the CP (cayman-si). |
2246 | * Update the page tables using the CP (cayman/TN). |
| 1758 | */ |
2247 | */ |
| - | 2248 | void cayman_vm_set_page(struct radeon_device *rdev, |
|
| - | 2249 | struct radeon_ib *ib, |
|
| 1759 | void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, |
2250 | uint64_t pe, |
| 1760 | uint64_t addr, unsigned count, |
2251 | uint64_t addr, unsigned count, |
| 1761 | uint32_t incr, uint32_t flags) |
2252 | uint32_t incr, uint32_t flags) |
| 1762 | { |
- | |
| 1763 | struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index]; |
2253 | { |
| 1764 | uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); |
2254 | uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); |
| 1765 | uint64_t value; |
2255 | uint64_t value; |
| Line 1766... | Line 2256... | ||
| 1766 | unsigned ndw; |
2256 | unsigned ndw; |
| 1767 | 2257 | ||
| 1768 | if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) { |
2258 | if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) { |
| 1769 | while (count) { |
2259 | while (count) { |
| 1770 | ndw = 1 + count * 2; |
2260 | ndw = 1 + count * 2; |
| Line 1771... | Line 2261... | ||
| 1771 | if (ndw > 0x3FFF) |
2261 | if (ndw > 0x3FFF) |
| 1772 | ndw = 0x3FFF; |
2262 | ndw = 0x3FFF; |
| 1773 | 2263 | ||
| 1774 | radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, ndw)); |
2264 | ib->ptr[ib->length_dw++] = PACKET3(PACKET3_ME_WRITE, ndw); |
| 1775 | radeon_ring_write(ring, pe); |
2265 | ib->ptr[ib->length_dw++] = pe; |
| 1776 | radeon_ring_write(ring, upper_32_bits(pe) & 0xff); |
2266 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; |
| 1777 | for (; ndw > 1; ndw -= 2, --count, pe += 8) { |
2267 | for (; ndw > 1; ndw -= 2, --count, pe += 8) { |
| 1778 | if (flags & RADEON_VM_PAGE_SYSTEM) { |
2268 | if (flags & RADEON_VM_PAGE_SYSTEM) { |
| Line 1783... | Line 2273... | ||
| 1783 | } else { |
2273 | } else { |
| 1784 | value = 0; |
2274 | value = 0; |
| 1785 | } |
2275 | } |
| 1786 | addr += incr; |
2276 | addr += incr; |
| 1787 | value |= r600_flags; |
2277 | value |= r600_flags; |
| 1788 | radeon_ring_write(ring, value); |
2278 | ib->ptr[ib->length_dw++] = value; |
| 1789 | radeon_ring_write(ring, upper_32_bits(value)); |
2279 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
| 1790 | } |
2280 | } |
| 1791 | } |
2281 | } |
| 1792 | } else { |
2282 | } else { |
| - | 2283 | if ((flags & RADEON_VM_PAGE_SYSTEM) || |
|
| - | 2284 | (count == 1)) { |
|
| 1793 | while (count) { |
2285 | while (count) { |
| 1794 | ndw = count * 2; |
2286 | ndw = count * 2; |
| 1795 | if (ndw > 0xFFFFE) |
2287 | if (ndw > 0xFFFFE) |
| 1796 | ndw = 0xFFFFE; |
2288 | ndw = 0xFFFFE; |
| Line 1797... | Line 2289... | ||
| 1797 | 2289 | ||
| 1798 | /* for non-physically contiguous pages (system) */ |
2290 | /* for non-physically contiguous pages (system) */ |
| 1799 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw)); |
2291 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw); |
| 1800 | radeon_ring_write(ring, pe); |
2292 | ib->ptr[ib->length_dw++] = pe; |
| 1801 | radeon_ring_write(ring, upper_32_bits(pe) & 0xff); |
2293 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; |
| 1802 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { |
2294 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { |
| 1803 | if (flags & RADEON_VM_PAGE_SYSTEM) { |
2295 | if (flags & RADEON_VM_PAGE_SYSTEM) { |
| 1804 | value = radeon_vm_map_gart(rdev, addr); |
2296 | value = radeon_vm_map_gart(rdev, addr); |
| 1805 | value &= 0xFFFFFFFFFFFFF000ULL; |
2297 | value &= 0xFFFFFFFFFFFFF000ULL; |
| Line 1808... | Line 2300... | ||
| 1808 | } else { |
2300 | } else { |
| 1809 | value = 0; |
2301 | value = 0; |
| 1810 | } |
2302 | } |
| 1811 | addr += incr; |
2303 | addr += incr; |
| 1812 | value |= r600_flags; |
2304 | value |= r600_flags; |
| 1813 | radeon_ring_write(ring, value); |
2305 | ib->ptr[ib->length_dw++] = value; |
| 1814 | radeon_ring_write(ring, upper_32_bits(value)); |
2306 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
| - | 2307 | } |
|
| - | 2308 | } |
|
| - | 2309 | while (ib->length_dw & 0x7) |
|
| - | 2310 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0); |
|
| - | 2311 | } else { |
|
| - | 2312 | while (count) { |
|
| - | 2313 | ndw = count * 2; |
|
| - | 2314 | if (ndw > 0xFFFFE) |
|
| - | 2315 | ndw = 0xFFFFE; |
|
| - | 2316 | ||
| - | 2317 | if (flags & RADEON_VM_PAGE_VALID) |
|
| - | 2318 | value = addr; |
|
| - | 2319 | else |
|
| - | 2320 | value = 0; |
|
| - | 2321 | /* for physically contiguous pages (vram) */ |
|
| - | 2322 | ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); |
|
| - | 2323 | ib->ptr[ib->length_dw++] = pe; /* dst addr */ |
|
| - | 2324 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; |
|
| - | 2325 | ib->ptr[ib->length_dw++] = r600_flags; /* mask */ |
|
| - | 2326 | ib->ptr[ib->length_dw++] = 0; |
|
| - | 2327 | ib->ptr[ib->length_dw++] = value; /* value */ |
|
| - | 2328 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
|
| - | 2329 | ib->ptr[ib->length_dw++] = incr; /* increment size */ |
|
| - | 2330 | ib->ptr[ib->length_dw++] = 0; |
|
| - | 2331 | pe += ndw * 4; |
|
| - | 2332 | addr += (ndw / 2) * incr; |
|
| - | 2333 | count -= ndw / 2; |
|
| 1815 | } |
2334 | } |
| 1816 | } |
2335 | } |
| - | 2336 | while (ib->length_dw & 0x7) |
|
| - | 2337 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0); |
|
| 1817 | } |
2338 | } |
| 1818 | } |
2339 | } |
| Line 1819... | Line 2340... | ||
| 1819 | 2340 | ||
| 1820 | /** |
2341 | /** |