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1 | /* |
1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. |
2 | * Copyright 2010 Advanced Micro Devices, Inc. |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
12 | * all copies or substantial portions of the Software. |
13 | * |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
21 | * |
22 | * Authors: Alex Deucher |
22 | * Authors: Alex Deucher |
23 | */ |
23 | */ |
24 | #include |
24 | #include |
25 | //#include |
25 | //#include |
26 | #include |
26 | #include |
27 | #include "drmP.h" |
27 | #include "drmP.h" |
28 | #include "radeon.h" |
28 | #include "radeon.h" |
29 | #include "radeon_asic.h" |
29 | #include "radeon_asic.h" |
30 | #include "radeon_drm.h" |
30 | #include "radeon_drm.h" |
31 | #include "nid.h" |
31 | #include "nid.h" |
32 | #include "atom.h" |
32 | #include "atom.h" |
33 | #include "ni_reg.h" |
33 | #include "ni_reg.h" |
34 | #include "cayman_blit_shaders.h" |
34 | #include "cayman_blit_shaders.h" |
35 | 35 | ||
36 | extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); |
36 | extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); |
37 | extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); |
37 | extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); |
38 | extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
38 | extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
39 | extern void evergreen_mc_program(struct radeon_device *rdev); |
39 | extern void evergreen_mc_program(struct radeon_device *rdev); |
40 | extern void evergreen_irq_suspend(struct radeon_device *rdev); |
40 | extern void evergreen_irq_suspend(struct radeon_device *rdev); |
41 | extern int evergreen_mc_init(struct radeon_device *rdev); |
41 | extern int evergreen_mc_init(struct radeon_device *rdev); |
42 | 42 | ||
43 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
43 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
44 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
44 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
45 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
45 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
46 | #define BTC_MC_UCODE_SIZE 6024 |
46 | #define BTC_MC_UCODE_SIZE 6024 |
47 | 47 | ||
48 | #define CAYMAN_PFP_UCODE_SIZE 2176 |
48 | #define CAYMAN_PFP_UCODE_SIZE 2176 |
49 | #define CAYMAN_PM4_UCODE_SIZE 2176 |
49 | #define CAYMAN_PM4_UCODE_SIZE 2176 |
50 | #define CAYMAN_RLC_UCODE_SIZE 1024 |
50 | #define CAYMAN_RLC_UCODE_SIZE 1024 |
51 | #define CAYMAN_MC_UCODE_SIZE 6037 |
51 | #define CAYMAN_MC_UCODE_SIZE 6037 |
52 | 52 | ||
53 | /* Firmware Names */ |
53 | /* Firmware Names */ |
54 | MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); |
54 | MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); |
55 | MODULE_FIRMWARE("radeon/BARTS_me.bin"); |
55 | MODULE_FIRMWARE("radeon/BARTS_me.bin"); |
56 | MODULE_FIRMWARE("radeon/BARTS_mc.bin"); |
56 | MODULE_FIRMWARE("radeon/BARTS_mc.bin"); |
57 | MODULE_FIRMWARE("radeon/BTC_rlc.bin"); |
57 | MODULE_FIRMWARE("radeon/BTC_rlc.bin"); |
58 | MODULE_FIRMWARE("radeon/TURKS_pfp.bin"); |
58 | MODULE_FIRMWARE("radeon/TURKS_pfp.bin"); |
59 | MODULE_FIRMWARE("radeon/TURKS_me.bin"); |
59 | MODULE_FIRMWARE("radeon/TURKS_me.bin"); |
60 | MODULE_FIRMWARE("radeon/TURKS_mc.bin"); |
60 | MODULE_FIRMWARE("radeon/TURKS_mc.bin"); |
61 | MODULE_FIRMWARE("radeon/CAICOS_pfp.bin"); |
61 | MODULE_FIRMWARE("radeon/CAICOS_pfp.bin"); |
62 | MODULE_FIRMWARE("radeon/CAICOS_me.bin"); |
62 | MODULE_FIRMWARE("radeon/CAICOS_me.bin"); |
63 | MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); |
63 | MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); |
64 | MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); |
64 | MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); |
65 | MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); |
65 | MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); |
66 | MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); |
66 | MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); |
67 | MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); |
67 | MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); |
68 | 68 | ||
69 | #define BTC_IO_MC_REGS_SIZE 29 |
69 | #define BTC_IO_MC_REGS_SIZE 29 |
70 | 70 | ||
71 | static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
71 | static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
72 | {0x00000077, 0xff010100}, |
72 | {0x00000077, 0xff010100}, |
73 | {0x00000078, 0x00000000}, |
73 | {0x00000078, 0x00000000}, |
74 | {0x00000079, 0x00001434}, |
74 | {0x00000079, 0x00001434}, |
75 | {0x0000007a, 0xcc08ec08}, |
75 | {0x0000007a, 0xcc08ec08}, |
76 | {0x0000007b, 0x00040000}, |
76 | {0x0000007b, 0x00040000}, |
77 | {0x0000007c, 0x000080c0}, |
77 | {0x0000007c, 0x000080c0}, |
78 | {0x0000007d, 0x09000000}, |
78 | {0x0000007d, 0x09000000}, |
79 | {0x0000007e, 0x00210404}, |
79 | {0x0000007e, 0x00210404}, |
80 | {0x00000081, 0x08a8e800}, |
80 | {0x00000081, 0x08a8e800}, |
81 | {0x00000082, 0x00030444}, |
81 | {0x00000082, 0x00030444}, |
82 | {0x00000083, 0x00000000}, |
82 | {0x00000083, 0x00000000}, |
83 | {0x00000085, 0x00000001}, |
83 | {0x00000085, 0x00000001}, |
84 | {0x00000086, 0x00000002}, |
84 | {0x00000086, 0x00000002}, |
85 | {0x00000087, 0x48490000}, |
85 | {0x00000087, 0x48490000}, |
86 | {0x00000088, 0x20244647}, |
86 | {0x00000088, 0x20244647}, |
87 | {0x00000089, 0x00000005}, |
87 | {0x00000089, 0x00000005}, |
88 | {0x0000008b, 0x66030000}, |
88 | {0x0000008b, 0x66030000}, |
89 | {0x0000008c, 0x00006603}, |
89 | {0x0000008c, 0x00006603}, |
90 | {0x0000008d, 0x00000100}, |
90 | {0x0000008d, 0x00000100}, |
91 | {0x0000008f, 0x00001c0a}, |
91 | {0x0000008f, 0x00001c0a}, |
92 | {0x00000090, 0xff000001}, |
92 | {0x00000090, 0xff000001}, |
93 | {0x00000094, 0x00101101}, |
93 | {0x00000094, 0x00101101}, |
94 | {0x00000095, 0x00000fff}, |
94 | {0x00000095, 0x00000fff}, |
95 | {0x00000096, 0x00116fff}, |
95 | {0x00000096, 0x00116fff}, |
96 | {0x00000097, 0x60010000}, |
96 | {0x00000097, 0x60010000}, |
97 | {0x00000098, 0x10010000}, |
97 | {0x00000098, 0x10010000}, |
98 | {0x00000099, 0x00006000}, |
98 | {0x00000099, 0x00006000}, |
99 | {0x0000009a, 0x00001000}, |
99 | {0x0000009a, 0x00001000}, |
100 | {0x0000009f, 0x00946a00} |
100 | {0x0000009f, 0x00946a00} |
101 | }; |
101 | }; |
102 | 102 | ||
103 | static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
103 | static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
104 | {0x00000077, 0xff010100}, |
104 | {0x00000077, 0xff010100}, |
105 | {0x00000078, 0x00000000}, |
105 | {0x00000078, 0x00000000}, |
106 | {0x00000079, 0x00001434}, |
106 | {0x00000079, 0x00001434}, |
107 | {0x0000007a, 0xcc08ec08}, |
107 | {0x0000007a, 0xcc08ec08}, |
108 | {0x0000007b, 0x00040000}, |
108 | {0x0000007b, 0x00040000}, |
109 | {0x0000007c, 0x000080c0}, |
109 | {0x0000007c, 0x000080c0}, |
110 | {0x0000007d, 0x09000000}, |
110 | {0x0000007d, 0x09000000}, |
111 | {0x0000007e, 0x00210404}, |
111 | {0x0000007e, 0x00210404}, |
112 | {0x00000081, 0x08a8e800}, |
112 | {0x00000081, 0x08a8e800}, |
113 | {0x00000082, 0x00030444}, |
113 | {0x00000082, 0x00030444}, |
114 | {0x00000083, 0x00000000}, |
114 | {0x00000083, 0x00000000}, |
115 | {0x00000085, 0x00000001}, |
115 | {0x00000085, 0x00000001}, |
116 | {0x00000086, 0x00000002}, |
116 | {0x00000086, 0x00000002}, |
117 | {0x00000087, 0x48490000}, |
117 | {0x00000087, 0x48490000}, |
118 | {0x00000088, 0x20244647}, |
118 | {0x00000088, 0x20244647}, |
119 | {0x00000089, 0x00000005}, |
119 | {0x00000089, 0x00000005}, |
120 | {0x0000008b, 0x66030000}, |
120 | {0x0000008b, 0x66030000}, |
121 | {0x0000008c, 0x00006603}, |
121 | {0x0000008c, 0x00006603}, |
122 | {0x0000008d, 0x00000100}, |
122 | {0x0000008d, 0x00000100}, |
123 | {0x0000008f, 0x00001c0a}, |
123 | {0x0000008f, 0x00001c0a}, |
124 | {0x00000090, 0xff000001}, |
124 | {0x00000090, 0xff000001}, |
125 | {0x00000094, 0x00101101}, |
125 | {0x00000094, 0x00101101}, |
126 | {0x00000095, 0x00000fff}, |
126 | {0x00000095, 0x00000fff}, |
127 | {0x00000096, 0x00116fff}, |
127 | {0x00000096, 0x00116fff}, |
128 | {0x00000097, 0x60010000}, |
128 | {0x00000097, 0x60010000}, |
129 | {0x00000098, 0x10010000}, |
129 | {0x00000098, 0x10010000}, |
130 | {0x00000099, 0x00006000}, |
130 | {0x00000099, 0x00006000}, |
131 | {0x0000009a, 0x00001000}, |
131 | {0x0000009a, 0x00001000}, |
132 | {0x0000009f, 0x00936a00} |
132 | {0x0000009f, 0x00936a00} |
133 | }; |
133 | }; |
134 | 134 | ||
135 | static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
135 | static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
136 | {0x00000077, 0xff010100}, |
136 | {0x00000077, 0xff010100}, |
137 | {0x00000078, 0x00000000}, |
137 | {0x00000078, 0x00000000}, |
138 | {0x00000079, 0x00001434}, |
138 | {0x00000079, 0x00001434}, |
139 | {0x0000007a, 0xcc08ec08}, |
139 | {0x0000007a, 0xcc08ec08}, |
140 | {0x0000007b, 0x00040000}, |
140 | {0x0000007b, 0x00040000}, |
141 | {0x0000007c, 0x000080c0}, |
141 | {0x0000007c, 0x000080c0}, |
142 | {0x0000007d, 0x09000000}, |
142 | {0x0000007d, 0x09000000}, |
143 | {0x0000007e, 0x00210404}, |
143 | {0x0000007e, 0x00210404}, |
144 | {0x00000081, 0x08a8e800}, |
144 | {0x00000081, 0x08a8e800}, |
145 | {0x00000082, 0x00030444}, |
145 | {0x00000082, 0x00030444}, |
146 | {0x00000083, 0x00000000}, |
146 | {0x00000083, 0x00000000}, |
147 | {0x00000085, 0x00000001}, |
147 | {0x00000085, 0x00000001}, |
148 | {0x00000086, 0x00000002}, |
148 | {0x00000086, 0x00000002}, |
149 | {0x00000087, 0x48490000}, |
149 | {0x00000087, 0x48490000}, |
150 | {0x00000088, 0x20244647}, |
150 | {0x00000088, 0x20244647}, |
151 | {0x00000089, 0x00000005}, |
151 | {0x00000089, 0x00000005}, |
152 | {0x0000008b, 0x66030000}, |
152 | {0x0000008b, 0x66030000}, |
153 | {0x0000008c, 0x00006603}, |
153 | {0x0000008c, 0x00006603}, |
154 | {0x0000008d, 0x00000100}, |
154 | {0x0000008d, 0x00000100}, |
155 | {0x0000008f, 0x00001c0a}, |
155 | {0x0000008f, 0x00001c0a}, |
156 | {0x00000090, 0xff000001}, |
156 | {0x00000090, 0xff000001}, |
157 | {0x00000094, 0x00101101}, |
157 | {0x00000094, 0x00101101}, |
158 | {0x00000095, 0x00000fff}, |
158 | {0x00000095, 0x00000fff}, |
159 | {0x00000096, 0x00116fff}, |
159 | {0x00000096, 0x00116fff}, |
160 | {0x00000097, 0x60010000}, |
160 | {0x00000097, 0x60010000}, |
161 | {0x00000098, 0x10010000}, |
161 | {0x00000098, 0x10010000}, |
162 | {0x00000099, 0x00006000}, |
162 | {0x00000099, 0x00006000}, |
163 | {0x0000009a, 0x00001000}, |
163 | {0x0000009a, 0x00001000}, |
164 | {0x0000009f, 0x00916a00} |
164 | {0x0000009f, 0x00916a00} |
165 | }; |
165 | }; |
166 | 166 | ||
167 | static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
167 | static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { |
168 | {0x00000077, 0xff010100}, |
168 | {0x00000077, 0xff010100}, |
169 | {0x00000078, 0x00000000}, |
169 | {0x00000078, 0x00000000}, |
170 | {0x00000079, 0x00001434}, |
170 | {0x00000079, 0x00001434}, |
171 | {0x0000007a, 0xcc08ec08}, |
171 | {0x0000007a, 0xcc08ec08}, |
172 | {0x0000007b, 0x00040000}, |
172 | {0x0000007b, 0x00040000}, |
173 | {0x0000007c, 0x000080c0}, |
173 | {0x0000007c, 0x000080c0}, |
174 | {0x0000007d, 0x09000000}, |
174 | {0x0000007d, 0x09000000}, |
175 | {0x0000007e, 0x00210404}, |
175 | {0x0000007e, 0x00210404}, |
176 | {0x00000081, 0x08a8e800}, |
176 | {0x00000081, 0x08a8e800}, |
177 | {0x00000082, 0x00030444}, |
177 | {0x00000082, 0x00030444}, |
178 | {0x00000083, 0x00000000}, |
178 | {0x00000083, 0x00000000}, |
179 | {0x00000085, 0x00000001}, |
179 | {0x00000085, 0x00000001}, |
180 | {0x00000086, 0x00000002}, |
180 | {0x00000086, 0x00000002}, |
181 | {0x00000087, 0x48490000}, |
181 | {0x00000087, 0x48490000}, |
182 | {0x00000088, 0x20244647}, |
182 | {0x00000088, 0x20244647}, |
183 | {0x00000089, 0x00000005}, |
183 | {0x00000089, 0x00000005}, |
184 | {0x0000008b, 0x66030000}, |
184 | {0x0000008b, 0x66030000}, |
185 | {0x0000008c, 0x00006603}, |
185 | {0x0000008c, 0x00006603}, |
186 | {0x0000008d, 0x00000100}, |
186 | {0x0000008d, 0x00000100}, |
187 | {0x0000008f, 0x00001c0a}, |
187 | {0x0000008f, 0x00001c0a}, |
188 | {0x00000090, 0xff000001}, |
188 | {0x00000090, 0xff000001}, |
189 | {0x00000094, 0x00101101}, |
189 | {0x00000094, 0x00101101}, |
190 | {0x00000095, 0x00000fff}, |
190 | {0x00000095, 0x00000fff}, |
191 | {0x00000096, 0x00116fff}, |
191 | {0x00000096, 0x00116fff}, |
192 | {0x00000097, 0x60010000}, |
192 | {0x00000097, 0x60010000}, |
193 | {0x00000098, 0x10010000}, |
193 | {0x00000098, 0x10010000}, |
194 | {0x00000099, 0x00006000}, |
194 | {0x00000099, 0x00006000}, |
195 | {0x0000009a, 0x00001000}, |
195 | {0x0000009a, 0x00001000}, |
196 | {0x0000009f, 0x00976b00} |
196 | {0x0000009f, 0x00976b00} |
197 | }; |
197 | }; |
198 | 198 | ||
199 | int ni_mc_load_microcode(struct radeon_device *rdev) |
199 | int ni_mc_load_microcode(struct radeon_device *rdev) |
200 | { |
200 | { |
201 | const __be32 *fw_data; |
201 | const __be32 *fw_data; |
202 | u32 mem_type, running, blackout = 0; |
202 | u32 mem_type, running, blackout = 0; |
203 | u32 *io_mc_regs; |
203 | u32 *io_mc_regs; |
204 | int i, ucode_size, regs_size; |
204 | int i, ucode_size, regs_size; |
205 | 205 | ||
206 | if (!rdev->mc_fw) |
206 | if (!rdev->mc_fw) |
207 | return -EINVAL; |
207 | return -EINVAL; |
208 | 208 | ||
209 | switch (rdev->family) { |
209 | switch (rdev->family) { |
210 | case CHIP_BARTS: |
210 | case CHIP_BARTS: |
211 | io_mc_regs = (u32 *)&barts_io_mc_regs; |
211 | io_mc_regs = (u32 *)&barts_io_mc_regs; |
212 | ucode_size = BTC_MC_UCODE_SIZE; |
212 | ucode_size = BTC_MC_UCODE_SIZE; |
213 | regs_size = BTC_IO_MC_REGS_SIZE; |
213 | regs_size = BTC_IO_MC_REGS_SIZE; |
214 | break; |
214 | break; |
215 | case CHIP_TURKS: |
215 | case CHIP_TURKS: |
216 | io_mc_regs = (u32 *)&turks_io_mc_regs; |
216 | io_mc_regs = (u32 *)&turks_io_mc_regs; |
217 | ucode_size = BTC_MC_UCODE_SIZE; |
217 | ucode_size = BTC_MC_UCODE_SIZE; |
218 | regs_size = BTC_IO_MC_REGS_SIZE; |
218 | regs_size = BTC_IO_MC_REGS_SIZE; |
219 | break; |
219 | break; |
220 | case CHIP_CAICOS: |
220 | case CHIP_CAICOS: |
221 | default: |
221 | default: |
222 | io_mc_regs = (u32 *)&caicos_io_mc_regs; |
222 | io_mc_regs = (u32 *)&caicos_io_mc_regs; |
223 | ucode_size = BTC_MC_UCODE_SIZE; |
223 | ucode_size = BTC_MC_UCODE_SIZE; |
224 | regs_size = BTC_IO_MC_REGS_SIZE; |
224 | regs_size = BTC_IO_MC_REGS_SIZE; |
225 | break; |
225 | break; |
226 | case CHIP_CAYMAN: |
226 | case CHIP_CAYMAN: |
227 | io_mc_regs = (u32 *)&cayman_io_mc_regs; |
227 | io_mc_regs = (u32 *)&cayman_io_mc_regs; |
228 | ucode_size = CAYMAN_MC_UCODE_SIZE; |
228 | ucode_size = CAYMAN_MC_UCODE_SIZE; |
229 | regs_size = BTC_IO_MC_REGS_SIZE; |
229 | regs_size = BTC_IO_MC_REGS_SIZE; |
230 | break; |
230 | break; |
231 | } |
231 | } |
232 | 232 | ||
233 | mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; |
233 | mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; |
234 | running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; |
234 | running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; |
235 | 235 | ||
236 | if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) { |
236 | if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) { |
237 | if (running) { |
237 | if (running) { |
238 | blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); |
238 | blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); |
239 | WREG32(MC_SHARED_BLACKOUT_CNTL, 1); |
239 | WREG32(MC_SHARED_BLACKOUT_CNTL, 1); |
240 | } |
240 | } |
241 | 241 | ||
242 | /* reset the engine and set to writable */ |
242 | /* reset the engine and set to writable */ |
243 | WREG32(MC_SEQ_SUP_CNTL, 0x00000008); |
243 | WREG32(MC_SEQ_SUP_CNTL, 0x00000008); |
244 | WREG32(MC_SEQ_SUP_CNTL, 0x00000010); |
244 | WREG32(MC_SEQ_SUP_CNTL, 0x00000010); |
245 | 245 | ||
246 | /* load mc io regs */ |
246 | /* load mc io regs */ |
247 | for (i = 0; i < regs_size; i++) { |
247 | for (i = 0; i < regs_size; i++) { |
248 | WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); |
248 | WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); |
249 | WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); |
249 | WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); |
250 | } |
250 | } |
251 | /* load the MC ucode */ |
251 | /* load the MC ucode */ |
252 | fw_data = (const __be32 *)rdev->mc_fw->data; |
252 | fw_data = (const __be32 *)rdev->mc_fw->data; |
253 | for (i = 0; i < ucode_size; i++) |
253 | for (i = 0; i < ucode_size; i++) |
254 | WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); |
254 | WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); |
255 | 255 | ||
256 | /* put the engine back into the active state */ |
256 | /* put the engine back into the active state */ |
257 | WREG32(MC_SEQ_SUP_CNTL, 0x00000008); |
257 | WREG32(MC_SEQ_SUP_CNTL, 0x00000008); |
258 | WREG32(MC_SEQ_SUP_CNTL, 0x00000004); |
258 | WREG32(MC_SEQ_SUP_CNTL, 0x00000004); |
259 | WREG32(MC_SEQ_SUP_CNTL, 0x00000001); |
259 | WREG32(MC_SEQ_SUP_CNTL, 0x00000001); |
260 | 260 | ||
261 | /* wait for training to complete */ |
261 | /* wait for training to complete */ |
262 | while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)) |
262 | while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)) |
263 | udelay(10); |
263 | udelay(10); |
264 | 264 | ||
265 | if (running) |
265 | if (running) |
266 | WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); |
266 | WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); |
267 | } |
267 | } |
268 | 268 | ||
269 | return 0; |
269 | return 0; |
270 | } |
270 | } |
271 | 271 | ||
272 | int ni_init_microcode(struct radeon_device *rdev) |
272 | int ni_init_microcode(struct radeon_device *rdev) |
273 | { |
273 | { |
274 | struct platform_device *pdev; |
274 | struct platform_device *pdev; |
275 | const char *chip_name; |
275 | const char *chip_name; |
276 | const char *rlc_chip_name; |
276 | const char *rlc_chip_name; |
277 | size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size; |
277 | size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size; |
278 | char fw_name[30]; |
278 | char fw_name[30]; |
279 | int err; |
279 | int err; |
280 | 280 | ||
281 | DRM_DEBUG("\n"); |
281 | DRM_DEBUG("\n"); |
282 | 282 | ||
283 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
283 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
284 | err = IS_ERR(pdev); |
284 | err = IS_ERR(pdev); |
285 | if (err) { |
285 | if (err) { |
286 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
286 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
287 | return -EINVAL; |
287 | return -EINVAL; |
288 | } |
288 | } |
289 | 289 | ||
290 | switch (rdev->family) { |
290 | switch (rdev->family) { |
291 | case CHIP_BARTS: |
291 | case CHIP_BARTS: |
292 | chip_name = "BARTS"; |
292 | chip_name = "BARTS"; |
293 | rlc_chip_name = "BTC"; |
293 | rlc_chip_name = "BTC"; |
294 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
294 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
295 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
295 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
296 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
296 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
297 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
297 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
298 | break; |
298 | break; |
299 | case CHIP_TURKS: |
299 | case CHIP_TURKS: |
300 | chip_name = "TURKS"; |
300 | chip_name = "TURKS"; |
301 | rlc_chip_name = "BTC"; |
301 | rlc_chip_name = "BTC"; |
302 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
302 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
303 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
303 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
304 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
304 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
305 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
305 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
306 | break; |
306 | break; |
307 | case CHIP_CAICOS: |
307 | case CHIP_CAICOS: |
308 | chip_name = "CAICOS"; |
308 | chip_name = "CAICOS"; |
309 | rlc_chip_name = "BTC"; |
309 | rlc_chip_name = "BTC"; |
310 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
310 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
311 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
311 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
312 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
312 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
313 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
313 | mc_req_size = BTC_MC_UCODE_SIZE * 4; |
314 | break; |
314 | break; |
315 | case CHIP_CAYMAN: |
315 | case CHIP_CAYMAN: |
316 | chip_name = "CAYMAN"; |
316 | chip_name = "CAYMAN"; |
317 | rlc_chip_name = "CAYMAN"; |
317 | rlc_chip_name = "CAYMAN"; |
318 | pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; |
318 | pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; |
319 | me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; |
319 | me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; |
320 | rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; |
320 | rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; |
321 | mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; |
321 | mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; |
322 | break; |
322 | break; |
323 | default: BUG(); |
323 | default: BUG(); |
324 | } |
324 | } |
325 | 325 | ||
326 | DRM_INFO("Loading %s Microcode\n", chip_name); |
326 | DRM_INFO("Loading %s Microcode\n", chip_name); |
327 | 327 | ||
328 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); |
328 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); |
329 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); |
329 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); |
330 | if (err) |
330 | if (err) |
331 | goto out; |
331 | goto out; |
332 | if (rdev->pfp_fw->size != pfp_req_size) { |
332 | if (rdev->pfp_fw->size != pfp_req_size) { |
333 | printk(KERN_ERR |
333 | printk(KERN_ERR |
334 | "ni_cp: Bogus length %zu in firmware \"%s\"\n", |
334 | "ni_cp: Bogus length %zu in firmware \"%s\"\n", |
335 | rdev->pfp_fw->size, fw_name); |
335 | rdev->pfp_fw->size, fw_name); |
336 | err = -EINVAL; |
336 | err = -EINVAL; |
337 | goto out; |
337 | goto out; |
338 | } |
338 | } |
339 | 339 | ||
340 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); |
340 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); |
341 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
341 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
342 | if (err) |
342 | if (err) |
343 | goto out; |
343 | goto out; |
344 | if (rdev->me_fw->size != me_req_size) { |
344 | if (rdev->me_fw->size != me_req_size) { |
345 | printk(KERN_ERR |
345 | printk(KERN_ERR |
346 | "ni_cp: Bogus length %zu in firmware \"%s\"\n", |
346 | "ni_cp: Bogus length %zu in firmware \"%s\"\n", |
347 | rdev->me_fw->size, fw_name); |
347 | rdev->me_fw->size, fw_name); |
348 | err = -EINVAL; |
348 | err = -EINVAL; |
349 | } |
349 | } |
350 | 350 | ||
351 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); |
351 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); |
352 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); |
352 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); |
353 | if (err) |
353 | if (err) |
354 | goto out; |
354 | goto out; |
355 | if (rdev->rlc_fw->size != rlc_req_size) { |
355 | if (rdev->rlc_fw->size != rlc_req_size) { |
356 | printk(KERN_ERR |
356 | printk(KERN_ERR |
357 | "ni_rlc: Bogus length %zu in firmware \"%s\"\n", |
357 | "ni_rlc: Bogus length %zu in firmware \"%s\"\n", |
358 | rdev->rlc_fw->size, fw_name); |
358 | rdev->rlc_fw->size, fw_name); |
359 | err = -EINVAL; |
359 | err = -EINVAL; |
360 | } |
360 | } |
361 | 361 | ||
362 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); |
362 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); |
363 | err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev); |
363 | err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev); |
364 | if (err) |
364 | if (err) |
365 | goto out; |
365 | goto out; |
366 | if (rdev->mc_fw->size != mc_req_size) { |
366 | if (rdev->mc_fw->size != mc_req_size) { |
367 | printk(KERN_ERR |
367 | printk(KERN_ERR |
368 | "ni_mc: Bogus length %zu in firmware \"%s\"\n", |
368 | "ni_mc: Bogus length %zu in firmware \"%s\"\n", |
369 | rdev->mc_fw->size, fw_name); |
369 | rdev->mc_fw->size, fw_name); |
370 | err = -EINVAL; |
370 | err = -EINVAL; |
371 | } |
371 | } |
372 | out: |
372 | out: |
373 | platform_device_unregister(pdev); |
373 | platform_device_unregister(pdev); |
374 | 374 | ||
375 | if (err) { |
375 | if (err) { |
376 | if (err != -EINVAL) |
376 | if (err != -EINVAL) |
377 | printk(KERN_ERR |
377 | printk(KERN_ERR |
378 | "ni_cp: Failed to load firmware \"%s\"\n", |
378 | "ni_cp: Failed to load firmware \"%s\"\n", |
379 | fw_name); |
379 | fw_name); |
380 | release_firmware(rdev->pfp_fw); |
380 | release_firmware(rdev->pfp_fw); |
381 | rdev->pfp_fw = NULL; |
381 | rdev->pfp_fw = NULL; |
382 | release_firmware(rdev->me_fw); |
382 | release_firmware(rdev->me_fw); |
383 | rdev->me_fw = NULL; |
383 | rdev->me_fw = NULL; |
384 | release_firmware(rdev->rlc_fw); |
384 | release_firmware(rdev->rlc_fw); |
385 | rdev->rlc_fw = NULL; |
385 | rdev->rlc_fw = NULL; |
386 | release_firmware(rdev->mc_fw); |
386 | release_firmware(rdev->mc_fw); |
387 | rdev->mc_fw = NULL; |
387 | rdev->mc_fw = NULL; |
388 | } |
388 | } |
389 | return err; |
389 | return err; |
390 | } |
390 | } |
391 | 391 | ||
392 | /* |
392 | /* |
393 | * Core functions |
393 | * Core functions |
394 | */ |
394 | */ |
395 | static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, |
395 | static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, |
396 | u32 num_tile_pipes, |
396 | u32 num_tile_pipes, |
397 | u32 num_backends_per_asic, |
397 | u32 num_backends_per_asic, |
398 | u32 *backend_disable_mask_per_asic, |
398 | u32 *backend_disable_mask_per_asic, |
399 | u32 num_shader_engines) |
399 | u32 num_shader_engines) |
400 | { |
400 | { |
401 | u32 backend_map = 0; |
401 | u32 backend_map = 0; |
402 | u32 enabled_backends_mask = 0; |
402 | u32 enabled_backends_mask = 0; |
403 | u32 enabled_backends_count = 0; |
403 | u32 enabled_backends_count = 0; |
404 | u32 num_backends_per_se; |
404 | u32 num_backends_per_se; |
405 | u32 cur_pipe; |
405 | u32 cur_pipe; |
406 | u32 swizzle_pipe[CAYMAN_MAX_PIPES]; |
406 | u32 swizzle_pipe[CAYMAN_MAX_PIPES]; |
407 | u32 cur_backend = 0; |
407 | u32 cur_backend = 0; |
408 | u32 i; |
408 | u32 i; |
409 | bool force_no_swizzle; |
409 | bool force_no_swizzle; |
410 | 410 | ||
411 | /* force legal values */ |
411 | /* force legal values */ |
412 | if (num_tile_pipes < 1) |
412 | if (num_tile_pipes < 1) |
413 | num_tile_pipes = 1; |
413 | num_tile_pipes = 1; |
414 | if (num_tile_pipes > rdev->config.cayman.max_tile_pipes) |
414 | if (num_tile_pipes > rdev->config.cayman.max_tile_pipes) |
415 | num_tile_pipes = rdev->config.cayman.max_tile_pipes; |
415 | num_tile_pipes = rdev->config.cayman.max_tile_pipes; |
416 | if (num_shader_engines < 1) |
416 | if (num_shader_engines < 1) |
417 | num_shader_engines = 1; |
417 | num_shader_engines = 1; |
418 | if (num_shader_engines > rdev->config.cayman.max_shader_engines) |
418 | if (num_shader_engines > rdev->config.cayman.max_shader_engines) |
419 | num_shader_engines = rdev->config.cayman.max_shader_engines; |
419 | num_shader_engines = rdev->config.cayman.max_shader_engines; |
420 | if (num_backends_per_asic < num_shader_engines) |
420 | if (num_backends_per_asic < num_shader_engines) |
421 | num_backends_per_asic = num_shader_engines; |
421 | num_backends_per_asic = num_shader_engines; |
422 | if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines)) |
422 | if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines)) |
423 | num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines; |
423 | num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines; |
424 | 424 | ||
425 | /* make sure we have the same number of backends per se */ |
425 | /* make sure we have the same number of backends per se */ |
426 | num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines); |
426 | num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines); |
427 | /* set up the number of backends per se */ |
427 | /* set up the number of backends per se */ |
428 | num_backends_per_se = num_backends_per_asic / num_shader_engines; |
428 | num_backends_per_se = num_backends_per_asic / num_shader_engines; |
429 | if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) { |
429 | if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) { |
430 | num_backends_per_se = rdev->config.cayman.max_backends_per_se; |
430 | num_backends_per_se = rdev->config.cayman.max_backends_per_se; |
431 | num_backends_per_asic = num_backends_per_se * num_shader_engines; |
431 | num_backends_per_asic = num_backends_per_se * num_shader_engines; |
432 | } |
432 | } |
433 | 433 | ||
434 | /* create enable mask and count for enabled backends */ |
434 | /* create enable mask and count for enabled backends */ |
435 | for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { |
435 | for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { |
436 | if (((*backend_disable_mask_per_asic >> i) & 1) == 0) { |
436 | if (((*backend_disable_mask_per_asic >> i) & 1) == 0) { |
437 | enabled_backends_mask |= (1 << i); |
437 | enabled_backends_mask |= (1 << i); |
438 | ++enabled_backends_count; |
438 | ++enabled_backends_count; |
439 | } |
439 | } |
440 | if (enabled_backends_count == num_backends_per_asic) |
440 | if (enabled_backends_count == num_backends_per_asic) |
441 | break; |
441 | break; |
442 | } |
442 | } |
443 | 443 | ||
444 | /* force the backends mask to match the current number of backends */ |
444 | /* force the backends mask to match the current number of backends */ |
445 | if (enabled_backends_count != num_backends_per_asic) { |
445 | if (enabled_backends_count != num_backends_per_asic) { |
446 | u32 this_backend_enabled; |
446 | u32 this_backend_enabled; |
447 | u32 shader_engine; |
447 | u32 shader_engine; |
448 | u32 backend_per_se; |
448 | u32 backend_per_se; |
449 | 449 | ||
450 | enabled_backends_mask = 0; |
450 | enabled_backends_mask = 0; |
451 | enabled_backends_count = 0; |
451 | enabled_backends_count = 0; |
452 | *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK; |
452 | *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK; |
453 | for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { |
453 | for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { |
454 | /* calc the current se */ |
454 | /* calc the current se */ |
455 | shader_engine = i / rdev->config.cayman.max_backends_per_se; |
455 | shader_engine = i / rdev->config.cayman.max_backends_per_se; |
456 | /* calc the backend per se */ |
456 | /* calc the backend per se */ |
457 | backend_per_se = i % rdev->config.cayman.max_backends_per_se; |
457 | backend_per_se = i % rdev->config.cayman.max_backends_per_se; |
458 | /* default to not enabled */ |
458 | /* default to not enabled */ |
459 | this_backend_enabled = 0; |
459 | this_backend_enabled = 0; |
460 | if ((shader_engine < num_shader_engines) && |
460 | if ((shader_engine < num_shader_engines) && |
461 | (backend_per_se < num_backends_per_se)) |
461 | (backend_per_se < num_backends_per_se)) |
462 | this_backend_enabled = 1; |
462 | this_backend_enabled = 1; |
463 | if (this_backend_enabled) { |
463 | if (this_backend_enabled) { |
464 | enabled_backends_mask |= (1 << i); |
464 | enabled_backends_mask |= (1 << i); |
465 | *backend_disable_mask_per_asic &= ~(1 << i); |
465 | *backend_disable_mask_per_asic &= ~(1 << i); |
466 | ++enabled_backends_count; |
466 | ++enabled_backends_count; |
467 | } |
467 | } |
468 | } |
468 | } |
469 | } |
469 | } |
470 | 470 | ||
471 | 471 | ||
472 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES); |
472 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES); |
473 | switch (rdev->family) { |
473 | switch (rdev->family) { |
474 | case CHIP_CAYMAN: |
474 | case CHIP_CAYMAN: |
475 | force_no_swizzle = true; |
475 | force_no_swizzle = true; |
476 | break; |
476 | break; |
477 | default: |
477 | default: |
478 | force_no_swizzle = false; |
478 | force_no_swizzle = false; |
479 | break; |
479 | break; |
480 | } |
480 | } |
481 | if (force_no_swizzle) { |
481 | if (force_no_swizzle) { |
482 | bool last_backend_enabled = false; |
482 | bool last_backend_enabled = false; |
483 | 483 | ||
484 | force_no_swizzle = false; |
484 | force_no_swizzle = false; |
485 | for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { |
485 | for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { |
486 | if (((enabled_backends_mask >> i) & 1) == 1) { |
486 | if (((enabled_backends_mask >> i) & 1) == 1) { |
487 | if (last_backend_enabled) |
487 | if (last_backend_enabled) |
488 | force_no_swizzle = true; |
488 | force_no_swizzle = true; |
489 | last_backend_enabled = true; |
489 | last_backend_enabled = true; |
490 | } else |
490 | } else |
491 | last_backend_enabled = false; |
491 | last_backend_enabled = false; |
492 | } |
492 | } |
493 | } |
493 | } |
494 | 494 | ||
495 | switch (num_tile_pipes) { |
495 | switch (num_tile_pipes) { |
496 | case 1: |
496 | case 1: |
497 | case 3: |
497 | case 3: |
498 | case 5: |
498 | case 5: |
499 | case 7: |
499 | case 7: |
500 | DRM_ERROR("odd number of pipes!\n"); |
500 | DRM_ERROR("odd number of pipes!\n"); |
501 | break; |
501 | break; |
502 | case 2: |
502 | case 2: |
503 | swizzle_pipe[0] = 0; |
503 | swizzle_pipe[0] = 0; |
504 | swizzle_pipe[1] = 1; |
504 | swizzle_pipe[1] = 1; |
505 | break; |
505 | break; |
506 | case 4: |
506 | case 4: |
507 | if (force_no_swizzle) { |
507 | if (force_no_swizzle) { |
508 | swizzle_pipe[0] = 0; |
508 | swizzle_pipe[0] = 0; |
509 | swizzle_pipe[1] = 1; |
509 | swizzle_pipe[1] = 1; |
510 | swizzle_pipe[2] = 2; |
510 | swizzle_pipe[2] = 2; |
511 | swizzle_pipe[3] = 3; |
511 | swizzle_pipe[3] = 3; |
512 | } else { |
512 | } else { |
513 | swizzle_pipe[0] = 0; |
513 | swizzle_pipe[0] = 0; |
514 | swizzle_pipe[1] = 2; |
514 | swizzle_pipe[1] = 2; |
515 | swizzle_pipe[2] = 1; |
515 | swizzle_pipe[2] = 1; |
516 | swizzle_pipe[3] = 3; |
516 | swizzle_pipe[3] = 3; |
517 | } |
517 | } |
518 | break; |
518 | break; |
519 | case 6: |
519 | case 6: |
520 | if (force_no_swizzle) { |
520 | if (force_no_swizzle) { |
521 | swizzle_pipe[0] = 0; |
521 | swizzle_pipe[0] = 0; |
522 | swizzle_pipe[1] = 1; |
522 | swizzle_pipe[1] = 1; |
523 | swizzle_pipe[2] = 2; |
523 | swizzle_pipe[2] = 2; |
524 | swizzle_pipe[3] = 3; |
524 | swizzle_pipe[3] = 3; |
525 | swizzle_pipe[4] = 4; |
525 | swizzle_pipe[4] = 4; |
526 | swizzle_pipe[5] = 5; |
526 | swizzle_pipe[5] = 5; |
527 | } else { |
527 | } else { |
528 | swizzle_pipe[0] = 0; |
528 | swizzle_pipe[0] = 0; |
529 | swizzle_pipe[1] = 2; |
529 | swizzle_pipe[1] = 2; |
530 | swizzle_pipe[2] = 4; |
530 | swizzle_pipe[2] = 4; |
531 | swizzle_pipe[3] = 1; |
531 | swizzle_pipe[3] = 1; |
532 | swizzle_pipe[4] = 3; |
532 | swizzle_pipe[4] = 3; |
533 | swizzle_pipe[5] = 5; |
533 | swizzle_pipe[5] = 5; |
534 | } |
534 | } |
535 | break; |
535 | break; |
536 | case 8: |
536 | case 8: |
537 | if (force_no_swizzle) { |
537 | if (force_no_swizzle) { |
538 | swizzle_pipe[0] = 0; |
538 | swizzle_pipe[0] = 0; |
539 | swizzle_pipe[1] = 1; |
539 | swizzle_pipe[1] = 1; |
540 | swizzle_pipe[2] = 2; |
540 | swizzle_pipe[2] = 2; |
541 | swizzle_pipe[3] = 3; |
541 | swizzle_pipe[3] = 3; |
542 | swizzle_pipe[4] = 4; |
542 | swizzle_pipe[4] = 4; |
543 | swizzle_pipe[5] = 5; |
543 | swizzle_pipe[5] = 5; |
544 | swizzle_pipe[6] = 6; |
544 | swizzle_pipe[6] = 6; |
545 | swizzle_pipe[7] = 7; |
545 | swizzle_pipe[7] = 7; |
546 | } else { |
546 | } else { |
547 | swizzle_pipe[0] = 0; |
547 | swizzle_pipe[0] = 0; |
548 | swizzle_pipe[1] = 2; |
548 | swizzle_pipe[1] = 2; |
549 | swizzle_pipe[2] = 4; |
549 | swizzle_pipe[2] = 4; |
550 | swizzle_pipe[3] = 6; |
550 | swizzle_pipe[3] = 6; |
551 | swizzle_pipe[4] = 1; |
551 | swizzle_pipe[4] = 1; |
552 | swizzle_pipe[5] = 3; |
552 | swizzle_pipe[5] = 3; |
553 | swizzle_pipe[6] = 5; |
553 | swizzle_pipe[6] = 5; |
554 | swizzle_pipe[7] = 7; |
554 | swizzle_pipe[7] = 7; |
555 | } |
555 | } |
556 | break; |
556 | break; |
557 | } |
557 | } |
558 | 558 | ||
559 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { |
559 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { |
560 | while (((1 << cur_backend) & enabled_backends_mask) == 0) |
560 | while (((1 << cur_backend) & enabled_backends_mask) == 0) |
561 | cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; |
561 | cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; |
562 | 562 | ||
563 | backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); |
563 | backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); |
564 | 564 | ||
565 | cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; |
565 | cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; |
566 | } |
566 | } |
567 | 567 | ||
568 | return backend_map; |
568 | return backend_map; |
569 | } |
569 | } |
570 | 570 | ||
571 | static void cayman_program_channel_remap(struct radeon_device *rdev) |
571 | static void cayman_program_channel_remap(struct radeon_device *rdev) |
572 | { |
572 | { |
573 | u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp; |
573 | u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp; |
574 | 574 | ||
575 | tmp = RREG32(MC_SHARED_CHMAP); |
575 | tmp = RREG32(MC_SHARED_CHMAP); |
576 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
576 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
577 | case 0: |
577 | case 0: |
578 | case 1: |
578 | case 1: |
579 | case 2: |
579 | case 2: |
580 | case 3: |
580 | case 3: |
581 | default: |
581 | default: |
582 | /* default mapping */ |
582 | /* default mapping */ |
583 | mc_shared_chremap = 0x00fac688; |
583 | mc_shared_chremap = 0x00fac688; |
584 | break; |
584 | break; |
585 | } |
585 | } |
586 | 586 | ||
587 | switch (rdev->family) { |
587 | switch (rdev->family) { |
588 | case CHIP_CAYMAN: |
588 | case CHIP_CAYMAN: |
589 | default: |
589 | default: |
590 | //tcp_chan_steer_lo = 0x54763210 |
590 | //tcp_chan_steer_lo = 0x54763210 |
591 | tcp_chan_steer_lo = 0x76543210; |
591 | tcp_chan_steer_lo = 0x76543210; |
592 | tcp_chan_steer_hi = 0x0000ba98; |
592 | tcp_chan_steer_hi = 0x0000ba98; |
593 | break; |
593 | break; |
594 | } |
594 | } |
595 | 595 | ||
596 | WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo); |
596 | WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo); |
597 | WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi); |
597 | WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi); |
598 | WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); |
598 | WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); |
599 | } |
599 | } |
600 | 600 | ||
601 | static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev, |
601 | static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev, |
602 | u32 disable_mask_per_se, |
602 | u32 disable_mask_per_se, |
603 | u32 max_disable_mask_per_se, |
603 | u32 max_disable_mask_per_se, |
604 | u32 num_shader_engines) |
604 | u32 num_shader_engines) |
605 | { |
605 | { |
606 | u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se); |
606 | u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se); |
607 | u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se; |
607 | u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se; |
608 | 608 | ||
609 | if (num_shader_engines == 1) |
609 | if (num_shader_engines == 1) |
610 | return disable_mask_per_asic; |
610 | return disable_mask_per_asic; |
611 | else if (num_shader_engines == 2) |
611 | else if (num_shader_engines == 2) |
612 | return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se); |
612 | return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se); |
613 | else |
613 | else |
614 | return 0xffffffff; |
614 | return 0xffffffff; |
615 | } |
615 | } |
616 | 616 | ||
617 | static void cayman_gpu_init(struct radeon_device *rdev) |
617 | static void cayman_gpu_init(struct radeon_device *rdev) |
618 | { |
618 | { |
619 | u32 cc_rb_backend_disable = 0; |
619 | u32 cc_rb_backend_disable = 0; |
620 | u32 cc_gc_shader_pipe_config; |
620 | u32 cc_gc_shader_pipe_config; |
621 | u32 gb_addr_config = 0; |
621 | u32 gb_addr_config = 0; |
622 | u32 mc_shared_chmap, mc_arb_ramcfg; |
622 | u32 mc_shared_chmap, mc_arb_ramcfg; |
623 | u32 gb_backend_map; |
623 | u32 gb_backend_map; |
624 | u32 cgts_tcc_disable; |
624 | u32 cgts_tcc_disable; |
625 | u32 sx_debug_1; |
625 | u32 sx_debug_1; |
626 | u32 smx_dc_ctl0; |
626 | u32 smx_dc_ctl0; |
627 | u32 gc_user_shader_pipe_config; |
627 | u32 gc_user_shader_pipe_config; |
628 | u32 gc_user_rb_backend_disable; |
628 | u32 gc_user_rb_backend_disable; |
629 | u32 cgts_user_tcc_disable; |
629 | u32 cgts_user_tcc_disable; |
630 | u32 cgts_sm_ctrl_reg; |
630 | u32 cgts_sm_ctrl_reg; |
631 | u32 hdp_host_path_cntl; |
631 | u32 hdp_host_path_cntl; |
632 | u32 tmp; |
632 | u32 tmp; |
633 | int i, j; |
633 | int i, j; |
634 | 634 | ||
635 | switch (rdev->family) { |
635 | switch (rdev->family) { |
636 | case CHIP_CAYMAN: |
636 | case CHIP_CAYMAN: |
637 | default: |
637 | default: |
638 | rdev->config.cayman.max_shader_engines = 2; |
638 | rdev->config.cayman.max_shader_engines = 2; |
639 | rdev->config.cayman.max_pipes_per_simd = 4; |
639 | rdev->config.cayman.max_pipes_per_simd = 4; |
640 | rdev->config.cayman.max_tile_pipes = 8; |
640 | rdev->config.cayman.max_tile_pipes = 8; |
641 | rdev->config.cayman.max_simds_per_se = 12; |
641 | rdev->config.cayman.max_simds_per_se = 12; |
642 | rdev->config.cayman.max_backends_per_se = 4; |
642 | rdev->config.cayman.max_backends_per_se = 4; |
643 | rdev->config.cayman.max_texture_channel_caches = 8; |
643 | rdev->config.cayman.max_texture_channel_caches = 8; |
644 | rdev->config.cayman.max_gprs = 256; |
644 | rdev->config.cayman.max_gprs = 256; |
645 | rdev->config.cayman.max_threads = 256; |
645 | rdev->config.cayman.max_threads = 256; |
646 | rdev->config.cayman.max_gs_threads = 32; |
646 | rdev->config.cayman.max_gs_threads = 32; |
647 | rdev->config.cayman.max_stack_entries = 512; |
647 | rdev->config.cayman.max_stack_entries = 512; |
648 | rdev->config.cayman.sx_num_of_sets = 8; |
648 | rdev->config.cayman.sx_num_of_sets = 8; |
649 | rdev->config.cayman.sx_max_export_size = 256; |
649 | rdev->config.cayman.sx_max_export_size = 256; |
650 | rdev->config.cayman.sx_max_export_pos_size = 64; |
650 | rdev->config.cayman.sx_max_export_pos_size = 64; |
651 | rdev->config.cayman.sx_max_export_smx_size = 192; |
651 | rdev->config.cayman.sx_max_export_smx_size = 192; |
652 | rdev->config.cayman.max_hw_contexts = 8; |
652 | rdev->config.cayman.max_hw_contexts = 8; |
653 | rdev->config.cayman.sq_num_cf_insts = 2; |
653 | rdev->config.cayman.sq_num_cf_insts = 2; |
654 | 654 | ||
655 | rdev->config.cayman.sc_prim_fifo_size = 0x100; |
655 | rdev->config.cayman.sc_prim_fifo_size = 0x100; |
656 | rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; |
656 | rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; |
657 | rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; |
657 | rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; |
658 | break; |
658 | break; |
659 | } |
659 | } |
660 | 660 | ||
661 | /* Initialize HDP */ |
661 | /* Initialize HDP */ |
662 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
662 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
663 | WREG32((0x2c14 + j), 0x00000000); |
663 | WREG32((0x2c14 + j), 0x00000000); |
664 | WREG32((0x2c18 + j), 0x00000000); |
664 | WREG32((0x2c18 + j), 0x00000000); |
665 | WREG32((0x2c1c + j), 0x00000000); |
665 | WREG32((0x2c1c + j), 0x00000000); |
666 | WREG32((0x2c20 + j), 0x00000000); |
666 | WREG32((0x2c20 + j), 0x00000000); |
667 | WREG32((0x2c24 + j), 0x00000000); |
667 | WREG32((0x2c24 + j), 0x00000000); |
668 | } |
668 | } |
669 | 669 | ||
670 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
670 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
671 | 671 | ||
672 | mc_shared_chmap = RREG32(MC_SHARED_CHMAP); |
672 | mc_shared_chmap = RREG32(MC_SHARED_CHMAP); |
673 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
673 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
674 | 674 | ||
675 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE); |
675 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE); |
676 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); |
676 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); |
677 | cgts_tcc_disable = 0xff000000; |
677 | cgts_tcc_disable = 0xff000000; |
678 | gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE); |
678 | gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE); |
679 | gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG); |
679 | gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG); |
680 | cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE); |
680 | cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE); |
681 | 681 | ||
682 | rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines; |
682 | rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines; |
683 | tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; |
683 | tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; |
684 | rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp); |
684 | rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp); |
685 | rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes; |
685 | rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes; |
686 | tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT; |
686 | tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT; |
687 | rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp); |
687 | rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp); |
688 | tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; |
688 | tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; |
689 | rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp); |
689 | rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp); |
690 | tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; |
690 | tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; |
691 | rdev->config.cayman.backend_disable_mask_per_asic = |
691 | rdev->config.cayman.backend_disable_mask_per_asic = |
692 | cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK, |
692 | cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK, |
693 | rdev->config.cayman.num_shader_engines); |
693 | rdev->config.cayman.num_shader_engines); |
694 | rdev->config.cayman.backend_map = |
694 | rdev->config.cayman.backend_map = |
695 | cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, |
695 | cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, |
696 | rdev->config.cayman.num_backends_per_se * |
696 | rdev->config.cayman.num_backends_per_se * |
697 | rdev->config.cayman.num_shader_engines, |
697 | rdev->config.cayman.num_shader_engines, |
698 | &rdev->config.cayman.backend_disable_mask_per_asic, |
698 | &rdev->config.cayman.backend_disable_mask_per_asic, |
699 | rdev->config.cayman.num_shader_engines); |
699 | rdev->config.cayman.num_shader_engines); |
700 | tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT; |
700 | tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT; |
701 | rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp); |
701 | rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp); |
702 | tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT; |
702 | tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT; |
703 | rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; |
703 | rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; |
704 | if (rdev->config.cayman.mem_max_burst_length_bytes > 512) |
704 | if (rdev->config.cayman.mem_max_burst_length_bytes > 512) |
705 | rdev->config.cayman.mem_max_burst_length_bytes = 512; |
705 | rdev->config.cayman.mem_max_burst_length_bytes = 512; |
706 | tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; |
706 | tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; |
707 | rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; |
707 | rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; |
708 | if (rdev->config.cayman.mem_row_size_in_kb > 4) |
708 | if (rdev->config.cayman.mem_row_size_in_kb > 4) |
709 | rdev->config.cayman.mem_row_size_in_kb = 4; |
709 | rdev->config.cayman.mem_row_size_in_kb = 4; |
710 | /* XXX use MC settings? */ |
710 | /* XXX use MC settings? */ |
711 | rdev->config.cayman.shader_engine_tile_size = 32; |
711 | rdev->config.cayman.shader_engine_tile_size = 32; |
712 | rdev->config.cayman.num_gpus = 1; |
712 | rdev->config.cayman.num_gpus = 1; |
713 | rdev->config.cayman.multi_gpu_tile_size = 64; |
713 | rdev->config.cayman.multi_gpu_tile_size = 64; |
714 | 714 | ||
715 | //gb_addr_config = 0x02011003 |
715 | //gb_addr_config = 0x02011003 |
716 | #if 0 |
716 | #if 0 |
717 | gb_addr_config = RREG32(GB_ADDR_CONFIG); |
717 | gb_addr_config = RREG32(GB_ADDR_CONFIG); |
718 | #else |
718 | #else |
719 | gb_addr_config = 0; |
719 | gb_addr_config = 0; |
720 | switch (rdev->config.cayman.num_tile_pipes) { |
720 | switch (rdev->config.cayman.num_tile_pipes) { |
721 | case 1: |
721 | case 1: |
722 | default: |
722 | default: |
723 | gb_addr_config |= NUM_PIPES(0); |
723 | gb_addr_config |= NUM_PIPES(0); |
724 | break; |
724 | break; |
725 | case 2: |
725 | case 2: |
726 | gb_addr_config |= NUM_PIPES(1); |
726 | gb_addr_config |= NUM_PIPES(1); |
727 | break; |
727 | break; |
728 | case 4: |
728 | case 4: |
729 | gb_addr_config |= NUM_PIPES(2); |
729 | gb_addr_config |= NUM_PIPES(2); |
730 | break; |
730 | break; |
731 | case 8: |
731 | case 8: |
732 | gb_addr_config |= NUM_PIPES(3); |
732 | gb_addr_config |= NUM_PIPES(3); |
733 | break; |
733 | break; |
734 | } |
734 | } |
735 | 735 | ||
736 | tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1; |
736 | tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1; |
737 | gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp); |
737 | gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp); |
738 | gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1); |
738 | gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1); |
739 | tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1; |
739 | tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1; |
740 | gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp); |
740 | gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp); |
741 | switch (rdev->config.cayman.num_gpus) { |
741 | switch (rdev->config.cayman.num_gpus) { |
742 | case 1: |
742 | case 1: |
743 | default: |
743 | default: |
744 | gb_addr_config |= NUM_GPUS(0); |
744 | gb_addr_config |= NUM_GPUS(0); |
745 | break; |
745 | break; |
746 | case 2: |
746 | case 2: |
747 | gb_addr_config |= NUM_GPUS(1); |
747 | gb_addr_config |= NUM_GPUS(1); |
748 | break; |
748 | break; |
749 | case 4: |
749 | case 4: |
750 | gb_addr_config |= NUM_GPUS(2); |
750 | gb_addr_config |= NUM_GPUS(2); |
751 | break; |
751 | break; |
752 | } |
752 | } |
753 | switch (rdev->config.cayman.multi_gpu_tile_size) { |
753 | switch (rdev->config.cayman.multi_gpu_tile_size) { |
754 | case 16: |
754 | case 16: |
755 | gb_addr_config |= MULTI_GPU_TILE_SIZE(0); |
755 | gb_addr_config |= MULTI_GPU_TILE_SIZE(0); |
756 | break; |
756 | break; |
757 | case 32: |
757 | case 32: |
758 | default: |
758 | default: |
759 | gb_addr_config |= MULTI_GPU_TILE_SIZE(1); |
759 | gb_addr_config |= MULTI_GPU_TILE_SIZE(1); |
760 | break; |
760 | break; |
761 | case 64: |
761 | case 64: |
762 | gb_addr_config |= MULTI_GPU_TILE_SIZE(2); |
762 | gb_addr_config |= MULTI_GPU_TILE_SIZE(2); |
763 | break; |
763 | break; |
764 | case 128: |
764 | case 128: |
765 | gb_addr_config |= MULTI_GPU_TILE_SIZE(3); |
765 | gb_addr_config |= MULTI_GPU_TILE_SIZE(3); |
766 | break; |
766 | break; |
767 | } |
767 | } |
768 | switch (rdev->config.cayman.mem_row_size_in_kb) { |
768 | switch (rdev->config.cayman.mem_row_size_in_kb) { |
769 | case 1: |
769 | case 1: |
770 | default: |
770 | default: |
771 | gb_addr_config |= ROW_SIZE(0); |
771 | gb_addr_config |= ROW_SIZE(0); |
772 | break; |
772 | break; |
773 | case 2: |
773 | case 2: |
774 | gb_addr_config |= ROW_SIZE(1); |
774 | gb_addr_config |= ROW_SIZE(1); |
775 | break; |
775 | break; |
776 | case 4: |
776 | case 4: |
777 | gb_addr_config |= ROW_SIZE(2); |
777 | gb_addr_config |= ROW_SIZE(2); |
778 | break; |
778 | break; |
779 | } |
779 | } |
780 | #endif |
780 | #endif |
781 | 781 | ||
782 | tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; |
782 | tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; |
783 | rdev->config.cayman.num_tile_pipes = (1 << tmp); |
783 | rdev->config.cayman.num_tile_pipes = (1 << tmp); |
784 | tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; |
784 | tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; |
785 | rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; |
785 | rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; |
786 | tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; |
786 | tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; |
787 | rdev->config.cayman.num_shader_engines = tmp + 1; |
787 | rdev->config.cayman.num_shader_engines = tmp + 1; |
788 | tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; |
788 | tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; |
789 | rdev->config.cayman.num_gpus = tmp + 1; |
789 | rdev->config.cayman.num_gpus = tmp + 1; |
790 | tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; |
790 | tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; |
791 | rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; |
791 | rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; |
792 | tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; |
792 | tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; |
793 | rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; |
793 | rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; |
794 | 794 | ||
795 | //gb_backend_map = 0x76541032; |
795 | //gb_backend_map = 0x76541032; |
796 | #if 0 |
796 | #if 0 |
797 | gb_backend_map = RREG32(GB_BACKEND_MAP); |
797 | gb_backend_map = RREG32(GB_BACKEND_MAP); |
798 | #else |
798 | #else |
799 | gb_backend_map = |
799 | gb_backend_map = |
800 | cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, |
800 | cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, |
801 | rdev->config.cayman.num_backends_per_se * |
801 | rdev->config.cayman.num_backends_per_se * |
802 | rdev->config.cayman.num_shader_engines, |
802 | rdev->config.cayman.num_shader_engines, |
803 | &rdev->config.cayman.backend_disable_mask_per_asic, |
803 | &rdev->config.cayman.backend_disable_mask_per_asic, |
804 | rdev->config.cayman.num_shader_engines); |
804 | rdev->config.cayman.num_shader_engines); |
805 | #endif |
805 | #endif |
806 | /* setup tiling info dword. gb_addr_config is not adequate since it does |
806 | /* setup tiling info dword. gb_addr_config is not adequate since it does |
807 | * not have bank info, so create a custom tiling dword. |
807 | * not have bank info, so create a custom tiling dword. |
808 | * bits 3:0 num_pipes |
808 | * bits 3:0 num_pipes |
809 | * bits 7:4 num_banks |
809 | * bits 7:4 num_banks |
810 | * bits 11:8 group_size |
810 | * bits 11:8 group_size |
811 | * bits 15:12 row_size |
811 | * bits 15:12 row_size |
812 | */ |
812 | */ |
813 | rdev->config.cayman.tile_config = 0; |
813 | rdev->config.cayman.tile_config = 0; |
814 | switch (rdev->config.cayman.num_tile_pipes) { |
814 | switch (rdev->config.cayman.num_tile_pipes) { |
815 | case 1: |
815 | case 1: |
816 | default: |
816 | default: |
817 | rdev->config.cayman.tile_config |= (0 << 0); |
817 | rdev->config.cayman.tile_config |= (0 << 0); |
818 | break; |
818 | break; |
819 | case 2: |
819 | case 2: |
820 | rdev->config.cayman.tile_config |= (1 << 0); |
820 | rdev->config.cayman.tile_config |= (1 << 0); |
821 | break; |
821 | break; |
822 | case 4: |
822 | case 4: |
823 | rdev->config.cayman.tile_config |= (2 << 0); |
823 | rdev->config.cayman.tile_config |= (2 << 0); |
824 | break; |
824 | break; |
825 | case 8: |
825 | case 8: |
826 | rdev->config.cayman.tile_config |= (3 << 0); |
826 | rdev->config.cayman.tile_config |= (3 << 0); |
827 | break; |
827 | break; |
828 | } |
828 | } |
829 | rdev->config.cayman.tile_config |= |
829 | rdev->config.cayman.tile_config |= |
830 | ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; |
830 | ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; |
831 | rdev->config.cayman.tile_config |= |
831 | rdev->config.cayman.tile_config |= |
832 | ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; |
832 | ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; |
833 | rdev->config.cayman.tile_config |= |
833 | rdev->config.cayman.tile_config |= |
834 | ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; |
834 | ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; |
- | 835 | ||
835 | 836 | rdev->config.cayman.backend_map = gb_backend_map; |
|
836 | WREG32(GB_BACKEND_MAP, gb_backend_map); |
837 | WREG32(GB_BACKEND_MAP, gb_backend_map); |
837 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
838 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
838 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
839 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
839 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
840 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
840 | 841 | ||
841 | cayman_program_channel_remap(rdev); |
842 | cayman_program_channel_remap(rdev); |
842 | 843 | ||
843 | /* primary versions */ |
844 | /* primary versions */ |
844 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
845 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
845 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
846 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
846 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
847 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
847 | 848 | ||
848 | WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); |
849 | WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); |
849 | WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); |
850 | WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); |
850 | 851 | ||
851 | /* user versions */ |
852 | /* user versions */ |
852 | WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
853 | WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
853 | WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
854 | WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
854 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
855 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
855 | 856 | ||
856 | WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); |
857 | WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); |
857 | WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); |
858 | WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); |
858 | 859 | ||
859 | /* reprogram the shader complex */ |
860 | /* reprogram the shader complex */ |
860 | cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG); |
861 | cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG); |
861 | for (i = 0; i < 16; i++) |
862 | for (i = 0; i < 16; i++) |
862 | WREG32(CGTS_SM_CTRL_REG, OVERRIDE); |
863 | WREG32(CGTS_SM_CTRL_REG, OVERRIDE); |
863 | WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); |
864 | WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); |
864 | 865 | ||
865 | /* set HW defaults for 3D engine */ |
866 | /* set HW defaults for 3D engine */ |
866 | WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); |
867 | WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); |
867 | 868 | ||
868 | sx_debug_1 = RREG32(SX_DEBUG_1); |
869 | sx_debug_1 = RREG32(SX_DEBUG_1); |
869 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; |
870 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; |
870 | WREG32(SX_DEBUG_1, sx_debug_1); |
871 | WREG32(SX_DEBUG_1, sx_debug_1); |
871 | 872 | ||
872 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); |
873 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); |
873 | smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); |
874 | smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); |
874 | smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); |
875 | smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); |
875 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); |
876 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); |
876 | 877 | ||
877 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE); |
878 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE); |
878 | 879 | ||
879 | /* need to be explicitly zero-ed */ |
880 | /* need to be explicitly zero-ed */ |
880 | WREG32(VGT_OFFCHIP_LDS_BASE, 0); |
881 | WREG32(VGT_OFFCHIP_LDS_BASE, 0); |
881 | WREG32(SQ_LSTMP_RING_BASE, 0); |
882 | WREG32(SQ_LSTMP_RING_BASE, 0); |
882 | WREG32(SQ_HSTMP_RING_BASE, 0); |
883 | WREG32(SQ_HSTMP_RING_BASE, 0); |
883 | WREG32(SQ_ESTMP_RING_BASE, 0); |
884 | WREG32(SQ_ESTMP_RING_BASE, 0); |
884 | WREG32(SQ_GSTMP_RING_BASE, 0); |
885 | WREG32(SQ_GSTMP_RING_BASE, 0); |
885 | WREG32(SQ_VSTMP_RING_BASE, 0); |
886 | WREG32(SQ_VSTMP_RING_BASE, 0); |
886 | WREG32(SQ_PSTMP_RING_BASE, 0); |
887 | WREG32(SQ_PSTMP_RING_BASE, 0); |
887 | 888 | ||
888 | WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO); |
889 | WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO); |
889 | 890 | ||
890 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) | |
891 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) | |
891 | POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | |
892 | POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | |
892 | SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); |
893 | SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); |
893 | 894 | ||
894 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | |
895 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | |
895 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | |
896 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | |
896 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); |
897 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); |
897 | 898 | ||
898 | 899 | ||
899 | WREG32(VGT_NUM_INSTANCES, 1); |
900 | WREG32(VGT_NUM_INSTANCES, 1); |
900 | 901 | ||
901 | WREG32(CP_PERFMON_CNTL, 0); |
902 | WREG32(CP_PERFMON_CNTL, 0); |
902 | 903 | ||
903 | WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | |
904 | WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | |
904 | FETCH_FIFO_HIWATER(0x4) | |
905 | FETCH_FIFO_HIWATER(0x4) | |
905 | DONE_FIFO_HIWATER(0xe0) | |
906 | DONE_FIFO_HIWATER(0xe0) | |
906 | ALU_UPDATE_FIFO_HIWATER(0x8))); |
907 | ALU_UPDATE_FIFO_HIWATER(0x8))); |
907 | 908 | ||
908 | WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4)); |
909 | WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4)); |
909 | WREG32(SQ_CONFIG, (VC_ENABLE | |
910 | WREG32(SQ_CONFIG, (VC_ENABLE | |
910 | EXPORT_SRC_C | |
911 | EXPORT_SRC_C | |
911 | GFX_PRIO(0) | |
912 | GFX_PRIO(0) | |
912 | CS1_PRIO(0) | |
913 | CS1_PRIO(0) | |
913 | CS2_PRIO(1))); |
914 | CS2_PRIO(1))); |
914 | WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE); |
915 | WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE); |
915 | 916 | ||
916 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | |
917 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | |
917 | FORCE_EOV_MAX_REZ_CNT(255))); |
918 | FORCE_EOV_MAX_REZ_CNT(255))); |
918 | 919 | ||
919 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | |
920 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | |
920 | AUTO_INVLD_EN(ES_AND_GS_AUTO)); |
921 | AUTO_INVLD_EN(ES_AND_GS_AUTO)); |
921 | 922 | ||
922 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
923 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
923 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
924 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
924 | 925 | ||
925 | WREG32(CB_PERF_CTR0_SEL_0, 0); |
926 | WREG32(CB_PERF_CTR0_SEL_0, 0); |
926 | WREG32(CB_PERF_CTR0_SEL_1, 0); |
927 | WREG32(CB_PERF_CTR0_SEL_1, 0); |
927 | WREG32(CB_PERF_CTR1_SEL_0, 0); |
928 | WREG32(CB_PERF_CTR1_SEL_0, 0); |
928 | WREG32(CB_PERF_CTR1_SEL_1, 0); |
929 | WREG32(CB_PERF_CTR1_SEL_1, 0); |
929 | WREG32(CB_PERF_CTR2_SEL_0, 0); |
930 | WREG32(CB_PERF_CTR2_SEL_0, 0); |
930 | WREG32(CB_PERF_CTR2_SEL_1, 0); |
931 | WREG32(CB_PERF_CTR2_SEL_1, 0); |
931 | WREG32(CB_PERF_CTR3_SEL_0, 0); |
932 | WREG32(CB_PERF_CTR3_SEL_0, 0); |
932 | WREG32(CB_PERF_CTR3_SEL_1, 0); |
933 | WREG32(CB_PERF_CTR3_SEL_1, 0); |
933 | 934 | ||
934 | tmp = RREG32(HDP_MISC_CNTL); |
935 | tmp = RREG32(HDP_MISC_CNTL); |
935 | tmp |= HDP_FLUSH_INVALIDATE_CACHE; |
936 | tmp |= HDP_FLUSH_INVALIDATE_CACHE; |
936 | WREG32(HDP_MISC_CNTL, tmp); |
937 | WREG32(HDP_MISC_CNTL, tmp); |
937 | 938 | ||
938 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
939 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
939 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
940 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
940 | 941 | ||
941 | WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); |
942 | WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); |
942 | 943 | ||
943 | udelay(50); |
944 | udelay(50); |
944 | } |
945 | } |
945 | 946 | ||
946 | /* |
947 | /* |
947 | * GART |
948 | * GART |
948 | */ |
949 | */ |
949 | void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) |
950 | void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) |
950 | { |
951 | { |
951 | /* flush hdp cache */ |
952 | /* flush hdp cache */ |
952 | WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); |
953 | WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); |
953 | 954 | ||
954 | /* bits 0-7 are the VM contexts0-7 */ |
955 | /* bits 0-7 are the VM contexts0-7 */ |
955 | WREG32(VM_INVALIDATE_REQUEST, 1); |
956 | WREG32(VM_INVALIDATE_REQUEST, 1); |
956 | } |
957 | } |
957 | 958 | ||
958 | int cayman_pcie_gart_enable(struct radeon_device *rdev) |
959 | int cayman_pcie_gart_enable(struct radeon_device *rdev) |
959 | { |
960 | { |
960 | int r; |
961 | int r; |
961 | 962 | ||
962 | if (rdev->gart.table.vram.robj == NULL) { |
963 | if (rdev->gart.table.vram.robj == NULL) { |
963 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
964 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
964 | return -EINVAL; |
965 | return -EINVAL; |
965 | } |
966 | } |
966 | r = radeon_gart_table_vram_pin(rdev); |
967 | r = radeon_gart_table_vram_pin(rdev); |
967 | if (r) |
968 | if (r) |
968 | return r; |
969 | return r; |
969 | radeon_gart_restore(rdev); |
970 | radeon_gart_restore(rdev); |
970 | /* Setup TLB control */ |
971 | /* Setup TLB control */ |
971 | WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB | |
972 | WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB | |
972 | ENABLE_L1_FRAGMENT_PROCESSING | |
973 | ENABLE_L1_FRAGMENT_PROCESSING | |
973 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
974 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
974 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); |
975 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); |
975 | /* Setup L2 cache */ |
976 | /* Setup L2 cache */ |
976 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | |
977 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | |
977 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
978 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
978 | ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | |
979 | ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | |
979 | EFFECTIVE_L2_QUEUE_SIZE(7) | |
980 | EFFECTIVE_L2_QUEUE_SIZE(7) | |
980 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); |
981 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); |
981 | WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); |
982 | WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); |
982 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | |
983 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | |
983 | L2_CACHE_BIGK_FRAGMENT_SIZE(6)); |
984 | L2_CACHE_BIGK_FRAGMENT_SIZE(6)); |
984 | /* setup context0 */ |
985 | /* setup context0 */ |
985 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
986 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
986 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
987 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
987 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
988 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
988 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
989 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
989 | (u32)(rdev->dummy_page.addr >> 12)); |
990 | (u32)(rdev->dummy_page.addr >> 12)); |
990 | WREG32(VM_CONTEXT0_CNTL2, 0); |
991 | WREG32(VM_CONTEXT0_CNTL2, 0); |
991 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
992 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
992 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
993 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
993 | /* disable context1-7 */ |
994 | /* disable context1-7 */ |
994 | WREG32(VM_CONTEXT1_CNTL2, 0); |
995 | WREG32(VM_CONTEXT1_CNTL2, 0); |
995 | WREG32(VM_CONTEXT1_CNTL, 0); |
996 | WREG32(VM_CONTEXT1_CNTL, 0); |
996 | 997 | ||
997 | cayman_pcie_gart_tlb_flush(rdev); |
998 | cayman_pcie_gart_tlb_flush(rdev); |
998 | rdev->gart.ready = true; |
999 | rdev->gart.ready = true; |
999 | return 0; |
1000 | return 0; |
1000 | } |
1001 | } |
1001 | 1002 | ||
1002 | void cayman_pcie_gart_disable(struct radeon_device *rdev) |
1003 | void cayman_pcie_gart_disable(struct radeon_device *rdev) |
1003 | { |
1004 | { |
1004 | int r; |
1005 | int r; |
1005 | 1006 | ||
1006 | /* Disable all tables */ |
1007 | /* Disable all tables */ |
1007 | WREG32(VM_CONTEXT0_CNTL, 0); |
1008 | WREG32(VM_CONTEXT0_CNTL, 0); |
1008 | WREG32(VM_CONTEXT1_CNTL, 0); |
1009 | WREG32(VM_CONTEXT1_CNTL, 0); |
1009 | /* Setup TLB control */ |
1010 | /* Setup TLB control */ |
1010 | WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING | |
1011 | WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING | |
1011 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
1012 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
1012 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); |
1013 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); |
1013 | /* Setup L2 cache */ |
1014 | /* Setup L2 cache */ |
1014 | WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
1015 | WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
1015 | ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | |
1016 | ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | |
1016 | EFFECTIVE_L2_QUEUE_SIZE(7) | |
1017 | EFFECTIVE_L2_QUEUE_SIZE(7) | |
1017 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); |
1018 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); |
1018 | WREG32(VM_L2_CNTL2, 0); |
1019 | WREG32(VM_L2_CNTL2, 0); |
1019 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | |
1020 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | |
1020 | L2_CACHE_BIGK_FRAGMENT_SIZE(6)); |
1021 | L2_CACHE_BIGK_FRAGMENT_SIZE(6)); |
1021 | if (rdev->gart.table.vram.robj) { |
1022 | if (rdev->gart.table.vram.robj) { |
1022 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
1023 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
1023 | if (likely(r == 0)) { |
1024 | if (likely(r == 0)) { |
1024 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
1025 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
1025 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
1026 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
1026 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
1027 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
1027 | } |
1028 | } |
1028 | } |
1029 | } |
1029 | } |
1030 | } |
1030 | 1031 | ||
1031 | 1032 | ||
1032 | /* |
1033 | /* |
1033 | * CP. |
1034 | * CP. |
1034 | */ |
1035 | */ |
1035 | static void cayman_cp_enable(struct radeon_device *rdev, bool enable) |
1036 | static void cayman_cp_enable(struct radeon_device *rdev, bool enable) |
1036 | { |
1037 | { |
1037 | if (enable) |
1038 | if (enable) |
1038 | WREG32(CP_ME_CNTL, 0); |
1039 | WREG32(CP_ME_CNTL, 0); |
1039 | else { |
1040 | else { |
1040 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
1041 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
1041 | WREG32(SCRATCH_UMSK, 0); |
1042 | WREG32(SCRATCH_UMSK, 0); |
1042 | } |
1043 | } |
1043 | } |
1044 | } |
1044 | 1045 | ||
1045 | static int cayman_cp_load_microcode(struct radeon_device *rdev) |
1046 | static int cayman_cp_load_microcode(struct radeon_device *rdev) |
1046 | { |
1047 | { |
1047 | const __be32 *fw_data; |
1048 | const __be32 *fw_data; |
1048 | int i; |
1049 | int i; |
1049 | 1050 | ||
1050 | if (!rdev->me_fw || !rdev->pfp_fw) |
1051 | if (!rdev->me_fw || !rdev->pfp_fw) |
1051 | return -EINVAL; |
1052 | return -EINVAL; |
1052 | 1053 | ||
1053 | cayman_cp_enable(rdev, false); |
1054 | cayman_cp_enable(rdev, false); |
1054 | 1055 | ||
1055 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
1056 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
1056 | WREG32(CP_PFP_UCODE_ADDR, 0); |
1057 | WREG32(CP_PFP_UCODE_ADDR, 0); |
1057 | for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++) |
1058 | for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++) |
1058 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); |
1059 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); |
1059 | WREG32(CP_PFP_UCODE_ADDR, 0); |
1060 | WREG32(CP_PFP_UCODE_ADDR, 0); |
1060 | 1061 | ||
1061 | fw_data = (const __be32 *)rdev->me_fw->data; |
1062 | fw_data = (const __be32 *)rdev->me_fw->data; |
1062 | WREG32(CP_ME_RAM_WADDR, 0); |
1063 | WREG32(CP_ME_RAM_WADDR, 0); |
1063 | for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++) |
1064 | for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++) |
1064 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); |
1065 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); |
1065 | 1066 | ||
1066 | WREG32(CP_PFP_UCODE_ADDR, 0); |
1067 | WREG32(CP_PFP_UCODE_ADDR, 0); |
1067 | WREG32(CP_ME_RAM_WADDR, 0); |
1068 | WREG32(CP_ME_RAM_WADDR, 0); |
1068 | WREG32(CP_ME_RAM_RADDR, 0); |
1069 | WREG32(CP_ME_RAM_RADDR, 0); |
1069 | return 0; |
1070 | return 0; |
1070 | } |
1071 | } |
1071 | 1072 | ||
1072 | static int cayman_cp_start(struct radeon_device *rdev) |
1073 | static int cayman_cp_start(struct radeon_device *rdev) |
1073 | { |
1074 | { |
1074 | int r, i; |
1075 | int r, i; |
1075 | 1076 | ||
1076 | r = radeon_ring_lock(rdev, 7); |
1077 | r = radeon_ring_lock(rdev, 7); |
1077 | if (r) { |
1078 | if (r) { |
1078 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
1079 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
1079 | return r; |
1080 | return r; |
1080 | } |
1081 | } |
1081 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
1082 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
1082 | radeon_ring_write(rdev, 0x1); |
1083 | radeon_ring_write(rdev, 0x1); |
1083 | radeon_ring_write(rdev, 0x0); |
1084 | radeon_ring_write(rdev, 0x0); |
1084 | radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1); |
1085 | radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1); |
1085 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
1086 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
1086 | radeon_ring_write(rdev, 0); |
1087 | radeon_ring_write(rdev, 0); |
1087 | radeon_ring_write(rdev, 0); |
1088 | radeon_ring_write(rdev, 0); |
1088 | radeon_ring_unlock_commit(rdev); |
1089 | radeon_ring_unlock_commit(rdev); |
1089 | 1090 | ||
1090 | cayman_cp_enable(rdev, true); |
1091 | cayman_cp_enable(rdev, true); |
1091 | 1092 | ||
1092 | r = radeon_ring_lock(rdev, cayman_default_size + 19); |
1093 | r = radeon_ring_lock(rdev, cayman_default_size + 19); |
1093 | if (r) { |
1094 | if (r) { |
1094 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
1095 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
1095 | return r; |
1096 | return r; |
1096 | } |
1097 | } |
1097 | 1098 | ||
1098 | /* setup clear context state */ |
1099 | /* setup clear context state */ |
1099 | radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
1100 | radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
1100 | radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); |
1101 | radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); |
1101 | 1102 | ||
1102 | for (i = 0; i < cayman_default_size; i++) |
1103 | for (i = 0; i < cayman_default_size; i++) |
1103 | radeon_ring_write(rdev, cayman_default_state[i]); |
1104 | radeon_ring_write(rdev, cayman_default_state[i]); |
1104 | 1105 | ||
1105 | radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
1106 | radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
1106 | radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE); |
1107 | radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE); |
1107 | 1108 | ||
1108 | /* set clear context state */ |
1109 | /* set clear context state */ |
1109 | radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); |
1110 | radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); |
1110 | radeon_ring_write(rdev, 0); |
1111 | radeon_ring_write(rdev, 0); |
1111 | 1112 | ||
1112 | /* SQ_VTX_BASE_VTX_LOC */ |
1113 | /* SQ_VTX_BASE_VTX_LOC */ |
1113 | radeon_ring_write(rdev, 0xc0026f00); |
1114 | radeon_ring_write(rdev, 0xc0026f00); |
1114 | radeon_ring_write(rdev, 0x00000000); |
1115 | radeon_ring_write(rdev, 0x00000000); |
1115 | radeon_ring_write(rdev, 0x00000000); |
1116 | radeon_ring_write(rdev, 0x00000000); |
1116 | radeon_ring_write(rdev, 0x00000000); |
1117 | radeon_ring_write(rdev, 0x00000000); |
1117 | 1118 | ||
1118 | /* Clear consts */ |
1119 | /* Clear consts */ |
1119 | radeon_ring_write(rdev, 0xc0036f00); |
1120 | radeon_ring_write(rdev, 0xc0036f00); |
1120 | radeon_ring_write(rdev, 0x00000bc4); |
1121 | radeon_ring_write(rdev, 0x00000bc4); |
1121 | radeon_ring_write(rdev, 0xffffffff); |
1122 | radeon_ring_write(rdev, 0xffffffff); |
1122 | radeon_ring_write(rdev, 0xffffffff); |
1123 | radeon_ring_write(rdev, 0xffffffff); |
1123 | radeon_ring_write(rdev, 0xffffffff); |
1124 | radeon_ring_write(rdev, 0xffffffff); |
1124 | 1125 | ||
1125 | radeon_ring_write(rdev, 0xc0026900); |
1126 | radeon_ring_write(rdev, 0xc0026900); |
1126 | radeon_ring_write(rdev, 0x00000316); |
1127 | radeon_ring_write(rdev, 0x00000316); |
1127 | radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
1128 | radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
1128 | radeon_ring_write(rdev, 0x00000010); /* */ |
1129 | radeon_ring_write(rdev, 0x00000010); /* */ |
1129 | 1130 | ||
1130 | radeon_ring_unlock_commit(rdev); |
1131 | radeon_ring_unlock_commit(rdev); |
1131 | 1132 | ||
1132 | /* XXX init other rings */ |
1133 | /* XXX init other rings */ |
1133 | 1134 | ||
1134 | return 0; |
1135 | return 0; |
1135 | } |
1136 | } |
1136 | 1137 | ||
1137 | 1138 | ||
1138 | 1139 | ||
1139 | int cayman_cp_resume(struct radeon_device *rdev) |
1140 | int cayman_cp_resume(struct radeon_device *rdev) |
1140 | { |
1141 | { |
1141 | u32 tmp; |
1142 | u32 tmp; |
1142 | u32 rb_bufsz; |
1143 | u32 rb_bufsz; |
1143 | int r; |
1144 | int r; |
1144 | 1145 | ||
1145 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ |
1146 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ |
1146 | WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | |
1147 | WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | |
1147 | SOFT_RESET_PA | |
1148 | SOFT_RESET_PA | |
1148 | SOFT_RESET_SH | |
1149 | SOFT_RESET_SH | |
1149 | SOFT_RESET_VGT | |
1150 | SOFT_RESET_VGT | |
- | 1151 | SOFT_RESET_SPI | |
|
1150 | SOFT_RESET_SX)); |
1152 | SOFT_RESET_SX)); |
1151 | RREG32(GRBM_SOFT_RESET); |
1153 | RREG32(GRBM_SOFT_RESET); |
1152 | mdelay(15); |
1154 | mdelay(15); |
1153 | WREG32(GRBM_SOFT_RESET, 0); |
1155 | WREG32(GRBM_SOFT_RESET, 0); |
1154 | RREG32(GRBM_SOFT_RESET); |
1156 | RREG32(GRBM_SOFT_RESET); |
1155 | 1157 | ||
1156 | WREG32(CP_SEM_WAIT_TIMER, 0x4); |
1158 | WREG32(CP_SEM_WAIT_TIMER, 0x4); |
1157 | 1159 | ||
1158 | /* Set the write pointer delay */ |
1160 | /* Set the write pointer delay */ |
1159 | WREG32(CP_RB_WPTR_DELAY, 0); |
1161 | WREG32(CP_RB_WPTR_DELAY, 0); |
1160 | 1162 | ||
1161 | WREG32(CP_DEBUG, (1 << 27)); |
1163 | WREG32(CP_DEBUG, (1 << 27)); |
1162 | 1164 | ||
1163 | /* ring 0 - compute and gfx */ |
1165 | /* ring 0 - compute and gfx */ |
1164 | /* Set ring buffer size */ |
1166 | /* Set ring buffer size */ |
1165 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); |
1167 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); |
1166 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
1168 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
1167 | #ifdef __BIG_ENDIAN |
1169 | #ifdef __BIG_ENDIAN |
1168 | tmp |= BUF_SWAP_32BIT; |
1170 | tmp |= BUF_SWAP_32BIT; |
1169 | #endif |
1171 | #endif |
1170 | WREG32(CP_RB0_CNTL, tmp); |
1172 | WREG32(CP_RB0_CNTL, tmp); |
1171 | 1173 | ||
1172 | /* Initialize the ring buffer's read and write pointers */ |
1174 | /* Initialize the ring buffer's read and write pointers */ |
1173 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); |
1175 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); |
1174 | WREG32(CP_RB0_WPTR, 0); |
1176 | WREG32(CP_RB0_WPTR, 0); |
1175 | 1177 | ||
1176 | /* set the wb address wether it's enabled or not */ |
1178 | /* set the wb address wether it's enabled or not */ |
1177 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); |
1179 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); |
1178 | WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
1180 | WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
1179 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
1181 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
1180 | 1182 | ||
1181 | if (rdev->wb.enabled) |
1183 | if (rdev->wb.enabled) |
1182 | WREG32(SCRATCH_UMSK, 0xff); |
1184 | WREG32(SCRATCH_UMSK, 0xff); |
1183 | else { |
1185 | else { |
1184 | tmp |= RB_NO_UPDATE; |
1186 | tmp |= RB_NO_UPDATE; |
1185 | WREG32(SCRATCH_UMSK, 0); |
1187 | WREG32(SCRATCH_UMSK, 0); |
1186 | } |
1188 | } |
1187 | 1189 | ||
1188 | mdelay(1); |
1190 | mdelay(1); |
1189 | WREG32(CP_RB0_CNTL, tmp); |
1191 | WREG32(CP_RB0_CNTL, tmp); |
1190 | 1192 | ||
1191 | WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8); |
1193 | WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8); |
1192 | 1194 | ||
1193 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); |
1195 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); |
1194 | rdev->cp.wptr = RREG32(CP_RB0_WPTR); |
1196 | rdev->cp.wptr = RREG32(CP_RB0_WPTR); |
1195 | 1197 | ||
1196 | /* ring1 - compute only */ |
1198 | /* ring1 - compute only */ |
1197 | /* Set ring buffer size */ |
1199 | /* Set ring buffer size */ |
1198 | rb_bufsz = drm_order(rdev->cp1.ring_size / 8); |
1200 | rb_bufsz = drm_order(rdev->cp1.ring_size / 8); |
1199 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
1201 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
1200 | #ifdef __BIG_ENDIAN |
1202 | #ifdef __BIG_ENDIAN |
1201 | tmp |= BUF_SWAP_32BIT; |
1203 | tmp |= BUF_SWAP_32BIT; |
1202 | #endif |
1204 | #endif |
1203 | WREG32(CP_RB1_CNTL, tmp); |
1205 | WREG32(CP_RB1_CNTL, tmp); |
1204 | 1206 | ||
1205 | /* Initialize the ring buffer's read and write pointers */ |
1207 | /* Initialize the ring buffer's read and write pointers */ |
1206 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); |
1208 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); |
1207 | WREG32(CP_RB1_WPTR, 0); |
1209 | WREG32(CP_RB1_WPTR, 0); |
1208 | 1210 | ||
1209 | /* set the wb address wether it's enabled or not */ |
1211 | /* set the wb address wether it's enabled or not */ |
1210 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); |
1212 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); |
1211 | WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); |
1213 | WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); |
1212 | 1214 | ||
1213 | mdelay(1); |
1215 | mdelay(1); |
1214 | WREG32(CP_RB1_CNTL, tmp); |
1216 | WREG32(CP_RB1_CNTL, tmp); |
1215 | 1217 | ||
1216 | WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8); |
1218 | WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8); |
1217 | 1219 | ||
1218 | rdev->cp1.rptr = RREG32(CP_RB1_RPTR); |
1220 | rdev->cp1.rptr = RREG32(CP_RB1_RPTR); |
1219 | rdev->cp1.wptr = RREG32(CP_RB1_WPTR); |
1221 | rdev->cp1.wptr = RREG32(CP_RB1_WPTR); |
1220 | 1222 | ||
1221 | /* ring2 - compute only */ |
1223 | /* ring2 - compute only */ |
1222 | /* Set ring buffer size */ |
1224 | /* Set ring buffer size */ |
1223 | rb_bufsz = drm_order(rdev->cp2.ring_size / 8); |
1225 | rb_bufsz = drm_order(rdev->cp2.ring_size / 8); |
1224 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
1226 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
1225 | #ifdef __BIG_ENDIAN |
1227 | #ifdef __BIG_ENDIAN |
1226 | tmp |= BUF_SWAP_32BIT; |
1228 | tmp |= BUF_SWAP_32BIT; |
1227 | #endif |
1229 | #endif |
1228 | WREG32(CP_RB2_CNTL, tmp); |
1230 | WREG32(CP_RB2_CNTL, tmp); |
1229 | 1231 | ||
1230 | /* Initialize the ring buffer's read and write pointers */ |
1232 | /* Initialize the ring buffer's read and write pointers */ |
1231 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); |
1233 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); |
1232 | WREG32(CP_RB2_WPTR, 0); |
1234 | WREG32(CP_RB2_WPTR, 0); |
1233 | 1235 | ||
1234 | /* set the wb address wether it's enabled or not */ |
1236 | /* set the wb address wether it's enabled or not */ |
1235 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); |
1237 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); |
1236 | WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); |
1238 | WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); |
1237 | 1239 | ||
1238 | mdelay(1); |
1240 | mdelay(1); |
1239 | WREG32(CP_RB2_CNTL, tmp); |
1241 | WREG32(CP_RB2_CNTL, tmp); |
1240 | 1242 | ||
1241 | WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8); |
1243 | WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8); |
1242 | 1244 | ||
1243 | rdev->cp2.rptr = RREG32(CP_RB2_RPTR); |
1245 | rdev->cp2.rptr = RREG32(CP_RB2_RPTR); |
1244 | rdev->cp2.wptr = RREG32(CP_RB2_WPTR); |
1246 | rdev->cp2.wptr = RREG32(CP_RB2_WPTR); |
1245 | 1247 | ||
1246 | /* start the rings */ |
1248 | /* start the rings */ |
1247 | cayman_cp_start(rdev); |
1249 | cayman_cp_start(rdev); |
1248 | rdev->cp.ready = true; |
1250 | rdev->cp.ready = true; |
1249 | rdev->cp1.ready = true; |
1251 | rdev->cp1.ready = true; |
1250 | rdev->cp2.ready = true; |
1252 | rdev->cp2.ready = true; |
1251 | /* this only test cp0 */ |
1253 | /* this only test cp0 */ |
1252 | r = radeon_ring_test(rdev); |
1254 | r = radeon_ring_test(rdev); |
1253 | if (r) { |
1255 | if (r) { |
1254 | rdev->cp.ready = false; |
1256 | rdev->cp.ready = false; |
1255 | rdev->cp1.ready = false; |
1257 | rdev->cp1.ready = false; |
1256 | rdev->cp2.ready = false; |
1258 | rdev->cp2.ready = false; |
1257 | return r; |
1259 | return r; |
1258 | } |
1260 | } |
1259 | 1261 | ||
1260 | return 0; |
1262 | return 0; |
1261 | } |
1263 | } |
1262 | 1264 | ||
1263 | bool cayman_gpu_is_lockup(struct radeon_device *rdev) |
1265 | bool cayman_gpu_is_lockup(struct radeon_device *rdev) |
1264 | { |
1266 | { |
1265 | u32 srbm_status; |
1267 | u32 srbm_status; |
1266 | u32 grbm_status; |
1268 | u32 grbm_status; |
1267 | u32 grbm_status_se0, grbm_status_se1; |
1269 | u32 grbm_status_se0, grbm_status_se1; |
1268 | struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup; |
1270 | struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup; |
1269 | int r; |
1271 | int r; |
1270 | 1272 | ||
1271 | srbm_status = RREG32(SRBM_STATUS); |
1273 | srbm_status = RREG32(SRBM_STATUS); |
1272 | grbm_status = RREG32(GRBM_STATUS); |
1274 | grbm_status = RREG32(GRBM_STATUS); |
1273 | grbm_status_se0 = RREG32(GRBM_STATUS_SE0); |
1275 | grbm_status_se0 = RREG32(GRBM_STATUS_SE0); |
1274 | grbm_status_se1 = RREG32(GRBM_STATUS_SE1); |
1276 | grbm_status_se1 = RREG32(GRBM_STATUS_SE1); |
1275 | if (!(grbm_status & GUI_ACTIVE)) { |
1277 | if (!(grbm_status & GUI_ACTIVE)) { |
1276 | r100_gpu_lockup_update(lockup, &rdev->cp); |
1278 | r100_gpu_lockup_update(lockup, &rdev->cp); |
1277 | return false; |
1279 | return false; |
1278 | } |
1280 | } |
1279 | /* force CP activities */ |
1281 | /* force CP activities */ |
1280 | r = radeon_ring_lock(rdev, 2); |
1282 | r = radeon_ring_lock(rdev, 2); |
1281 | if (!r) { |
1283 | if (!r) { |
1282 | /* PACKET2 NOP */ |
1284 | /* PACKET2 NOP */ |
1283 | radeon_ring_write(rdev, 0x80000000); |
1285 | radeon_ring_write(rdev, 0x80000000); |
1284 | radeon_ring_write(rdev, 0x80000000); |
1286 | radeon_ring_write(rdev, 0x80000000); |
1285 | radeon_ring_unlock_commit(rdev); |
1287 | radeon_ring_unlock_commit(rdev); |
1286 | } |
1288 | } |
1287 | /* XXX deal with CP0,1,2 */ |
1289 | /* XXX deal with CP0,1,2 */ |
1288 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); |
1290 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); |
1289 | return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp); |
1291 | return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp); |
1290 | } |
1292 | } |
1291 | 1293 | ||
1292 | static int cayman_gpu_soft_reset(struct radeon_device *rdev) |
1294 | static int cayman_gpu_soft_reset(struct radeon_device *rdev) |
1293 | { |
1295 | { |
1294 | struct evergreen_mc_save save; |
1296 | struct evergreen_mc_save save; |
1295 | u32 grbm_reset = 0; |
1297 | u32 grbm_reset = 0; |
1296 | 1298 | ||
1297 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) |
1299 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) |
1298 | return 0; |
1300 | return 0; |
1299 | 1301 | ||
1300 | dev_info(rdev->dev, "GPU softreset \n"); |
1302 | dev_info(rdev->dev, "GPU softreset \n"); |
1301 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
1303 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
1302 | RREG32(GRBM_STATUS)); |
1304 | RREG32(GRBM_STATUS)); |
1303 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
1305 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
1304 | RREG32(GRBM_STATUS_SE0)); |
1306 | RREG32(GRBM_STATUS_SE0)); |
1305 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
1307 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
1306 | RREG32(GRBM_STATUS_SE1)); |
1308 | RREG32(GRBM_STATUS_SE1)); |
1307 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
1309 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
1308 | RREG32(SRBM_STATUS)); |
1310 | RREG32(SRBM_STATUS)); |
1309 | evergreen_mc_stop(rdev, &save); |
1311 | evergreen_mc_stop(rdev, &save); |
1310 | if (evergreen_mc_wait_for_idle(rdev)) { |
1312 | if (evergreen_mc_wait_for_idle(rdev)) { |
1311 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
1313 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
1312 | } |
1314 | } |
1313 | /* Disable CP parsing/prefetching */ |
1315 | /* Disable CP parsing/prefetching */ |
1314 | WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); |
1316 | WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); |
1315 | 1317 | ||
1316 | /* reset all the gfx blocks */ |
1318 | /* reset all the gfx blocks */ |
1317 | grbm_reset = (SOFT_RESET_CP | |
1319 | grbm_reset = (SOFT_RESET_CP | |
1318 | SOFT_RESET_CB | |
1320 | SOFT_RESET_CB | |
1319 | SOFT_RESET_DB | |
1321 | SOFT_RESET_DB | |
1320 | SOFT_RESET_GDS | |
1322 | SOFT_RESET_GDS | |
1321 | SOFT_RESET_PA | |
1323 | SOFT_RESET_PA | |
1322 | SOFT_RESET_SC | |
1324 | SOFT_RESET_SC | |
1323 | SOFT_RESET_SPI | |
1325 | SOFT_RESET_SPI | |
1324 | SOFT_RESET_SH | |
1326 | SOFT_RESET_SH | |
1325 | SOFT_RESET_SX | |
1327 | SOFT_RESET_SX | |
1326 | SOFT_RESET_TC | |
1328 | SOFT_RESET_TC | |
1327 | SOFT_RESET_TA | |
1329 | SOFT_RESET_TA | |
1328 | SOFT_RESET_VGT | |
1330 | SOFT_RESET_VGT | |
1329 | SOFT_RESET_IA); |
1331 | SOFT_RESET_IA); |
1330 | 1332 | ||
1331 | dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); |
1333 | dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); |
1332 | WREG32(GRBM_SOFT_RESET, grbm_reset); |
1334 | WREG32(GRBM_SOFT_RESET, grbm_reset); |
1333 | (void)RREG32(GRBM_SOFT_RESET); |
1335 | (void)RREG32(GRBM_SOFT_RESET); |
1334 | udelay(50); |
1336 | udelay(50); |
1335 | WREG32(GRBM_SOFT_RESET, 0); |
1337 | WREG32(GRBM_SOFT_RESET, 0); |
1336 | (void)RREG32(GRBM_SOFT_RESET); |
1338 | (void)RREG32(GRBM_SOFT_RESET); |
1337 | /* Wait a little for things to settle down */ |
1339 | /* Wait a little for things to settle down */ |
1338 | udelay(50); |
1340 | udelay(50); |
1339 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
1341 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
1340 | RREG32(GRBM_STATUS)); |
1342 | RREG32(GRBM_STATUS)); |
1341 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
1343 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
1342 | RREG32(GRBM_STATUS_SE0)); |
1344 | RREG32(GRBM_STATUS_SE0)); |
1343 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
1345 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
1344 | RREG32(GRBM_STATUS_SE1)); |
1346 | RREG32(GRBM_STATUS_SE1)); |
1345 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
1347 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
1346 | RREG32(SRBM_STATUS)); |
1348 | RREG32(SRBM_STATUS)); |
1347 | evergreen_mc_resume(rdev, &save); |
1349 | evergreen_mc_resume(rdev, &save); |
1348 | return 0; |
1350 | return 0; |
1349 | } |
1351 | } |
1350 | 1352 | ||
1351 | int cayman_asic_reset(struct radeon_device *rdev) |
1353 | int cayman_asic_reset(struct radeon_device *rdev) |
1352 | { |
1354 | { |
1353 | return cayman_gpu_soft_reset(rdev); |
1355 | return cayman_gpu_soft_reset(rdev); |
1354 | } |
1356 | } |
1355 | 1357 | ||
1356 | static int cayman_startup(struct radeon_device *rdev) |
1358 | static int cayman_startup(struct radeon_device *rdev) |
1357 | { |
1359 | { |
1358 | int r; |
1360 | int r; |
1359 | 1361 | ||
1360 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { |
1362 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { |
1361 | r = ni_init_microcode(rdev); |
1363 | r = ni_init_microcode(rdev); |
1362 | if (r) { |
1364 | if (r) { |
1363 | DRM_ERROR("Failed to load firmware!\n"); |
1365 | DRM_ERROR("Failed to load firmware!\n"); |
1364 | return r; |
1366 | return r; |
1365 | } |
1367 | } |
1366 | } |
1368 | } |
1367 | r = ni_mc_load_microcode(rdev); |
1369 | r = ni_mc_load_microcode(rdev); |
1368 | if (r) { |
1370 | if (r) { |
1369 | DRM_ERROR("Failed to load MC firmware!\n"); |
1371 | DRM_ERROR("Failed to load MC firmware!\n"); |
1370 | return r; |
1372 | return r; |
1371 | } |
1373 | } |
1372 | 1374 | ||
1373 | evergreen_mc_program(rdev); |
1375 | evergreen_mc_program(rdev); |
1374 | r = cayman_pcie_gart_enable(rdev); |
1376 | r = cayman_pcie_gart_enable(rdev); |
1375 | if (r) |
1377 | if (r) |
1376 | return r; |
1378 | return r; |
1377 | cayman_gpu_init(rdev); |
1379 | cayman_gpu_init(rdev); |
1378 | 1380 | ||
1379 | r = evergreen_blit_init(rdev); |
1381 | r = evergreen_blit_init(rdev); |
1380 | if (r) { |
1382 | if (r) { |
1381 | // evergreen_blit_fini(rdev); |
1383 | // evergreen_blit_fini(rdev); |
1382 | rdev->asic->copy = NULL; |
1384 | rdev->asic->copy = NULL; |
1383 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
1385 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
1384 | } |
1386 | } |
1385 | 1387 | ||
1386 | /* allocate wb buffer */ |
1388 | /* allocate wb buffer */ |
1387 | r = radeon_wb_init(rdev); |
1389 | r = radeon_wb_init(rdev); |
1388 | if (r) |
1390 | if (r) |
1389 | return r; |
1391 | return r; |
1390 | 1392 | ||
1391 | /* Enable IRQ */ |
1393 | /* Enable IRQ */ |
1392 | r = r600_irq_init(rdev); |
1394 | r = r600_irq_init(rdev); |
1393 | if (r) { |
1395 | if (r) { |
1394 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
1396 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
1395 | // radeon_irq_kms_fini(rdev); |
1397 | // radeon_irq_kms_fini(rdev); |
1396 | return r; |
1398 | return r; |
1397 | } |
1399 | } |
1398 | evergreen_irq_set(rdev); |
1400 | evergreen_irq_set(rdev); |
1399 | 1401 | ||
1400 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
1402 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
1401 | if (r) |
1403 | if (r) |
1402 | return r; |
1404 | return r; |
1403 | r = cayman_cp_load_microcode(rdev); |
1405 | r = cayman_cp_load_microcode(rdev); |
1404 | if (r) |
1406 | if (r) |
1405 | return r; |
1407 | return r; |
1406 | r = cayman_cp_resume(rdev); |
1408 | r = cayman_cp_resume(rdev); |
1407 | if (r) |
1409 | if (r) |
1408 | return r; |
1410 | return r; |
1409 | 1411 | ||
1410 | return 0; |
1412 | return 0; |
1411 | } |
1413 | } |
1412 | 1414 | ||
1413 | 1415 | ||
1414 | 1416 | ||
1415 | 1417 | ||
1416 | 1418 | ||
1417 | /* Plan is to move initialization in that function and use |
1419 | /* Plan is to move initialization in that function and use |
1418 | * helper function so that radeon_device_init pretty much |
1420 | * helper function so that radeon_device_init pretty much |
1419 | * do nothing more than calling asic specific function. This |
1421 | * do nothing more than calling asic specific function. This |
1420 | * should also allow to remove a bunch of callback function |
1422 | * should also allow to remove a bunch of callback function |
1421 | * like vram_info. |
1423 | * like vram_info. |
1422 | */ |
1424 | */ |
1423 | int cayman_init(struct radeon_device *rdev) |
1425 | int cayman_init(struct radeon_device *rdev) |
1424 | { |
1426 | { |
1425 | int r; |
1427 | int r; |
1426 | 1428 | ||
1427 | /* This don't do much */ |
1429 | /* This don't do much */ |
1428 | r = radeon_gem_init(rdev); |
1430 | r = radeon_gem_init(rdev); |
1429 | if (r) |
1431 | if (r) |
1430 | return r; |
1432 | return r; |
1431 | /* Read BIOS */ |
1433 | /* Read BIOS */ |
1432 | if (!radeon_get_bios(rdev)) { |
1434 | if (!radeon_get_bios(rdev)) { |
1433 | if (ASIC_IS_AVIVO(rdev)) |
1435 | if (ASIC_IS_AVIVO(rdev)) |
1434 | return -EINVAL; |
1436 | return -EINVAL; |
1435 | } |
1437 | } |
1436 | /* Must be an ATOMBIOS */ |
1438 | /* Must be an ATOMBIOS */ |
1437 | if (!rdev->is_atom_bios) { |
1439 | if (!rdev->is_atom_bios) { |
1438 | dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); |
1440 | dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); |
1439 | return -EINVAL; |
1441 | return -EINVAL; |
1440 | } |
1442 | } |
1441 | r = radeon_atombios_init(rdev); |
1443 | r = radeon_atombios_init(rdev); |
1442 | if (r) |
1444 | if (r) |
1443 | return r; |
1445 | return r; |
1444 | 1446 | ||
1445 | /* Post card if necessary */ |
1447 | /* Post card if necessary */ |
1446 | if (!radeon_card_posted(rdev)) { |
1448 | if (!radeon_card_posted(rdev)) { |
1447 | if (!rdev->bios) { |
1449 | if (!rdev->bios) { |
1448 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
1450 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
1449 | return -EINVAL; |
1451 | return -EINVAL; |
1450 | } |
1452 | } |
1451 | DRM_INFO("GPU not posted. posting now...\n"); |
1453 | DRM_INFO("GPU not posted. posting now...\n"); |
1452 | atom_asic_init(rdev->mode_info.atom_context); |
1454 | atom_asic_init(rdev->mode_info.atom_context); |
1453 | } |
1455 | } |
1454 | /* Initialize scratch registers */ |
1456 | /* Initialize scratch registers */ |
1455 | r600_scratch_init(rdev); |
1457 | r600_scratch_init(rdev); |
1456 | /* Initialize surface registers */ |
1458 | /* Initialize surface registers */ |
1457 | radeon_surface_init(rdev); |
1459 | radeon_surface_init(rdev); |
1458 | /* Initialize clocks */ |
1460 | /* Initialize clocks */ |
1459 | radeon_get_clock_info(rdev->ddev); |
1461 | radeon_get_clock_info(rdev->ddev); |
1460 | /* Fence driver */ |
1462 | /* Fence driver */ |
1461 | r = radeon_fence_driver_init(rdev); |
1463 | r = radeon_fence_driver_init(rdev); |
1462 | if (r) |
1464 | if (r) |
1463 | return r; |
1465 | return r; |
1464 | /* initialize memory controller */ |
1466 | /* initialize memory controller */ |
1465 | r = evergreen_mc_init(rdev); |
1467 | r = evergreen_mc_init(rdev); |
1466 | if (r) |
1468 | if (r) |
1467 | return r; |
1469 | return r; |
1468 | /* Memory manager */ |
1470 | /* Memory manager */ |
1469 | r = radeon_bo_init(rdev); |
1471 | r = radeon_bo_init(rdev); |
1470 | if (r) |
1472 | if (r) |
1471 | return r; |
1473 | return r; |
1472 | 1474 | ||
1473 | r = radeon_irq_kms_init(rdev); |
1475 | r = radeon_irq_kms_init(rdev); |
1474 | if (r) |
1476 | if (r) |
1475 | return r; |
1477 | return r; |
1476 | 1478 | ||
1477 | rdev->cp.ring_obj = NULL; |
1479 | rdev->cp.ring_obj = NULL; |
1478 | r600_ring_init(rdev, 1024 * 1024); |
1480 | r600_ring_init(rdev, 1024 * 1024); |
1479 | 1481 | ||
1480 | rdev->ih.ring_obj = NULL; |
1482 | rdev->ih.ring_obj = NULL; |
1481 | r600_ih_ring_init(rdev, 64 * 1024); |
1483 | r600_ih_ring_init(rdev, 64 * 1024); |
1482 | 1484 | ||
1483 | r = r600_pcie_gart_init(rdev); |
1485 | r = r600_pcie_gart_init(rdev); |
1484 | if (r) |
1486 | if (r) |
1485 | return r; |
1487 | return r; |
1486 | 1488 | ||
1487 | rdev->accel_working = true; |
1489 | rdev->accel_working = true; |
1488 | r = cayman_startup(rdev); |
1490 | r = cayman_startup(rdev); |
1489 | if (r) { |
1491 | if (r) { |
1490 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
1492 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
1491 | rdev->accel_working = false; |
1493 | rdev->accel_working = false; |
1492 | } |
1494 | } |
1493 | if (rdev->accel_working) { |
1495 | if (rdev->accel_working) { |
1494 | r = radeon_ib_pool_init(rdev); |
1496 | r = radeon_ib_pool_init(rdev); |
1495 | if (r) { |
1497 | if (r) { |
1496 | DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); |
1498 | DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); |
1497 | rdev->accel_working = false; |
1499 | rdev->accel_working = false; |
1498 | } |
1500 | } |
1499 | r = r600_ib_test(rdev); |
1501 | r = r600_ib_test(rdev); |
1500 | if (r) { |
1502 | if (r) { |
1501 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
1503 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
1502 | rdev->accel_working = false; |
1504 | rdev->accel_working = false; |
1503 | } |
1505 | } |
1504 | } |
1506 | } |
1505 | 1507 | ||
1506 | /* Don't start up if the MC ucode is missing. |
1508 | /* Don't start up if the MC ucode is missing. |
1507 | * The default clocks and voltages before the MC ucode |
1509 | * The default clocks and voltages before the MC ucode |
1508 | * is loaded are not suffient for advanced operations. |
1510 | * is loaded are not suffient for advanced operations. |
1509 | */ |
1511 | */ |
1510 | if (!rdev->mc_fw) { |
1512 | if (!rdev->mc_fw) { |
1511 | DRM_ERROR("radeon: MC ucode required for NI+.\n"); |
1513 | DRM_ERROR("radeon: MC ucode required for NI+.\n"); |
1512 | return -EINVAL; |
1514 | return -EINVAL; |
1513 | } |
1515 | } |
1514 | 1516 | ||
1515 | return 0; |
1517 | return 0; |
1516 | }><>><>><>><>>>>>><>><>><>><>><>><>><>><>><>><>><>>><>><>><>>>><>><>>>>><>>>>>>><>><>> |
1518 | }><>><>><>><>>>>>><>><>><>><>><>><>><>><>><>><>><>>><>><>><>>>><>><>>>>><>>>>>>><>><>> |