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#define DCCG_AUDIO_DTO1_PHASE             0x05c0

#define DCCG_AUDIO_DTO1_PHASE             0x05c0

#define DCCG_AUDIO_DTO1_MODULE            0x05c4

#define DCCG_AUDIO_DTO1_MODULE            0x05c4

#define DCCG_AUDIO_DTO1_LOAD              0x05c8

#define DCCG_AUDIO_DTO1_LOAD              0x05c8

#define DCCG_AUDIO_DTO1_CNTL              0x05cc

#       define DCCG_AUDIO_DTO1_USE_512FBR_DTO (1 << 3)

/* DCE 4.0 AFMT */

/* DCE 4.0 AFMT */

#define HDMI_CONTROL                         0x7030

#define HDMI_CONTROL                         0x7030

#define		SOFT_RESET_DMA				(1 << 20)

#define		SOFT_RESET_DMA				(1 << 20)

#define		SOFT_RESET_TST				(1 << 21)

#define		SOFT_RESET_TST				(1 << 21)

#define		SOFT_RESET_REGBB			(1 << 22)

#define		SOFT_RESET_REGBB			(1 << 22)

#define		SOFT_RESET_ORB				(1 << 23)

#define		SOFT_RESET_ORB				(1 << 23)

/* display watermarks */

/* display watermarks */

#define	DC_LB_MEMORY_SPLIT				  0x6b0c

#define	DC_LB_MEMORY_SPLIT				  0x6b0c

#define	PRIORITY_A_CNT			                  0x6b18

#define	PRIORITY_A_CNT			                  0x6b18

#define		PRIORITY_MARK_MASK			  0x7fff

#define		PRIORITY_MARK_MASK			  0x7fff

#define UVD_UDEC_ADDR_CONFIG				0xef4c

#define UVD_UDEC_ADDR_CONFIG				0xef4c

#define UVD_UDEC_DB_ADDR_CONFIG				0xef50

#define UVD_UDEC_DB_ADDR_CONFIG				0xef50

#define UVD_UDEC_DBW_ADDR_CONFIG			0xef54

#define UVD_UDEC_DBW_ADDR_CONFIG			0xef54

#define UVD_RBC_RB_RPTR					0xf690

#define UVD_RBC_RB_RPTR					0xf690

#define UVD_RBC_RB_WPTR					0xf694

#define UVD_RBC_RB_WPTR					0xf694

/*

/*

 * PM4

 * PM4

 */

 */