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Rev 3192 Rev 3764
Line 51... Line 51...
51 
/* Registers */
 51 
/* Registers */
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 52 
 
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#define RCU_IND_INDEX           			0x100
 53 
#define RCU_IND_INDEX           			0x100
Line -... Line 54...
- 
 
 54 
#define RCU_IND_DATA            			0x104
- 
 
 55 
 
- 
 
 56 
/* discrete uvd clocks */
- 
 
 57 
#define CG_UPLL_FUNC_CNTL				0x718
- 
 
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#	define UPLL_RESET_MASK				0x00000001
- 
 
 59 
#	define UPLL_SLEEP_MASK				0x00000002
- 
 
 60 
#	define UPLL_BYPASS_EN_MASK			0x00000004
- 
 
 61 
#	define UPLL_CTLREQ_MASK				0x00000008
- 
 
 62 
#	define UPLL_REF_DIV_MASK			0x003F0000
- 
 
 63 
#	define UPLL_VCO_MODE_MASK			0x00000200
- 
 
 64 
#	define UPLL_CTLACK_MASK				0x40000000
- 
 
 65 
#	define UPLL_CTLACK2_MASK			0x80000000
- 
 
 66 
#define CG_UPLL_FUNC_CNTL_2				0x71c
- 
 
 67 
#	define UPLL_PDIV_A(x)				((x) << 0)
- 
 
 68 
#	define UPLL_PDIV_A_MASK				0x0000007F
- 
 
 69 
#	define UPLL_PDIV_B(x)				((x) << 8)
- 
 
 70 
#	define UPLL_PDIV_B_MASK				0x00007F00
- 
 
 71 
#	define VCLK_SRC_SEL(x)				((x) << 20)
- 
 
 72 
#	define VCLK_SRC_SEL_MASK			0x01F00000
- 
 
 73 
#	define DCLK_SRC_SEL(x)				((x) << 25)
- 
 
 74 
#	define DCLK_SRC_SEL_MASK			0x3E000000
- 
 
 75 
#define CG_UPLL_FUNC_CNTL_3				0x720
- 
 
 76 
#	define UPLL_FB_DIV(x)				((x) << 0)
- 
 
 77 
#	define UPLL_FB_DIV_MASK				0x01FFFFFF
- 
 
 78 
#define CG_UPLL_FUNC_CNTL_4				0x854
- 
 
 79 
#	define UPLL_SPARE_ISPARE9			0x00020000
- 
 
 80 
#define CG_UPLL_SPREAD_SPECTRUM				0x79c
- 
 
 81 
#	define SSEN_MASK				0x00000001
- 
 
 82 
 
- 
 
 83 
/* fusion uvd clocks */
- 
 
 84 
#define CG_DCLK_CNTL                                    0x610
- 
 
 85 
#       define DCLK_DIVIDER_MASK                        0x7f
- 
 
 86 
#       define DCLK_DIR_CNTL_EN                         (1 << 8)
- 
 
 87 
#define CG_DCLK_STATUS                                  0x614
- 
 
 88 
#       define DCLK_STATUS                              (1 << 0)
- 
 
 89 
#define CG_VCLK_CNTL                                    0x618
- 
 
 90 
#define CG_VCLK_STATUS                                  0x61c
54 
#define RCU_IND_DATA            			0x104
 91 
#define	CG_SCRATCH1					0x820
55 
 
 92 
 
56 
#define GRBM_GFX_INDEX          			0x802C
 93 
#define GRBM_GFX_INDEX          			0x802C
57 
#define		INSTANCE_INDEX(x)			((x) << 0)
 94 
#define		INSTANCE_INDEX(x)			((x) << 0)
58 
#define		SE_INDEX(x)     			((x) << 16)
 95 
#define		SE_INDEX(x)     			((x) << 16)
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195 
#       define HDMI_AUDIO_INFO_CONT          (1 << 5)
 232 
#       define HDMI_AUDIO_INFO_CONT          (1 << 5)
196 
#       define HDMI_MPEG_INFO_SEND           (1 << 8)
 233 
#       define HDMI_MPEG_INFO_SEND           (1 << 8)
197 
#       define HDMI_MPEG_INFO_CONT           (1 << 9)
 234 
#       define HDMI_MPEG_INFO_CONT           (1 << 9)
198 
#define HDMI_INFOFRAME_CONTROL1              0x7048
 235 
#define HDMI_INFOFRAME_CONTROL1              0x7048
199 
#       define HDMI_AVI_INFO_LINE(x)         (((x) & 0x3f) << 0)
 236 
#       define HDMI_AVI_INFO_LINE(x)         (((x) & 0x3f) << 0)
- 
 
 237 
#       define HDMI_AVI_INFO_LINE_MASK       (0x3f << 0)
200 
#       define HDMI_AUDIO_INFO_LINE(x)       (((x) & 0x3f) << 8)
 238 
#       define HDMI_AUDIO_INFO_LINE(x)       (((x) & 0x3f) << 8)
201 
#       define HDMI_MPEG_INFO_LINE(x)        (((x) & 0x3f) << 16)
 239 
#       define HDMI_MPEG_INFO_LINE(x)        (((x) & 0x3f) << 16)
202 
#define HDMI_GENERIC_PACKET_CONTROL          0x704c
 240 
#define HDMI_GENERIC_PACKET_CONTROL          0x704c
203 
#       define HDMI_GENERIC0_SEND            (1 << 0)
 241 
#       define HDMI_GENERIC0_SEND            (1 << 0)
204 
#       define HDMI_GENERIC0_CONT            (1 << 1)
 242 
#       define HDMI_GENERIC0_CONT            (1 << 1)
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#define	VM_CONTEXT1_PROTECTION_FAULT_STATUS		0x14DC
 765 
#define	VM_CONTEXT1_PROTECTION_FAULT_STATUS		0x14DC
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 766 
 
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#define	WAIT_UNTIL					0x8040
 767 
#define	WAIT_UNTIL					0x8040
- 
 
 768 
 
- 
 
 769 
#define	SRBM_STATUS				        0x0E50
- 
 
 770 
#define		RLC_RQ_PENDING 				(1 << 3)
- 
 
 771 
#define		GRBM_RQ_PENDING 			(1 << 5)
- 
 
 772 
#define		VMC_BUSY 				(1 << 8)
- 
 
 773 
#define		MCB_BUSY 				(1 << 9)
- 
 
 774 
#define		MCB_NON_DISPLAY_BUSY 			(1 << 10)
- 
 
 775 
#define		MCC_BUSY 				(1 << 11)
- 
 
 776 
#define		MCD_BUSY 				(1 << 12)
- 
 
 777 
#define		SEM_BUSY 				(1 << 14)
- 
 
 778 
#define		RLC_BUSY 				(1 << 15)
- 
 
 779 
#define		IH_BUSY 				(1 << 17)
730 
 
 780 
#define	SRBM_STATUS2				        0x0EC4
731 
#define	SRBM_STATUS				        0x0E50
 781 
#define		DMA_BUSY 				(1 << 5)
732 
#define	SRBM_SOFT_RESET				        0x0E60
 782 
#define	SRBM_SOFT_RESET				        0x0E60
733 
#define		SRBM_SOFT_RESET_ALL_MASK    	       	0x00FEEFA6
 783 
#define		SRBM_SOFT_RESET_ALL_MASK    	       	0x00FEEFA6
734 
#define		SOFT_RESET_BIF				(1 << 1)
 784 
#define		SOFT_RESET_BIF				(1 << 1)
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922 
#define DMA_TILING_CONFIG  				  0xD0B8
 972 
#define DMA_TILING_CONFIG  				  0xD0B8
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923 
 
 973 
 
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924 
#define CAYMAN_DMA1_CNTL                                  0xd82c
 974 
#define CAYMAN_DMA1_CNTL                                  0xd82c
925 
 
 975 
 
926 
/* async DMA packets */
 - 
 
927 
#define DMA_PACKET(cmd, t, s, n)	((((cmd) & 0xF) << 28) |	\
 976 
/* async DMA packets */
928 
					 (((t) & 0x1) << 23) |		\
 977 
#define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) |    \
- 
 
 978 
                                    (((sub_cmd) & 0xFF) << 20) |\
- 
 
 979 
					 (((n) & 0xFFFFF) << 0))
- 
 
 980 
#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
- 
 
 981 
#define GET_DMA_COUNT(h) ((h) & 0x000fffff)
929 
					 (((s) & 0x1) << 22) |		\
 982 
#define GET_DMA_SUB_CMD(h) (((h) & 0x0ff00000) >> 20)
930 
					 (((n) & 0xFFFFF) << 0))
 983 
 
931 
/* async DMA Packet types */
 984 
/* async DMA Packet types */
932 
#define	DMA_PACKET_WRITE				  0x2
 985 
#define	DMA_PACKET_WRITE				  0x2
933 
#define	DMA_PACKET_COPY					  0x3
 986 
#define	DMA_PACKET_COPY					  0x3
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975 
#       define MM_WR_TO_CFG_EN                            (1 << 3)
 1028 
#       define MM_WR_TO_CFG_EN                            (1 << 3)
976 
#define LINK_CNTL2                                        0x88 /* F0 */
 1029 
#define LINK_CNTL2                                        0x88 /* F0 */
977 
#       define TARGET_LINK_SPEED_MASK                     (0xf << 0)
 1030 
#       define TARGET_LINK_SPEED_MASK                     (0xf << 0)
978 
#       define SELECTABLE_DEEMPHASIS                      (1 << 6)
 1031 
#       define SELECTABLE_DEEMPHASIS                      (1 << 6)
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- 
 
 1032 
 
- 
 
 1033 
 
- 
 
 1034 
/*
- 
 
 1035 
 * UVD
- 
 
 1036 
 */
- 
 
 1037 
#define UVD_UDEC_ADDR_CONFIG				0xef4c
- 
 
 1038 
#define UVD_UDEC_DB_ADDR_CONFIG				0xef50
- 
 
 1039 
#define UVD_UDEC_DBW_ADDR_CONFIG			0xef54
- 
 
 1040 
#define UVD_RBC_RB_RPTR					0xf690
- 
 
 1041 
#define UVD_RBC_RB_WPTR					0xf694
979 
 
 1042 
 
980 
/*
 1043 
/*
981 
 * PM4
 1044 
 * PM4
982 
 */
 - 
 
983 
#define	PACKET_TYPE0	0
 - 
 
984 
#define	PACKET_TYPE1	1
 - 
 
985 
#define	PACKET_TYPE2	2
 - 
 
986 
#define	PACKET_TYPE3	3
 - 
 
987 
 
 - 
 
988 
#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
 - 
 
989 
#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
 - 
 
990 
#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
 - 
 
991 
#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
 1045 
 */
992 
#define PACKET0(reg, n)	((PACKET_TYPE0 << 30) |				\
 1046 
#define PACKET0(reg, n)	((RADEON_PACKET_TYPE0 << 30) |			\
993 
			 (((reg) >> 2) & 0xFFFF) |			\
 1047 
			 (((reg) >> 2) & 0xFFFF) |			\
994 
			 ((n) & 0x3FFF) << 16)
 1048 
			 ((n) & 0x3FFF) << 16)
995 
#define CP_PACKET2			0x80000000
 1049 
#define CP_PACKET2			0x80000000
996 
#define		PACKET2_PAD_SHIFT		0
 1050 
#define		PACKET2_PAD_SHIFT		0
Line 997... Line 1051...
997 
#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
 1051 
#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
Line 998... Line 1052...
998 
 
 1052 
 
999 
#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
 1053 
#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1000 
 
 1054 
 
Line 1001... Line 1055...
1001 
#define PACKET3(op, n)	((PACKET_TYPE3 << 30) |				\
 1055 
#define PACKET3(op, n)	((RADEON_PACKET_TYPE3 << 30) |			\
1002 
			 (((op) & 0xFF) << 8) |				\
 1056 
			 (((op) & 0xFF) << 8) |				\