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1 | /* |
1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. |
2 | * Copyright 2010 Advanced Micro Devices, Inc. |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
12 | * all copies or substantial portions of the Software. |
13 | * |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
21 | * |
22 | * Authors: Alex Deucher |
22 | * Authors: Alex Deucher |
23 | */ |
23 | */ |
24 | #ifndef EVERGREEND_H |
24 | #ifndef EVERGREEND_H |
25 | #define EVERGREEND_H |
25 | #define EVERGREEND_H |
26 | 26 | ||
27 | #define EVERGREEN_MAX_SH_GPRS 256 |
27 | #define EVERGREEN_MAX_SH_GPRS 256 |
28 | #define EVERGREEN_MAX_TEMP_GPRS 16 |
28 | #define EVERGREEN_MAX_TEMP_GPRS 16 |
29 | #define EVERGREEN_MAX_SH_THREADS 256 |
29 | #define EVERGREEN_MAX_SH_THREADS 256 |
30 | #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 |
30 | #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 |
31 | #define EVERGREEN_MAX_FRC_EOV_CNT 16384 |
31 | #define EVERGREEN_MAX_FRC_EOV_CNT 16384 |
32 | #define EVERGREEN_MAX_BACKENDS 8 |
32 | #define EVERGREEN_MAX_BACKENDS 8 |
33 | #define EVERGREEN_MAX_BACKENDS_MASK 0xFF |
33 | #define EVERGREEN_MAX_BACKENDS_MASK 0xFF |
34 | #define EVERGREEN_MAX_SIMDS 16 |
34 | #define EVERGREEN_MAX_SIMDS 16 |
35 | #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF |
35 | #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF |
36 | #define EVERGREEN_MAX_PIPES 8 |
36 | #define EVERGREEN_MAX_PIPES 8 |
37 | #define EVERGREEN_MAX_PIPES_MASK 0xFF |
37 | #define EVERGREEN_MAX_PIPES_MASK 0xFF |
38 | #define EVERGREEN_MAX_LDS_NUM 0xFFFF |
38 | #define EVERGREEN_MAX_LDS_NUM 0xFFFF |
39 | 39 | ||
40 | /* Registers */ |
40 | /* Registers */ |
41 | 41 | ||
42 | #define RCU_IND_INDEX 0x100 |
42 | #define RCU_IND_INDEX 0x100 |
43 | #define RCU_IND_DATA 0x104 |
43 | #define RCU_IND_DATA 0x104 |
44 | 44 | ||
45 | #define GRBM_GFX_INDEX 0x802C |
45 | #define GRBM_GFX_INDEX 0x802C |
46 | #define INSTANCE_INDEX(x) ((x) << 0) |
46 | #define INSTANCE_INDEX(x) ((x) << 0) |
47 | #define SE_INDEX(x) ((x) << 16) |
47 | #define SE_INDEX(x) ((x) << 16) |
48 | #define INSTANCE_BROADCAST_WRITES (1 << 30) |
48 | #define INSTANCE_BROADCAST_WRITES (1 << 30) |
49 | #define SE_BROADCAST_WRITES (1 << 31) |
49 | #define SE_BROADCAST_WRITES (1 << 31) |
50 | #define RLC_GFX_INDEX 0x3fC4 |
50 | #define RLC_GFX_INDEX 0x3fC4 |
51 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 |
51 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 |
52 | #define WRITE_DIS (1 << 0) |
52 | #define WRITE_DIS (1 << 0) |
53 | #define CC_RB_BACKEND_DISABLE 0x98F4 |
53 | #define CC_RB_BACKEND_DISABLE 0x98F4 |
54 | #define BACKEND_DISABLE(x) ((x) << 16) |
54 | #define BACKEND_DISABLE(x) ((x) << 16) |
55 | #define GB_ADDR_CONFIG 0x98F8 |
55 | #define GB_ADDR_CONFIG 0x98F8 |
56 | #define NUM_PIPES(x) ((x) << 0) |
56 | #define NUM_PIPES(x) ((x) << 0) |
57 | #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) |
57 | #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) |
58 | #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) |
58 | #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) |
59 | #define NUM_SHADER_ENGINES(x) ((x) << 12) |
59 | #define NUM_SHADER_ENGINES(x) ((x) << 12) |
60 | #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) |
60 | #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) |
61 | #define NUM_GPUS(x) ((x) << 20) |
61 | #define NUM_GPUS(x) ((x) << 20) |
62 | #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) |
62 | #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) |
63 | #define ROW_SIZE(x) ((x) << 28) |
63 | #define ROW_SIZE(x) ((x) << 28) |
64 | #define GB_BACKEND_MAP 0x98FC |
64 | #define GB_BACKEND_MAP 0x98FC |
65 | #define DMIF_ADDR_CONFIG 0xBD4 |
65 | #define DMIF_ADDR_CONFIG 0xBD4 |
66 | #define HDP_ADDR_CONFIG 0x2F48 |
66 | #define HDP_ADDR_CONFIG 0x2F48 |
67 | #define HDP_MISC_CNTL 0x2F4C |
67 | #define HDP_MISC_CNTL 0x2F4C |
68 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) |
68 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) |
69 | 69 | ||
70 | #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 |
70 | #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 |
71 | #define GC_USER_RB_BACKEND_DISABLE 0x9B7C |
71 | #define GC_USER_RB_BACKEND_DISABLE 0x9B7C |
72 | 72 | ||
73 | #define CGTS_SYS_TCC_DISABLE 0x3F90 |
73 | #define CGTS_SYS_TCC_DISABLE 0x3F90 |
74 | #define CGTS_TCC_DISABLE 0x9148 |
74 | #define CGTS_TCC_DISABLE 0x9148 |
75 | #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 |
75 | #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 |
76 | #define CGTS_USER_TCC_DISABLE 0x914C |
76 | #define CGTS_USER_TCC_DISABLE 0x914C |
77 | 77 | ||
78 | #define CONFIG_MEMSIZE 0x5428 |
78 | #define CONFIG_MEMSIZE 0x5428 |
79 | 79 | ||
80 | #define CP_ME_CNTL 0x86D8 |
80 | #define CP_ME_CNTL 0x86D8 |
81 | #define CP_ME_HALT (1 << 28) |
81 | #define CP_ME_HALT (1 << 28) |
82 | #define CP_PFP_HALT (1 << 26) |
82 | #define CP_PFP_HALT (1 << 26) |
83 | #define CP_ME_RAM_DATA 0xC160 |
83 | #define CP_ME_RAM_DATA 0xC160 |
84 | #define CP_ME_RAM_RADDR 0xC158 |
84 | #define CP_ME_RAM_RADDR 0xC158 |
85 | #define CP_ME_RAM_WADDR 0xC15C |
85 | #define CP_ME_RAM_WADDR 0xC15C |
86 | #define CP_MEQ_THRESHOLDS 0x8764 |
86 | #define CP_MEQ_THRESHOLDS 0x8764 |
87 | #define STQ_SPLIT(x) ((x) << 0) |
87 | #define STQ_SPLIT(x) ((x) << 0) |
88 | #define CP_PERFMON_CNTL 0x87FC |
88 | #define CP_PERFMON_CNTL 0x87FC |
89 | #define CP_PFP_UCODE_ADDR 0xC150 |
89 | #define CP_PFP_UCODE_ADDR 0xC150 |
90 | #define CP_PFP_UCODE_DATA 0xC154 |
90 | #define CP_PFP_UCODE_DATA 0xC154 |
91 | #define CP_QUEUE_THRESHOLDS 0x8760 |
91 | #define CP_QUEUE_THRESHOLDS 0x8760 |
92 | #define ROQ_IB1_START(x) ((x) << 0) |
92 | #define ROQ_IB1_START(x) ((x) << 0) |
93 | #define ROQ_IB2_START(x) ((x) << 8) |
93 | #define ROQ_IB2_START(x) ((x) << 8) |
94 | #define CP_RB_BASE 0xC100 |
94 | #define CP_RB_BASE 0xC100 |
95 | #define CP_RB_CNTL 0xC104 |
95 | #define CP_RB_CNTL 0xC104 |
96 | #define RB_BUFSZ(x) ((x) << 0) |
96 | #define RB_BUFSZ(x) ((x) << 0) |
97 | #define RB_BLKSZ(x) ((x) << 8) |
97 | #define RB_BLKSZ(x) ((x) << 8) |
98 | #define RB_NO_UPDATE (1 << 27) |
98 | #define RB_NO_UPDATE (1 << 27) |
99 | #define RB_RPTR_WR_ENA (1 << 31) |
99 | #define RB_RPTR_WR_ENA (1 << 31) |
100 | #define BUF_SWAP_32BIT (2 << 16) |
100 | #define BUF_SWAP_32BIT (2 << 16) |
101 | #define CP_RB_RPTR 0x8700 |
101 | #define CP_RB_RPTR 0x8700 |
102 | #define CP_RB_RPTR_ADDR 0xC10C |
102 | #define CP_RB_RPTR_ADDR 0xC10C |
103 | #define RB_RPTR_SWAP(x) ((x) << 0) |
103 | #define RB_RPTR_SWAP(x) ((x) << 0) |
104 | #define CP_RB_RPTR_ADDR_HI 0xC110 |
104 | #define CP_RB_RPTR_ADDR_HI 0xC110 |
105 | #define CP_RB_RPTR_WR 0xC108 |
105 | #define CP_RB_RPTR_WR 0xC108 |
106 | #define CP_RB_WPTR 0xC114 |
106 | #define CP_RB_WPTR 0xC114 |
107 | #define CP_RB_WPTR_ADDR 0xC118 |
107 | #define CP_RB_WPTR_ADDR 0xC118 |
108 | #define CP_RB_WPTR_ADDR_HI 0xC11C |
108 | #define CP_RB_WPTR_ADDR_HI 0xC11C |
109 | #define CP_RB_WPTR_DELAY 0x8704 |
109 | #define CP_RB_WPTR_DELAY 0x8704 |
110 | #define CP_SEM_WAIT_TIMER 0x85BC |
110 | #define CP_SEM_WAIT_TIMER 0x85BC |
111 | #define CP_DEBUG 0xC1FC |
111 | #define CP_DEBUG 0xC1FC |
112 | 112 | ||
113 | 113 | ||
114 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 |
114 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 |
115 | #define INACTIVE_QD_PIPES(x) ((x) << 8) |
115 | #define INACTIVE_QD_PIPES(x) ((x) << 8) |
116 | #define INACTIVE_QD_PIPES_MASK 0x0000FF00 |
116 | #define INACTIVE_QD_PIPES_MASK 0x0000FF00 |
117 | #define INACTIVE_SIMDS(x) ((x) << 16) |
117 | #define INACTIVE_SIMDS(x) ((x) << 16) |
118 | #define INACTIVE_SIMDS_MASK 0x00FF0000 |
118 | #define INACTIVE_SIMDS_MASK 0x00FF0000 |
119 | 119 | ||
120 | #define GRBM_CNTL 0x8000 |
120 | #define GRBM_CNTL 0x8000 |
121 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) |
121 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) |
122 | #define GRBM_SOFT_RESET 0x8020 |
122 | #define GRBM_SOFT_RESET 0x8020 |
123 | #define SOFT_RESET_CP (1 << 0) |
123 | #define SOFT_RESET_CP (1 << 0) |
124 | #define SOFT_RESET_CB (1 << 1) |
124 | #define SOFT_RESET_CB (1 << 1) |
125 | #define SOFT_RESET_DB (1 << 3) |
125 | #define SOFT_RESET_DB (1 << 3) |
126 | #define SOFT_RESET_PA (1 << 5) |
126 | #define SOFT_RESET_PA (1 << 5) |
127 | #define SOFT_RESET_SC (1 << 6) |
127 | #define SOFT_RESET_SC (1 << 6) |
128 | #define SOFT_RESET_SPI (1 << 8) |
128 | #define SOFT_RESET_SPI (1 << 8) |
129 | #define SOFT_RESET_SH (1 << 9) |
129 | #define SOFT_RESET_SH (1 << 9) |
130 | #define SOFT_RESET_SX (1 << 10) |
130 | #define SOFT_RESET_SX (1 << 10) |
131 | #define SOFT_RESET_TC (1 << 11) |
131 | #define SOFT_RESET_TC (1 << 11) |
132 | #define SOFT_RESET_TA (1 << 12) |
132 | #define SOFT_RESET_TA (1 << 12) |
133 | #define SOFT_RESET_VC (1 << 13) |
133 | #define SOFT_RESET_VC (1 << 13) |
134 | #define SOFT_RESET_VGT (1 << 14) |
134 | #define SOFT_RESET_VGT (1 << 14) |
135 | 135 | ||
136 | #define GRBM_STATUS 0x8010 |
136 | #define GRBM_STATUS 0x8010 |
137 | #define CMDFIFO_AVAIL_MASK 0x0000000F |
137 | #define CMDFIFO_AVAIL_MASK 0x0000000F |
138 | #define SRBM_RQ_PENDING (1 << 5) |
138 | #define SRBM_RQ_PENDING (1 << 5) |
139 | #define CF_RQ_PENDING (1 << 7) |
139 | #define CF_RQ_PENDING (1 << 7) |
140 | #define PF_RQ_PENDING (1 << 8) |
140 | #define PF_RQ_PENDING (1 << 8) |
141 | #define GRBM_EE_BUSY (1 << 10) |
141 | #define GRBM_EE_BUSY (1 << 10) |
142 | #define SX_CLEAN (1 << 11) |
142 | #define SX_CLEAN (1 << 11) |
143 | #define DB_CLEAN (1 << 12) |
143 | #define DB_CLEAN (1 << 12) |
144 | #define CB_CLEAN (1 << 13) |
144 | #define CB_CLEAN (1 << 13) |
145 | #define TA_BUSY (1 << 14) |
145 | #define TA_BUSY (1 << 14) |
146 | #define VGT_BUSY_NO_DMA (1 << 16) |
146 | #define VGT_BUSY_NO_DMA (1 << 16) |
147 | #define VGT_BUSY (1 << 17) |
147 | #define VGT_BUSY (1 << 17) |
148 | #define SX_BUSY (1 << 20) |
148 | #define SX_BUSY (1 << 20) |
149 | #define SH_BUSY (1 << 21) |
149 | #define SH_BUSY (1 << 21) |
150 | #define SPI_BUSY (1 << 22) |
150 | #define SPI_BUSY (1 << 22) |
151 | #define SC_BUSY (1 << 24) |
151 | #define SC_BUSY (1 << 24) |
152 | #define PA_BUSY (1 << 25) |
152 | #define PA_BUSY (1 << 25) |
153 | #define DB_BUSY (1 << 26) |
153 | #define DB_BUSY (1 << 26) |
154 | #define CP_COHERENCY_BUSY (1 << 28) |
154 | #define CP_COHERENCY_BUSY (1 << 28) |
155 | #define CP_BUSY (1 << 29) |
155 | #define CP_BUSY (1 << 29) |
156 | #define CB_BUSY (1 << 30) |
156 | #define CB_BUSY (1 << 30) |
157 | #define GUI_ACTIVE (1 << 31) |
157 | #define GUI_ACTIVE (1 << 31) |
158 | #define GRBM_STATUS_SE0 0x8014 |
158 | #define GRBM_STATUS_SE0 0x8014 |
159 | #define GRBM_STATUS_SE1 0x8018 |
159 | #define GRBM_STATUS_SE1 0x8018 |
160 | #define SE_SX_CLEAN (1 << 0) |
160 | #define SE_SX_CLEAN (1 << 0) |
161 | #define SE_DB_CLEAN (1 << 1) |
161 | #define SE_DB_CLEAN (1 << 1) |
162 | #define SE_CB_CLEAN (1 << 2) |
162 | #define SE_CB_CLEAN (1 << 2) |
163 | #define SE_TA_BUSY (1 << 25) |
163 | #define SE_TA_BUSY (1 << 25) |
164 | #define SE_SX_BUSY (1 << 26) |
164 | #define SE_SX_BUSY (1 << 26) |
165 | #define SE_SPI_BUSY (1 << 27) |
165 | #define SE_SPI_BUSY (1 << 27) |
166 | #define SE_SH_BUSY (1 << 28) |
166 | #define SE_SH_BUSY (1 << 28) |
167 | #define SE_SC_BUSY (1 << 29) |
167 | #define SE_SC_BUSY (1 << 29) |
168 | #define SE_DB_BUSY (1 << 30) |
168 | #define SE_DB_BUSY (1 << 30) |
169 | #define SE_CB_BUSY (1 << 31) |
169 | #define SE_CB_BUSY (1 << 31) |
170 | /* evergreen */ |
170 | /* evergreen */ |
171 | #define CG_THERMAL_CTRL 0x72c |
171 | #define CG_THERMAL_CTRL 0x72c |
172 | #define TOFFSET_MASK 0x00003FE0 |
172 | #define TOFFSET_MASK 0x00003FE0 |
173 | #define TOFFSET_SHIFT 5 |
173 | #define TOFFSET_SHIFT 5 |
174 | #define CG_MULT_THERMAL_STATUS 0x740 |
174 | #define CG_MULT_THERMAL_STATUS 0x740 |
175 | #define ASIC_T(x) ((x) << 16) |
175 | #define ASIC_T(x) ((x) << 16) |
176 | #define ASIC_T_MASK 0x07FF0000 |
176 | #define ASIC_T_MASK 0x07FF0000 |
177 | #define ASIC_T_SHIFT 16 |
177 | #define ASIC_T_SHIFT 16 |
178 | #define CG_TS0_STATUS 0x760 |
178 | #define CG_TS0_STATUS 0x760 |
179 | #define TS0_ADC_DOUT_MASK 0x000003FF |
179 | #define TS0_ADC_DOUT_MASK 0x000003FF |
180 | #define TS0_ADC_DOUT_SHIFT 0 |
180 | #define TS0_ADC_DOUT_SHIFT 0 |
181 | /* APU */ |
181 | /* APU */ |
182 | #define CG_THERMAL_STATUS 0x678 |
182 | #define CG_THERMAL_STATUS 0x678 |
183 | 183 | ||
184 | #define HDP_HOST_PATH_CNTL 0x2C00 |
184 | #define HDP_HOST_PATH_CNTL 0x2C00 |
185 | #define HDP_NONSURFACE_BASE 0x2C04 |
185 | #define HDP_NONSURFACE_BASE 0x2C04 |
186 | #define HDP_NONSURFACE_INFO 0x2C08 |
186 | #define HDP_NONSURFACE_INFO 0x2C08 |
187 | #define HDP_NONSURFACE_SIZE 0x2C0C |
187 | #define HDP_NONSURFACE_SIZE 0x2C0C |
188 | #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 |
188 | #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 |
189 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
189 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
190 | #define HDP_TILING_CONFIG 0x2F3C |
190 | #define HDP_TILING_CONFIG 0x2F3C |
191 | 191 | ||
192 | #define MC_SHARED_CHMAP 0x2004 |
192 | #define MC_SHARED_CHMAP 0x2004 |
193 | #define NOOFCHAN_SHIFT 12 |
193 | #define NOOFCHAN_SHIFT 12 |
194 | #define NOOFCHAN_MASK 0x00003000 |
194 | #define NOOFCHAN_MASK 0x00003000 |
195 | #define MC_SHARED_CHREMAP 0x2008 |
195 | #define MC_SHARED_CHREMAP 0x2008 |
196 | 196 | ||
197 | #define MC_ARB_RAMCFG 0x2760 |
197 | #define MC_ARB_RAMCFG 0x2760 |
198 | #define NOOFBANK_SHIFT 0 |
198 | #define NOOFBANK_SHIFT 0 |
199 | #define NOOFBANK_MASK 0x00000003 |
199 | #define NOOFBANK_MASK 0x00000003 |
200 | #define NOOFRANK_SHIFT 2 |
200 | #define NOOFRANK_SHIFT 2 |
201 | #define NOOFRANK_MASK 0x00000004 |
201 | #define NOOFRANK_MASK 0x00000004 |
202 | #define NOOFROWS_SHIFT 3 |
202 | #define NOOFROWS_SHIFT 3 |
203 | #define NOOFROWS_MASK 0x00000038 |
203 | #define NOOFROWS_MASK 0x00000038 |
204 | #define NOOFCOLS_SHIFT 6 |
204 | #define NOOFCOLS_SHIFT 6 |
205 | #define NOOFCOLS_MASK 0x000000C0 |
205 | #define NOOFCOLS_MASK 0x000000C0 |
206 | #define CHANSIZE_SHIFT 8 |
206 | #define CHANSIZE_SHIFT 8 |
207 | #define CHANSIZE_MASK 0x00000100 |
207 | #define CHANSIZE_MASK 0x00000100 |
208 | #define BURSTLENGTH_SHIFT 9 |
208 | #define BURSTLENGTH_SHIFT 9 |
209 | #define BURSTLENGTH_MASK 0x00000200 |
209 | #define BURSTLENGTH_MASK 0x00000200 |
210 | #define CHANSIZE_OVERRIDE (1 << 11) |
210 | #define CHANSIZE_OVERRIDE (1 << 11) |
211 | #define FUS_MC_ARB_RAMCFG 0x2768 |
211 | #define FUS_MC_ARB_RAMCFG 0x2768 |
212 | #define MC_VM_AGP_TOP 0x2028 |
212 | #define MC_VM_AGP_TOP 0x2028 |
213 | #define MC_VM_AGP_BOT 0x202C |
213 | #define MC_VM_AGP_BOT 0x202C |
214 | #define MC_VM_AGP_BASE 0x2030 |
214 | #define MC_VM_AGP_BASE 0x2030 |
215 | #define MC_VM_FB_LOCATION 0x2024 |
215 | #define MC_VM_FB_LOCATION 0x2024 |
216 | #define MC_FUS_VM_FB_OFFSET 0x2898 |
216 | #define MC_FUS_VM_FB_OFFSET 0x2898 |
217 | #define MC_VM_MB_L1_TLB0_CNTL 0x2234 |
217 | #define MC_VM_MB_L1_TLB0_CNTL 0x2234 |
218 | #define MC_VM_MB_L1_TLB1_CNTL 0x2238 |
218 | #define MC_VM_MB_L1_TLB1_CNTL 0x2238 |
219 | #define MC_VM_MB_L1_TLB2_CNTL 0x223C |
219 | #define MC_VM_MB_L1_TLB2_CNTL 0x223C |
220 | #define MC_VM_MB_L1_TLB3_CNTL 0x2240 |
220 | #define MC_VM_MB_L1_TLB3_CNTL 0x2240 |
221 | #define ENABLE_L1_TLB (1 << 0) |
221 | #define ENABLE_L1_TLB (1 << 0) |
222 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) |
222 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) |
223 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) |
223 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) |
224 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) |
224 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) |
225 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) |
225 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) |
226 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) |
226 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) |
227 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) |
227 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) |
228 | #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) |
228 | #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) |
229 | #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) |
229 | #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) |
230 | #define MC_VM_MD_L1_TLB0_CNTL 0x2654 |
230 | #define MC_VM_MD_L1_TLB0_CNTL 0x2654 |
231 | #define MC_VM_MD_L1_TLB1_CNTL 0x2658 |
231 | #define MC_VM_MD_L1_TLB1_CNTL 0x2658 |
232 | #define MC_VM_MD_L1_TLB2_CNTL 0x265C |
232 | #define MC_VM_MD_L1_TLB2_CNTL 0x265C |
233 | 233 | ||
234 | #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C |
234 | #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C |
235 | #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 |
235 | #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 |
236 | #define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 |
236 | #define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 |
237 | 237 | ||
238 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C |
238 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C |
239 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 |
239 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 |
240 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 |
240 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 |
241 | 241 | ||
242 | #define PA_CL_ENHANCE 0x8A14 |
242 | #define PA_CL_ENHANCE 0x8A14 |
243 | #define CLIP_VTX_REORDER_ENA (1 << 0) |
243 | #define CLIP_VTX_REORDER_ENA (1 << 0) |
244 | #define NUM_CLIP_SEQ(x) ((x) << 1) |
244 | #define NUM_CLIP_SEQ(x) ((x) << 1) |
245 | #define PA_SC_AA_CONFIG 0x28C04 |
245 | #define PA_SC_AA_CONFIG 0x28C04 |
246 | #define MSAA_NUM_SAMPLES_SHIFT 0 |
246 | #define MSAA_NUM_SAMPLES_SHIFT 0 |
247 | #define MSAA_NUM_SAMPLES_MASK 0x3 |
247 | #define MSAA_NUM_SAMPLES_MASK 0x3 |
248 | #define PA_SC_CLIPRECT_RULE 0x2820C |
248 | #define PA_SC_CLIPRECT_RULE 0x2820C |
249 | #define PA_SC_EDGERULE 0x28230 |
249 | #define PA_SC_EDGERULE 0x28230 |
250 | #define PA_SC_FIFO_SIZE 0x8BCC |
250 | #define PA_SC_FIFO_SIZE 0x8BCC |
251 | #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) |
251 | #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) |
252 | #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) |
252 | #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) |
253 | #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) |
253 | #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) |
254 | #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 |
254 | #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 |
255 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) |
255 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) |
256 | #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) |
256 | #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) |
257 | #define PA_SC_LINE_STIPPLE 0x28A0C |
257 | #define PA_SC_LINE_STIPPLE 0x28A0C |
258 | #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 |
258 | #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 |
259 | #define PA_SC_LINE_STIPPLE_STATE 0x8B10 |
259 | #define PA_SC_LINE_STIPPLE_STATE 0x8B10 |
260 | 260 | ||
261 | #define SCRATCH_REG0 0x8500 |
261 | #define SCRATCH_REG0 0x8500 |
262 | #define SCRATCH_REG1 0x8504 |
262 | #define SCRATCH_REG1 0x8504 |
263 | #define SCRATCH_REG2 0x8508 |
263 | #define SCRATCH_REG2 0x8508 |
264 | #define SCRATCH_REG3 0x850C |
264 | #define SCRATCH_REG3 0x850C |
265 | #define SCRATCH_REG4 0x8510 |
265 | #define SCRATCH_REG4 0x8510 |
266 | #define SCRATCH_REG5 0x8514 |
266 | #define SCRATCH_REG5 0x8514 |
267 | #define SCRATCH_REG6 0x8518 |
267 | #define SCRATCH_REG6 0x8518 |
268 | #define SCRATCH_REG7 0x851C |
268 | #define SCRATCH_REG7 0x851C |
269 | #define SCRATCH_UMSK 0x8540 |
269 | #define SCRATCH_UMSK 0x8540 |
270 | #define SCRATCH_ADDR 0x8544 |
270 | #define SCRATCH_ADDR 0x8544 |
271 | 271 | ||
272 | #define SMX_DC_CTL0 0xA020 |
272 | #define SMX_DC_CTL0 0xA020 |
273 | #define USE_HASH_FUNCTION (1 << 0) |
273 | #define USE_HASH_FUNCTION (1 << 0) |
274 | #define NUMBER_OF_SETS(x) ((x) << 1) |
274 | #define NUMBER_OF_SETS(x) ((x) << 1) |
275 | #define FLUSH_ALL_ON_EVENT (1 << 10) |
275 | #define FLUSH_ALL_ON_EVENT (1 << 10) |
276 | #define STALL_ON_EVENT (1 << 11) |
276 | #define STALL_ON_EVENT (1 << 11) |
277 | #define SMX_EVENT_CTL 0xA02C |
277 | #define SMX_EVENT_CTL 0xA02C |
278 | #define ES_FLUSH_CTL(x) ((x) << 0) |
278 | #define ES_FLUSH_CTL(x) ((x) << 0) |
279 | #define GS_FLUSH_CTL(x) ((x) << 3) |
279 | #define GS_FLUSH_CTL(x) ((x) << 3) |
280 | #define ACK_FLUSH_CTL(x) ((x) << 6) |
280 | #define ACK_FLUSH_CTL(x) ((x) << 6) |
281 | #define SYNC_FLUSH_CTL (1 << 8) |
281 | #define SYNC_FLUSH_CTL (1 << 8) |
282 | 282 | ||
283 | #define SPI_CONFIG_CNTL 0x9100 |
283 | #define SPI_CONFIG_CNTL 0x9100 |
284 | #define GPR_WRITE_PRIORITY(x) ((x) << 0) |
284 | #define GPR_WRITE_PRIORITY(x) ((x) << 0) |
285 | #define SPI_CONFIG_CNTL_1 0x913C |
285 | #define SPI_CONFIG_CNTL_1 0x913C |
286 | #define VTX_DONE_DELAY(x) ((x) << 0) |
286 | #define VTX_DONE_DELAY(x) ((x) << 0) |
287 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) |
287 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) |
288 | #define SPI_INPUT_Z 0x286D8 |
288 | #define SPI_INPUT_Z 0x286D8 |
289 | #define SPI_PS_IN_CONTROL_0 0x286CC |
289 | #define SPI_PS_IN_CONTROL_0 0x286CC |
290 | #define NUM_INTERP(x) ((x)<<0) |
290 | #define NUM_INTERP(x) ((x)<<0) |
291 | #define POSITION_ENA (1<<8) |
291 | #define POSITION_ENA (1<<8) |
292 | #define POSITION_CENTROID (1<<9) |
292 | #define POSITION_CENTROID (1<<9) |
293 | #define POSITION_ADDR(x) ((x)<<10) |
293 | #define POSITION_ADDR(x) ((x)<<10) |
294 | #define PARAM_GEN(x) ((x)<<15) |
294 | #define PARAM_GEN(x) ((x)<<15) |
295 | #define PARAM_GEN_ADDR(x) ((x)<<19) |
295 | #define PARAM_GEN_ADDR(x) ((x)<<19) |
296 | #define BARYC_SAMPLE_CNTL(x) ((x)<<26) |
296 | #define BARYC_SAMPLE_CNTL(x) ((x)<<26) |
297 | #define PERSP_GRADIENT_ENA (1<<28) |
297 | #define PERSP_GRADIENT_ENA (1<<28) |
298 | #define LINEAR_GRADIENT_ENA (1<<29) |
298 | #define LINEAR_GRADIENT_ENA (1<<29) |
299 | #define POSITION_SAMPLE (1<<30) |
299 | #define POSITION_SAMPLE (1<<30) |
300 | #define BARYC_AT_SAMPLE_ENA (1<<31) |
300 | #define BARYC_AT_SAMPLE_ENA (1<<31) |
301 | 301 | ||
302 | #define SQ_CONFIG 0x8C00 |
302 | #define SQ_CONFIG 0x8C00 |
303 | #define VC_ENABLE (1 << 0) |
303 | #define VC_ENABLE (1 << 0) |
304 | #define EXPORT_SRC_C (1 << 1) |
304 | #define EXPORT_SRC_C (1 << 1) |
305 | #define CS_PRIO(x) ((x) << 18) |
305 | #define CS_PRIO(x) ((x) << 18) |
306 | #define LS_PRIO(x) ((x) << 20) |
306 | #define LS_PRIO(x) ((x) << 20) |
307 | #define HS_PRIO(x) ((x) << 22) |
307 | #define HS_PRIO(x) ((x) << 22) |
308 | #define PS_PRIO(x) ((x) << 24) |
308 | #define PS_PRIO(x) ((x) << 24) |
309 | #define VS_PRIO(x) ((x) << 26) |
309 | #define VS_PRIO(x) ((x) << 26) |
310 | #define GS_PRIO(x) ((x) << 28) |
310 | #define GS_PRIO(x) ((x) << 28) |
311 | #define ES_PRIO(x) ((x) << 30) |
311 | #define ES_PRIO(x) ((x) << 30) |
312 | #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 |
312 | #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 |
313 | #define NUM_PS_GPRS(x) ((x) << 0) |
313 | #define NUM_PS_GPRS(x) ((x) << 0) |
314 | #define NUM_VS_GPRS(x) ((x) << 16) |
314 | #define NUM_VS_GPRS(x) ((x) << 16) |
315 | #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) |
315 | #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) |
316 | #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 |
316 | #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 |
317 | #define NUM_GS_GPRS(x) ((x) << 0) |
317 | #define NUM_GS_GPRS(x) ((x) << 0) |
318 | #define NUM_ES_GPRS(x) ((x) << 16) |
318 | #define NUM_ES_GPRS(x) ((x) << 16) |
319 | #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C |
319 | #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C |
320 | #define NUM_HS_GPRS(x) ((x) << 0) |
320 | #define NUM_HS_GPRS(x) ((x) << 0) |
321 | #define NUM_LS_GPRS(x) ((x) << 16) |
321 | #define NUM_LS_GPRS(x) ((x) << 16) |
322 | #define SQ_THREAD_RESOURCE_MGMT 0x8C18 |
322 | #define SQ_THREAD_RESOURCE_MGMT 0x8C18 |
323 | #define NUM_PS_THREADS(x) ((x) << 0) |
323 | #define NUM_PS_THREADS(x) ((x) << 0) |
324 | #define NUM_VS_THREADS(x) ((x) << 8) |
324 | #define NUM_VS_THREADS(x) ((x) << 8) |
325 | #define NUM_GS_THREADS(x) ((x) << 16) |
325 | #define NUM_GS_THREADS(x) ((x) << 16) |
326 | #define NUM_ES_THREADS(x) ((x) << 24) |
326 | #define NUM_ES_THREADS(x) ((x) << 24) |
327 | #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C |
327 | #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C |
328 | #define NUM_HS_THREADS(x) ((x) << 0) |
328 | #define NUM_HS_THREADS(x) ((x) << 0) |
329 | #define NUM_LS_THREADS(x) ((x) << 8) |
329 | #define NUM_LS_THREADS(x) ((x) << 8) |
330 | #define SQ_STACK_RESOURCE_MGMT_1 0x8C20 |
330 | #define SQ_STACK_RESOURCE_MGMT_1 0x8C20 |
331 | #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) |
331 | #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) |
332 | #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) |
332 | #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) |
333 | #define SQ_STACK_RESOURCE_MGMT_2 0x8C24 |
333 | #define SQ_STACK_RESOURCE_MGMT_2 0x8C24 |
334 | #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) |
334 | #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) |
335 | #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) |
335 | #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) |
336 | #define SQ_STACK_RESOURCE_MGMT_3 0x8C28 |
336 | #define SQ_STACK_RESOURCE_MGMT_3 0x8C28 |
337 | #define NUM_HS_STACK_ENTRIES(x) ((x) << 0) |
337 | #define NUM_HS_STACK_ENTRIES(x) ((x) << 0) |
338 | #define NUM_LS_STACK_ENTRIES(x) ((x) << 16) |
338 | #define NUM_LS_STACK_ENTRIES(x) ((x) << 16) |
339 | #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C |
339 | #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C |
340 | #define SQ_LDS_RESOURCE_MGMT 0x8E2C |
340 | #define SQ_LDS_RESOURCE_MGMT 0x8E2C |
341 | 341 | ||
342 | #define SQ_MS_FIFO_SIZES 0x8CF0 |
342 | #define SQ_MS_FIFO_SIZES 0x8CF0 |
343 | #define CACHE_FIFO_SIZE(x) ((x) << 0) |
343 | #define CACHE_FIFO_SIZE(x) ((x) << 0) |
344 | #define FETCH_FIFO_HIWATER(x) ((x) << 8) |
344 | #define FETCH_FIFO_HIWATER(x) ((x) << 8) |
345 | #define DONE_FIFO_HIWATER(x) ((x) << 16) |
345 | #define DONE_FIFO_HIWATER(x) ((x) << 16) |
346 | #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) |
346 | #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) |
347 | 347 | ||
348 | #define SX_DEBUG_1 0x9058 |
348 | #define SX_DEBUG_1 0x9058 |
349 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) |
349 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) |
350 | #define SX_EXPORT_BUFFER_SIZES 0x900C |
350 | #define SX_EXPORT_BUFFER_SIZES 0x900C |
351 | #define COLOR_BUFFER_SIZE(x) ((x) << 0) |
351 | #define COLOR_BUFFER_SIZE(x) ((x) << 0) |
352 | #define POSITION_BUFFER_SIZE(x) ((x) << 8) |
352 | #define POSITION_BUFFER_SIZE(x) ((x) << 8) |
353 | #define SMX_BUFFER_SIZE(x) ((x) << 16) |
353 | #define SMX_BUFFER_SIZE(x) ((x) << 16) |
- | 354 | #define SX_MEMORY_EXPORT_BASE 0x9010 |
|
354 | #define SX_MISC 0x28350 |
355 | #define SX_MISC 0x28350 |
355 | 356 | ||
356 | #define CB_PERF_CTR0_SEL_0 0x9A20 |
357 | #define CB_PERF_CTR0_SEL_0 0x9A20 |
357 | #define CB_PERF_CTR0_SEL_1 0x9A24 |
358 | #define CB_PERF_CTR0_SEL_1 0x9A24 |
358 | #define CB_PERF_CTR1_SEL_0 0x9A28 |
359 | #define CB_PERF_CTR1_SEL_0 0x9A28 |
359 | #define CB_PERF_CTR1_SEL_1 0x9A2C |
360 | #define CB_PERF_CTR1_SEL_1 0x9A2C |
360 | #define CB_PERF_CTR2_SEL_0 0x9A30 |
361 | #define CB_PERF_CTR2_SEL_0 0x9A30 |
361 | #define CB_PERF_CTR2_SEL_1 0x9A34 |
362 | #define CB_PERF_CTR2_SEL_1 0x9A34 |
362 | #define CB_PERF_CTR3_SEL_0 0x9A38 |
363 | #define CB_PERF_CTR3_SEL_0 0x9A38 |
363 | #define CB_PERF_CTR3_SEL_1 0x9A3C |
364 | #define CB_PERF_CTR3_SEL_1 0x9A3C |
364 | 365 | ||
365 | #define TA_CNTL_AUX 0x9508 |
366 | #define TA_CNTL_AUX 0x9508 |
366 | #define DISABLE_CUBE_WRAP (1 << 0) |
367 | #define DISABLE_CUBE_WRAP (1 << 0) |
367 | #define DISABLE_CUBE_ANISO (1 << 1) |
368 | #define DISABLE_CUBE_ANISO (1 << 1) |
368 | #define SYNC_GRADIENT (1 << 24) |
369 | #define SYNC_GRADIENT (1 << 24) |
369 | #define SYNC_WALKER (1 << 25) |
370 | #define SYNC_WALKER (1 << 25) |
370 | #define SYNC_ALIGNER (1 << 26) |
371 | #define SYNC_ALIGNER (1 << 26) |
371 | 372 | ||
372 | #define TCP_CHAN_STEER_LO 0x960c |
373 | #define TCP_CHAN_STEER_LO 0x960c |
373 | #define TCP_CHAN_STEER_HI 0x9610 |
374 | #define TCP_CHAN_STEER_HI 0x9610 |
374 | 375 | ||
375 | #define VGT_CACHE_INVALIDATION 0x88C4 |
376 | #define VGT_CACHE_INVALIDATION 0x88C4 |
376 | #define CACHE_INVALIDATION(x) ((x) << 0) |
377 | #define CACHE_INVALIDATION(x) ((x) << 0) |
377 | #define VC_ONLY 0 |
378 | #define VC_ONLY 0 |
378 | #define TC_ONLY 1 |
379 | #define TC_ONLY 1 |
379 | #define VC_AND_TC 2 |
380 | #define VC_AND_TC 2 |
380 | #define AUTO_INVLD_EN(x) ((x) << 6) |
381 | #define AUTO_INVLD_EN(x) ((x) << 6) |
381 | #define NO_AUTO 0 |
382 | #define NO_AUTO 0 |
382 | #define ES_AUTO 1 |
383 | #define ES_AUTO 1 |
383 | #define GS_AUTO 2 |
384 | #define GS_AUTO 2 |
384 | #define ES_AND_GS_AUTO 3 |
385 | #define ES_AND_GS_AUTO 3 |
385 | #define VGT_GS_VERTEX_REUSE 0x88D4 |
386 | #define VGT_GS_VERTEX_REUSE 0x88D4 |
386 | #define VGT_NUM_INSTANCES 0x8974 |
387 | #define VGT_NUM_INSTANCES 0x8974 |
387 | #define VGT_OUT_DEALLOC_CNTL 0x28C5C |
388 | #define VGT_OUT_DEALLOC_CNTL 0x28C5C |
388 | #define DEALLOC_DIST_MASK 0x0000007F |
389 | #define DEALLOC_DIST_MASK 0x0000007F |
389 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 |
390 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 |
390 | #define VTX_REUSE_DEPTH_MASK 0x000000FF |
391 | #define VTX_REUSE_DEPTH_MASK 0x000000FF |
391 | 392 | ||
392 | #define VM_CONTEXT0_CNTL 0x1410 |
393 | #define VM_CONTEXT0_CNTL 0x1410 |
393 | #define ENABLE_CONTEXT (1 << 0) |
394 | #define ENABLE_CONTEXT (1 << 0) |
394 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) |
395 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) |
395 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) |
396 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) |
396 | #define VM_CONTEXT1_CNTL 0x1414 |
397 | #define VM_CONTEXT1_CNTL 0x1414 |
397 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C |
398 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C |
398 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C |
399 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C |
399 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C |
400 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C |
400 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 |
401 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 |
401 | #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 |
402 | #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 |
402 | #define REQUEST_TYPE(x) (((x) & 0xf) << 0) |
403 | #define REQUEST_TYPE(x) (((x) & 0xf) << 0) |
403 | #define RESPONSE_TYPE_MASK 0x000000F0 |
404 | #define RESPONSE_TYPE_MASK 0x000000F0 |
404 | #define RESPONSE_TYPE_SHIFT 4 |
405 | #define RESPONSE_TYPE_SHIFT 4 |
405 | #define VM_L2_CNTL 0x1400 |
406 | #define VM_L2_CNTL 0x1400 |
406 | #define ENABLE_L2_CACHE (1 << 0) |
407 | #define ENABLE_L2_CACHE (1 << 0) |
407 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) |
408 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) |
408 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) |
409 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) |
409 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) |
410 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) |
410 | #define VM_L2_CNTL2 0x1404 |
411 | #define VM_L2_CNTL2 0x1404 |
411 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) |
412 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) |
412 | #define INVALIDATE_L2_CACHE (1 << 1) |
413 | #define INVALIDATE_L2_CACHE (1 << 1) |
413 | #define VM_L2_CNTL3 0x1408 |
414 | #define VM_L2_CNTL3 0x1408 |
414 | #define BANK_SELECT(x) ((x) << 0) |
415 | #define BANK_SELECT(x) ((x) << 0) |
415 | #define CACHE_UPDATE_MODE(x) ((x) << 6) |
416 | #define CACHE_UPDATE_MODE(x) ((x) << 6) |
416 | #define VM_L2_STATUS 0x140C |
417 | #define VM_L2_STATUS 0x140C |
417 | #define L2_BUSY (1 << 0) |
418 | #define L2_BUSY (1 << 0) |
418 | 419 | ||
419 | #define WAIT_UNTIL 0x8040 |
420 | #define WAIT_UNTIL 0x8040 |
420 | 421 | ||
421 | #define SRBM_STATUS 0x0E50 |
422 | #define SRBM_STATUS 0x0E50 |
422 | #define SRBM_SOFT_RESET 0x0E60 |
423 | #define SRBM_SOFT_RESET 0x0E60 |
423 | #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 |
424 | #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 |
424 | #define SOFT_RESET_BIF (1 << 1) |
425 | #define SOFT_RESET_BIF (1 << 1) |
425 | #define SOFT_RESET_CG (1 << 2) |
426 | #define SOFT_RESET_CG (1 << 2) |
426 | #define SOFT_RESET_DC (1 << 5) |
427 | #define SOFT_RESET_DC (1 << 5) |
427 | #define SOFT_RESET_GRBM (1 << 8) |
428 | #define SOFT_RESET_GRBM (1 << 8) |
428 | #define SOFT_RESET_HDP (1 << 9) |
429 | #define SOFT_RESET_HDP (1 << 9) |
429 | #define SOFT_RESET_IH (1 << 10) |
430 | #define SOFT_RESET_IH (1 << 10) |
430 | #define SOFT_RESET_MC (1 << 11) |
431 | #define SOFT_RESET_MC (1 << 11) |
431 | #define SOFT_RESET_RLC (1 << 13) |
432 | #define SOFT_RESET_RLC (1 << 13) |
432 | #define SOFT_RESET_ROM (1 << 14) |
433 | #define SOFT_RESET_ROM (1 << 14) |
433 | #define SOFT_RESET_SEM (1 << 15) |
434 | #define SOFT_RESET_SEM (1 << 15) |
434 | #define SOFT_RESET_VMC (1 << 17) |
435 | #define SOFT_RESET_VMC (1 << 17) |
435 | #define SOFT_RESET_TST (1 << 21) |
436 | #define SOFT_RESET_TST (1 << 21) |
436 | #define SOFT_RESET_REGBB (1 << 22) |
437 | #define SOFT_RESET_REGBB (1 << 22) |
437 | #define SOFT_RESET_ORB (1 << 23) |
438 | #define SOFT_RESET_ORB (1 << 23) |
438 | 439 | ||
439 | /* display watermarks */ |
440 | /* display watermarks */ |
440 | #define DC_LB_MEMORY_SPLIT 0x6b0c |
441 | #define DC_LB_MEMORY_SPLIT 0x6b0c |
441 | #define PRIORITY_A_CNT 0x6b18 |
442 | #define PRIORITY_A_CNT 0x6b18 |
442 | #define PRIORITY_MARK_MASK 0x7fff |
443 | #define PRIORITY_MARK_MASK 0x7fff |
443 | #define PRIORITY_OFF (1 << 16) |
444 | #define PRIORITY_OFF (1 << 16) |
444 | #define PRIORITY_ALWAYS_ON (1 << 20) |
445 | #define PRIORITY_ALWAYS_ON (1 << 20) |
445 | #define PRIORITY_B_CNT 0x6b1c |
446 | #define PRIORITY_B_CNT 0x6b1c |
446 | #define PIPE0_ARBITRATION_CONTROL3 0x0bf0 |
447 | #define PIPE0_ARBITRATION_CONTROL3 0x0bf0 |
447 | # define LATENCY_WATERMARK_MASK(x) ((x) << 16) |
448 | # define LATENCY_WATERMARK_MASK(x) ((x) << 16) |
448 | #define PIPE0_LATENCY_CONTROL 0x0bf4 |
449 | #define PIPE0_LATENCY_CONTROL 0x0bf4 |
449 | # define LATENCY_LOW_WATERMARK(x) ((x) << 0) |
450 | # define LATENCY_LOW_WATERMARK(x) ((x) << 0) |
450 | # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) |
451 | # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) |
451 | 452 | ||
452 | #define IH_RB_CNTL 0x3e00 |
453 | #define IH_RB_CNTL 0x3e00 |
453 | # define IH_RB_ENABLE (1 << 0) |
454 | # define IH_RB_ENABLE (1 << 0) |
454 | # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ |
455 | # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ |
455 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) |
456 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) |
456 | # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) |
457 | # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) |
457 | # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ |
458 | # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ |
458 | # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) |
459 | # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) |
459 | # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) |
460 | # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) |
460 | #define IH_RB_BASE 0x3e04 |
461 | #define IH_RB_BASE 0x3e04 |
461 | #define IH_RB_RPTR 0x3e08 |
462 | #define IH_RB_RPTR 0x3e08 |
462 | #define IH_RB_WPTR 0x3e0c |
463 | #define IH_RB_WPTR 0x3e0c |
463 | # define RB_OVERFLOW (1 << 0) |
464 | # define RB_OVERFLOW (1 << 0) |
464 | # define WPTR_OFFSET_MASK 0x3fffc |
465 | # define WPTR_OFFSET_MASK 0x3fffc |
465 | #define IH_RB_WPTR_ADDR_HI 0x3e10 |
466 | #define IH_RB_WPTR_ADDR_HI 0x3e10 |
466 | #define IH_RB_WPTR_ADDR_LO 0x3e14 |
467 | #define IH_RB_WPTR_ADDR_LO 0x3e14 |
467 | #define IH_CNTL 0x3e18 |
468 | #define IH_CNTL 0x3e18 |
468 | # define ENABLE_INTR (1 << 0) |
469 | # define ENABLE_INTR (1 << 0) |
469 | # define IH_MC_SWAP(x) ((x) << 1) |
470 | # define IH_MC_SWAP(x) ((x) << 1) |
470 | # define IH_MC_SWAP_NONE 0 |
471 | # define IH_MC_SWAP_NONE 0 |
471 | # define IH_MC_SWAP_16BIT 1 |
472 | # define IH_MC_SWAP_16BIT 1 |
472 | # define IH_MC_SWAP_32BIT 2 |
473 | # define IH_MC_SWAP_32BIT 2 |
473 | # define IH_MC_SWAP_64BIT 3 |
474 | # define IH_MC_SWAP_64BIT 3 |
474 | # define RPTR_REARM (1 << 4) |
475 | # define RPTR_REARM (1 << 4) |
475 | # define MC_WRREQ_CREDIT(x) ((x) << 15) |
476 | # define MC_WRREQ_CREDIT(x) ((x) << 15) |
476 | # define MC_WR_CLEAN_CNT(x) ((x) << 20) |
477 | # define MC_WR_CLEAN_CNT(x) ((x) << 20) |
477 | 478 | ||
478 | #define CP_INT_CNTL 0xc124 |
479 | #define CP_INT_CNTL 0xc124 |
479 | # define CNTX_BUSY_INT_ENABLE (1 << 19) |
480 | # define CNTX_BUSY_INT_ENABLE (1 << 19) |
480 | # define CNTX_EMPTY_INT_ENABLE (1 << 20) |
481 | # define CNTX_EMPTY_INT_ENABLE (1 << 20) |
481 | # define SCRATCH_INT_ENABLE (1 << 25) |
482 | # define SCRATCH_INT_ENABLE (1 << 25) |
482 | # define TIME_STAMP_INT_ENABLE (1 << 26) |
483 | # define TIME_STAMP_INT_ENABLE (1 << 26) |
483 | # define IB2_INT_ENABLE (1 << 29) |
484 | # define IB2_INT_ENABLE (1 << 29) |
484 | # define IB1_INT_ENABLE (1 << 30) |
485 | # define IB1_INT_ENABLE (1 << 30) |
485 | # define RB_INT_ENABLE (1 << 31) |
486 | # define RB_INT_ENABLE (1 << 31) |
486 | #define CP_INT_STATUS 0xc128 |
487 | #define CP_INT_STATUS 0xc128 |
487 | # define SCRATCH_INT_STAT (1 << 25) |
488 | # define SCRATCH_INT_STAT (1 << 25) |
488 | # define TIME_STAMP_INT_STAT (1 << 26) |
489 | # define TIME_STAMP_INT_STAT (1 << 26) |
489 | # define IB2_INT_STAT (1 << 29) |
490 | # define IB2_INT_STAT (1 << 29) |
490 | # define IB1_INT_STAT (1 << 30) |
491 | # define IB1_INT_STAT (1 << 30) |
491 | # define RB_INT_STAT (1 << 31) |
492 | # define RB_INT_STAT (1 << 31) |
492 | 493 | ||
493 | #define GRBM_INT_CNTL 0x8060 |
494 | #define GRBM_INT_CNTL 0x8060 |
494 | # define RDERR_INT_ENABLE (1 << 0) |
495 | # define RDERR_INT_ENABLE (1 << 0) |
495 | # define GUI_IDLE_INT_ENABLE (1 << 19) |
496 | # define GUI_IDLE_INT_ENABLE (1 << 19) |
496 | 497 | ||
497 | /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ |
498 | /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ |
498 | #define CRTC_STATUS_FRAME_COUNT 0x6e98 |
499 | #define CRTC_STATUS_FRAME_COUNT 0x6e98 |
499 | 500 | ||
500 | /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ |
501 | /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ |
501 | #define VLINE_STATUS 0x6bb8 |
502 | #define VLINE_STATUS 0x6bb8 |
502 | # define VLINE_OCCURRED (1 << 0) |
503 | # define VLINE_OCCURRED (1 << 0) |
503 | # define VLINE_ACK (1 << 4) |
504 | # define VLINE_ACK (1 << 4) |
504 | # define VLINE_STAT (1 << 12) |
505 | # define VLINE_STAT (1 << 12) |
505 | # define VLINE_INTERRUPT (1 << 16) |
506 | # define VLINE_INTERRUPT (1 << 16) |
506 | # define VLINE_INTERRUPT_TYPE (1 << 17) |
507 | # define VLINE_INTERRUPT_TYPE (1 << 17) |
507 | /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ |
508 | /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ |
508 | #define VBLANK_STATUS 0x6bbc |
509 | #define VBLANK_STATUS 0x6bbc |
509 | # define VBLANK_OCCURRED (1 << 0) |
510 | # define VBLANK_OCCURRED (1 << 0) |
510 | # define VBLANK_ACK (1 << 4) |
511 | # define VBLANK_ACK (1 << 4) |
511 | # define VBLANK_STAT (1 << 12) |
512 | # define VBLANK_STAT (1 << 12) |
512 | # define VBLANK_INTERRUPT (1 << 16) |
513 | # define VBLANK_INTERRUPT (1 << 16) |
513 | # define VBLANK_INTERRUPT_TYPE (1 << 17) |
514 | # define VBLANK_INTERRUPT_TYPE (1 << 17) |
514 | 515 | ||
515 | /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ |
516 | /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ |
516 | #define INT_MASK 0x6b40 |
517 | #define INT_MASK 0x6b40 |
517 | # define VBLANK_INT_MASK (1 << 0) |
518 | # define VBLANK_INT_MASK (1 << 0) |
518 | # define VLINE_INT_MASK (1 << 4) |
519 | # define VLINE_INT_MASK (1 << 4) |
519 | 520 | ||
520 | #define DISP_INTERRUPT_STATUS 0x60f4 |
521 | #define DISP_INTERRUPT_STATUS 0x60f4 |
521 | # define LB_D1_VLINE_INTERRUPT (1 << 2) |
522 | # define LB_D1_VLINE_INTERRUPT (1 << 2) |
522 | # define LB_D1_VBLANK_INTERRUPT (1 << 3) |
523 | # define LB_D1_VBLANK_INTERRUPT (1 << 3) |
523 | # define DC_HPD1_INTERRUPT (1 << 17) |
524 | # define DC_HPD1_INTERRUPT (1 << 17) |
524 | # define DC_HPD1_RX_INTERRUPT (1 << 18) |
525 | # define DC_HPD1_RX_INTERRUPT (1 << 18) |
525 | # define DACA_AUTODETECT_INTERRUPT (1 << 22) |
526 | # define DACA_AUTODETECT_INTERRUPT (1 << 22) |
526 | # define DACB_AUTODETECT_INTERRUPT (1 << 23) |
527 | # define DACB_AUTODETECT_INTERRUPT (1 << 23) |
527 | # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) |
528 | # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) |
528 | # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) |
529 | # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) |
529 | #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 |
530 | #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 |
530 | # define LB_D2_VLINE_INTERRUPT (1 << 2) |
531 | # define LB_D2_VLINE_INTERRUPT (1 << 2) |
531 | # define LB_D2_VBLANK_INTERRUPT (1 << 3) |
532 | # define LB_D2_VBLANK_INTERRUPT (1 << 3) |
532 | # define DC_HPD2_INTERRUPT (1 << 17) |
533 | # define DC_HPD2_INTERRUPT (1 << 17) |
533 | # define DC_HPD2_RX_INTERRUPT (1 << 18) |
534 | # define DC_HPD2_RX_INTERRUPT (1 << 18) |
534 | # define DISP_TIMER_INTERRUPT (1 << 24) |
535 | # define DISP_TIMER_INTERRUPT (1 << 24) |
535 | #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc |
536 | #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc |
536 | # define LB_D3_VLINE_INTERRUPT (1 << 2) |
537 | # define LB_D3_VLINE_INTERRUPT (1 << 2) |
537 | # define LB_D3_VBLANK_INTERRUPT (1 << 3) |
538 | # define LB_D3_VBLANK_INTERRUPT (1 << 3) |
538 | # define DC_HPD3_INTERRUPT (1 << 17) |
539 | # define DC_HPD3_INTERRUPT (1 << 17) |
539 | # define DC_HPD3_RX_INTERRUPT (1 << 18) |
540 | # define DC_HPD3_RX_INTERRUPT (1 << 18) |
540 | #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 |
541 | #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 |
541 | # define LB_D4_VLINE_INTERRUPT (1 << 2) |
542 | # define LB_D4_VLINE_INTERRUPT (1 << 2) |
542 | # define LB_D4_VBLANK_INTERRUPT (1 << 3) |
543 | # define LB_D4_VBLANK_INTERRUPT (1 << 3) |
543 | # define DC_HPD4_INTERRUPT (1 << 17) |
544 | # define DC_HPD4_INTERRUPT (1 << 17) |
544 | # define DC_HPD4_RX_INTERRUPT (1 << 18) |
545 | # define DC_HPD4_RX_INTERRUPT (1 << 18) |
545 | #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c |
546 | #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c |
546 | # define LB_D5_VLINE_INTERRUPT (1 << 2) |
547 | # define LB_D5_VLINE_INTERRUPT (1 << 2) |
547 | # define LB_D5_VBLANK_INTERRUPT (1 << 3) |
548 | # define LB_D5_VBLANK_INTERRUPT (1 << 3) |
548 | # define DC_HPD5_INTERRUPT (1 << 17) |
549 | # define DC_HPD5_INTERRUPT (1 << 17) |
549 | # define DC_HPD5_RX_INTERRUPT (1 << 18) |
550 | # define DC_HPD5_RX_INTERRUPT (1 << 18) |
550 | #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 |
551 | #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 |
551 | # define LB_D6_VLINE_INTERRUPT (1 << 2) |
552 | # define LB_D6_VLINE_INTERRUPT (1 << 2) |
552 | # define LB_D6_VBLANK_INTERRUPT (1 << 3) |
553 | # define LB_D6_VBLANK_INTERRUPT (1 << 3) |
553 | # define DC_HPD6_INTERRUPT (1 << 17) |
554 | # define DC_HPD6_INTERRUPT (1 << 17) |
554 | # define DC_HPD6_RX_INTERRUPT (1 << 18) |
555 | # define DC_HPD6_RX_INTERRUPT (1 << 18) |
555 | 556 | ||
556 | /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ |
557 | /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ |
557 | #define GRPH_INT_STATUS 0x6858 |
558 | #define GRPH_INT_STATUS 0x6858 |
558 | # define GRPH_PFLIP_INT_OCCURRED (1 << 0) |
559 | # define GRPH_PFLIP_INT_OCCURRED (1 << 0) |
559 | # define GRPH_PFLIP_INT_CLEAR (1 << 8) |
560 | # define GRPH_PFLIP_INT_CLEAR (1 << 8) |
560 | /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ |
561 | /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ |
561 | #define GRPH_INT_CONTROL 0x685c |
562 | #define GRPH_INT_CONTROL 0x685c |
562 | # define GRPH_PFLIP_INT_MASK (1 << 0) |
563 | # define GRPH_PFLIP_INT_MASK (1 << 0) |
563 | # define GRPH_PFLIP_INT_TYPE (1 << 8) |
564 | # define GRPH_PFLIP_INT_TYPE (1 << 8) |
564 | 565 | ||
565 | #define DACA_AUTODETECT_INT_CONTROL 0x66c8 |
566 | #define DACA_AUTODETECT_INT_CONTROL 0x66c8 |
566 | #define DACB_AUTODETECT_INT_CONTROL 0x67c8 |
567 | #define DACB_AUTODETECT_INT_CONTROL 0x67c8 |
567 | 568 | ||
568 | #define DC_HPD1_INT_STATUS 0x601c |
569 | #define DC_HPD1_INT_STATUS 0x601c |
569 | #define DC_HPD2_INT_STATUS 0x6028 |
570 | #define DC_HPD2_INT_STATUS 0x6028 |
570 | #define DC_HPD3_INT_STATUS 0x6034 |
571 | #define DC_HPD3_INT_STATUS 0x6034 |
571 | #define DC_HPD4_INT_STATUS 0x6040 |
572 | #define DC_HPD4_INT_STATUS 0x6040 |
572 | #define DC_HPD5_INT_STATUS 0x604c |
573 | #define DC_HPD5_INT_STATUS 0x604c |
573 | #define DC_HPD6_INT_STATUS 0x6058 |
574 | #define DC_HPD6_INT_STATUS 0x6058 |
574 | # define DC_HPDx_INT_STATUS (1 << 0) |
575 | # define DC_HPDx_INT_STATUS (1 << 0) |
575 | # define DC_HPDx_SENSE (1 << 1) |
576 | # define DC_HPDx_SENSE (1 << 1) |
576 | # define DC_HPDx_RX_INT_STATUS (1 << 8) |
577 | # define DC_HPDx_RX_INT_STATUS (1 << 8) |
577 | 578 | ||
578 | #define DC_HPD1_INT_CONTROL 0x6020 |
579 | #define DC_HPD1_INT_CONTROL 0x6020 |
579 | #define DC_HPD2_INT_CONTROL 0x602c |
580 | #define DC_HPD2_INT_CONTROL 0x602c |
580 | #define DC_HPD3_INT_CONTROL 0x6038 |
581 | #define DC_HPD3_INT_CONTROL 0x6038 |
581 | #define DC_HPD4_INT_CONTROL 0x6044 |
582 | #define DC_HPD4_INT_CONTROL 0x6044 |
582 | #define DC_HPD5_INT_CONTROL 0x6050 |
583 | #define DC_HPD5_INT_CONTROL 0x6050 |
583 | #define DC_HPD6_INT_CONTROL 0x605c |
584 | #define DC_HPD6_INT_CONTROL 0x605c |
584 | # define DC_HPDx_INT_ACK (1 << 0) |
585 | # define DC_HPDx_INT_ACK (1 << 0) |
585 | # define DC_HPDx_INT_POLARITY (1 << 8) |
586 | # define DC_HPDx_INT_POLARITY (1 << 8) |
586 | # define DC_HPDx_INT_EN (1 << 16) |
587 | # define DC_HPDx_INT_EN (1 << 16) |
587 | # define DC_HPDx_RX_INT_ACK (1 << 20) |
588 | # define DC_HPDx_RX_INT_ACK (1 << 20) |
588 | # define DC_HPDx_RX_INT_EN (1 << 24) |
589 | # define DC_HPDx_RX_INT_EN (1 << 24) |
589 | 590 | ||
590 | #define DC_HPD1_CONTROL 0x6024 |
591 | #define DC_HPD1_CONTROL 0x6024 |
591 | #define DC_HPD2_CONTROL 0x6030 |
592 | #define DC_HPD2_CONTROL 0x6030 |
592 | #define DC_HPD3_CONTROL 0x603c |
593 | #define DC_HPD3_CONTROL 0x603c |
593 | #define DC_HPD4_CONTROL 0x6048 |
594 | #define DC_HPD4_CONTROL 0x6048 |
594 | #define DC_HPD5_CONTROL 0x6054 |
595 | #define DC_HPD5_CONTROL 0x6054 |
595 | #define DC_HPD6_CONTROL 0x6060 |
596 | #define DC_HPD6_CONTROL 0x6060 |
596 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) |
597 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) |
597 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) |
598 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) |
598 | # define DC_HPDx_EN (1 << 28) |
599 | # define DC_HPDx_EN (1 << 28) |
599 | 600 | ||
600 | /* PCIE link stuff */ |
601 | /* PCIE link stuff */ |
601 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
602 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
602 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ |
603 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ |
603 | # define LC_LINK_WIDTH_SHIFT 0 |
604 | # define LC_LINK_WIDTH_SHIFT 0 |
604 | # define LC_LINK_WIDTH_MASK 0x7 |
605 | # define LC_LINK_WIDTH_MASK 0x7 |
605 | # define LC_LINK_WIDTH_X0 0 |
606 | # define LC_LINK_WIDTH_X0 0 |
606 | # define LC_LINK_WIDTH_X1 1 |
607 | # define LC_LINK_WIDTH_X1 1 |
607 | # define LC_LINK_WIDTH_X2 2 |
608 | # define LC_LINK_WIDTH_X2 2 |
608 | # define LC_LINK_WIDTH_X4 3 |
609 | # define LC_LINK_WIDTH_X4 3 |
609 | # define LC_LINK_WIDTH_X8 4 |
610 | # define LC_LINK_WIDTH_X8 4 |
610 | # define LC_LINK_WIDTH_X16 6 |
611 | # define LC_LINK_WIDTH_X16 6 |
611 | # define LC_LINK_WIDTH_RD_SHIFT 4 |
612 | # define LC_LINK_WIDTH_RD_SHIFT 4 |
612 | # define LC_LINK_WIDTH_RD_MASK 0x70 |
613 | # define LC_LINK_WIDTH_RD_MASK 0x70 |
613 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) |
614 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) |
614 | # define LC_RECONFIG_NOW (1 << 8) |
615 | # define LC_RECONFIG_NOW (1 << 8) |
615 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) |
616 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) |
616 | # define LC_RENEGOTIATE_EN (1 << 10) |
617 | # define LC_RENEGOTIATE_EN (1 << 10) |
617 | # define LC_SHORT_RECONFIG_EN (1 << 11) |
618 | # define LC_SHORT_RECONFIG_EN (1 << 11) |
618 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) |
619 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) |
619 | # define LC_UPCONFIGURE_DIS (1 << 13) |
620 | # define LC_UPCONFIGURE_DIS (1 << 13) |
620 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
621 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
621 | # define LC_GEN2_EN_STRAP (1 << 0) |
622 | # define LC_GEN2_EN_STRAP (1 << 0) |
622 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) |
623 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) |
623 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) |
624 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) |
624 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) |
625 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) |
625 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) |
626 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) |
626 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 |
627 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 |
627 | # define LC_CURRENT_DATA_RATE (1 << 11) |
628 | # define LC_CURRENT_DATA_RATE (1 << 11) |
628 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
629 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
629 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) |
630 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) |
630 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) |
631 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) |
631 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) |
632 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) |
632 | #define MM_CFGREGS_CNTL 0x544c |
633 | #define MM_CFGREGS_CNTL 0x544c |
633 | # define MM_WR_TO_CFG_EN (1 << 3) |
634 | # define MM_WR_TO_CFG_EN (1 << 3) |
634 | #define LINK_CNTL2 0x88 /* F0 */ |
635 | #define LINK_CNTL2 0x88 /* F0 */ |
635 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
636 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
636 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
637 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
637 | 638 | ||
638 | /* |
639 | /* |
639 | * PM4 |
640 | * PM4 |
640 | */ |
641 | */ |
641 | #define PACKET_TYPE0 0 |
642 | #define PACKET_TYPE0 0 |
642 | #define PACKET_TYPE1 1 |
643 | #define PACKET_TYPE1 1 |
643 | #define PACKET_TYPE2 2 |
644 | #define PACKET_TYPE2 2 |
644 | #define PACKET_TYPE3 3 |
645 | #define PACKET_TYPE3 3 |
645 | 646 | ||
646 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
647 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
647 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
648 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
648 | #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) |
649 | #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) |
649 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
650 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
650 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ |
651 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ |
651 | (((reg) >> 2) & 0xFFFF) | \ |
652 | (((reg) >> 2) & 0xFFFF) | \ |
652 | ((n) & 0x3FFF) << 16) |
653 | ((n) & 0x3FFF) << 16) |
653 | #define CP_PACKET2 0x80000000 |
654 | #define CP_PACKET2 0x80000000 |
654 | #define PACKET2_PAD_SHIFT 0 |
655 | #define PACKET2_PAD_SHIFT 0 |
655 | #define PACKET2_PAD_MASK (0x3fffffff << 0) |
656 | #define PACKET2_PAD_MASK (0x3fffffff << 0) |
656 | 657 | ||
657 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
658 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
658 | 659 | ||
659 | #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ |
660 | #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ |
660 | (((op) & 0xFF) << 8) | \ |
661 | (((op) & 0xFF) << 8) | \ |
661 | ((n) & 0x3FFF) << 16) |
662 | ((n) & 0x3FFF) << 16) |
662 | 663 | ||
663 | /* Packet 3 types */ |
664 | /* Packet 3 types */ |
664 | #define PACKET3_NOP 0x10 |
665 | #define PACKET3_NOP 0x10 |
665 | #define PACKET3_SET_BASE 0x11 |
666 | #define PACKET3_SET_BASE 0x11 |
666 | #define PACKET3_CLEAR_STATE 0x12 |
667 | #define PACKET3_CLEAR_STATE 0x12 |
667 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 |
668 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 |
668 | #define PACKET3_DISPATCH_DIRECT 0x15 |
669 | #define PACKET3_DISPATCH_DIRECT 0x15 |
669 | #define PACKET3_DISPATCH_INDIRECT 0x16 |
670 | #define PACKET3_DISPATCH_INDIRECT 0x16 |
670 | #define PACKET3_INDIRECT_BUFFER_END 0x17 |
671 | #define PACKET3_INDIRECT_BUFFER_END 0x17 |
671 | #define PACKET3_MODE_CONTROL 0x18 |
672 | #define PACKET3_MODE_CONTROL 0x18 |
672 | #define PACKET3_SET_PREDICATION 0x20 |
673 | #define PACKET3_SET_PREDICATION 0x20 |
673 | #define PACKET3_REG_RMW 0x21 |
674 | #define PACKET3_REG_RMW 0x21 |
674 | #define PACKET3_COND_EXEC 0x22 |
675 | #define PACKET3_COND_EXEC 0x22 |
675 | #define PACKET3_PRED_EXEC 0x23 |
676 | #define PACKET3_PRED_EXEC 0x23 |
676 | #define PACKET3_DRAW_INDIRECT 0x24 |
677 | #define PACKET3_DRAW_INDIRECT 0x24 |
677 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 |
678 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 |
678 | #define PACKET3_INDEX_BASE 0x26 |
679 | #define PACKET3_INDEX_BASE 0x26 |
679 | #define PACKET3_DRAW_INDEX_2 0x27 |
680 | #define PACKET3_DRAW_INDEX_2 0x27 |
680 | #define PACKET3_CONTEXT_CONTROL 0x28 |
681 | #define PACKET3_CONTEXT_CONTROL 0x28 |
681 | #define PACKET3_DRAW_INDEX_OFFSET 0x29 |
682 | #define PACKET3_DRAW_INDEX_OFFSET 0x29 |
682 | #define PACKET3_INDEX_TYPE 0x2A |
683 | #define PACKET3_INDEX_TYPE 0x2A |
683 | #define PACKET3_DRAW_INDEX 0x2B |
684 | #define PACKET3_DRAW_INDEX 0x2B |
684 | #define PACKET3_DRAW_INDEX_AUTO 0x2D |
685 | #define PACKET3_DRAW_INDEX_AUTO 0x2D |
685 | #define PACKET3_DRAW_INDEX_IMMD 0x2E |
686 | #define PACKET3_DRAW_INDEX_IMMD 0x2E |
686 | #define PACKET3_NUM_INSTANCES 0x2F |
687 | #define PACKET3_NUM_INSTANCES 0x2F |
687 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 |
688 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 |
688 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 |
689 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 |
689 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 |
690 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 |
690 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 |
691 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 |
691 | #define PACKET3_MEM_SEMAPHORE 0x39 |
692 | #define PACKET3_MEM_SEMAPHORE 0x39 |
692 | #define PACKET3_MPEG_INDEX 0x3A |
693 | #define PACKET3_MPEG_INDEX 0x3A |
693 | #define PACKET3_WAIT_REG_MEM 0x3C |
694 | #define PACKET3_WAIT_REG_MEM 0x3C |
694 | #define PACKET3_MEM_WRITE 0x3D |
695 | #define PACKET3_MEM_WRITE 0x3D |
695 | #define PACKET3_INDIRECT_BUFFER 0x32 |
696 | #define PACKET3_INDIRECT_BUFFER 0x32 |
696 | #define PACKET3_SURFACE_SYNC 0x43 |
697 | #define PACKET3_SURFACE_SYNC 0x43 |
697 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
698 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
698 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) |
699 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) |
699 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) |
700 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) |
700 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) |
701 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) |
701 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) |
702 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) |
702 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) |
703 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) |
703 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) |
704 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) |
704 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) |
705 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) |
705 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) |
706 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) |
706 | # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) |
707 | # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) |
707 | # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) |
708 | # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) |
708 | # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) |
709 | # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) |
709 | # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) |
710 | # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) |
710 | # define PACKET3_FULL_CACHE_ENA (1 << 20) |
711 | # define PACKET3_FULL_CACHE_ENA (1 << 20) |
711 | # define PACKET3_TC_ACTION_ENA (1 << 23) |
712 | # define PACKET3_TC_ACTION_ENA (1 << 23) |
712 | # define PACKET3_VC_ACTION_ENA (1 << 24) |
713 | # define PACKET3_VC_ACTION_ENA (1 << 24) |
713 | # define PACKET3_CB_ACTION_ENA (1 << 25) |
714 | # define PACKET3_CB_ACTION_ENA (1 << 25) |
714 | # define PACKET3_DB_ACTION_ENA (1 << 26) |
715 | # define PACKET3_DB_ACTION_ENA (1 << 26) |
715 | # define PACKET3_SH_ACTION_ENA (1 << 27) |
716 | # define PACKET3_SH_ACTION_ENA (1 << 27) |
716 | # define PACKET3_SX_ACTION_ENA (1 << 28) |
717 | # define PACKET3_SX_ACTION_ENA (1 << 28) |
717 | #define PACKET3_ME_INITIALIZE 0x44 |
718 | #define PACKET3_ME_INITIALIZE 0x44 |
718 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) |
719 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) |
719 | #define PACKET3_COND_WRITE 0x45 |
720 | #define PACKET3_COND_WRITE 0x45 |
720 | #define PACKET3_EVENT_WRITE 0x46 |
721 | #define PACKET3_EVENT_WRITE 0x46 |
721 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
722 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
722 | #define PACKET3_EVENT_WRITE_EOS 0x48 |
723 | #define PACKET3_EVENT_WRITE_EOS 0x48 |
723 | #define PACKET3_PREAMBLE_CNTL 0x4A |
724 | #define PACKET3_PREAMBLE_CNTL 0x4A |
724 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) |
725 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) |
725 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) |
726 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) |
726 | #define PACKET3_RB_OFFSET 0x4B |
727 | #define PACKET3_RB_OFFSET 0x4B |
727 | #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C |
728 | #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C |
728 | #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D |
729 | #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D |
729 | #define PACKET3_ALU_PS_CONST_UPDATE 0x4E |
730 | #define PACKET3_ALU_PS_CONST_UPDATE 0x4E |
730 | #define PACKET3_ALU_VS_CONST_UPDATE 0x4F |
731 | #define PACKET3_ALU_VS_CONST_UPDATE 0x4F |
731 | #define PACKET3_ONE_REG_WRITE 0x57 |
732 | #define PACKET3_ONE_REG_WRITE 0x57 |
732 | #define PACKET3_SET_CONFIG_REG 0x68 |
733 | #define PACKET3_SET_CONFIG_REG 0x68 |
733 | #define PACKET3_SET_CONFIG_REG_START 0x00008000 |
734 | #define PACKET3_SET_CONFIG_REG_START 0x00008000 |
734 | #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 |
735 | #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 |
735 | #define PACKET3_SET_CONTEXT_REG 0x69 |
736 | #define PACKET3_SET_CONTEXT_REG 0x69 |
736 | #define PACKET3_SET_CONTEXT_REG_START 0x00028000 |
737 | #define PACKET3_SET_CONTEXT_REG_START 0x00028000 |
737 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 |
738 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 |
738 | #define PACKET3_SET_ALU_CONST 0x6A |
739 | #define PACKET3_SET_ALU_CONST 0x6A |
739 | /* alu const buffers only; no reg file */ |
740 | /* alu const buffers only; no reg file */ |
740 | #define PACKET3_SET_BOOL_CONST 0x6B |
741 | #define PACKET3_SET_BOOL_CONST 0x6B |
741 | #define PACKET3_SET_BOOL_CONST_START 0x0003a500 |
742 | #define PACKET3_SET_BOOL_CONST_START 0x0003a500 |
742 | #define PACKET3_SET_BOOL_CONST_END 0x0003a518 |
743 | #define PACKET3_SET_BOOL_CONST_END 0x0003a518 |
743 | #define PACKET3_SET_LOOP_CONST 0x6C |
744 | #define PACKET3_SET_LOOP_CONST 0x6C |
744 | #define PACKET3_SET_LOOP_CONST_START 0x0003a200 |
745 | #define PACKET3_SET_LOOP_CONST_START 0x0003a200 |
745 | #define PACKET3_SET_LOOP_CONST_END 0x0003a500 |
746 | #define PACKET3_SET_LOOP_CONST_END 0x0003a500 |
746 | #define PACKET3_SET_RESOURCE 0x6D |
747 | #define PACKET3_SET_RESOURCE 0x6D |
747 | #define PACKET3_SET_RESOURCE_START 0x00030000 |
748 | #define PACKET3_SET_RESOURCE_START 0x00030000 |
748 | #define PACKET3_SET_RESOURCE_END 0x00038000 |
749 | #define PACKET3_SET_RESOURCE_END 0x00038000 |
749 | #define PACKET3_SET_SAMPLER 0x6E |
750 | #define PACKET3_SET_SAMPLER 0x6E |
750 | #define PACKET3_SET_SAMPLER_START 0x0003c000 |
751 | #define PACKET3_SET_SAMPLER_START 0x0003c000 |
751 | #define PACKET3_SET_SAMPLER_END 0x0003c600 |
752 | #define PACKET3_SET_SAMPLER_END 0x0003c600 |
752 | #define PACKET3_SET_CTL_CONST 0x6F |
753 | #define PACKET3_SET_CTL_CONST 0x6F |
753 | #define PACKET3_SET_CTL_CONST_START 0x0003cff0 |
754 | #define PACKET3_SET_CTL_CONST_START 0x0003cff0 |
754 | #define PACKET3_SET_CTL_CONST_END 0x0003ff0c |
755 | #define PACKET3_SET_CTL_CONST_END 0x0003ff0c |
755 | #define PACKET3_SET_RESOURCE_OFFSET 0x70 |
756 | #define PACKET3_SET_RESOURCE_OFFSET 0x70 |
756 | #define PACKET3_SET_ALU_CONST_VS 0x71 |
757 | #define PACKET3_SET_ALU_CONST_VS 0x71 |
757 | #define PACKET3_SET_ALU_CONST_DI 0x72 |
758 | #define PACKET3_SET_ALU_CONST_DI 0x72 |
758 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 |
759 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 |
759 | #define PACKET3_SET_RESOURCE_INDIRECT 0x74 |
760 | #define PACKET3_SET_RESOURCE_INDIRECT 0x74 |
760 | #define PACKET3_SET_APPEND_CNT 0x75 |
761 | #define PACKET3_SET_APPEND_CNT 0x75 |
761 | 762 | ||
762 | #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c |
763 | #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c |
763 | #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) |
764 | #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) |
764 | #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) |
765 | #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) |
765 | #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 |
766 | #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 |
766 | #define SQ_TEX_VTX_INVALID_BUFFER 0x1 |
767 | #define SQ_TEX_VTX_INVALID_BUFFER 0x1 |
767 | #define SQ_TEX_VTX_VALID_TEXTURE 0x2 |
768 | #define SQ_TEX_VTX_VALID_TEXTURE 0x2 |
768 | #define SQ_TEX_VTX_VALID_BUFFER 0x3 |
769 | #define SQ_TEX_VTX_VALID_BUFFER 0x3 |
769 | 770 | ||
770 | #define SQ_CONST_MEM_BASE 0x8df8 |
771 | #define SQ_CONST_MEM_BASE 0x8df8 |
771 | 772 | ||
772 | #define SQ_ESGS_RING_BASE 0x8c40 |
773 | #define SQ_ESGS_RING_BASE 0x8c40 |
773 | #define SQ_ESGS_RING_SIZE 0x8c44 |
774 | #define SQ_ESGS_RING_SIZE 0x8c44 |
774 | #define SQ_GSVS_RING_BASE 0x8c48 |
775 | #define SQ_GSVS_RING_BASE 0x8c48 |
775 | #define SQ_GSVS_RING_SIZE 0x8c4c |
776 | #define SQ_GSVS_RING_SIZE 0x8c4c |
776 | #define SQ_ESTMP_RING_BASE 0x8c50 |
777 | #define SQ_ESTMP_RING_BASE 0x8c50 |
777 | #define SQ_ESTMP_RING_SIZE 0x8c54 |
778 | #define SQ_ESTMP_RING_SIZE 0x8c54 |
778 | #define SQ_GSTMP_RING_BASE 0x8c58 |
779 | #define SQ_GSTMP_RING_BASE 0x8c58 |
779 | #define SQ_GSTMP_RING_SIZE 0x8c5c |
780 | #define SQ_GSTMP_RING_SIZE 0x8c5c |
780 | #define SQ_VSTMP_RING_BASE 0x8c60 |
781 | #define SQ_VSTMP_RING_BASE 0x8c60 |
781 | #define SQ_VSTMP_RING_SIZE 0x8c64 |
782 | #define SQ_VSTMP_RING_SIZE 0x8c64 |
782 | #define SQ_PSTMP_RING_BASE 0x8c68 |
783 | #define SQ_PSTMP_RING_BASE 0x8c68 |
783 | #define SQ_PSTMP_RING_SIZE 0x8c6c |
784 | #define SQ_PSTMP_RING_SIZE 0x8c6c |
784 | #define SQ_LSTMP_RING_BASE 0x8e10 |
785 | #define SQ_LSTMP_RING_BASE 0x8e10 |
785 | #define SQ_LSTMP_RING_SIZE 0x8e14 |
786 | #define SQ_LSTMP_RING_SIZE 0x8e14 |
786 | #define SQ_HSTMP_RING_BASE 0x8e18 |
787 | #define SQ_HSTMP_RING_BASE 0x8e18 |
787 | #define SQ_HSTMP_RING_SIZE 0x8e1c |
788 | #define SQ_HSTMP_RING_SIZE 0x8e1c |
788 | #define VGT_TF_RING_SIZE 0x8988 |
789 | #define VGT_TF_RING_SIZE 0x8988 |
789 | 790 | ||
790 | #define SQ_ESGS_RING_ITEMSIZE 0x28900 |
791 | #define SQ_ESGS_RING_ITEMSIZE 0x28900 |
791 | #define SQ_GSVS_RING_ITEMSIZE 0x28904 |
792 | #define SQ_GSVS_RING_ITEMSIZE 0x28904 |
792 | #define SQ_ESTMP_RING_ITEMSIZE 0x28908 |
793 | #define SQ_ESTMP_RING_ITEMSIZE 0x28908 |
793 | #define SQ_GSTMP_RING_ITEMSIZE 0x2890c |
794 | #define SQ_GSTMP_RING_ITEMSIZE 0x2890c |
794 | #define SQ_VSTMP_RING_ITEMSIZE 0x28910 |
795 | #define SQ_VSTMP_RING_ITEMSIZE 0x28910 |
795 | #define SQ_PSTMP_RING_ITEMSIZE 0x28914 |
796 | #define SQ_PSTMP_RING_ITEMSIZE 0x28914 |
796 | #define SQ_LSTMP_RING_ITEMSIZE 0x28830 |
797 | #define SQ_LSTMP_RING_ITEMSIZE 0x28830 |
797 | #define SQ_HSTMP_RING_ITEMSIZE 0x28834 |
798 | #define SQ_HSTMP_RING_ITEMSIZE 0x28834 |
798 | 799 | ||
799 | #define SQ_GS_VERT_ITEMSIZE 0x2891c |
800 | #define SQ_GS_VERT_ITEMSIZE 0x2891c |
800 | #define SQ_GS_VERT_ITEMSIZE_1 0x28920 |
801 | #define SQ_GS_VERT_ITEMSIZE_1 0x28920 |
801 | #define SQ_GS_VERT_ITEMSIZE_2 0x28924 |
802 | #define SQ_GS_VERT_ITEMSIZE_2 0x28924 |
802 | #define SQ_GS_VERT_ITEMSIZE_3 0x28928 |
803 | #define SQ_GS_VERT_ITEMSIZE_3 0x28928 |
803 | #define SQ_GSVS_RING_OFFSET_1 0x2892c |
804 | #define SQ_GSVS_RING_OFFSET_1 0x2892c |
804 | #define SQ_GSVS_RING_OFFSET_2 0x28930 |
805 | #define SQ_GSVS_RING_OFFSET_2 0x28930 |
805 | #define SQ_GSVS_RING_OFFSET_3 0x28934 |
806 | #define SQ_GSVS_RING_OFFSET_3 0x28934 |
806 | 807 | ||
807 | #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 |
808 | #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 |
808 | #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 |
809 | #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 |
809 | 810 | ||
810 | #define SQ_ALU_CONST_CACHE_PS_0 0x28940 |
811 | #define SQ_ALU_CONST_CACHE_PS_0 0x28940 |
811 | #define SQ_ALU_CONST_CACHE_PS_1 0x28944 |
812 | #define SQ_ALU_CONST_CACHE_PS_1 0x28944 |
812 | #define SQ_ALU_CONST_CACHE_PS_2 0x28948 |
813 | #define SQ_ALU_CONST_CACHE_PS_2 0x28948 |
813 | #define SQ_ALU_CONST_CACHE_PS_3 0x2894c |
814 | #define SQ_ALU_CONST_CACHE_PS_3 0x2894c |
814 | #define SQ_ALU_CONST_CACHE_PS_4 0x28950 |
815 | #define SQ_ALU_CONST_CACHE_PS_4 0x28950 |
815 | #define SQ_ALU_CONST_CACHE_PS_5 0x28954 |
816 | #define SQ_ALU_CONST_CACHE_PS_5 0x28954 |
816 | #define SQ_ALU_CONST_CACHE_PS_6 0x28958 |
817 | #define SQ_ALU_CONST_CACHE_PS_6 0x28958 |
817 | #define SQ_ALU_CONST_CACHE_PS_7 0x2895c |
818 | #define SQ_ALU_CONST_CACHE_PS_7 0x2895c |
818 | #define SQ_ALU_CONST_CACHE_PS_8 0x28960 |
819 | #define SQ_ALU_CONST_CACHE_PS_8 0x28960 |
819 | #define SQ_ALU_CONST_CACHE_PS_9 0x28964 |
820 | #define SQ_ALU_CONST_CACHE_PS_9 0x28964 |
820 | #define SQ_ALU_CONST_CACHE_PS_10 0x28968 |
821 | #define SQ_ALU_CONST_CACHE_PS_10 0x28968 |
821 | #define SQ_ALU_CONST_CACHE_PS_11 0x2896c |
822 | #define SQ_ALU_CONST_CACHE_PS_11 0x2896c |
822 | #define SQ_ALU_CONST_CACHE_PS_12 0x28970 |
823 | #define SQ_ALU_CONST_CACHE_PS_12 0x28970 |
823 | #define SQ_ALU_CONST_CACHE_PS_13 0x28974 |
824 | #define SQ_ALU_CONST_CACHE_PS_13 0x28974 |
824 | #define SQ_ALU_CONST_CACHE_PS_14 0x28978 |
825 | #define SQ_ALU_CONST_CACHE_PS_14 0x28978 |
825 | #define SQ_ALU_CONST_CACHE_PS_15 0x2897c |
826 | #define SQ_ALU_CONST_CACHE_PS_15 0x2897c |
826 | #define SQ_ALU_CONST_CACHE_VS_0 0x28980 |
827 | #define SQ_ALU_CONST_CACHE_VS_0 0x28980 |
827 | #define SQ_ALU_CONST_CACHE_VS_1 0x28984 |
828 | #define SQ_ALU_CONST_CACHE_VS_1 0x28984 |
828 | #define SQ_ALU_CONST_CACHE_VS_2 0x28988 |
829 | #define SQ_ALU_CONST_CACHE_VS_2 0x28988 |
829 | #define SQ_ALU_CONST_CACHE_VS_3 0x2898c |
830 | #define SQ_ALU_CONST_CACHE_VS_3 0x2898c |
830 | #define SQ_ALU_CONST_CACHE_VS_4 0x28990 |
831 | #define SQ_ALU_CONST_CACHE_VS_4 0x28990 |
831 | #define SQ_ALU_CONST_CACHE_VS_5 0x28994 |
832 | #define SQ_ALU_CONST_CACHE_VS_5 0x28994 |
832 | #define SQ_ALU_CONST_CACHE_VS_6 0x28998 |
833 | #define SQ_ALU_CONST_CACHE_VS_6 0x28998 |
833 | #define SQ_ALU_CONST_CACHE_VS_7 0x2899c |
834 | #define SQ_ALU_CONST_CACHE_VS_7 0x2899c |
834 | #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 |
835 | #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 |
835 | #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 |
836 | #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 |
836 | #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 |
837 | #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 |
837 | #define SQ_ALU_CONST_CACHE_VS_11 0x289ac |
838 | #define SQ_ALU_CONST_CACHE_VS_11 0x289ac |
838 | #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 |
839 | #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 |
839 | #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 |
840 | #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 |
840 | #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 |
841 | #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 |
841 | #define SQ_ALU_CONST_CACHE_VS_15 0x289bc |
842 | #define SQ_ALU_CONST_CACHE_VS_15 0x289bc |
842 | #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 |
843 | #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 |
843 | #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 |
844 | #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 |
844 | #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 |
845 | #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 |
845 | #define SQ_ALU_CONST_CACHE_GS_3 0x289cc |
846 | #define SQ_ALU_CONST_CACHE_GS_3 0x289cc |
846 | #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 |
847 | #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 |
847 | #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 |
848 | #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 |
848 | #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 |
849 | #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 |
849 | #define SQ_ALU_CONST_CACHE_GS_7 0x289dc |
850 | #define SQ_ALU_CONST_CACHE_GS_7 0x289dc |
850 | #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 |
851 | #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 |
851 | #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 |
852 | #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 |
852 | #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 |
853 | #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 |
853 | #define SQ_ALU_CONST_CACHE_GS_11 0x289ec |
854 | #define SQ_ALU_CONST_CACHE_GS_11 0x289ec |
854 | #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 |
855 | #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 |
855 | #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 |
856 | #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 |
856 | #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 |
857 | #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 |
857 | #define SQ_ALU_CONST_CACHE_GS_15 0x289fc |
858 | #define SQ_ALU_CONST_CACHE_GS_15 0x289fc |
858 | #define SQ_ALU_CONST_CACHE_HS_0 0x28f00 |
859 | #define SQ_ALU_CONST_CACHE_HS_0 0x28f00 |
859 | #define SQ_ALU_CONST_CACHE_HS_1 0x28f04 |
860 | #define SQ_ALU_CONST_CACHE_HS_1 0x28f04 |
860 | #define SQ_ALU_CONST_CACHE_HS_2 0x28f08 |
861 | #define SQ_ALU_CONST_CACHE_HS_2 0x28f08 |
861 | #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c |
862 | #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c |
862 | #define SQ_ALU_CONST_CACHE_HS_4 0x28f10 |
863 | #define SQ_ALU_CONST_CACHE_HS_4 0x28f10 |
863 | #define SQ_ALU_CONST_CACHE_HS_5 0x28f14 |
864 | #define SQ_ALU_CONST_CACHE_HS_5 0x28f14 |
864 | #define SQ_ALU_CONST_CACHE_HS_6 0x28f18 |
865 | #define SQ_ALU_CONST_CACHE_HS_6 0x28f18 |
865 | #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c |
866 | #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c |
866 | #define SQ_ALU_CONST_CACHE_HS_8 0x28f20 |
867 | #define SQ_ALU_CONST_CACHE_HS_8 0x28f20 |
867 | #define SQ_ALU_CONST_CACHE_HS_9 0x28f24 |
868 | #define SQ_ALU_CONST_CACHE_HS_9 0x28f24 |
868 | #define SQ_ALU_CONST_CACHE_HS_10 0x28f28 |
869 | #define SQ_ALU_CONST_CACHE_HS_10 0x28f28 |
869 | #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c |
870 | #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c |
870 | #define SQ_ALU_CONST_CACHE_HS_12 0x28f30 |
871 | #define SQ_ALU_CONST_CACHE_HS_12 0x28f30 |
871 | #define SQ_ALU_CONST_CACHE_HS_13 0x28f34 |
872 | #define SQ_ALU_CONST_CACHE_HS_13 0x28f34 |
872 | #define SQ_ALU_CONST_CACHE_HS_14 0x28f38 |
873 | #define SQ_ALU_CONST_CACHE_HS_14 0x28f38 |
873 | #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c |
874 | #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c |
874 | #define SQ_ALU_CONST_CACHE_LS_0 0x28f40 |
875 | #define SQ_ALU_CONST_CACHE_LS_0 0x28f40 |
875 | #define SQ_ALU_CONST_CACHE_LS_1 0x28f44 |
876 | #define SQ_ALU_CONST_CACHE_LS_1 0x28f44 |
876 | #define SQ_ALU_CONST_CACHE_LS_2 0x28f48 |
877 | #define SQ_ALU_CONST_CACHE_LS_2 0x28f48 |
877 | #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c |
878 | #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c |
878 | #define SQ_ALU_CONST_CACHE_LS_4 0x28f50 |
879 | #define SQ_ALU_CONST_CACHE_LS_4 0x28f50 |
879 | #define SQ_ALU_CONST_CACHE_LS_5 0x28f54 |
880 | #define SQ_ALU_CONST_CACHE_LS_5 0x28f54 |
880 | #define SQ_ALU_CONST_CACHE_LS_6 0x28f58 |
881 | #define SQ_ALU_CONST_CACHE_LS_6 0x28f58 |
881 | #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c |
882 | #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c |
882 | #define SQ_ALU_CONST_CACHE_LS_8 0x28f60 |
883 | #define SQ_ALU_CONST_CACHE_LS_8 0x28f60 |
883 | #define SQ_ALU_CONST_CACHE_LS_9 0x28f64 |
884 | #define SQ_ALU_CONST_CACHE_LS_9 0x28f64 |
884 | #define SQ_ALU_CONST_CACHE_LS_10 0x28f68 |
885 | #define SQ_ALU_CONST_CACHE_LS_10 0x28f68 |
885 | #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c |
886 | #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c |
886 | #define SQ_ALU_CONST_CACHE_LS_12 0x28f70 |
887 | #define SQ_ALU_CONST_CACHE_LS_12 0x28f70 |
887 | #define SQ_ALU_CONST_CACHE_LS_13 0x28f74 |
888 | #define SQ_ALU_CONST_CACHE_LS_13 0x28f74 |
888 | #define SQ_ALU_CONST_CACHE_LS_14 0x28f78 |
889 | #define SQ_ALU_CONST_CACHE_LS_14 0x28f78 |
889 | #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c |
890 | #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c |
890 | 891 | ||
891 | #define PA_SC_SCREEN_SCISSOR_TL 0x28030 |
892 | #define PA_SC_SCREEN_SCISSOR_TL 0x28030 |
892 | #define PA_SC_GENERIC_SCISSOR_TL 0x28240 |
893 | #define PA_SC_GENERIC_SCISSOR_TL 0x28240 |
893 | #define PA_SC_WINDOW_SCISSOR_TL 0x28204 |
894 | #define PA_SC_WINDOW_SCISSOR_TL 0x28204 |
894 | #define VGT_PRIMITIVE_TYPE 0x8958 |
895 | #define VGT_PRIMITIVE_TYPE 0x8958 |
895 | 896 | ||
896 | #define DB_DEPTH_CONTROL 0x28800 |
897 | #define DB_DEPTH_CONTROL 0x28800 |
897 | #define DB_DEPTH_VIEW 0x28008 |
898 | #define DB_DEPTH_VIEW 0x28008 |
898 | #define DB_HTILE_DATA_BASE 0x28014 |
899 | #define DB_HTILE_DATA_BASE 0x28014 |
899 | #define DB_Z_INFO 0x28040 |
900 | #define DB_Z_INFO 0x28040 |
900 | # define Z_ARRAY_MODE(x) ((x) << 4) |
901 | # define Z_ARRAY_MODE(x) ((x) << 4) |
901 | #define DB_STENCIL_INFO 0x28044 |
902 | #define DB_STENCIL_INFO 0x28044 |
902 | #define DB_Z_READ_BASE 0x28048 |
903 | #define DB_Z_READ_BASE 0x28048 |
903 | #define DB_STENCIL_READ_BASE 0x2804c |
904 | #define DB_STENCIL_READ_BASE 0x2804c |
904 | #define DB_Z_WRITE_BASE 0x28050 |
905 | #define DB_Z_WRITE_BASE 0x28050 |
905 | #define DB_STENCIL_WRITE_BASE 0x28054 |
906 | #define DB_STENCIL_WRITE_BASE 0x28054 |
906 | #define DB_DEPTH_SIZE 0x28058 |
907 | #define DB_DEPTH_SIZE 0x28058 |
907 | 908 | ||
908 | #define SQ_PGM_START_PS 0x28840 |
909 | #define SQ_PGM_START_PS 0x28840 |
909 | #define SQ_PGM_START_VS 0x2885c |
910 | #define SQ_PGM_START_VS 0x2885c |
910 | #define SQ_PGM_START_GS 0x28874 |
911 | #define SQ_PGM_START_GS 0x28874 |
911 | #define SQ_PGM_START_ES 0x2888c |
912 | #define SQ_PGM_START_ES 0x2888c |
912 | #define SQ_PGM_START_FS 0x288a4 |
913 | #define SQ_PGM_START_FS 0x288a4 |
913 | #define SQ_PGM_START_HS 0x288b8 |
914 | #define SQ_PGM_START_HS 0x288b8 |
914 | #define SQ_PGM_START_LS 0x288d0 |
915 | #define SQ_PGM_START_LS 0x288d0 |
915 | 916 | ||
916 | #define VGT_STRMOUT_CONFIG 0x28b94 |
917 | #define VGT_STRMOUT_CONFIG 0x28b94 |
917 | #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 |
918 | #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 |
918 | 919 | ||
919 | #define CB_TARGET_MASK 0x28238 |
920 | #define CB_TARGET_MASK 0x28238 |
920 | #define CB_SHADER_MASK 0x2823c |
921 | #define CB_SHADER_MASK 0x2823c |
921 | 922 | ||
922 | #define GDS_ADDR_BASE 0x28720 |
923 | #define GDS_ADDR_BASE 0x28720 |
923 | 924 | ||
924 | #define CB_IMMED0_BASE 0x28b9c |
925 | #define CB_IMMED0_BASE 0x28b9c |
925 | #define CB_IMMED1_BASE 0x28ba0 |
926 | #define CB_IMMED1_BASE 0x28ba0 |
926 | #define CB_IMMED2_BASE 0x28ba4 |
927 | #define CB_IMMED2_BASE 0x28ba4 |
927 | #define CB_IMMED3_BASE 0x28ba8 |
928 | #define CB_IMMED3_BASE 0x28ba8 |
928 | #define CB_IMMED4_BASE 0x28bac |
929 | #define CB_IMMED4_BASE 0x28bac |
929 | #define CB_IMMED5_BASE 0x28bb0 |
930 | #define CB_IMMED5_BASE 0x28bb0 |
930 | #define CB_IMMED6_BASE 0x28bb4 |
931 | #define CB_IMMED6_BASE 0x28bb4 |
931 | #define CB_IMMED7_BASE 0x28bb8 |
932 | #define CB_IMMED7_BASE 0x28bb8 |
932 | #define CB_IMMED8_BASE 0x28bbc |
933 | #define CB_IMMED8_BASE 0x28bbc |
933 | #define CB_IMMED9_BASE 0x28bc0 |
934 | #define CB_IMMED9_BASE 0x28bc0 |
934 | #define CB_IMMED10_BASE 0x28bc4 |
935 | #define CB_IMMED10_BASE 0x28bc4 |
935 | #define CB_IMMED11_BASE 0x28bc8 |
936 | #define CB_IMMED11_BASE 0x28bc8 |
936 | 937 | ||
937 | /* all 12 CB blocks have these regs */ |
938 | /* all 12 CB blocks have these regs */ |
938 | #define CB_COLOR0_BASE 0x28c60 |
939 | #define CB_COLOR0_BASE 0x28c60 |
939 | #define CB_COLOR0_PITCH 0x28c64 |
940 | #define CB_COLOR0_PITCH 0x28c64 |
940 | #define CB_COLOR0_SLICE 0x28c68 |
941 | #define CB_COLOR0_SLICE 0x28c68 |
941 | #define CB_COLOR0_VIEW 0x28c6c |
942 | #define CB_COLOR0_VIEW 0x28c6c |
942 | #define CB_COLOR0_INFO 0x28c70 |
943 | #define CB_COLOR0_INFO 0x28c70 |
943 | # define CB_ARRAY_MODE(x) ((x) << 8) |
944 | # define CB_ARRAY_MODE(x) ((x) << 8) |
944 | # define ARRAY_LINEAR_GENERAL 0 |
945 | # define ARRAY_LINEAR_GENERAL 0 |
945 | # define ARRAY_LINEAR_ALIGNED 1 |
946 | # define ARRAY_LINEAR_ALIGNED 1 |
946 | # define ARRAY_1D_TILED_THIN1 2 |
947 | # define ARRAY_1D_TILED_THIN1 2 |
947 | # define ARRAY_2D_TILED_THIN1 4 |
948 | # define ARRAY_2D_TILED_THIN1 4 |
948 | #define CB_COLOR0_ATTRIB 0x28c74 |
949 | #define CB_COLOR0_ATTRIB 0x28c74 |
949 | #define CB_COLOR0_DIM 0x28c78 |
950 | #define CB_COLOR0_DIM 0x28c78 |
950 | /* only CB0-7 blocks have these regs */ |
951 | /* only CB0-7 blocks have these regs */ |
951 | #define CB_COLOR0_CMASK 0x28c7c |
952 | #define CB_COLOR0_CMASK 0x28c7c |
952 | #define CB_COLOR0_CMASK_SLICE 0x28c80 |
953 | #define CB_COLOR0_CMASK_SLICE 0x28c80 |
953 | #define CB_COLOR0_FMASK 0x28c84 |
954 | #define CB_COLOR0_FMASK 0x28c84 |
954 | #define CB_COLOR0_FMASK_SLICE 0x28c88 |
955 | #define CB_COLOR0_FMASK_SLICE 0x28c88 |
955 | #define CB_COLOR0_CLEAR_WORD0 0x28c8c |
956 | #define CB_COLOR0_CLEAR_WORD0 0x28c8c |
956 | #define CB_COLOR0_CLEAR_WORD1 0x28c90 |
957 | #define CB_COLOR0_CLEAR_WORD1 0x28c90 |
957 | #define CB_COLOR0_CLEAR_WORD2 0x28c94 |
958 | #define CB_COLOR0_CLEAR_WORD2 0x28c94 |
958 | #define CB_COLOR0_CLEAR_WORD3 0x28c98 |
959 | #define CB_COLOR0_CLEAR_WORD3 0x28c98 |
959 | 960 | ||
960 | #define CB_COLOR1_BASE 0x28c9c |
961 | #define CB_COLOR1_BASE 0x28c9c |
961 | #define CB_COLOR2_BASE 0x28cd8 |
962 | #define CB_COLOR2_BASE 0x28cd8 |
962 | #define CB_COLOR3_BASE 0x28d14 |
963 | #define CB_COLOR3_BASE 0x28d14 |
963 | #define CB_COLOR4_BASE 0x28d50 |
964 | #define CB_COLOR4_BASE 0x28d50 |
964 | #define CB_COLOR5_BASE 0x28d8c |
965 | #define CB_COLOR5_BASE 0x28d8c |
965 | #define CB_COLOR6_BASE 0x28dc8 |
966 | #define CB_COLOR6_BASE 0x28dc8 |
966 | #define CB_COLOR7_BASE 0x28e04 |
967 | #define CB_COLOR7_BASE 0x28e04 |
967 | #define CB_COLOR8_BASE 0x28e40 |
968 | #define CB_COLOR8_BASE 0x28e40 |
968 | #define CB_COLOR9_BASE 0x28e5c |
969 | #define CB_COLOR9_BASE 0x28e5c |
969 | #define CB_COLOR10_BASE 0x28e78 |
970 | #define CB_COLOR10_BASE 0x28e78 |
970 | #define CB_COLOR11_BASE 0x28e94 |
971 | #define CB_COLOR11_BASE 0x28e94 |
971 | 972 | ||
972 | #define CB_COLOR1_PITCH 0x28ca0 |
973 | #define CB_COLOR1_PITCH 0x28ca0 |
973 | #define CB_COLOR2_PITCH 0x28cdc |
974 | #define CB_COLOR2_PITCH 0x28cdc |
974 | #define CB_COLOR3_PITCH 0x28d18 |
975 | #define CB_COLOR3_PITCH 0x28d18 |
975 | #define CB_COLOR4_PITCH 0x28d54 |
976 | #define CB_COLOR4_PITCH 0x28d54 |
976 | #define CB_COLOR5_PITCH 0x28d90 |
977 | #define CB_COLOR5_PITCH 0x28d90 |
977 | #define CB_COLOR6_PITCH 0x28dcc |
978 | #define CB_COLOR6_PITCH 0x28dcc |
978 | #define CB_COLOR7_PITCH 0x28e08 |
979 | #define CB_COLOR7_PITCH 0x28e08 |
979 | #define CB_COLOR8_PITCH 0x28e44 |
980 | #define CB_COLOR8_PITCH 0x28e44 |
980 | #define CB_COLOR9_PITCH 0x28e60 |
981 | #define CB_COLOR9_PITCH 0x28e60 |
981 | #define CB_COLOR10_PITCH 0x28e7c |
982 | #define CB_COLOR10_PITCH 0x28e7c |
982 | #define CB_COLOR11_PITCH 0x28e98 |
983 | #define CB_COLOR11_PITCH 0x28e98 |
983 | 984 | ||
984 | #define CB_COLOR1_SLICE 0x28ca4 |
985 | #define CB_COLOR1_SLICE 0x28ca4 |
985 | #define CB_COLOR2_SLICE 0x28ce0 |
986 | #define CB_COLOR2_SLICE 0x28ce0 |
986 | #define CB_COLOR3_SLICE 0x28d1c |
987 | #define CB_COLOR3_SLICE 0x28d1c |
987 | #define CB_COLOR4_SLICE 0x28d58 |
988 | #define CB_COLOR4_SLICE 0x28d58 |
988 | #define CB_COLOR5_SLICE 0x28d94 |
989 | #define CB_COLOR5_SLICE 0x28d94 |
989 | #define CB_COLOR6_SLICE 0x28dd0 |
990 | #define CB_COLOR6_SLICE 0x28dd0 |
990 | #define CB_COLOR7_SLICE 0x28e0c |
991 | #define CB_COLOR7_SLICE 0x28e0c |
991 | #define CB_COLOR8_SLICE 0x28e48 |
992 | #define CB_COLOR8_SLICE 0x28e48 |
992 | #define CB_COLOR9_SLICE 0x28e64 |
993 | #define CB_COLOR9_SLICE 0x28e64 |
993 | #define CB_COLOR10_SLICE 0x28e80 |
994 | #define CB_COLOR10_SLICE 0x28e80 |
994 | #define CB_COLOR11_SLICE 0x28e9c |
995 | #define CB_COLOR11_SLICE 0x28e9c |
995 | 996 | ||
996 | #define CB_COLOR1_VIEW 0x28ca8 |
997 | #define CB_COLOR1_VIEW 0x28ca8 |
997 | #define CB_COLOR2_VIEW 0x28ce4 |
998 | #define CB_COLOR2_VIEW 0x28ce4 |
998 | #define CB_COLOR3_VIEW 0x28d20 |
999 | #define CB_COLOR3_VIEW 0x28d20 |
999 | #define CB_COLOR4_VIEW 0x28d5c |
1000 | #define CB_COLOR4_VIEW 0x28d5c |
1000 | #define CB_COLOR5_VIEW 0x28d98 |
1001 | #define CB_COLOR5_VIEW 0x28d98 |
1001 | #define CB_COLOR6_VIEW 0x28dd4 |
1002 | #define CB_COLOR6_VIEW 0x28dd4 |
1002 | #define CB_COLOR7_VIEW 0x28e10 |
1003 | #define CB_COLOR7_VIEW 0x28e10 |
1003 | #define CB_COLOR8_VIEW 0x28e4c |
1004 | #define CB_COLOR8_VIEW 0x28e4c |
1004 | #define CB_COLOR9_VIEW 0x28e68 |
1005 | #define CB_COLOR9_VIEW 0x28e68 |
1005 | #define CB_COLOR10_VIEW 0x28e84 |
1006 | #define CB_COLOR10_VIEW 0x28e84 |
1006 | #define CB_COLOR11_VIEW 0x28ea0 |
1007 | #define CB_COLOR11_VIEW 0x28ea0 |
1007 | 1008 | ||
1008 | #define CB_COLOR1_INFO 0x28cac |
1009 | #define CB_COLOR1_INFO 0x28cac |
1009 | #define CB_COLOR2_INFO 0x28ce8 |
1010 | #define CB_COLOR2_INFO 0x28ce8 |
1010 | #define CB_COLOR3_INFO 0x28d24 |
1011 | #define CB_COLOR3_INFO 0x28d24 |
1011 | #define CB_COLOR4_INFO 0x28d60 |
1012 | #define CB_COLOR4_INFO 0x28d60 |
1012 | #define CB_COLOR5_INFO 0x28d9c |
1013 | #define CB_COLOR5_INFO 0x28d9c |
1013 | #define CB_COLOR6_INFO 0x28dd8 |
1014 | #define CB_COLOR6_INFO 0x28dd8 |
1014 | #define CB_COLOR7_INFO 0x28e14 |
1015 | #define CB_COLOR7_INFO 0x28e14 |
1015 | #define CB_COLOR8_INFO 0x28e50 |
1016 | #define CB_COLOR8_INFO 0x28e50 |
1016 | #define CB_COLOR9_INFO 0x28e6c |
1017 | #define CB_COLOR9_INFO 0x28e6c |
1017 | #define CB_COLOR10_INFO 0x28e88 |
1018 | #define CB_COLOR10_INFO 0x28e88 |
1018 | #define CB_COLOR11_INFO 0x28ea4 |
1019 | #define CB_COLOR11_INFO 0x28ea4 |
1019 | 1020 | ||
1020 | #define CB_COLOR1_ATTRIB 0x28cb0 |
1021 | #define CB_COLOR1_ATTRIB 0x28cb0 |
1021 | #define CB_COLOR2_ATTRIB 0x28cec |
1022 | #define CB_COLOR2_ATTRIB 0x28cec |
1022 | #define CB_COLOR3_ATTRIB 0x28d28 |
1023 | #define CB_COLOR3_ATTRIB 0x28d28 |
1023 | #define CB_COLOR4_ATTRIB 0x28d64 |
1024 | #define CB_COLOR4_ATTRIB 0x28d64 |
1024 | #define CB_COLOR5_ATTRIB 0x28da0 |
1025 | #define CB_COLOR5_ATTRIB 0x28da0 |
1025 | #define CB_COLOR6_ATTRIB 0x28ddc |
1026 | #define CB_COLOR6_ATTRIB 0x28ddc |
1026 | #define CB_COLOR7_ATTRIB 0x28e18 |
1027 | #define CB_COLOR7_ATTRIB 0x28e18 |
1027 | #define CB_COLOR8_ATTRIB 0x28e54 |
1028 | #define CB_COLOR8_ATTRIB 0x28e54 |
1028 | #define CB_COLOR9_ATTRIB 0x28e70 |
1029 | #define CB_COLOR9_ATTRIB 0x28e70 |
1029 | #define CB_COLOR10_ATTRIB 0x28e8c |
1030 | #define CB_COLOR10_ATTRIB 0x28e8c |
1030 | #define CB_COLOR11_ATTRIB 0x28ea8 |
1031 | #define CB_COLOR11_ATTRIB 0x28ea8 |
1031 | 1032 | ||
1032 | #define CB_COLOR1_DIM 0x28cb4 |
1033 | #define CB_COLOR1_DIM 0x28cb4 |
1033 | #define CB_COLOR2_DIM 0x28cf0 |
1034 | #define CB_COLOR2_DIM 0x28cf0 |
1034 | #define CB_COLOR3_DIM 0x28d2c |
1035 | #define CB_COLOR3_DIM 0x28d2c |
1035 | #define CB_COLOR4_DIM 0x28d68 |
1036 | #define CB_COLOR4_DIM 0x28d68 |
1036 | #define CB_COLOR5_DIM 0x28da4 |
1037 | #define CB_COLOR5_DIM 0x28da4 |
1037 | #define CB_COLOR6_DIM 0x28de0 |
1038 | #define CB_COLOR6_DIM 0x28de0 |
1038 | #define CB_COLOR7_DIM 0x28e1c |
1039 | #define CB_COLOR7_DIM 0x28e1c |
1039 | #define CB_COLOR8_DIM 0x28e58 |
1040 | #define CB_COLOR8_DIM 0x28e58 |
1040 | #define CB_COLOR9_DIM 0x28e74 |
1041 | #define CB_COLOR9_DIM 0x28e74 |
1041 | #define CB_COLOR10_DIM 0x28e90 |
1042 | #define CB_COLOR10_DIM 0x28e90 |
1042 | #define CB_COLOR11_DIM 0x28eac |
1043 | #define CB_COLOR11_DIM 0x28eac |
1043 | 1044 | ||
1044 | #define CB_COLOR1_CMASK 0x28cb8 |
1045 | #define CB_COLOR1_CMASK 0x28cb8 |
1045 | #define CB_COLOR2_CMASK 0x28cf4 |
1046 | #define CB_COLOR2_CMASK 0x28cf4 |
1046 | #define CB_COLOR3_CMASK 0x28d30 |
1047 | #define CB_COLOR3_CMASK 0x28d30 |
1047 | #define CB_COLOR4_CMASK 0x28d6c |
1048 | #define CB_COLOR4_CMASK 0x28d6c |
1048 | #define CB_COLOR5_CMASK 0x28da8 |
1049 | #define CB_COLOR5_CMASK 0x28da8 |
1049 | #define CB_COLOR6_CMASK 0x28de4 |
1050 | #define CB_COLOR6_CMASK 0x28de4 |
1050 | #define CB_COLOR7_CMASK 0x28e20 |
1051 | #define CB_COLOR7_CMASK 0x28e20 |
1051 | 1052 | ||
1052 | #define CB_COLOR1_CMASK_SLICE 0x28cbc |
1053 | #define CB_COLOR1_CMASK_SLICE 0x28cbc |
1053 | #define CB_COLOR2_CMASK_SLICE 0x28cf8 |
1054 | #define CB_COLOR2_CMASK_SLICE 0x28cf8 |
1054 | #define CB_COLOR3_CMASK_SLICE 0x28d34 |
1055 | #define CB_COLOR3_CMASK_SLICE 0x28d34 |
1055 | #define CB_COLOR4_CMASK_SLICE 0x28d70 |
1056 | #define CB_COLOR4_CMASK_SLICE 0x28d70 |
1056 | #define CB_COLOR5_CMASK_SLICE 0x28dac |
1057 | #define CB_COLOR5_CMASK_SLICE 0x28dac |
1057 | #define CB_COLOR6_CMASK_SLICE 0x28de8 |
1058 | #define CB_COLOR6_CMASK_SLICE 0x28de8 |
1058 | #define CB_COLOR7_CMASK_SLICE 0x28e24 |
1059 | #define CB_COLOR7_CMASK_SLICE 0x28e24 |
1059 | 1060 | ||
1060 | #define CB_COLOR1_FMASK 0x28cc0 |
1061 | #define CB_COLOR1_FMASK 0x28cc0 |
1061 | #define CB_COLOR2_FMASK 0x28cfc |
1062 | #define CB_COLOR2_FMASK 0x28cfc |
1062 | #define CB_COLOR3_FMASK 0x28d38 |
1063 | #define CB_COLOR3_FMASK 0x28d38 |
1063 | #define CB_COLOR4_FMASK 0x28d74 |
1064 | #define CB_COLOR4_FMASK 0x28d74 |
1064 | #define CB_COLOR5_FMASK 0x28db0 |
1065 | #define CB_COLOR5_FMASK 0x28db0 |
1065 | #define CB_COLOR6_FMASK 0x28dec |
1066 | #define CB_COLOR6_FMASK 0x28dec |
1066 | #define CB_COLOR7_FMASK 0x28e28 |
1067 | #define CB_COLOR7_FMASK 0x28e28 |
1067 | 1068 | ||
1068 | #define CB_COLOR1_FMASK_SLICE 0x28cc4 |
1069 | #define CB_COLOR1_FMASK_SLICE 0x28cc4 |
1069 | #define CB_COLOR2_FMASK_SLICE 0x28d00 |
1070 | #define CB_COLOR2_FMASK_SLICE 0x28d00 |
1070 | #define CB_COLOR3_FMASK_SLICE 0x28d3c |
1071 | #define CB_COLOR3_FMASK_SLICE 0x28d3c |
1071 | #define CB_COLOR4_FMASK_SLICE 0x28d78 |
1072 | #define CB_COLOR4_FMASK_SLICE 0x28d78 |
1072 | #define CB_COLOR5_FMASK_SLICE 0x28db4 |
1073 | #define CB_COLOR5_FMASK_SLICE 0x28db4 |
1073 | #define CB_COLOR6_FMASK_SLICE 0x28df0 |
1074 | #define CB_COLOR6_FMASK_SLICE 0x28df0 |
1074 | #define CB_COLOR7_FMASK_SLICE 0x28e2c |
1075 | #define CB_COLOR7_FMASK_SLICE 0x28e2c |
1075 | 1076 | ||
1076 | #define CB_COLOR1_CLEAR_WORD0 0x28cc8 |
1077 | #define CB_COLOR1_CLEAR_WORD0 0x28cc8 |
1077 | #define CB_COLOR2_CLEAR_WORD0 0x28d04 |
1078 | #define CB_COLOR2_CLEAR_WORD0 0x28d04 |
1078 | #define CB_COLOR3_CLEAR_WORD0 0x28d40 |
1079 | #define CB_COLOR3_CLEAR_WORD0 0x28d40 |
1079 | #define CB_COLOR4_CLEAR_WORD0 0x28d7c |
1080 | #define CB_COLOR4_CLEAR_WORD0 0x28d7c |
1080 | #define CB_COLOR5_CLEAR_WORD0 0x28db8 |
1081 | #define CB_COLOR5_CLEAR_WORD0 0x28db8 |
1081 | #define CB_COLOR6_CLEAR_WORD0 0x28df4 |
1082 | #define CB_COLOR6_CLEAR_WORD0 0x28df4 |
1082 | #define CB_COLOR7_CLEAR_WORD0 0x28e30 |
1083 | #define CB_COLOR7_CLEAR_WORD0 0x28e30 |
1083 | 1084 | ||
1084 | #define CB_COLOR1_CLEAR_WORD1 0x28ccc |
1085 | #define CB_COLOR1_CLEAR_WORD1 0x28ccc |
1085 | #define CB_COLOR2_CLEAR_WORD1 0x28d08 |
1086 | #define CB_COLOR2_CLEAR_WORD1 0x28d08 |
1086 | #define CB_COLOR3_CLEAR_WORD1 0x28d44 |
1087 | #define CB_COLOR3_CLEAR_WORD1 0x28d44 |
1087 | #define CB_COLOR4_CLEAR_WORD1 0x28d80 |
1088 | #define CB_COLOR4_CLEAR_WORD1 0x28d80 |
1088 | #define CB_COLOR5_CLEAR_WORD1 0x28dbc |
1089 | #define CB_COLOR5_CLEAR_WORD1 0x28dbc |
1089 | #define CB_COLOR6_CLEAR_WORD1 0x28df8 |
1090 | #define CB_COLOR6_CLEAR_WORD1 0x28df8 |
1090 | #define CB_COLOR7_CLEAR_WORD1 0x28e34 |
1091 | #define CB_COLOR7_CLEAR_WORD1 0x28e34 |
1091 | 1092 | ||
1092 | #define CB_COLOR1_CLEAR_WORD2 0x28cd0 |
1093 | #define CB_COLOR1_CLEAR_WORD2 0x28cd0 |
1093 | #define CB_COLOR2_CLEAR_WORD2 0x28d0c |
1094 | #define CB_COLOR2_CLEAR_WORD2 0x28d0c |
1094 | #define CB_COLOR3_CLEAR_WORD2 0x28d48 |
1095 | #define CB_COLOR3_CLEAR_WORD2 0x28d48 |
1095 | #define CB_COLOR4_CLEAR_WORD2 0x28d84 |
1096 | #define CB_COLOR4_CLEAR_WORD2 0x28d84 |
1096 | #define CB_COLOR5_CLEAR_WORD2 0x28dc0 |
1097 | #define CB_COLOR5_CLEAR_WORD2 0x28dc0 |
1097 | #define CB_COLOR6_CLEAR_WORD2 0x28dfc |
1098 | #define CB_COLOR6_CLEAR_WORD2 0x28dfc |
1098 | #define CB_COLOR7_CLEAR_WORD2 0x28e38 |
1099 | #define CB_COLOR7_CLEAR_WORD2 0x28e38 |
1099 | 1100 | ||
1100 | #define CB_COLOR1_CLEAR_WORD3 0x28cd4 |
1101 | #define CB_COLOR1_CLEAR_WORD3 0x28cd4 |
1101 | #define CB_COLOR2_CLEAR_WORD3 0x28d10 |
1102 | #define CB_COLOR2_CLEAR_WORD3 0x28d10 |
1102 | #define CB_COLOR3_CLEAR_WORD3 0x28d4c |
1103 | #define CB_COLOR3_CLEAR_WORD3 0x28d4c |
1103 | #define CB_COLOR4_CLEAR_WORD3 0x28d88 |
1104 | #define CB_COLOR4_CLEAR_WORD3 0x28d88 |
1104 | #define CB_COLOR5_CLEAR_WORD3 0x28dc4 |
1105 | #define CB_COLOR5_CLEAR_WORD3 0x28dc4 |
1105 | #define CB_COLOR6_CLEAR_WORD3 0x28e00 |
1106 | #define CB_COLOR6_CLEAR_WORD3 0x28e00 |
1106 | #define CB_COLOR7_CLEAR_WORD3 0x28e3c |
1107 | #define CB_COLOR7_CLEAR_WORD3 0x28e3c |
1107 | 1108 | ||
1108 | #define SQ_TEX_RESOURCE_WORD0_0 0x30000 |
1109 | #define SQ_TEX_RESOURCE_WORD0_0 0x30000 |
1109 | #define SQ_TEX_RESOURCE_WORD1_0 0x30004 |
1110 | #define SQ_TEX_RESOURCE_WORD1_0 0x30004 |
1110 | # define TEX_ARRAY_MODE(x) ((x) << 28) |
1111 | # define TEX_ARRAY_MODE(x) ((x) << 28) |
1111 | #define SQ_TEX_RESOURCE_WORD2_0 0x30008 |
1112 | #define SQ_TEX_RESOURCE_WORD2_0 0x30008 |
1112 | #define SQ_TEX_RESOURCE_WORD3_0 0x3000C |
1113 | #define SQ_TEX_RESOURCE_WORD3_0 0x3000C |
1113 | #define SQ_TEX_RESOURCE_WORD4_0 0x30010 |
1114 | #define SQ_TEX_RESOURCE_WORD4_0 0x30010 |
1114 | #define SQ_TEX_RESOURCE_WORD5_0 0x30014 |
1115 | #define SQ_TEX_RESOURCE_WORD5_0 0x30014 |
1115 | #define SQ_TEX_RESOURCE_WORD6_0 0x30018 |
1116 | #define SQ_TEX_RESOURCE_WORD6_0 0x30018 |
1116 | #define SQ_TEX_RESOURCE_WORD7_0 0x3001c |
1117 | #define SQ_TEX_RESOURCE_WORD7_0 0x3001c |
1117 | 1118 | ||
1118 | /* cayman 3D regs */ |
1119 | /* cayman 3D regs */ |
1119 | #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B0 |
1120 | #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B0 |
1120 | #define CAYMAN_DB_EQAA 0x28804 |
1121 | #define CAYMAN_DB_EQAA 0x28804 |
1121 | #define CAYMAN_DB_DEPTH_INFO 0x2803C |
1122 | #define CAYMAN_DB_DEPTH_INFO 0x2803C |
1122 | #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 |
1123 | #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 |
1123 | #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 |
1124 | #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 |
1124 | #define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 |
1125 | #define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 |
- | 1126 | #define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 |
|
1125 | /* cayman packet3 addition */ |
1127 | /* cayman packet3 addition */ |
1126 | #define CAYMAN_PACKET3_DEALLOC_STATE 0x14 |
1128 | #define CAYMAN_PACKET3_DEALLOC_STATE 0x14 |
1127 | 1129 | ||
1128 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>31) |
1130 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>31) |
1129 | 1131 | ||
1130 | #define><31) |
1132 | #define><31) |
1131 | 1133 | ||
1132 | #define>30) |
1134 | #define>30) |
1133 | #define><30) |
1135 | #define><30) |
1134 | #define>29) |
1136 | #define>29) |
1135 | #define><29) |
1137 | #define><29) |
1136 | #define>28) |
1138 | #define>28) |
1137 | #define><28) |
1139 | #define><28) |
1138 | #define>26) |
1140 | #define>26) |
1139 | #define><26) |
1141 | #define><26) |
1140 | #define>19) |
1142 | #define>19) |
1141 | #define><19) |
1143 | #define><19) |
1142 | #define>15) |
1144 | #define>15) |
1143 | #define><15) |
1145 | #define><15) |
1144 | #define>10) |
1146 | #define>10) |
1145 | #define><10) |
1147 | #define><10) |
1146 | #define>9) |
1148 | #define>9) |
1147 | #define><9) |
1149 | #define><9) |
1148 | #define>8) |
1150 | #define>8) |
1149 | #define><8) |
1151 | #define><8) |
1150 | #define>0) |
1152 | #define>0) |
1151 | #define><0) |
1153 | #define><0) |
1152 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>18) |
1154 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>18) |
1153 | #define><18) |
1155 | #define><18) |
1154 | #define>15) |
1156 | #define>15) |
1155 | #define><15) |
1157 | #define><15) |
1156 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
1158 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |