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| Rev 1963 | Rev 2004 | ||
|---|---|---|---|
| Line 464... | Line 464... | ||
| 464 | # define WPTR_OFFSET_MASK 0x3fffc |
464 | # define WPTR_OFFSET_MASK 0x3fffc |
| 465 | #define IH_RB_WPTR_ADDR_HI 0x3e10 |
465 | #define IH_RB_WPTR_ADDR_HI 0x3e10 |
| 466 | #define IH_RB_WPTR_ADDR_LO 0x3e14 |
466 | #define IH_RB_WPTR_ADDR_LO 0x3e14 |
| 467 | #define IH_CNTL 0x3e18 |
467 | #define IH_CNTL 0x3e18 |
| 468 | # define ENABLE_INTR (1 << 0) |
468 | # define ENABLE_INTR (1 << 0) |
| 469 | # define IH_MC_SWAP(x) ((x) << 2) |
469 | # define IH_MC_SWAP(x) ((x) << 1) |
| 470 | # define IH_MC_SWAP_NONE 0 |
470 | # define IH_MC_SWAP_NONE 0 |
| 471 | # define IH_MC_SWAP_16BIT 1 |
471 | # define IH_MC_SWAP_16BIT 1 |
| 472 | # define IH_MC_SWAP_32BIT 2 |
472 | # define IH_MC_SWAP_32BIT 2 |
| 473 | # define IH_MC_SWAP_64BIT 3 |
473 | # define IH_MC_SWAP_64BIT 3 |
| 474 | # define RPTR_REARM (1 << 4) |
474 | # define RPTR_REARM (1 << 4) |
| Line 545... | Line 545... | ||
| 545 | #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c |
545 | #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c |
| 546 | # define LB_D5_VLINE_INTERRUPT (1 << 2) |
546 | # define LB_D5_VLINE_INTERRUPT (1 << 2) |
| 547 | # define LB_D5_VBLANK_INTERRUPT (1 << 3) |
547 | # define LB_D5_VBLANK_INTERRUPT (1 << 3) |
| 548 | # define DC_HPD5_INTERRUPT (1 << 17) |
548 | # define DC_HPD5_INTERRUPT (1 << 17) |
| 549 | # define DC_HPD5_RX_INTERRUPT (1 << 18) |
549 | # define DC_HPD5_RX_INTERRUPT (1 << 18) |
| 550 | #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6050 |
550 | #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 |
| 551 | # define LB_D6_VLINE_INTERRUPT (1 << 2) |
551 | # define LB_D6_VLINE_INTERRUPT (1 << 2) |
| 552 | # define LB_D6_VBLANK_INTERRUPT (1 << 3) |
552 | # define LB_D6_VBLANK_INTERRUPT (1 << 3) |
| 553 | # define DC_HPD6_INTERRUPT (1 << 17) |
553 | # define DC_HPD6_INTERRUPT (1 << 17) |
| 554 | # define DC_HPD6_RX_INTERRUPT (1 << 18) |
554 | # define DC_HPD6_RX_INTERRUPT (1 << 18) |