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Rev 6104 Rev 6661
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#define EVERGREEN_DC_GPIO_HPD_EN                        0x64b8
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#define EVERGREEN_DC_GPIO_HPD_EN                        0x64b8
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#define EVERGREEN_DC_GPIO_HPD_Y                         0x64bc
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#define EVERGREEN_DC_GPIO_HPD_Y                         0x64bc
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/* HDMI blocks at 0x7030, 0x7c30, 0x10830, 0x11430, 0x12030, 0x12c30 */
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/* HDMI blocks at 0x7030, 0x7c30, 0x10830, 0x11430, 0x12030, 0x12c30 */
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#define EVERGREEN_HDMI_BASE				0x7030
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/*DIG block*/
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#define NI_DIG0_REGISTER_OFFSET                 (0x7000  - 0x7000)
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#define NI_DIG1_REGISTER_OFFSET                 (0x7C00  - 0x7000)
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#define NI_DIG2_REGISTER_OFFSET                 (0x10800 - 0x7000)
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#define NI_DIG3_REGISTER_OFFSET                 (0x11400 - 0x7000)
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#define NI_DIG4_REGISTER_OFFSET                 (0x12000 - 0x7000)
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#define NI_DIG5_REGISTER_OFFSET                 (0x12C00 - 0x7000)
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#define NI_DIG_FE_CNTL                               0x7000
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#       define NI_DIG_FE_CNTL_SOURCE_SELECT(x)        ((x) & 0x3)
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#       define NI_DIG_FE_CNTL_SYMCLK_FE_ON            (1<<24)
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#define NI_DIG_BE_CNTL                    0x7140
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#       define NI_DIG_BE_CNTL_FE_SOURCE_SELECT(x)     (((x) >> 8 ) & 0x3F)
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#       define NI_DIG_FE_CNTL_MODE(x)                 (((x) >> 16) & 0x7 )
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#define NI_DIG_BE_EN_CNTL                              0x7144
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#       define NI_DIG_BE_EN_CNTL_ENABLE               (1 << 0)
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#       define NI_DIG_BE_EN_CNTL_SYMBCLK_ON           (1 << 8)
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#define EVERGREEN_HDMI_BASE				0x7030
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#       define NI_DIG_BE_DPSST 0
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/* Display Port block */
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#define EVERGREEN_DP0_REGISTER_OFFSET                 (0x730C  - 0x730C)
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#define EVERGREEN_DP1_REGISTER_OFFSET                 (0x7F0C  - 0x730C)
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#define EVERGREEN_DP2_REGISTER_OFFSET                 (0x10B0C - 0x730C)
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#define EVERGREEN_DP3_REGISTER_OFFSET                 (0x1170C - 0x730C)
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#define EVERGREEN_DP4_REGISTER_OFFSET                 (0x1230C - 0x730C)
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#define EVERGREEN_DP5_REGISTER_OFFSET                 (0x12F0C - 0x730C)
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#define EVERGREEN_DP_VID_STREAM_CNTL                    0x730C
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#       define EVERGREEN_DP_VID_STREAM_CNTL_ENABLE     (1 << 0)
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#       define EVERGREEN_DP_VID_STREAM_STATUS          (1 <<16)
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#define EVERGREEN_DP_STEER_FIFO                         0x7310
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/* Display Port block */
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#       define EVERGREEN_DP_STEER_FIFO_RESET           (1 << 0)
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#define EVERGREEN_DP_SEC_CNTL                           0x7280
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#define EVERGREEN_DP_SEC_CNTL                           0x7280
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#       define EVERGREEN_DP_SEC_STREAM_ENABLE           (1 << 0)
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#       define EVERGREEN_DP_SEC_STREAM_ENABLE           (1 << 0)
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#       define EVERGREEN_DP_SEC_ASP_ENABLE              (1 << 4)
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#       define EVERGREEN_DP_SEC_ASP_ENABLE              (1 << 4)
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#       define EVERGREEN_DP_SEC_TIMESTAMP_MODE(x)       (((x) & 0x3) << 0)
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#       define EVERGREEN_DP_SEC_TIMESTAMP_MODE(x)       (((x) & 0x3) << 0)
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#define EVERGREEN_DP_SEC_AUD_N                          0x7294
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#define EVERGREEN_DP_SEC_AUD_N                          0x7294
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#       define EVERGREEN_DP_SEC_N_BASE_MULTIPLE(x)      (((x) & 0xf) << 24)
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#       define EVERGREEN_DP_SEC_N_BASE_MULTIPLE(x)      (((x) & 0xf) << 24)
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#       define EVERGREEN_DP_SEC_SS_EN                   (1 << 28)
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#       define EVERGREEN_DP_SEC_SS_EN                   (1 << 28)
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/*DCIO_UNIPHY block*/
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#define NI_DCIO_UNIPHY0_UNIPHY_TX_CONTROL1            (0x6600  -0x6600)
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#define NI_DCIO_UNIPHY1_UNIPHY_TX_CONTROL1            (0x6640  -0x6600)
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#define NI_DCIO_UNIPHY2_UNIPHY_TX_CONTROL1            (0x6680 - 0x6600)
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#define NI_DCIO_UNIPHY3_UNIPHY_TX_CONTROL1            (0x66C0 - 0x6600)
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#define NI_DCIO_UNIPHY4_UNIPHY_TX_CONTROL1            (0x6700 - 0x6600)
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#define NI_DCIO_UNIPHY5_UNIPHY_TX_CONTROL1            (0x6740 - 0x6600)
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#define NI_DCIO_UNIPHY0_PLL_CONTROL1                   0x6618
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#       define NI_DCIO_UNIPHY0_PLL_CONTROL1_ENABLE     (1 << 0)
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