Rev 6104 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 6104 | Rev 6321 | ||
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| Line 287... | Line 287... | ||
| 287 | 287 | ||
| 288 | /* Express [24MHz / target pixel clock] as an exact rational |
288 | /* Express [24MHz / target pixel clock] as an exact rational |
| 289 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
289 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
| 290 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
290 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
| - | 291 | */ |
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| - | 292 | if (ASIC_IS_DCE41(rdev)) { |
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| - | 293 | unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) & |
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| - | 294 | DENTIST_DPREFCLK_WDIVIDER_MASK) >> |
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| - | 295 | DENTIST_DPREFCLK_WDIVIDER_SHIFT; |
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| - | 296 | div = radeon_audio_decode_dfs_div(div); |
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| - | 297 | ||
| - | 298 | if (div) |
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| - | 299 | clock = 100 * clock / div; |
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| - | 300 | } |
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| 291 | */ |
301 | |
| 292 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); |
302 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); |
| 293 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); |
303 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); |
| Line 294... | Line 304... | ||
| 294 | } |
304 | } |