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| Rev 5271 | Rev 6104 | ||
|---|---|---|---|
| Line 27... | Line 27... | ||
| 27 | #include |
27 | #include |
| 28 | #include |
28 | #include |
| 29 | #include |
29 | #include |
| 30 | #include "radeon.h" |
30 | #include "radeon.h" |
| 31 | #include "radeon_asic.h" |
31 | #include "radeon_asic.h" |
| - | 32 | #include "radeon_audio.h" |
|
| 32 | #include "evergreend.h" |
33 | #include "evergreend.h" |
| 33 | #include "atom.h" |
34 | #include "atom.h" |
| Line 34... | Line -... | ||
| 34 | - | ||
| 35 | extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder); |
- | |
| 36 | extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder); |
- | |
| 37 | extern void dce6_afmt_select_pin(struct drm_encoder *encoder); |
- | |
| 38 | extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, |
- | |
| 39 | struct drm_display_mode *mode); |
- | |
| 40 | 35 | ||
| 41 | /* enable the audio stream */ |
36 | /* enable the audio stream */ |
| 42 | static void dce4_audio_enable(struct radeon_device *rdev, |
37 | void dce4_audio_enable(struct radeon_device *rdev, |
| 43 | struct r600_audio_pin *pin, |
38 | struct r600_audio_pin *pin, |
| 44 | u8 enable_mask) |
39 | u8 enable_mask) |
| 45 | { |
40 | { |
| Line 67... | Line 62... | ||
| 67 | } |
62 | } |
| Line 68... | Line 63... | ||
| 68 | 63 | ||
| 69 | WREG32(AZ_HOT_PLUG_CONTROL, tmp); |
64 | WREG32(AZ_HOT_PLUG_CONTROL, tmp); |
| Line 70... | Line -... | ||
| 70 | } |
- | |
| 71 | 65 | } |
|
| 72 | /* |
- | |
| 73 | * update the N and CTS parameters for a given pixel clock rate |
66 | |
| 74 | */ |
67 | void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset, |
| 75 | static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
68 | const struct radeon_hdmi_acr *acr) |
| 76 | { |
69 | { |
| 77 | struct drm_device *dev = encoder->dev; |
- | |
| 78 | struct radeon_device *rdev = dev->dev_private; |
- | |
| 79 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
- | |
| 80 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
70 | struct drm_device *dev = encoder->dev; |
| Line -... | Line 71... | ||
| - | 71 | struct radeon_device *rdev = dev->dev_private; |
|
| 81 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
72 | int bpc = 8; |
| 82 | uint32_t offset = dig->afmt->offset; |
73 | |
| - | 74 | if (encoder->crtc) { |
|
| Line -... | Line 75... | ||
| - | 75 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
|
| - | 76 | bpc = radeon_crtc->bpc; |
|
| - | 77 | } |
|
| - | 78 | ||
| - | 79 | if (bpc > 8) |
|
| - | 80 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
|
| - | 81 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
|
| - | 82 | else |
|
| - | 83 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
|
| - | 84 | HDMI_ACR_SOURCE | /* select SW CTS value */ |
|
| - | 85 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
|
| 83 | 86 | ||
| 84 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); |
87 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); |
| Line 85... | Line 88... | ||
| 85 | WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); |
88 | WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); |
| 86 | 89 | ||
| 87 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); |
90 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); |
| Line 88... | Line 91... | ||
| 88 | WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); |
91 | WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); |
| 89 | 92 | ||
| 90 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); |
93 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); |
| 91 | WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); |
94 | WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); |
| 92 | } |
- | |
| 93 | - | ||
| 94 | static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
95 | } |
| Line 95... | Line -... | ||
| 95 | struct drm_display_mode *mode) |
- | |
| 96 | { |
- | |
| 97 | struct radeon_device *rdev = encoder->dev->dev_private; |
- | |
| 98 | struct drm_connector *connector; |
- | |
| 99 | struct radeon_connector *radeon_connector = NULL; |
- | |
| 100 | u32 tmp = 0; |
- | |
| 101 | - | ||
| 102 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
- | |
| 103 | if (connector->encoder == encoder) { |
- | |
| 104 | radeon_connector = to_radeon_connector(connector); |
- | |
| 105 | break; |
- | |
| 106 | } |
- | |
| 107 | } |
96 | |
| 108 | 97 | void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
|
| 109 | if (!radeon_connector) { |
98 | struct drm_connector *connector, struct drm_display_mode *mode) |
| 110 | DRM_ERROR("Couldn't find encoder's connector\n"); |
99 | { |
| 111 | return; |
100 | struct radeon_device *rdev = encoder->dev->dev_private; |
| Line 122... | Line 111... | ||
| 122 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
111 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
| 123 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
112 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
| 124 | else |
113 | else |
| 125 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
114 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
| 126 | } |
115 | } |
| 127 | WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); |
116 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); |
| 128 | } |
117 | } |
| Line 129... | Line 118... | ||
| 129 | 118 | ||
| - | 119 | void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
|
| 130 | static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder) |
120 | u8 *sadb, int sad_count) |
| 131 | { |
121 | { |
| 132 | struct radeon_device *rdev = encoder->dev->dev_private; |
- | |
| 133 | struct drm_connector *connector; |
- | |
| 134 | struct radeon_connector *radeon_connector = NULL; |
122 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 135 | u32 tmp; |
- | |
| 136 | u8 *sadb = NULL; |
- | |
| 137 | int sad_count; |
- | |
| 138 | - | ||
| 139 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
- | |
| 140 | if (connector->encoder == encoder) { |
- | |
| 141 | radeon_connector = to_radeon_connector(connector); |
- | |
| 142 | break; |
- | |
| 143 | } |
- | |
| 144 | } |
- | |
| 145 | - | ||
| 146 | if (!radeon_connector) { |
- | |
| 147 | DRM_ERROR("Couldn't find encoder's connector\n"); |
- | |
| 148 | return; |
- | |
| 149 | } |
- | |
| 150 | - | ||
| 151 | sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), &sadb); |
- | |
| 152 | if (sad_count < 0) { |
- | |
| 153 | DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
- | |
| 154 | sad_count = 0; |
- | |
| Line 155... | Line 123... | ||
| 155 | } |
123 | u32 tmp; |
| 156 | 124 | ||
| 157 | /* program the speaker allocation */ |
125 | /* program the speaker allocation */ |
| 158 | tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
126 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
| 159 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
127 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
| 160 | /* set HDMI mode */ |
128 | /* set HDMI mode */ |
| 161 | tmp |= HDMI_CONNECTION; |
129 | tmp |= HDMI_CONNECTION; |
| 162 | if (sad_count) |
130 | if (sad_count) |
| 163 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
131 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
| 164 | else |
132 | else |
| 165 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
- | |
| 166 | WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
- | |
| 167 | 133 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
|
| Line 168... | Line 134... | ||
| 168 | kfree(sadb); |
134 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
| - | 135 | } |
|
| 169 | } |
136 | |
| 170 | 137 | void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, |
|
| 171 | static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder) |
- | |
| 172 | { |
- | |
| 173 | struct radeon_device *rdev = encoder->dev->dev_private; |
- | |
| 174 | struct drm_connector *connector; |
138 | u8 *sadb, int sad_count) |
| Line -... | Line 139... | ||
| - | 139 | { |
|
| - | 140 | struct radeon_device *rdev = encoder->dev->dev_private; |
|
| - | 141 | u32 tmp; |
|
| - | 142 | ||
| - | 143 | /* program the speaker allocation */ |
|
| - | 144 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
|
| - | 145 | tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); |
|
| - | 146 | /* set DP mode */ |
|
| - | 147 | tmp |= DP_CONNECTION; |
|
| - | 148 | if (sad_count) |
|
| - | 149 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
|
| - | 150 | else |
|
| - | 151 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
|
| - | 152 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
|
| - | 153 | } |
|
| - | 154 | ||
| - | 155 | void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder, |
|
| 175 | struct radeon_connector *radeon_connector = NULL; |
156 | struct cea_sad *sads, int sad_count) |
| 176 | struct cea_sad *sads; |
157 | { |
| 177 | int i, sad_count; |
158 | int i; |
| 178 | 159 | struct radeon_device *rdev = encoder->dev->dev_private; |
|
| 179 | static const u16 eld_reg_to_type[][2] = { |
160 | static const u16 eld_reg_to_type[][2] = { |
| Line 189... | Line 170... | ||
| 189 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
170 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
| 190 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
171 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
| 191 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
172 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
| 192 | }; |
173 | }; |
| Line 193... | Line -... | ||
| 193 | - | ||
| 194 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
- | |
| 195 | if (connector->encoder == encoder) { |
- | |
| 196 | radeon_connector = to_radeon_connector(connector); |
- | |
| 197 | break; |
- | |
| 198 | } |
- | |
| 199 | } |
- | |
| 200 | - | ||
| 201 | if (!radeon_connector) { |
- | |
| 202 | DRM_ERROR("Couldn't find encoder's connector\n"); |
- | |
| 203 | return; |
- | |
| 204 | } |
- | |
| 205 | - | ||
| 206 | sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads); |
- | |
| 207 | if (sad_count <= 0) { |
- | |
| 208 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
- | |
| 209 | return; |
- | |
| 210 | } |
- | |
| 211 | BUG_ON(!sads); |
- | |
| 212 | 174 | ||
| 213 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
175 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
| 214 | u32 value = 0; |
176 | u32 value = 0; |
| 215 | u8 stereo_freqs = 0; |
177 | u8 stereo_freqs = 0; |
| 216 | int max_channels = -1; |
178 | int max_channels = -1; |
| Line 234... | Line 196... | ||
| 234 | } |
196 | } |
| 235 | } |
197 | } |
| Line 236... | Line 198... | ||
| 236 | 198 | ||
| Line 237... | Line 199... | ||
| 237 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
199 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
| 238 | 200 | ||
| 239 | WREG32(eld_reg_to_type[i][0], value); |
- | |
| 240 | } |
- | |
| 241 | 201 | WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); |
|
| Line 242... | Line 202... | ||
| 242 | kfree(sads); |
202 | } |
| 243 | } |
203 | } |
| 244 | 204 | ||
| 245 | /* |
205 | /* |
| 246 | * build a HDMI Video Info Frame |
206 | * build a AVI Info Frame |
| 247 | */ |
207 | */ |
| 248 | static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, |
- | |
| 249 | void *buffer, size_t size) |
- | |
| 250 | { |
- | |
| 251 | struct drm_device *dev = encoder->dev; |
- | |
| 252 | struct radeon_device *rdev = dev->dev_private; |
- | |
| 253 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
208 | void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset, |
| 254 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
- | |
| Line 255... | Line 209... | ||
| 255 | uint32_t offset = dig->afmt->offset; |
209 | unsigned char *buffer, size_t size) |
| 256 | uint8_t *frame = buffer + 3; |
210 | { |
| 257 | uint8_t *header = buffer; |
211 | uint8_t *frame = buffer + 3; |
| 258 | 212 | ||
| 259 | WREG32(AFMT_AVI_INFO0 + offset, |
213 | WREG32(AFMT_AVI_INFO0 + offset, |
| 260 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
214 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
| 261 | WREG32(AFMT_AVI_INFO1 + offset, |
215 | WREG32(AFMT_AVI_INFO1 + offset, |
| 262 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
216 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
| - | 217 | WREG32(AFMT_AVI_INFO2 + offset, |
|
| - | 218 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
|
| - | 219 | WREG32(AFMT_AVI_INFO3 + offset, |
|
| - | 220 | frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24)); |
|
| 263 | WREG32(AFMT_AVI_INFO2 + offset, |
221 | |
| Line 264... | Line 222... | ||
| 264 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
222 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, |
| - | 223 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ |
|
| 265 | WREG32(AFMT_AVI_INFO3 + offset, |
224 | ~HDMI_AVI_INFO_LINE_MASK); |
| 266 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); |
- | |
| 267 | } |
- | |
| 268 | - | ||
| 269 | static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
- | |
| 270 | { |
- | |
| 271 | struct drm_device *dev = encoder->dev; |
- | |
| 272 | struct radeon_device *rdev = dev->dev_private; |
225 | } |
| 273 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
226 | |
| 274 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
- | |
| 275 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
227 | void dce4_hdmi_audio_set_dto(struct radeon_device *rdev, |
| 276 | u32 base_rate = 24000; |
228 | struct radeon_crtc *crtc, unsigned int clock) |
| 277 | u32 max_ratio = clock / base_rate; |
- | |
| 278 | u32 dto_phase; |
- | |
| 279 | u32 dto_modulo = clock; |
- | |
| Line 280... | Line -... | ||
| 280 | u32 wallclock_ratio; |
- | |
| 281 | u32 dto_cntl; |
- | |
| 282 | - | ||
| 283 | if (!dig || !dig->afmt) |
229 | { |
| 284 | return; |
230 | unsigned int max_ratio = clock / 24000; |
| 285 | 231 | u32 dto_phase; |
|
| 286 | if (ASIC_IS_DCE6(rdev)) { |
232 | u32 wallclock_ratio; |
| 287 | dto_phase = 24 * 1000; |
233 | u32 value; |
| Line 297... | Line 243... | ||
| 297 | wallclock_ratio = 1; |
243 | wallclock_ratio = 1; |
| 298 | } else { |
244 | } else { |
| 299 | dto_phase = 24 * 1000; |
245 | dto_phase = 24 * 1000; |
| 300 | wallclock_ratio = 0; |
246 | wallclock_ratio = 0; |
| 301 | } |
247 | } |
| 302 | dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
- | |
| 303 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
- | |
| 304 | WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); |
- | |
| 305 | } |
- | |
| Line -... | Line 248... | ||
| - | 248 | ||
| - | 249 | value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
|
| - | 250 | value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
|
| - | 251 | value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO; |
|
| - | 252 | WREG32(DCCG_AUDIO_DTO0_CNTL, value); |
|
| 306 | 253 | ||
| - | 254 | /* Two dtos; generally use dto0 for HDMI */ |
|
| - | 255 | value = 0; |
|
| - | 256 | ||
| - | 257 | if (crtc) |
|
| - | 258 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
|
| - | 259 | ||
| - | 260 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
|
| 307 | /* XXX two dtos; generally use dto0 for hdmi */ |
261 | |
| 308 | /* Express [24MHz / target pixel clock] as an exact rational |
262 | /* Express [24MHz / target pixel clock] as an exact rational |
| 309 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
263 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
| 310 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
264 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
| 311 | */ |
- | |
| 312 | WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); |
265 | */ |
| 313 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
266 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
| 314 | WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); |
267 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock); |
| Line 315... | Line -... | ||
| 315 | } |
- | |
| 316 | - | ||
| 317 | 268 | } |
|
| 318 | /* |
- | |
| 319 | * update the info frames with the data from the current display mode |
269 | |
| 320 | */ |
270 | void dce4_dp_audio_set_dto(struct radeon_device *rdev, |
| 321 | void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
- | |
| 322 | { |
- | |
| 323 | struct drm_device *dev = encoder->dev; |
- | |
| 324 | struct radeon_device *rdev = dev->dev_private; |
- | |
| 325 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
- | |
| 326 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
- | |
| 327 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
- | |
| 328 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
- | |
| 329 | struct hdmi_avi_infoframe frame; |
- | |
| 330 | uint32_t offset; |
271 | struct radeon_crtc *crtc, unsigned int clock) |
| 331 | ssize_t err; |
- | |
| Line -... | Line 272... | ||
| - | 272 | { |
|
| 332 | uint32_t val; |
273 | u32 value; |
| 333 | int bpc = 8; |
274 | |
| Line 334... | Line 275... | ||
| 334 | 275 | value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
|
| 335 | if (!dig || !dig->afmt) |
- | |
| 336 | return; |
276 | value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO; |
| 337 | 277 | WREG32(DCCG_AUDIO_DTO1_CNTL, value); |
|
| Line 338... | Line -... | ||
| 338 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
- | |
| 339 | if (!dig->afmt->enabled) |
278 | |
| 340 | return; |
279 | /* Two dtos; generally use dto1 for DP */ |
| 341 | offset = dig->afmt->offset; |
- | |
| 342 | - | ||
| Line 343... | Line 280... | ||
| 343 | /* hdmi deep color mode general control packets setup, if bpc > 8 */ |
280 | value = 0; |
| - | 281 | value |= DCCG_AUDIO_DTO_SEL; |
|
| 344 | if (encoder->crtc) { |
282 | |
| 345 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
283 | if (crtc) |
| 346 | bpc = radeon_crtc->bpc; |
284 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
| 347 | } |
285 | |
| 348 | 286 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
|
| 349 | /* disable audio prior to setting up hw */ |
287 | |
| 350 | if (ASIC_IS_DCE6(rdev)) { |
288 | /* Express [24MHz / target pixel clock] as an exact rational |
| Line -... | Line 289... | ||
| - | 289 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
|
| - | 290 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
|
| 351 | dig->afmt->pin = dce6_audio_get_pin(rdev); |
291 | */ |
| - | 292 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); |
|
| Line 352... | Line 293... | ||
| 352 | dce6_audio_enable(rdev, dig->afmt->pin, 0); |
293 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); |
| 353 | } else { |
294 | } |
| - | 295 | ||
| - | 296 | void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset) |
|
| - | 297 | { |
|
| Line -... | Line 298... | ||
| - | 298 | struct drm_device *dev = encoder->dev; |
|
| - | 299 | struct radeon_device *rdev = dev->dev_private; |
|
| - | 300 | ||
| 354 | dig->afmt->pin = r600_audio_get_pin(rdev); |
301 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
| - | 302 | HDMI_NULL_SEND | /* send null packets when required */ |
|
| - | 303 | HDMI_GC_SEND | /* send general control packets */ |
|
| Line 355... | Line 304... | ||
| 355 | dce4_audio_enable(rdev, dig->afmt->pin, 0); |
304 | HDMI_GC_CONT); /* send general control packets every frame */ |
| 356 | } |
305 | } |
| 357 | 306 | ||
| Line 388... | Line 337... | ||
| 388 | connector->name); |
337 | connector->name); |
| 389 | break; |
338 | break; |
| 390 | } |
339 | } |
| Line 391... | Line 340... | ||
| 391 | 340 | ||
| - | 341 | WREG32(HDMI_CONTROL + offset, val); |
|
| Line 392... | Line -... | ||
| 392 | WREG32(HDMI_CONTROL + offset, val); |
- | |
| 393 | - | ||
| 394 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
- | |
| 395 | HDMI_NULL_SEND | /* send null packets when required */ |
342 | } |
| 396 | HDMI_GC_SEND | /* send general control packets */ |
343 | |
| 397 | HDMI_GC_CONT); /* send general control packets every frame */ |
344 | void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset) |
| 398 | - | ||
| 399 | WREG32(HDMI_INFOFRAME_CONTROL0 + offset, |
345 | { |
| Line 400... | Line 346... | ||
| 400 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
346 | struct drm_device *dev = encoder->dev; |
| 401 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
347 | struct radeon_device *rdev = dev->dev_private; |
| Line 402... | Line -... | ||
| 402 | - | ||
| 403 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
- | |
| 404 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
- | |
| 405 | - | ||
| 406 | WREG32(HDMI_INFOFRAME_CONTROL1 + offset, |
- | |
| 407 | HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
- | |
| 408 | - | ||
| 409 | WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ |
- | |
| 410 | - | ||
| 411 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
- | |
| 412 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ |
- | |
| 413 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
- | |
| 414 | - | ||
| 415 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, |
- | |
| 416 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
- | |
| 417 | - | ||
| 418 | /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ |
- | |
| 419 | - | ||
| 420 | if (bpc > 8) |
- | |
| 421 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
- | |
| 422 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
- | |
| 423 | else |
- | |
| 424 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
- | |
| 425 | HDMI_ACR_SOURCE | /* select SW CTS value */ |
- | |
| 426 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
348 | |
| 427 | 349 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
|
| Line 428... | Line 350... | ||
| 428 | evergreen_hdmi_update_ACR(encoder, mode->clock); |
350 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
| 429 | 351 | ||
| Line 439... | Line 361... | ||
| 439 | AFMT_60958_CS_CHANNEL_NUMBER_4(5) | |
361 | AFMT_60958_CS_CHANNEL_NUMBER_4(5) | |
| 440 | AFMT_60958_CS_CHANNEL_NUMBER_5(6) | |
362 | AFMT_60958_CS_CHANNEL_NUMBER_5(6) | |
| 441 | AFMT_60958_CS_CHANNEL_NUMBER_6(7) | |
363 | AFMT_60958_CS_CHANNEL_NUMBER_6(7) | |
| 442 | AFMT_60958_CS_CHANNEL_NUMBER_7(8)); |
364 | AFMT_60958_CS_CHANNEL_NUMBER_7(8)); |
| Line 443... | Line -... | ||
| 443 | - | ||
| 444 | if (ASIC_IS_DCE6(rdev)) { |
- | |
| 445 | dce6_afmt_write_speaker_allocation(encoder); |
- | |
| 446 | } else { |
- | |
| 447 | dce4_afmt_write_speaker_allocation(encoder); |
- | |
| 448 | } |
- | |
| 449 | 365 | ||
| 450 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, |
366 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, |
| Line 451... | Line 367... | ||
| 451 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); |
367 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); |
| - | 368 | ||
| - | 369 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
|
| Line 452... | Line -... | ||
| 452 | - | ||
| 453 | /* fglrx sets 0x40 in 0x5f80 here */ |
- | |
| 454 | - | ||
| 455 | if (ASIC_IS_DCE6(rdev)) { |
370 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ |
| 456 | dce6_afmt_select_pin(encoder); |
- | |
| 457 | dce6_afmt_write_sad_regs(encoder); |
371 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
| 458 | dce6_afmt_write_latency_fields(encoder, mode); |
372 | |
| 459 | } else { |
373 | /* allow 60958 channel status and send audio packets fields to be updated */ |
| Line -... | Line 374... | ||
| - | 374 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, |
|
| - | 375 | AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE); |
|
| - | 376 | } |
|
| 460 | evergreen_hdmi_write_sad_regs(encoder); |
377 | |
| - | 378 | ||
| - | 379 | void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute) |
|
| 461 | dce4_afmt_write_latency_fields(encoder, mode); |
380 | { |
| 462 | } |
381 | struct drm_device *dev = encoder->dev; |
| 463 | 382 | struct radeon_device *rdev = dev->dev_private; |
|
| - | 383 | ||
| 464 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
384 | if (mute) |
| Line 465... | Line 385... | ||
| 465 | if (err < 0) { |
385 | WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE); |
| - | 386 | else |
|
| 466 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); |
387 | WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE); |
| - | 388 | } |
|
| 467 | return; |
389 | |
| - | 390 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) |
|
| - | 391 | { |
|
| - | 392 | struct drm_device *dev = encoder->dev; |
|
| 468 | } |
393 | struct radeon_device *rdev = dev->dev_private; |
| 469 | - | ||
| Line -... | Line 394... | ||
| - | 394 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
|
| 470 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
395 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| Line -... | Line 396... | ||
| - | 396 | ||
| 471 | if (err < 0) { |
397 | if (!dig || !dig->afmt) |
| - | 398 | return; |
|
| - | 399 | ||
| - | 400 | if (enable) { |
|
| - | 401 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
|
| - | 402 | ||
| - | 403 | if (connector && drm_detect_monitor_audio(radeon_connector_edid(connector))) { |
|
| - | 404 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, |
|
| - | 405 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
|
| 472 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); |
406 | HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */ |
| 473 | return; |
407 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
| - | 408 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
|
| - | 409 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
|
| - | 410 | AFMT_AUDIO_SAMPLE_SEND); |
|
| - | 411 | } else { |
|
| - | 412 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, |
|
| - | 413 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
|
| - | 414 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ |
|
| - | 415 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
|
| Line 474... | Line -... | ||
| 474 | } |
- | |
| 475 | - | ||
| 476 | evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
416 | ~AFMT_AUDIO_SAMPLE_SEND); |
| 477 | - | ||
| 478 | WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset, |
- | |
| 479 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
- | |
| Line 480... | Line -... | ||
| 480 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ |
- | |
| 481 | - | ||
| 482 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, |
- | |
| 483 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ |
- | |
| 484 | ~HDMI_AVI_INFO_LINE_MASK); |
417 | } |
| 485 | - | ||
| 486 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, |
- | |
| 487 | AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */ |
- | |
| 488 | - | ||
| 489 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
- | |
| 490 | WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
418 | } else { |
| 491 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); |
419 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
| Line 492... | Line 420... | ||
| 492 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); |
420 | ~AFMT_AUDIO_SAMPLE_SEND); |
| 493 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); |
421 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0); |
| 494 | 422 | } |
|
| 495 | /* enable audio after to setting up hw */ |
423 | |
| 496 | if (ASIC_IS_DCE6(rdev)) |
424 | dig->afmt->enabled = enable; |
| 497 | dce6_audio_enable(rdev, dig->afmt->pin, 1); |
425 | |
| - | 426 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
|
| Line 498... | Line 427... | ||
| 498 | else |
427 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); |
| 499 | dce4_audio_enable(rdev, dig->afmt->pin, 0xf); |
428 | } |
| Line -... | Line 429... | ||
| - | 429 | ||
| 500 | } |
430 | void evergreen_dp_enable(struct drm_encoder *encoder, bool enable) |
| - | 431 | { |
|
| - | 432 | struct drm_device *dev = encoder->dev; |
|
| 501 | 433 | struct radeon_device *rdev = dev->dev_private; |
|
| 502 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) |
434 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| - | 435 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
|
| 503 | { |
436 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
| 504 | struct drm_device *dev = encoder->dev; |
437 | |
| Line 505... | Line 438... | ||
| 505 | struct radeon_device *rdev = dev->dev_private; |
438 | if (!dig || !dig->afmt) |
| - | 439 | return; |
|
| - | 440 | ||
| 506 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
441 | if (enable && connector && |
| 507 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
442 | drm_detect_monitor_audio(radeon_connector_edid(connector))) { |
| - | 443 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
|
| - | 444 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
| - | 445 | struct radeon_connector_atom_dig *dig_connector; |
|
| - | 446 | uint32_t val; |
|
| - | 447 | ||
| 508 | 448 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
|
| 509 | if (!dig || !dig->afmt) |
449 | AFMT_AUDIO_SAMPLE_SEND); |
| - | 450 | ||
| 510 | return; |
451 | WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, |
| 511 | 452 | EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); |
|
| Line -... | Line 453... | ||
| - | 453 | ||
| - | 454 | if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) { |
|
| - | 455 | dig_connector = radeon_connector->con_priv; |
|
| - | 456 | val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset); |
|
| - | 457 | val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf); |
|
| - | 458 | ||
| - | 459 | if (dig_connector->dp_clock == 162000) |
|
| - | 460 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3); |
|
| 512 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
461 | else |
| - | 462 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5); |
|
| Line 513... | Line -... | ||
| 513 | if (enable && dig->afmt->enabled) |
- | |
| 514 | return; |
463 | |
| 515 | if (!enable && !dig->afmt->enabled) |
464 | WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val); |