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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Christian König. |
4 | * Copyright 2009 Christian König. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Christian König |
24 | * Authors: Christian König |
25 | * Rafał Miłecki |
25 | * Rafał Miłecki |
26 | */ |
26 | */ |
27 | #include |
27 | #include |
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include "radeon.h" |
30 | #include "radeon.h" |
31 | #include "radeon_asic.h" |
31 | #include "radeon_asic.h" |
32 | #include "evergreend.h" |
32 | #include "evergreend.h" |
33 | #include "atom.h" |
33 | #include "atom.h" |
34 | 34 | ||
35 | extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder); |
35 | extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder); |
36 | extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder); |
36 | extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder); |
37 | extern void dce6_afmt_select_pin(struct drm_encoder *encoder); |
37 | extern void dce6_afmt_select_pin(struct drm_encoder *encoder); |
38 | extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, |
38 | extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, |
39 | struct drm_display_mode *mode); |
39 | struct drm_display_mode *mode); |
- | 40 | ||
- | 41 | /* enable the audio stream */ |
|
- | 42 | static void dce4_audio_enable(struct radeon_device *rdev, |
|
- | 43 | struct r600_audio_pin *pin, |
|
- | 44 | u8 enable_mask) |
|
- | 45 | { |
|
- | 46 | u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); |
|
- | 47 | ||
- | 48 | if (!pin) |
|
- | 49 | return; |
|
- | 50 | ||
- | 51 | if (enable_mask) { |
|
- | 52 | tmp |= AUDIO_ENABLED; |
|
- | 53 | if (enable_mask & 1) |
|
- | 54 | tmp |= PIN0_AUDIO_ENABLED; |
|
- | 55 | if (enable_mask & 2) |
|
- | 56 | tmp |= PIN1_AUDIO_ENABLED; |
|
- | 57 | if (enable_mask & 4) |
|
- | 58 | tmp |= PIN2_AUDIO_ENABLED; |
|
- | 59 | if (enable_mask & 8) |
|
- | 60 | tmp |= PIN3_AUDIO_ENABLED; |
|
- | 61 | } else { |
|
- | 62 | tmp &= ~(AUDIO_ENABLED | |
|
- | 63 | PIN0_AUDIO_ENABLED | |
|
- | 64 | PIN1_AUDIO_ENABLED | |
|
- | 65 | PIN2_AUDIO_ENABLED | |
|
- | 66 | PIN3_AUDIO_ENABLED); |
|
- | 67 | } |
|
- | 68 | ||
- | 69 | WREG32(AZ_HOT_PLUG_CONTROL, tmp); |
|
- | 70 | } |
|
40 | 71 | ||
41 | /* |
72 | /* |
42 | * update the N and CTS parameters for a given pixel clock rate |
73 | * update the N and CTS parameters for a given pixel clock rate |
43 | */ |
74 | */ |
44 | static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
75 | static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
45 | { |
76 | { |
46 | struct drm_device *dev = encoder->dev; |
77 | struct drm_device *dev = encoder->dev; |
47 | struct radeon_device *rdev = dev->dev_private; |
78 | struct radeon_device *rdev = dev->dev_private; |
48 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
79 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
49 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
80 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
50 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
81 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
51 | uint32_t offset = dig->afmt->offset; |
82 | uint32_t offset = dig->afmt->offset; |
52 | 83 | ||
53 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); |
84 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); |
54 | WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); |
85 | WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); |
55 | 86 | ||
56 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); |
87 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); |
57 | WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); |
88 | WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); |
58 | 89 | ||
59 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); |
90 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); |
60 | WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); |
91 | WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); |
61 | } |
92 | } |
62 | 93 | ||
63 | static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
94 | static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
64 | struct drm_display_mode *mode) |
95 | struct drm_display_mode *mode) |
65 | { |
96 | { |
66 | struct radeon_device *rdev = encoder->dev->dev_private; |
97 | struct radeon_device *rdev = encoder->dev->dev_private; |
67 | struct drm_connector *connector; |
98 | struct drm_connector *connector; |
68 | struct radeon_connector *radeon_connector = NULL; |
99 | struct radeon_connector *radeon_connector = NULL; |
69 | u32 tmp = 0; |
100 | u32 tmp = 0; |
70 | 101 | ||
71 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
102 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
72 | if (connector->encoder == encoder) { |
103 | if (connector->encoder == encoder) { |
73 | radeon_connector = to_radeon_connector(connector); |
104 | radeon_connector = to_radeon_connector(connector); |
74 | break; |
105 | break; |
75 | } |
106 | } |
76 | } |
107 | } |
77 | 108 | ||
78 | if (!radeon_connector) { |
109 | if (!radeon_connector) { |
79 | DRM_ERROR("Couldn't find encoder's connector\n"); |
110 | DRM_ERROR("Couldn't find encoder's connector\n"); |
80 | return; |
111 | return; |
81 | } |
112 | } |
82 | 113 | ||
83 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
114 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
84 | if (connector->latency_present[1]) |
115 | if (connector->latency_present[1]) |
85 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | |
116 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | |
86 | AUDIO_LIPSYNC(connector->audio_latency[1]); |
117 | AUDIO_LIPSYNC(connector->audio_latency[1]); |
87 | else |
118 | else |
88 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
119 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
89 | } else { |
120 | } else { |
90 | if (connector->latency_present[0]) |
121 | if (connector->latency_present[0]) |
91 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
122 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
92 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
123 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
93 | else |
124 | else |
94 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
125 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
95 | } |
126 | } |
96 | WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); |
127 | WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); |
97 | } |
128 | } |
98 | 129 | ||
99 | static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder) |
130 | static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder) |
100 | { |
131 | { |
101 | struct radeon_device *rdev = encoder->dev->dev_private; |
132 | struct radeon_device *rdev = encoder->dev->dev_private; |
102 | struct drm_connector *connector; |
133 | struct drm_connector *connector; |
103 | struct radeon_connector *radeon_connector = NULL; |
134 | struct radeon_connector *radeon_connector = NULL; |
104 | u32 tmp; |
135 | u32 tmp; |
105 | u8 *sadb; |
136 | u8 *sadb = NULL; |
106 | int sad_count; |
137 | int sad_count; |
107 | 138 | ||
108 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
139 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
109 | if (connector->encoder == encoder) { |
140 | if (connector->encoder == encoder) { |
110 | radeon_connector = to_radeon_connector(connector); |
141 | radeon_connector = to_radeon_connector(connector); |
111 | break; |
142 | break; |
112 | } |
143 | } |
113 | } |
144 | } |
114 | 145 | ||
115 | if (!radeon_connector) { |
146 | if (!radeon_connector) { |
116 | DRM_ERROR("Couldn't find encoder's connector\n"); |
147 | DRM_ERROR("Couldn't find encoder's connector\n"); |
117 | return; |
148 | return; |
118 | } |
149 | } |
119 | 150 | ||
120 | sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), &sadb); |
151 | sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), &sadb); |
121 | if (sad_count < 0) { |
152 | if (sad_count < 0) { |
122 | DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
153 | DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
123 | sad_count = 0; |
154 | sad_count = 0; |
124 | } |
155 | } |
125 | 156 | ||
126 | /* program the speaker allocation */ |
157 | /* program the speaker allocation */ |
127 | tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
158 | tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
128 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
159 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
129 | /* set HDMI mode */ |
160 | /* set HDMI mode */ |
130 | tmp |= HDMI_CONNECTION; |
161 | tmp |= HDMI_CONNECTION; |
131 | if (sad_count) |
162 | if (sad_count) |
132 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
163 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
133 | else |
164 | else |
134 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
165 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
135 | WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
166 | WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
136 | 167 | ||
137 | kfree(sadb); |
168 | kfree(sadb); |
138 | } |
169 | } |
139 | 170 | ||
140 | static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder) |
171 | static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder) |
141 | { |
172 | { |
142 | struct radeon_device *rdev = encoder->dev->dev_private; |
173 | struct radeon_device *rdev = encoder->dev->dev_private; |
143 | struct drm_connector *connector; |
174 | struct drm_connector *connector; |
144 | struct radeon_connector *radeon_connector = NULL; |
175 | struct radeon_connector *radeon_connector = NULL; |
145 | struct cea_sad *sads; |
176 | struct cea_sad *sads; |
146 | int i, sad_count; |
177 | int i, sad_count; |
147 | 178 | ||
148 | static const u16 eld_reg_to_type[][2] = { |
179 | static const u16 eld_reg_to_type[][2] = { |
149 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
180 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
150 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
181 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
151 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
182 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
152 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
183 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
153 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
184 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
154 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
185 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
155 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
186 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
156 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
187 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
157 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
188 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
158 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
189 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
159 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
190 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
160 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
191 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
161 | }; |
192 | }; |
162 | 193 | ||
163 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
194 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
164 | if (connector->encoder == encoder) { |
195 | if (connector->encoder == encoder) { |
165 | radeon_connector = to_radeon_connector(connector); |
196 | radeon_connector = to_radeon_connector(connector); |
166 | break; |
197 | break; |
167 | } |
198 | } |
168 | } |
199 | } |
169 | 200 | ||
170 | if (!radeon_connector) { |
201 | if (!radeon_connector) { |
171 | DRM_ERROR("Couldn't find encoder's connector\n"); |
202 | DRM_ERROR("Couldn't find encoder's connector\n"); |
172 | return; |
203 | return; |
173 | } |
204 | } |
174 | 205 | ||
175 | sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads); |
206 | sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads); |
176 | if (sad_count <= 0) { |
207 | if (sad_count <= 0) { |
177 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
208 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
178 | return; |
209 | return; |
179 | } |
210 | } |
180 | BUG_ON(!sads); |
211 | BUG_ON(!sads); |
181 | 212 | ||
182 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
213 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
183 | u32 value = 0; |
214 | u32 value = 0; |
184 | u8 stereo_freqs = 0; |
215 | u8 stereo_freqs = 0; |
185 | int max_channels = -1; |
216 | int max_channels = -1; |
186 | int j; |
217 | int j; |
187 | 218 | ||
188 | for (j = 0; j < sad_count; j++) { |
219 | for (j = 0; j < sad_count; j++) { |
189 | struct cea_sad *sad = &sads[j]; |
220 | struct cea_sad *sad = &sads[j]; |
190 | 221 | ||
191 | if (sad->format == eld_reg_to_type[i][1]) { |
222 | if (sad->format == eld_reg_to_type[i][1]) { |
192 | if (sad->channels > max_channels) { |
223 | if (sad->channels > max_channels) { |
193 | value = MAX_CHANNELS(sad->channels) | |
224 | value = MAX_CHANNELS(sad->channels) | |
194 | DESCRIPTOR_BYTE_2(sad->byte2) | |
225 | DESCRIPTOR_BYTE_2(sad->byte2) | |
195 | SUPPORTED_FREQUENCIES(sad->freq); |
226 | SUPPORTED_FREQUENCIES(sad->freq); |
196 | max_channels = sad->channels; |
227 | max_channels = sad->channels; |
197 | } |
228 | } |
198 | 229 | ||
199 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
230 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
200 | stereo_freqs |= sad->freq; |
231 | stereo_freqs |= sad->freq; |
201 | else |
232 | else |
202 | break; |
233 | break; |
203 | } |
234 | } |
204 | } |
235 | } |
205 | 236 | ||
206 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
237 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
207 | 238 | ||
208 | WREG32(eld_reg_to_type[i][0], value); |
239 | WREG32(eld_reg_to_type[i][0], value); |
209 | } |
240 | } |
210 | 241 | ||
211 | kfree(sads); |
242 | kfree(sads); |
212 | } |
243 | } |
213 | 244 | ||
214 | /* |
245 | /* |
215 | * build a HDMI Video Info Frame |
246 | * build a HDMI Video Info Frame |
216 | */ |
247 | */ |
217 | static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, |
248 | static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, |
218 | void *buffer, size_t size) |
249 | void *buffer, size_t size) |
219 | { |
250 | { |
220 | struct drm_device *dev = encoder->dev; |
251 | struct drm_device *dev = encoder->dev; |
221 | struct radeon_device *rdev = dev->dev_private; |
252 | struct radeon_device *rdev = dev->dev_private; |
222 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
253 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
223 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
254 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
224 | uint32_t offset = dig->afmt->offset; |
255 | uint32_t offset = dig->afmt->offset; |
225 | uint8_t *frame = buffer + 3; |
256 | uint8_t *frame = buffer + 3; |
226 | uint8_t *header = buffer; |
257 | uint8_t *header = buffer; |
227 | 258 | ||
228 | WREG32(AFMT_AVI_INFO0 + offset, |
259 | WREG32(AFMT_AVI_INFO0 + offset, |
229 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
260 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
230 | WREG32(AFMT_AVI_INFO1 + offset, |
261 | WREG32(AFMT_AVI_INFO1 + offset, |
231 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
262 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
232 | WREG32(AFMT_AVI_INFO2 + offset, |
263 | WREG32(AFMT_AVI_INFO2 + offset, |
233 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
264 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
234 | WREG32(AFMT_AVI_INFO3 + offset, |
265 | WREG32(AFMT_AVI_INFO3 + offset, |
235 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); |
266 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); |
236 | } |
267 | } |
237 | 268 | ||
238 | static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
269 | static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
239 | { |
270 | { |
240 | struct drm_device *dev = encoder->dev; |
271 | struct drm_device *dev = encoder->dev; |
241 | struct radeon_device *rdev = dev->dev_private; |
272 | struct radeon_device *rdev = dev->dev_private; |
242 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
273 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
243 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
274 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
244 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
275 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
245 | u32 base_rate = 24000; |
276 | u32 base_rate = 24000; |
246 | u32 max_ratio = clock / base_rate; |
277 | u32 max_ratio = clock / base_rate; |
247 | u32 dto_phase; |
278 | u32 dto_phase; |
248 | u32 dto_modulo = clock; |
279 | u32 dto_modulo = clock; |
249 | u32 wallclock_ratio; |
280 | u32 wallclock_ratio; |
250 | u32 dto_cntl; |
281 | u32 dto_cntl; |
251 | 282 | ||
252 | if (!dig || !dig->afmt) |
283 | if (!dig || !dig->afmt) |
253 | return; |
284 | return; |
254 | 285 | ||
255 | if (ASIC_IS_DCE6(rdev)) { |
286 | if (ASIC_IS_DCE6(rdev)) { |
256 | dto_phase = 24 * 1000; |
287 | dto_phase = 24 * 1000; |
257 | } else { |
288 | } else { |
258 | if (max_ratio >= 8) { |
289 | if (max_ratio >= 8) { |
259 | dto_phase = 192 * 1000; |
290 | dto_phase = 192 * 1000; |
260 | wallclock_ratio = 3; |
291 | wallclock_ratio = 3; |
261 | } else if (max_ratio >= 4) { |
292 | } else if (max_ratio >= 4) { |
262 | dto_phase = 96 * 1000; |
293 | dto_phase = 96 * 1000; |
263 | wallclock_ratio = 2; |
294 | wallclock_ratio = 2; |
264 | } else if (max_ratio >= 2) { |
295 | } else if (max_ratio >= 2) { |
265 | dto_phase = 48 * 1000; |
296 | dto_phase = 48 * 1000; |
266 | wallclock_ratio = 1; |
297 | wallclock_ratio = 1; |
267 | } else { |
298 | } else { |
268 | dto_phase = 24 * 1000; |
299 | dto_phase = 24 * 1000; |
269 | wallclock_ratio = 0; |
300 | wallclock_ratio = 0; |
270 | } |
301 | } |
271 | dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
302 | dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
272 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
303 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
273 | WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); |
304 | WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); |
274 | } |
305 | } |
275 | 306 | ||
276 | /* XXX two dtos; generally use dto0 for hdmi */ |
307 | /* XXX two dtos; generally use dto0 for hdmi */ |
277 | /* Express [24MHz / target pixel clock] as an exact rational |
308 | /* Express [24MHz / target pixel clock] as an exact rational |
278 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
309 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
279 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
310 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
280 | */ |
311 | */ |
281 | WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); |
312 | WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); |
282 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
313 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
283 | WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); |
314 | WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); |
284 | } |
315 | } |
285 | 316 | ||
286 | 317 | ||
287 | /* |
318 | /* |
288 | * update the info frames with the data from the current display mode |
319 | * update the info frames with the data from the current display mode |
289 | */ |
320 | */ |
290 | void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
321 | void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
291 | { |
322 | { |
292 | struct drm_device *dev = encoder->dev; |
323 | struct drm_device *dev = encoder->dev; |
293 | struct radeon_device *rdev = dev->dev_private; |
324 | struct radeon_device *rdev = dev->dev_private; |
294 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
325 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
295 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
326 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
296 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
327 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
297 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
328 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
298 | struct hdmi_avi_infoframe frame; |
329 | struct hdmi_avi_infoframe frame; |
299 | uint32_t offset; |
330 | uint32_t offset; |
300 | ssize_t err; |
331 | ssize_t err; |
301 | uint32_t val; |
332 | uint32_t val; |
302 | int bpc = 8; |
333 | int bpc = 8; |
303 | 334 | ||
304 | if (!dig || !dig->afmt) |
335 | if (!dig || !dig->afmt) |
305 | return; |
336 | return; |
306 | 337 | ||
307 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
338 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
308 | if (!dig->afmt->enabled) |
339 | if (!dig->afmt->enabled) |
309 | return; |
340 | return; |
310 | offset = dig->afmt->offset; |
341 | offset = dig->afmt->offset; |
311 | 342 | ||
312 | /* hdmi deep color mode general control packets setup, if bpc > 8 */ |
343 | /* hdmi deep color mode general control packets setup, if bpc > 8 */ |
313 | if (encoder->crtc) { |
344 | if (encoder->crtc) { |
314 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
345 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
315 | bpc = radeon_crtc->bpc; |
346 | bpc = radeon_crtc->bpc; |
316 | } |
347 | } |
317 | 348 | ||
318 | /* disable audio prior to setting up hw */ |
349 | /* disable audio prior to setting up hw */ |
319 | if (ASIC_IS_DCE6(rdev)) { |
350 | if (ASIC_IS_DCE6(rdev)) { |
320 | dig->afmt->pin = dce6_audio_get_pin(rdev); |
351 | dig->afmt->pin = dce6_audio_get_pin(rdev); |
321 | dce6_audio_enable(rdev, dig->afmt->pin, false); |
352 | dce6_audio_enable(rdev, dig->afmt->pin, 0); |
322 | } else { |
353 | } else { |
323 | dig->afmt->pin = r600_audio_get_pin(rdev); |
354 | dig->afmt->pin = r600_audio_get_pin(rdev); |
324 | r600_audio_enable(rdev, dig->afmt->pin, false); |
355 | dce4_audio_enable(rdev, dig->afmt->pin, 0); |
325 | } |
356 | } |
326 | 357 | ||
327 | evergreen_audio_set_dto(encoder, mode->clock); |
358 | evergreen_audio_set_dto(encoder, mode->clock); |
328 | 359 | ||
329 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
360 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
330 | HDMI_NULL_SEND); /* send null packets when required */ |
361 | HDMI_NULL_SEND); /* send null packets when required */ |
331 | 362 | ||
332 | WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); |
363 | WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); |
333 | 364 | ||
334 | val = RREG32(HDMI_CONTROL + offset); |
365 | val = RREG32(HDMI_CONTROL + offset); |
335 | val &= ~HDMI_DEEP_COLOR_ENABLE; |
366 | val &= ~HDMI_DEEP_COLOR_ENABLE; |
336 | val &= ~HDMI_DEEP_COLOR_DEPTH_MASK; |
367 | val &= ~HDMI_DEEP_COLOR_DEPTH_MASK; |
337 | 368 | ||
338 | switch (bpc) { |
369 | switch (bpc) { |
339 | case 0: |
370 | case 0: |
340 | case 6: |
371 | case 6: |
341 | case 8: |
372 | case 8: |
342 | case 16: |
373 | case 16: |
343 | default: |
374 | default: |
344 | DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", |
375 | DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", |
345 | connector->name, bpc); |
376 | connector->name, bpc); |
346 | break; |
377 | break; |
347 | case 10: |
378 | case 10: |
348 | val |= HDMI_DEEP_COLOR_ENABLE; |
379 | val |= HDMI_DEEP_COLOR_ENABLE; |
349 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR); |
380 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR); |
350 | DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", |
381 | DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", |
351 | connector->name); |
382 | connector->name); |
352 | break; |
383 | break; |
353 | case 12: |
384 | case 12: |
354 | val |= HDMI_DEEP_COLOR_ENABLE; |
385 | val |= HDMI_DEEP_COLOR_ENABLE; |
355 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR); |
386 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR); |
356 | DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", |
387 | DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", |
357 | connector->name); |
388 | connector->name); |
358 | break; |
389 | break; |
359 | } |
390 | } |
360 | 391 | ||
361 | WREG32(HDMI_CONTROL + offset, val); |
392 | WREG32(HDMI_CONTROL + offset, val); |
362 | 393 | ||
363 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
394 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
364 | HDMI_NULL_SEND | /* send null packets when required */ |
395 | HDMI_NULL_SEND | /* send null packets when required */ |
365 | HDMI_GC_SEND | /* send general control packets */ |
396 | HDMI_GC_SEND | /* send general control packets */ |
366 | HDMI_GC_CONT); /* send general control packets every frame */ |
397 | HDMI_GC_CONT); /* send general control packets every frame */ |
367 | 398 | ||
368 | WREG32(HDMI_INFOFRAME_CONTROL0 + offset, |
399 | WREG32(HDMI_INFOFRAME_CONTROL0 + offset, |
369 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
400 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
370 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
401 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
371 | 402 | ||
372 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
403 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
373 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
404 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
374 | 405 | ||
375 | WREG32(HDMI_INFOFRAME_CONTROL1 + offset, |
406 | WREG32(HDMI_INFOFRAME_CONTROL1 + offset, |
376 | HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
407 | HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
377 | 408 | ||
378 | WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ |
409 | WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ |
379 | 410 | ||
380 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
411 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
381 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ |
412 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ |
382 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
413 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
383 | 414 | ||
384 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, |
415 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, |
385 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
416 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
386 | 417 | ||
387 | /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ |
418 | /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ |
388 | 419 | ||
389 | if (bpc > 8) |
420 | if (bpc > 8) |
390 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
421 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
391 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
422 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
392 | else |
423 | else |
393 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
424 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
394 | HDMI_ACR_SOURCE | /* select SW CTS value */ |
425 | HDMI_ACR_SOURCE | /* select SW CTS value */ |
395 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
426 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
396 | 427 | ||
397 | evergreen_hdmi_update_ACR(encoder, mode->clock); |
428 | evergreen_hdmi_update_ACR(encoder, mode->clock); |
398 | 429 | ||
399 | WREG32(AFMT_60958_0 + offset, |
430 | WREG32(AFMT_60958_0 + offset, |
400 | AFMT_60958_CS_CHANNEL_NUMBER_L(1)); |
431 | AFMT_60958_CS_CHANNEL_NUMBER_L(1)); |
401 | 432 | ||
402 | WREG32(AFMT_60958_1 + offset, |
433 | WREG32(AFMT_60958_1 + offset, |
403 | AFMT_60958_CS_CHANNEL_NUMBER_R(2)); |
434 | AFMT_60958_CS_CHANNEL_NUMBER_R(2)); |
404 | 435 | ||
405 | WREG32(AFMT_60958_2 + offset, |
436 | WREG32(AFMT_60958_2 + offset, |
406 | AFMT_60958_CS_CHANNEL_NUMBER_2(3) | |
437 | AFMT_60958_CS_CHANNEL_NUMBER_2(3) | |
407 | AFMT_60958_CS_CHANNEL_NUMBER_3(4) | |
438 | AFMT_60958_CS_CHANNEL_NUMBER_3(4) | |
408 | AFMT_60958_CS_CHANNEL_NUMBER_4(5) | |
439 | AFMT_60958_CS_CHANNEL_NUMBER_4(5) | |
409 | AFMT_60958_CS_CHANNEL_NUMBER_5(6) | |
440 | AFMT_60958_CS_CHANNEL_NUMBER_5(6) | |
410 | AFMT_60958_CS_CHANNEL_NUMBER_6(7) | |
441 | AFMT_60958_CS_CHANNEL_NUMBER_6(7) | |
411 | AFMT_60958_CS_CHANNEL_NUMBER_7(8)); |
442 | AFMT_60958_CS_CHANNEL_NUMBER_7(8)); |
412 | 443 | ||
413 | if (ASIC_IS_DCE6(rdev)) { |
444 | if (ASIC_IS_DCE6(rdev)) { |
414 | dce6_afmt_write_speaker_allocation(encoder); |
445 | dce6_afmt_write_speaker_allocation(encoder); |
415 | } else { |
446 | } else { |
416 | dce4_afmt_write_speaker_allocation(encoder); |
447 | dce4_afmt_write_speaker_allocation(encoder); |
417 | } |
448 | } |
418 | 449 | ||
419 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, |
450 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, |
420 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); |
451 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); |
421 | 452 | ||
422 | /* fglrx sets 0x40 in 0x5f80 here */ |
453 | /* fglrx sets 0x40 in 0x5f80 here */ |
423 | 454 | ||
424 | if (ASIC_IS_DCE6(rdev)) { |
455 | if (ASIC_IS_DCE6(rdev)) { |
425 | dce6_afmt_select_pin(encoder); |
456 | dce6_afmt_select_pin(encoder); |
426 | dce6_afmt_write_sad_regs(encoder); |
457 | dce6_afmt_write_sad_regs(encoder); |
427 | dce6_afmt_write_latency_fields(encoder, mode); |
458 | dce6_afmt_write_latency_fields(encoder, mode); |
428 | } else { |
459 | } else { |
429 | evergreen_hdmi_write_sad_regs(encoder); |
460 | evergreen_hdmi_write_sad_regs(encoder); |
430 | dce4_afmt_write_latency_fields(encoder, mode); |
461 | dce4_afmt_write_latency_fields(encoder, mode); |
431 | } |
462 | } |
432 | 463 | ||
433 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
464 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
434 | if (err < 0) { |
465 | if (err < 0) { |
435 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); |
466 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); |
436 | return; |
467 | return; |
437 | } |
468 | } |
438 | 469 | ||
439 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
470 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
440 | if (err < 0) { |
471 | if (err < 0) { |
441 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); |
472 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); |
442 | return; |
473 | return; |
443 | } |
474 | } |
444 | 475 | ||
445 | evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
476 | evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
446 | 477 | ||
447 | WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset, |
478 | WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset, |
448 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
479 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
449 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ |
480 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ |
450 | 481 | ||
451 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, |
482 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, |
452 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ |
483 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ |
453 | ~HDMI_AVI_INFO_LINE_MASK); |
484 | ~HDMI_AVI_INFO_LINE_MASK); |
454 | 485 | ||
455 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, |
486 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, |
456 | AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */ |
487 | AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */ |
457 | 488 | ||
458 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
489 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
459 | WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
490 | WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
460 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); |
491 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); |
461 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); |
492 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); |
462 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); |
493 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); |
463 | 494 | ||
464 | /* enable audio after to setting up hw */ |
495 | /* enable audio after to setting up hw */ |
465 | if (ASIC_IS_DCE6(rdev)) |
496 | if (ASIC_IS_DCE6(rdev)) |
466 | dce6_audio_enable(rdev, dig->afmt->pin, true); |
497 | dce6_audio_enable(rdev, dig->afmt->pin, 1); |
467 | else |
498 | else |
468 | r600_audio_enable(rdev, dig->afmt->pin, true); |
499 | dce4_audio_enable(rdev, dig->afmt->pin, 0xf); |
469 | } |
500 | } |
470 | 501 | ||
471 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) |
502 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) |
472 | { |
503 | { |
- | 504 | struct drm_device *dev = encoder->dev; |
|
- | 505 | struct radeon_device *rdev = dev->dev_private; |
|
473 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
506 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
474 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
507 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
475 | 508 | ||
476 | if (!dig || !dig->afmt) |
509 | if (!dig || !dig->afmt) |
477 | return; |
510 | return; |
478 | 511 | ||
479 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
512 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
480 | if (enable && dig->afmt->enabled) |
513 | if (enable && dig->afmt->enabled) |
481 | return; |
514 | return; |
482 | if (!enable && !dig->afmt->enabled) |
515 | if (!enable && !dig->afmt->enabled) |
483 | return; |
516 | return; |
- | 517 | ||
- | 518 | if (!enable && dig->afmt->pin) { |
|
- | 519 | if (ASIC_IS_DCE6(rdev)) |
|
- | 520 | dce6_audio_enable(rdev, dig->afmt->pin, 0); |
|
- | 521 | else |
|
- | 522 | dce4_audio_enable(rdev, dig->afmt->pin, 0); |
|
- | 523 | dig->afmt->pin = NULL; |
|
- | 524 | } |
|
484 | 525 | ||
485 | dig->afmt->enabled = enable; |
526 | dig->afmt->enabled = enable; |
486 | 527 | ||
487 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
528 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
488 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); |
529 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); |
489 | }>>><>><>><>><>><>><>><>><>><>><>><>>>=>> |
530 | }>>><>><>><>><>><>><>><>><>><>><>><>>>=>> |