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Rev 5078 | Rev 5271 | ||
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Line 102... | Line 102... | ||
102 | * |
102 | * |
103 | * Copy GPU paging using the DMA engine (evergreen-cayman). |
103 | * Copy GPU paging using the DMA engine (evergreen-cayman). |
104 | * Used by the radeon ttm implementation to move pages if |
104 | * Used by the radeon ttm implementation to move pages if |
105 | * registered as the asic copy callback. |
105 | * registered as the asic copy callback. |
106 | */ |
106 | */ |
107 | int evergreen_copy_dma(struct radeon_device *rdev, |
107 | struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev, |
108 | uint64_t src_offset, uint64_t dst_offset, |
108 | uint64_t src_offset, |
- | 109 | uint64_t dst_offset, |
|
109 | unsigned num_gpu_pages, |
110 | unsigned num_gpu_pages, |
110 | struct radeon_fence **fence) |
111 | struct reservation_object *resv) |
111 | { |
112 | { |
112 | struct radeon_semaphore *sem = NULL; |
113 | struct radeon_fence *fence; |
- | 114 | struct radeon_sync sync; |
|
113 | int ring_index = rdev->asic->copy.dma_ring_index; |
115 | int ring_index = rdev->asic->copy.dma_ring_index; |
114 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
116 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
115 | u32 size_in_dw, cur_size_in_dw; |
117 | u32 size_in_dw, cur_size_in_dw; |
116 | int i, num_loops; |
118 | int i, num_loops; |
117 | int r = 0; |
119 | int r = 0; |
Line 118... | Line 120... | ||
118 | 120 | ||
119 | r = radeon_semaphore_create(rdev, &sem); |
- | |
120 | if (r) { |
- | |
121 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
- | |
122 | return r; |
- | |
Line 123... | Line 121... | ||
123 | } |
121 | radeon_sync_create(&sync); |
124 | 122 | ||
125 | size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; |
123 | size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; |
126 | num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff); |
124 | num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff); |
127 | r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11); |
125 | r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11); |
128 | if (r) { |
126 | if (r) { |
129 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
127 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
130 | radeon_semaphore_free(rdev, &sem, NULL); |
128 | radeon_sync_free(rdev, &sync, NULL); |
Line 131... | Line 129... | ||
131 | return r; |
129 | return ERR_PTR(r); |
132 | } |
130 | } |
Line 133... | Line 131... | ||
133 | 131 | ||
134 | radeon_semaphore_sync_to(sem, *fence); |
132 | radeon_sync_resv(rdev, &sync, resv, false); |
135 | radeon_semaphore_sync_rings(rdev, sem, ring->idx); |
133 | radeon_sync_rings(rdev, &sync, ring->idx); |
136 | 134 | ||
Line 146... | Line 144... | ||
146 | radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); |
144 | radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); |
147 | src_offset += cur_size_in_dw * 4; |
145 | src_offset += cur_size_in_dw * 4; |
148 | dst_offset += cur_size_in_dw * 4; |
146 | dst_offset += cur_size_in_dw * 4; |
149 | } |
147 | } |
Line 150... | Line 148... | ||
150 | 148 | ||
151 | r = radeon_fence_emit(rdev, fence, ring->idx); |
149 | r = radeon_fence_emit(rdev, &fence, ring->idx); |
152 | if (r) { |
150 | if (r) { |
153 | radeon_ring_unlock_undo(rdev, ring); |
151 | radeon_ring_unlock_undo(rdev, ring); |
154 | radeon_semaphore_free(rdev, &sem, NULL); |
152 | radeon_sync_free(rdev, &sync, NULL); |
155 | return r; |
153 | return ERR_PTR(r); |
Line 156... | Line 154... | ||
156 | } |
154 | } |
157 | 155 | ||
Line 158... | Line 156... | ||
158 | radeon_ring_unlock_commit(rdev, ring, false); |
156 | radeon_ring_unlock_commit(rdev, ring, false); |
159 | radeon_semaphore_free(rdev, &sem, *fence); |
157 | radeon_sync_free(rdev, &sync, fence); |
Line 160... | Line 158... | ||
160 | 158 | ||
161 | return r; |
159 | return fence; |
162 | } |
160 | } |