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Rev 6104 | Rev 6661 | ||
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Line 2606... | Line 2606... | ||
2606 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
2606 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
2607 | WREG32(VM_CONTEXT0_CNTL, 0); |
2607 | WREG32(VM_CONTEXT0_CNTL, 0); |
2608 | WREG32(VM_CONTEXT1_CNTL, 0); |
2608 | WREG32(VM_CONTEXT1_CNTL, 0); |
2609 | } |
2609 | } |
Line -... | Line 2610... | ||
- | 2610 | ||
- | 2611 | static const unsigned ni_dig_offsets[] = |
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- | 2612 | { |
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- | 2613 | NI_DIG0_REGISTER_OFFSET, |
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- | 2614 | NI_DIG1_REGISTER_OFFSET, |
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- | 2615 | NI_DIG2_REGISTER_OFFSET, |
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- | 2616 | NI_DIG3_REGISTER_OFFSET, |
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- | 2617 | NI_DIG4_REGISTER_OFFSET, |
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- | 2618 | NI_DIG5_REGISTER_OFFSET |
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- | 2619 | }; |
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- | 2620 | ||
- | 2621 | static const unsigned ni_tx_offsets[] = |
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- | 2622 | { |
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- | 2623 | NI_DCIO_UNIPHY0_UNIPHY_TX_CONTROL1, |
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- | 2624 | NI_DCIO_UNIPHY1_UNIPHY_TX_CONTROL1, |
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- | 2625 | NI_DCIO_UNIPHY2_UNIPHY_TX_CONTROL1, |
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- | 2626 | NI_DCIO_UNIPHY3_UNIPHY_TX_CONTROL1, |
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- | 2627 | NI_DCIO_UNIPHY4_UNIPHY_TX_CONTROL1, |
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- | 2628 | NI_DCIO_UNIPHY5_UNIPHY_TX_CONTROL1 |
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- | 2629 | }; |
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- | 2630 | ||
- | 2631 | static const unsigned evergreen_dp_offsets[] = |
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- | 2632 | { |
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- | 2633 | EVERGREEN_DP0_REGISTER_OFFSET, |
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- | 2634 | EVERGREEN_DP1_REGISTER_OFFSET, |
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- | 2635 | EVERGREEN_DP2_REGISTER_OFFSET, |
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- | 2636 | EVERGREEN_DP3_REGISTER_OFFSET, |
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- | 2637 | EVERGREEN_DP4_REGISTER_OFFSET, |
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- | 2638 | EVERGREEN_DP5_REGISTER_OFFSET |
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- | 2639 | }; |
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- | 2640 | ||
- | 2641 | ||
- | 2642 | /* |
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- | 2643 | * Assumption is that EVERGREEN_CRTC_MASTER_EN enable for requested crtc |
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- | 2644 | * We go from crtc to connector and it is not relible since it |
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- | 2645 | * should be an opposite direction .If crtc is enable then |
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- | 2646 | * find the dig_fe which selects this crtc and insure that it enable. |
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- | 2647 | * if such dig_fe is found then find dig_be which selects found dig_be and |
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- | 2648 | * insure that it enable and in DP_SST mode. |
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- | 2649 | * if UNIPHY_PLL_CONTROL1.enable then we should disconnect timing |
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- | 2650 | * from dp symbols clocks . |
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- | 2651 | */ |
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- | 2652 | static bool evergreen_is_dp_sst_stream_enabled(struct radeon_device *rdev, |
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- | 2653 | unsigned crtc_id, unsigned *ret_dig_fe) |
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- | 2654 | { |
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- | 2655 | unsigned i; |
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- | 2656 | unsigned dig_fe; |
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- | 2657 | unsigned dig_be; |
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- | 2658 | unsigned dig_en_be; |
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- | 2659 | unsigned uniphy_pll; |
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- | 2660 | unsigned digs_fe_selected; |
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- | 2661 | unsigned dig_be_mode; |
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- | 2662 | unsigned dig_fe_mask; |
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- | 2663 | bool is_enabled = false; |
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- | 2664 | bool found_crtc = false; |
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- | 2665 | ||
- | 2666 | /* loop through all running dig_fe to find selected crtc */ |
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- | 2667 | for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) { |
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- | 2668 | dig_fe = RREG32(NI_DIG_FE_CNTL + ni_dig_offsets[i]); |
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- | 2669 | if (dig_fe & NI_DIG_FE_CNTL_SYMCLK_FE_ON && |
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- | 2670 | crtc_id == NI_DIG_FE_CNTL_SOURCE_SELECT(dig_fe)) { |
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- | 2671 | /* found running pipe */ |
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- | 2672 | found_crtc = true; |
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- | 2673 | dig_fe_mask = 1 << i; |
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- | 2674 | dig_fe = i; |
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- | 2675 | break; |
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- | 2676 | } |
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- | 2677 | } |
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- | 2678 | ||
- | 2679 | if (found_crtc) { |
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- | 2680 | /* loop through all running dig_be to find selected dig_fe */ |
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- | 2681 | for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) { |
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- | 2682 | dig_be = RREG32(NI_DIG_BE_CNTL + ni_dig_offsets[i]); |
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- | 2683 | /* if dig_fe_selected by dig_be? */ |
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- | 2684 | digs_fe_selected = NI_DIG_BE_CNTL_FE_SOURCE_SELECT(dig_be); |
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- | 2685 | dig_be_mode = NI_DIG_FE_CNTL_MODE(dig_be); |
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- | 2686 | if (dig_fe_mask & digs_fe_selected && |
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- | 2687 | /* if dig_be in sst mode? */ |
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- | 2688 | dig_be_mode == NI_DIG_BE_DPSST) { |
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- | 2689 | dig_en_be = RREG32(NI_DIG_BE_EN_CNTL + |
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- | 2690 | ni_dig_offsets[i]); |
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- | 2691 | uniphy_pll = RREG32(NI_DCIO_UNIPHY0_PLL_CONTROL1 + |
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- | 2692 | ni_tx_offsets[i]); |
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- | 2693 | /* dig_be enable and tx is running */ |
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- | 2694 | if (dig_en_be & NI_DIG_BE_EN_CNTL_ENABLE && |
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- | 2695 | dig_en_be & NI_DIG_BE_EN_CNTL_SYMBCLK_ON && |
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- | 2696 | uniphy_pll & NI_DCIO_UNIPHY0_PLL_CONTROL1_ENABLE) { |
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- | 2697 | is_enabled = true; |
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- | 2698 | *ret_dig_fe = dig_fe; |
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- | 2699 | break; |
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- | 2700 | } |
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- | 2701 | } |
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- | 2702 | } |
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- | 2703 | } |
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- | 2704 | ||
- | 2705 | return is_enabled; |
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- | 2706 | } |
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- | 2707 | ||
- | 2708 | /* |
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- | 2709 | * Blank dig when in dp sst mode |
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- | 2710 | * Dig ignores crtc timing |
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- | 2711 | */ |
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- | 2712 | static void evergreen_blank_dp_output(struct radeon_device *rdev, |
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- | 2713 | unsigned dig_fe) |
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- | 2714 | { |
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- | 2715 | unsigned stream_ctrl; |
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- | 2716 | unsigned fifo_ctrl; |
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- | 2717 | unsigned counter = 0; |
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- | 2718 | ||
- | 2719 | if (dig_fe >= ARRAY_SIZE(evergreen_dp_offsets)) { |
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- | 2720 | DRM_ERROR("invalid dig_fe %d\n", dig_fe); |
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- | 2721 | return; |
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- | 2722 | } |
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- | 2723 | ||
- | 2724 | stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + |
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- | 2725 | evergreen_dp_offsets[dig_fe]); |
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- | 2726 | if (!(stream_ctrl & EVERGREEN_DP_VID_STREAM_CNTL_ENABLE)) { |
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- | 2727 | DRM_ERROR("dig %d , should be enable\n", dig_fe); |
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- | 2728 | return; |
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- | 2729 | } |
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- | 2730 | ||
- | 2731 | stream_ctrl &=~EVERGREEN_DP_VID_STREAM_CNTL_ENABLE; |
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- | 2732 | WREG32(EVERGREEN_DP_VID_STREAM_CNTL + |
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- | 2733 | evergreen_dp_offsets[dig_fe], stream_ctrl); |
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- | 2734 | ||
- | 2735 | stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + |
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- | 2736 | evergreen_dp_offsets[dig_fe]); |
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- | 2737 | while (counter < 32 && stream_ctrl & EVERGREEN_DP_VID_STREAM_STATUS) { |
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- | 2738 | msleep(1); |
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- | 2739 | counter++; |
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- | 2740 | stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + |
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- | 2741 | evergreen_dp_offsets[dig_fe]); |
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- | 2742 | } |
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- | 2743 | if (counter >= 32 ) |
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- | 2744 | DRM_ERROR("counter exceeds %d\n", counter); |
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- | 2745 | ||
- | 2746 | fifo_ctrl = RREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe]); |
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- | 2747 | fifo_ctrl |= EVERGREEN_DP_STEER_FIFO_RESET; |
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- | 2748 | WREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe], fifo_ctrl); |
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- | 2749 | ||
- | 2750 | } |
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2610 | 2751 | ||
2611 | void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) |
2752 | void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) |
2612 | { |
2753 | { |
2613 | u32 crtc_enabled, tmp, frame_count, blackout; |
2754 | u32 crtc_enabled, tmp, frame_count, blackout; |
- | 2755 | int i, j; |
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Line 2614... | Line 2756... | ||
2614 | int i, j; |
2756 | unsigned dig_fe; |
2615 | 2757 | ||
2616 | if (!ASIC_IS_NODCE(rdev)) { |
2758 | if (!ASIC_IS_NODCE(rdev)) { |
Line 2649... | Line 2791... | ||
2649 | for (j = 0; j < rdev->usec_timeout; j++) { |
2791 | for (j = 0; j < rdev->usec_timeout; j++) { |
2650 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
2792 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
2651 | break; |
2793 | break; |
2652 | udelay(1); |
2794 | udelay(1); |
2653 | } |
2795 | } |
- | 2796 | /*we should disable dig if it drives dp sst*/ |
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- | 2797 | /*but we are in radeon_device_init and the topology is unknown*/ |
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- | 2798 | /*and it is available after radeon_modeset_init*/ |
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- | 2799 | /*the following method radeon_atom_encoder_dpms_dig*/ |
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- | 2800 | /*does the job if we initialize it properly*/ |
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- | 2801 | /*for now we do it this manually*/ |
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2654 | 2802 | /**/ |
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- | 2803 | if (ASIC_IS_DCE5(rdev) && |
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- | 2804 | evergreen_is_dp_sst_stream_enabled(rdev, i ,&dig_fe)) |
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- | 2805 | evergreen_blank_dp_output(rdev, dig_fe); |
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- | 2806 | /*we could remove 6 lines below*/ |
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2655 | /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ |
2807 | /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ |
2656 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
2808 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
2657 | tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); |
2809 | tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); |
2658 | tmp &= ~EVERGREEN_CRTC_MASTER_EN; |
2810 | tmp &= ~EVERGREEN_CRTC_MASTER_EN; |
2659 | WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); |
2811 | WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); |