WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/evergreen.c



 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Alex Deucher
 */
#include 
 
#include 
#include 
#include "radeon.h"
#include "radeon_asic.h"
#include 

	struct drm_display_mode *mode0 = NULL;
	struct drm_display_mode *mode1 = NULL;
	u32 num_heads = 0, lb_size;
	int i;

 
	if (!rdev->mode_info.mode_config_initialized)
		return;
 

	radeon_update_display_priority(rdev);
 
	for (i = 0; i < rdev->num_crtc; i++) {

				if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
					radeon_wait_for_vblank(rdev, i);
					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
					tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
					WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
				}
			} else {
				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
				if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
					radeon_wait_for_vblank(rdev, i);

	u32 sq_stack_resource_mgmt_2;
	u32 sq_stack_resource_mgmt_3;
	u32 vgt_cache_invalidation;
	u32 hdp_host_path_cntl, tmp;
	u32 disabled_rb_mask;
	int i, j, ps_thread_count;

 
	switch (rdev->family) {
	case CHIP_CYPRESS:
	case CHIP_HEMLOCK:

	}
	rdev->config.evergreen.tile_config |= 0 << 8;
	rdev->config.evergreen.tile_config |=
		((gb_addr_config & 0x30000000) >> 28) << 12;

 
 
 
	if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
		u32 efuse_straps_4;

		u32 efuse_straps_3;

	if (src_ptr) {
		/* save restore block */
		if (rdev->rlc.save_restore_obj == NULL) {
			r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
					     RADEON_GEM_DOMAIN_VRAM, 0, NULL,
					     NULL, &rdev->rlc.save_restore_obj);
			if (r) {
				dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
				return r;
			}
		}

		}

 
		if (rdev->rlc.clear_state_obj == NULL) {
			r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
					     RADEON_GEM_DOMAIN_VRAM, 0, NULL,
					     NULL, &rdev->rlc.clear_state_obj);
			if (r) {
				dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
				sumo_rlc_fini(rdev);
				return r;

	if (rdev->rlc.cp_table_size) {
		if (rdev->rlc.cp_table_obj == NULL) {
			r = radeon_bo_create(rdev, rdev->rlc.cp_table_size,
					     PAGE_SIZE, true,
					     RADEON_GEM_DOMAIN_VRAM, 0, NULL,
					     NULL, &rdev->rlc.cp_table_obj);
			if (r) {
				dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r);
				sumo_rlc_fini(rdev);
				return r;
			}

		}

 
		/* wptr/rptr are in bytes! */
		rptr += 16;
		rptr &= rdev->ih.ptr_mask;
		WREG32(IH_RB_RPTR, rptr);
	}
 
	rdev->ih.rptr = rptr;

	atomic_set(&rdev->ih.lock, 0);
 
	/* make sure wptr hasn't changed while processing */

Rev 5179	Rev 5271
Line 20...	Line 20...
20	* OTHER DEALINGS IN THE SOFTWARE.	20	* OTHER DEALINGS IN THE SOFTWARE.
21	*	21	*
22	* Authors: Alex Deucher	22	* Authors: Alex Deucher
23	*/	23	*/
24	#include	24	#include
25	//#include	-
26	#include	25	#include
27	#include	26	#include
28	#include "radeon.h"	27	#include "radeon.h"
29	#include "radeon_asic.h"	28	#include "radeon_asic.h"
30	#include	29	#include
Line 2344...	Line 2343...
2344	struct drm_display_mode *mode0 = NULL;	2343	struct drm_display_mode *mode0 = NULL;
2345	struct drm_display_mode *mode1 = NULL;	2344	struct drm_display_mode *mode1 = NULL;
2346	u32 num_heads = 0, lb_size;	2345	u32 num_heads = 0, lb_size;
2347	int i;	2346	int i;
Line -...	Line 2347...
-		2347
-		2348	if (!rdev->mode_info.mode_config_initialized)
-		2349	return;
2348		2350
Line 2349...	Line 2351...
2349	radeon_update_display_priority(rdev);	2351	radeon_update_display_priority(rdev);
2350		2352
2351	for (i = 0; i < rdev->num_crtc; i++) {	2353	for (i = 0; i < rdev->num_crtc; i++) {
Line 2551...	Line 2553...
2551	if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {	2553	if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
2552	radeon_wait_for_vblank(rdev, i);	2554	radeon_wait_for_vblank(rdev, i);
2553	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);	2555	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2554	tmp \|= EVERGREEN_CRTC_BLANK_DATA_EN;	2556	tmp \|= EVERGREEN_CRTC_BLANK_DATA_EN;
2555	WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);	2557	WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
-		2558	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2556	}	2559	}
2557	} else {	2560	} else {
2558	tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);	2561	tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
2559	if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {	2562	if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
2560	radeon_wait_for_vblank(rdev, i);	2563	radeon_wait_for_vblank(rdev, i);
Line 3004...	Line 3007...
3004	u32 sq_stack_resource_mgmt_2;	3007	u32 sq_stack_resource_mgmt_2;
3005	u32 sq_stack_resource_mgmt_3;	3008	u32 sq_stack_resource_mgmt_3;
3006	u32 vgt_cache_invalidation;	3009	u32 vgt_cache_invalidation;
3007	u32 hdp_host_path_cntl, tmp;	3010	u32 hdp_host_path_cntl, tmp;
3008	u32 disabled_rb_mask;	3011	u32 disabled_rb_mask;
3009	int i, j, num_shader_engines, ps_thread_count;	3012	int i, j, ps_thread_count;
Line 3010...	Line 3013...
3010		3013
3011	switch (rdev->family) {	3014	switch (rdev->family) {
3012	case CHIP_CYPRESS:	3015	case CHIP_CYPRESS:
3013	case CHIP_HEMLOCK:	3016	case CHIP_HEMLOCK:
Line 3302...	Line 3305...
3302	}	3305	}
3303	rdev->config.evergreen.tile_config \|= 0 << 8;	3306	rdev->config.evergreen.tile_config \|= 0 << 8;
3304	rdev->config.evergreen.tile_config \|=	3307	rdev->config.evergreen.tile_config \|=
3305	((gb_addr_config & 0x30000000) >> 28) << 12;	3308	((gb_addr_config & 0x30000000) >> 28) << 12;
Line 3306...	Line -...
3306		-
3307	num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;	-
3308		3309
3309	if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {	3310	if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
3310	u32 efuse_straps_4;	3311	u32 efuse_straps_4;
Line 3311...	Line 3312...
3311	u32 efuse_straps_3;	3312	u32 efuse_straps_3;
Line 4021...	Line 4022...
4021	if (src_ptr) {	4022	if (src_ptr) {
4022	/* save restore block */	4023	/* save restore block */
4023	if (rdev->rlc.save_restore_obj == NULL) {	4024	if (rdev->rlc.save_restore_obj == NULL) {
4024	r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,	4025	r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
4025	RADEON_GEM_DOMAIN_VRAM, 0, NULL,	4026	RADEON_GEM_DOMAIN_VRAM, 0, NULL,
4026	&rdev->rlc.save_restore_obj);	4027	NULL, &rdev->rlc.save_restore_obj);
4027	if (r) {	4028	if (r) {
4028	dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);	4029	dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
4029	return r;	4030	return r;
4030	}	4031	}
4031	}	4032	}
Line 4100...	Line 4101...
4100	}	4101	}
Line 4101...	Line 4102...
4101		4102
4102	if (rdev->rlc.clear_state_obj == NULL) {	4103	if (rdev->rlc.clear_state_obj == NULL) {
4103	r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,	4104	r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
4104	RADEON_GEM_DOMAIN_VRAM, 0, NULL,	4105	RADEON_GEM_DOMAIN_VRAM, 0, NULL,
4105	&rdev->rlc.clear_state_obj);	4106	NULL, &rdev->rlc.clear_state_obj);
4106	if (r) {	4107	if (r) {
4107	dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);	4108	dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
4108	sumo_rlc_fini(rdev);	4109	sumo_rlc_fini(rdev);
4109	return r;	4110	return r;
Line 4177...	Line 4178...
4177	if (rdev->rlc.cp_table_size) {	4178	if (rdev->rlc.cp_table_size) {
4178	if (rdev->rlc.cp_table_obj == NULL) {	4179	if (rdev->rlc.cp_table_obj == NULL) {
4179	r = radeon_bo_create(rdev, rdev->rlc.cp_table_size,	4180	r = radeon_bo_create(rdev, rdev->rlc.cp_table_size,
4180	PAGE_SIZE, true,	4181	PAGE_SIZE, true,
4181	RADEON_GEM_DOMAIN_VRAM, 0, NULL,	4182	RADEON_GEM_DOMAIN_VRAM, 0, NULL,
4182	&rdev->rlc.cp_table_obj);	4183	NULL, &rdev->rlc.cp_table_obj);
4183	if (r) {	4184	if (r) {
4184	dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r);	4185	dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r);
4185	sumo_rlc_fini(rdev);	4186	sumo_rlc_fini(rdev);
4186	return r;	4187	return r;
4187	}	4188	}
Line 5133...	Line 5134...
5133	}	5134	}
Line 5134...	Line 5135...
5134		5135
5135	/* wptr/rptr are in bytes! */	5136	/* wptr/rptr are in bytes! */
5136	rptr += 16;	5137	rptr += 16;
-		5138	rptr &= rdev->ih.ptr_mask;
5137	rptr &= rdev->ih.ptr_mask;	5139	WREG32(IH_RB_RPTR, rptr);
5138	}	5140	}
5139	rdev->ih.rptr = rptr;	-
5140	WREG32(IH_RB_RPTR, rdev->ih.rptr);	5141	rdev->ih.rptr = rptr;
Line 5141...	Line 5142...
5141	atomic_set(&rdev->ih.lock, 0);	5142	atomic_set(&rdev->ih.lock, 0);
5142		5143
5143	/* make sure wptr hasn't changed while processing */	5144	/* make sure wptr hasn't changed while processing */

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/evergreen.c – Rev 5179 → 5271