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Rev 2997 Rev 3031
Line 1283... Line 1283...
1283 
	WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
 1283 
	WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1284 
	/* allow CPU access */
 1284 
	/* allow CPU access */
1285 
	WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
 1285 
	WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
Line 1286... Line 1286...
1286 
 
 1286 
 
1287 
	for (i = 0; i < rdev->num_crtc; i++) {
 1287 
	for (i = 0; i < rdev->num_crtc; i++) {
1288 
		if (save->crtc_enabled) {
 1288 
		if (save->crtc_enabled[i]) {
1289 
			if (ASIC_IS_DCE6(rdev)) {
 1289 
			if (ASIC_IS_DCE6(rdev)) {
1290 
				tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
 1290 
				tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1291 
				tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
 1291 
				tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1292 
				WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 1292 
				WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);