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Rev 2004 Rev 2005
Line 317... Line 317...
317 
			break;
 317 
			break;
318 
		default:
 318 
		default:
319 
			break;
 319 
			break;
320 
		}
 320 
		}
321 
	}
 321 
	}
322 
//	if (rdev->irq.installed)
 322 
	if (rdev->irq.installed)
323 
//		evergreen_irq_set(rdev);
 323 
		evergreen_irq_set(rdev);
324 
}
 324 
}
Line 325... Line -...
325 
 
 - 
 
326 
#if 0
 - 
 
327 
 
 325 
 
328 
void evergreen_hpd_fini(struct radeon_device *rdev)
 326 
void evergreen_hpd_fini(struct radeon_device *rdev)
329 
{
 327 
{
330 
	struct drm_device *dev = rdev->ddev;
 328 
	struct drm_device *dev = rdev->ddev;
Line 361... Line 359...
361 
			break;
 359 
			break;
362 
		}
 360 
		}
363 
	}
 361 
	}
364 
}
 362 
}
Line 365... Line -...
365 
 
 - 
 
366 
#endif
 363 
 
Line 367... Line 364...
367 
/* watermark setup */
 364 
/* watermark setup */
368 
 
 365 
 
369 
static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 366 
static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
Line 976... Line 973...
976 
 
 973 
 
977 
void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
 974 
void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
978 
{
 975 
{
979 
	save->vga_control[0] = RREG32(D1VGA_CONTROL);
 976 
	save->vga_control[0] = RREG32(D1VGA_CONTROL);
980 
	save->vga_control[1] = RREG32(D2VGA_CONTROL);
 - 
 
981 
	save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
 - 
 
982 
	save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
 - 
 
983 
	save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
 - 
 
984 
	save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
 977 
	save->vga_control[1] = RREG32(D2VGA_CONTROL);
985 
	save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
 978 
	save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
986 
	save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
 979 
	save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
987 
	save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
 980 
	save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
988 
	save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 981 
	save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
- 
 
 982 
	if (rdev->num_crtc >= 4) {
- 
 
 983 
		save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
989 
	if (!(rdev->flags & RADEON_IS_IGP)) {
 984 
		save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
990 
	save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
 985 
	save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
- 
 
 986 
	save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
- 
 
 987 
	}
- 
 
 988 
	if (rdev->num_crtc >= 6) {
- 
 
 989 
		save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
991 
	save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
 990 
		save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
992 
	save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
 991 
	save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
993 
	save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 992 
	save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
Line 994... Line 993...
994 
	}
 993 
	}
995 
 
 994 
 
996 
	/* Stop all video */
 995 
	/* Stop all video */
997 
	WREG32(VGA_RENDER_CONTROL, 0);
 996 
	WREG32(VGA_RENDER_CONTROL, 0);
998 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
 997 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
999 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
 998 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1000 
	if (!(rdev->flags & RADEON_IS_IGP)) {
 999 
	if (rdev->num_crtc >= 4) {
- 
 
 1000 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
- 
 
 1001 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1001 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
 1002 
	}
1002 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
 1003 
	if (rdev->num_crtc >= 6) {
1003 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
 1004 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1004 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
 1005 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1005 
	}
 1006 
	}
1006 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 1007 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1007 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 1008 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1008 
	if (!(rdev->flags & RADEON_IS_IGP)) {
 1009 
	if (rdev->num_crtc >= 4) {
- 
 
 1010 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
- 
 
 1011 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1009 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 1012 
	}
1010 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 1013 
	if (rdev->num_crtc >= 6) {
1011 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
 1014 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1012 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
 1015 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1013 
	}
 1016 
	}
1014 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 1017 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1015 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 1018 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1016 
	if (!(rdev->flags & RADEON_IS_IGP)) {
 1019 
	if (rdev->num_crtc >= 4) {
- 
 
 1020 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
- 
 
 1021 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1017 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 1022 
	}
1018 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 1023 
	if (rdev->num_crtc >= 6) {
1019 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
 1024 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
Line 1020... Line 1025...
1020 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
 1025 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1021 
	}
 1026 
	}
- 
 
 1027 
 
1022 
 
 1028 
	WREG32(D1VGA_CONTROL, 0);
1023 
	WREG32(D1VGA_CONTROL, 0);
 1029 
	WREG32(D2VGA_CONTROL, 0);
- 
 
 1030 
	if (rdev->num_crtc >= 4) {
- 
 
 1031 
	WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1024 
	WREG32(D2VGA_CONTROL, 0);
 1032 
	WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1025 
	WREG32(EVERGREEN_D3VGA_CONTROL, 0);
 1033 
	}
1026 
	WREG32(EVERGREEN_D4VGA_CONTROL, 0);
 1034 
	if (rdev->num_crtc >= 6) {
- 
 
 1035 
	WREG32(EVERGREEN_D5VGA_CONTROL, 0);
Line 1027... Line 1036...
1027 
	WREG32(EVERGREEN_D5VGA_CONTROL, 0);
 1036 
	WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1028 
	WREG32(EVERGREEN_D6VGA_CONTROL, 0);
 1037 
	}
1029 
}
 1038 
}
1030 
 
 1039 
 
Line 1046... Line 1055...
1046 
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
 1055 
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1047 
	       (u32)rdev->mc.vram_start);
 1056 
	       (u32)rdev->mc.vram_start);
1048 
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
 1057 
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1049 
	       (u32)rdev->mc.vram_start);
 1058 
	       (u32)rdev->mc.vram_start);
Line 1050... Line 1059...
1050 
 
 1059 
 
1051 
	if (!(rdev->flags & RADEON_IS_IGP)) {
 1060 
	if (rdev->num_crtc >= 4) {
1052 
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
 1061 
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1053 
	       upper_32_bits(rdev->mc.vram_start));
 1062 
	       upper_32_bits(rdev->mc.vram_start));
1054 
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
 1063 
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1055 
	       upper_32_bits(rdev->mc.vram_start));
 1064 
	       upper_32_bits(rdev->mc.vram_start));
Line 1064... Line 1073...
1064 
	       upper_32_bits(rdev->mc.vram_start));
 1073 
	       upper_32_bits(rdev->mc.vram_start));
1065 
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
 1074 
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1066 
	       (u32)rdev->mc.vram_start);
 1075 
	       (u32)rdev->mc.vram_start);
1067 
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
 1076 
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1068 
	       (u32)rdev->mc.vram_start);
 1077 
	       (u32)rdev->mc.vram_start);
1069 
 
 1078 
	}
- 
 
 1079 
	if (rdev->num_crtc >= 6) {
1070 
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
 1080 
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1071 
	       upper_32_bits(rdev->mc.vram_start));
 1081 
	       upper_32_bits(rdev->mc.vram_start));
1072 
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
 1082 
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1073 
	       upper_32_bits(rdev->mc.vram_start));
 1083 
	       upper_32_bits(rdev->mc.vram_start));
1074 
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
 1084 
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
Line 1092... Line 1102...
1092 
	WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
 1102 
	WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1093 
	mdelay(1);
 1103 
	mdelay(1);
1094 
	/* Restore video state */
 1104 
	/* Restore video state */
1095 
	WREG32(D1VGA_CONTROL, save->vga_control[0]);
 1105 
	WREG32(D1VGA_CONTROL, save->vga_control[0]);
1096 
	WREG32(D2VGA_CONTROL, save->vga_control[1]);
 1106 
	WREG32(D2VGA_CONTROL, save->vga_control[1]);
- 
 
 1107 
	if (rdev->num_crtc >= 4) {
1097 
	WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
 1108 
	WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1098 
	WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
 1109 
	WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
- 
 
 1110 
	}
- 
 
 1111 
	if (rdev->num_crtc >= 6) {
1099 
	WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
 1112 
	WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1100 
	WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
 1113 
	WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
- 
 
 1114 
	}
1101 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
 1115 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1102 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
 1116 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1103 
	if (!(rdev->flags & RADEON_IS_IGP)) {
 1117 
	if (rdev->num_crtc >= 4) {
1104 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
 1118 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1105 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
 1119 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
- 
 
 1120 
	}
- 
 
 1121 
	if (rdev->num_crtc >= 6) {
1106 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
 1122 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1107 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
 1123 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1108 
	}
 1124 
	}
1109 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
 1125 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1110 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
 1126 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1111 
	if (!(rdev->flags & RADEON_IS_IGP)) {
 1127 
	if (rdev->num_crtc >= 4) {
1112 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
 1128 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1113 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
 1129 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
- 
 
 1130 
	}
- 
 
 1131 
	if (rdev->num_crtc >= 6) {
1114 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
 1132 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1115 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
 1133 
	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1116 
	}
 1134 
	}
1117 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 1135 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1118 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 1136 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1119 
	if (!(rdev->flags & RADEON_IS_IGP)) {
 1137 
	if (rdev->num_crtc >= 4) {
1120 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 1138 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1121 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 1139 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
- 
 
 1140 
	}
- 
 
 1141 
	if (rdev->num_crtc >= 6) {
1122 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
 1142 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1123 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
 1143 
	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1124 
	}
 1144 
	}
1125 
	WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
 1145 
	WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1126 
}
 1146 
}
Line 1968... Line 1988...
1968 
		case CHIP_HEMLOCK:
 1988 
		case CHIP_HEMLOCK:
1969 
		case CHIP_BARTS:
 1989 
		case CHIP_BARTS:
1970 
			gb_backend_map = 0x66442200;
 1990 
			gb_backend_map = 0x66442200;
1971 
			break;
 1991 
			break;
1972 
		case CHIP_JUNIPER:
 1992 
		case CHIP_JUNIPER:
1973 
			gb_backend_map = 0x00006420;
 1993 
			gb_backend_map = 0x00002200;
1974 
			break;
 1994 
			break;
1975 
		default:
 1995 
		default:
1976 
			gb_backend_map =
 1996 
			gb_backend_map =
1977 
				evergreen_get_tile_pipe_to_backend_map(rdev,
 1997 
				evergreen_get_tile_pipe_to_backend_map(rdev,
1978 
								       rdev->config.evergreen.max_tile_pipes,
 1998 
								       rdev->config.evergreen.max_tile_pipes,
Line 2408... Line 2428...
2408 
 
 2428 
 
2409 
	WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
 2429 
	WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2410 
	WREG32(GRBM_INT_CNTL, 0);
 2430 
	WREG32(GRBM_INT_CNTL, 0);
2411 
	WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 2431 
	WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2412 
	WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 2432 
	WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2413 
	if (!(rdev->flags & RADEON_IS_IGP)) {
 2433 
	if (rdev->num_crtc >= 4) {
2414 
	WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 2434 
	WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
- 
 
 2435 
	WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
- 
 
 2436 
	}
2415 
	WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 2437 
	if (rdev->num_crtc >= 6) {
2416 
	WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
 2438 
	WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2417 
	WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
 2439 
	WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
Line 2418... Line 2440...
2418 
	}
 2440 
	}
2419 
 
 2441 
 
2420 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 2442 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2421 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 2443 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2422 
	if (!(rdev->flags & RADEON_IS_IGP)) {
 2444 
	if (rdev->num_crtc >= 4) {
- 
 
 2445 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
- 
 
 2446 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2423 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 2447 
	}
2424 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 2448 
	if (rdev->num_crtc >= 6) {
2425 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
 2449 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
Line 2426... Line 2450...
2426 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
 2450 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
Line 2441... Line 2465...
2441 
	WREG32(DC_HPD5_INT_CONTROL, tmp);
 2465 
	WREG32(DC_HPD5_INT_CONTROL, tmp);
2442 
	tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
 2466 
	tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2443 
	WREG32(DC_HPD6_INT_CONTROL, tmp);
 2467 
	WREG32(DC_HPD6_INT_CONTROL, tmp);
Line 2444... Line 2468...
2444 
 
 2468 
 
- 
 
 2469 
}
- 
 
 2470 
 
- 
 
 2471 
int evergreen_irq_set(struct radeon_device *rdev)
- 
 
 2472 
{
- 
 
 2473 
	u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
- 
 
 2474 
	u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
- 
 
 2475 
	u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
- 
 
 2476 
	u32 grbm_int_cntl = 0;
- 
 
 2477 
	u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
- 
 
 2478 
 
- 
 
 2479 
	if (!rdev->irq.installed) {
- 
 
 2480 
		WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
- 
 
 2481 
		return -EINVAL;
- 
 
 2482 
	}
- 
 
 2483 
	/* don't enable anything if the ih is disabled */
- 
 
 2484 
	if (!rdev->ih.enabled) {
- 
 
 2485 
		r600_disable_interrupts(rdev);
- 
 
 2486 
		/* force the active interrupt state to all disabled */
- 
 
 2487 
		evergreen_disable_interrupt_state(rdev);
- 
 
 2488 
		return 0;
- 
 
 2489 
	}
- 
 
 2490 
 
- 
 
 2491 
	hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
- 
 
 2492 
	hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
- 
 
 2493 
	hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
- 
 
 2494 
	hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
- 
 
 2495 
	hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
- 
 
 2496 
	hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
- 
 
 2497 
 
- 
 
 2498 
	if (rdev->irq.sw_int) {
- 
 
 2499 
		DRM_DEBUG("evergreen_irq_set: sw int\n");
- 
 
 2500 
		cp_int_cntl |= RB_INT_ENABLE;
- 
 
 2501 
		cp_int_cntl |= TIME_STAMP_INT_ENABLE;
- 
 
 2502 
	}
- 
 
 2503 
	if (rdev->irq.crtc_vblank_int[0] ||
- 
 
 2504 
	    rdev->irq.pflip[0]) {
- 
 
 2505 
		DRM_DEBUG("evergreen_irq_set: vblank 0\n");
- 
 
 2506 
		crtc1 |= VBLANK_INT_MASK;
- 
 
 2507 
	}
- 
 
 2508 
	if (rdev->irq.crtc_vblank_int[1] ||
- 
 
 2509 
	    rdev->irq.pflip[1]) {
- 
 
 2510 
		DRM_DEBUG("evergreen_irq_set: vblank 1\n");
- 
 
 2511 
		crtc2 |= VBLANK_INT_MASK;
- 
 
 2512 
	}
- 
 
 2513 
	if (rdev->irq.crtc_vblank_int[2] ||
- 
 
 2514 
	    rdev->irq.pflip[2]) {
- 
 
 2515 
		DRM_DEBUG("evergreen_irq_set: vblank 2\n");
- 
 
 2516 
		crtc3 |= VBLANK_INT_MASK;
- 
 
 2517 
	}
- 
 
 2518 
	if (rdev->irq.crtc_vblank_int[3] ||
- 
 
 2519 
	    rdev->irq.pflip[3]) {
- 
 
 2520 
		DRM_DEBUG("evergreen_irq_set: vblank 3\n");
- 
 
 2521 
		crtc4 |= VBLANK_INT_MASK;
- 
 
 2522 
	}
- 
 
 2523 
	if (rdev->irq.crtc_vblank_int[4] ||
- 
 
 2524 
	    rdev->irq.pflip[4]) {
- 
 
 2525 
		DRM_DEBUG("evergreen_irq_set: vblank 4\n");
- 
 
 2526 
		crtc5 |= VBLANK_INT_MASK;
- 
 
 2527 
	}
- 
 
 2528 
	if (rdev->irq.crtc_vblank_int[5] ||
- 
 
 2529 
	    rdev->irq.pflip[5]) {
- 
 
 2530 
		DRM_DEBUG("evergreen_irq_set: vblank 5\n");
- 
 
 2531 
		crtc6 |= VBLANK_INT_MASK;
- 
 
 2532 
	}
- 
 
 2533 
	if (rdev->irq.hpd[0]) {
- 
 
 2534 
		DRM_DEBUG("evergreen_irq_set: hpd 1\n");
- 
 
 2535 
		hpd1 |= DC_HPDx_INT_EN;
- 
 
 2536 
	}
- 
 
 2537 
	if (rdev->irq.hpd[1]) {
- 
 
 2538 
		DRM_DEBUG("evergreen_irq_set: hpd 2\n");
- 
 
 2539 
		hpd2 |= DC_HPDx_INT_EN;
- 
 
 2540 
	}
- 
 
 2541 
	if (rdev->irq.hpd[2]) {
- 
 
 2542 
		DRM_DEBUG("evergreen_irq_set: hpd 3\n");
- 
 
 2543 
		hpd3 |= DC_HPDx_INT_EN;
- 
 
 2544 
	}
- 
 
 2545 
	if (rdev->irq.hpd[3]) {
- 
 
 2546 
		DRM_DEBUG("evergreen_irq_set: hpd 4\n");
- 
 
 2547 
		hpd4 |= DC_HPDx_INT_EN;
- 
 
 2548 
	}
- 
 
 2549 
	if (rdev->irq.hpd[4]) {
- 
 
 2550 
		DRM_DEBUG("evergreen_irq_set: hpd 5\n");
- 
 
 2551 
		hpd5 |= DC_HPDx_INT_EN;
- 
 
 2552 
	}
- 
 
 2553 
	if (rdev->irq.hpd[5]) {
- 
 
 2554 
		DRM_DEBUG("evergreen_irq_set: hpd 6\n");
- 
 
 2555 
		hpd6 |= DC_HPDx_INT_EN;
- 
 
 2556 
	}
- 
 
 2557 
	if (rdev->irq.gui_idle) {
- 
 
 2558 
		DRM_DEBUG("gui idle\n");
- 
 
 2559 
		grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
- 
 
 2560 
	}
- 
 
 2561 
 
- 
 
 2562 
	WREG32(CP_INT_CNTL, cp_int_cntl);
- 
 
 2563 
	WREG32(GRBM_INT_CNTL, grbm_int_cntl);
- 
 
 2564 
 
- 
 
 2565 
	WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
- 
 
 2566 
	WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
- 
 
 2567 
	if (rdev->num_crtc >= 4) {
- 
 
 2568 
		WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
- 
 
 2569 
		WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
- 
 
 2570 
	}
- 
 
 2571 
	if (rdev->num_crtc >= 6) {
- 
 
 2572 
		WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
- 
 
 2573 
		WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
- 
 
 2574 
	}
- 
 
 2575 
 
- 
 
 2576 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
- 
 
 2577 
	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
- 
 
 2578 
	if (rdev->num_crtc >= 4) {
- 
 
 2579 
		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
- 
 
 2580 
		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
- 
 
 2581 
	}
- 
 
 2582 
	if (rdev->num_crtc >= 6) {
- 
 
 2583 
		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
- 
 
 2584 
		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
- 
 
 2585 
	}
- 
 
 2586 
 
- 
 
 2587 
	WREG32(DC_HPD1_INT_CONTROL, hpd1);
- 
 
 2588 
	WREG32(DC_HPD2_INT_CONTROL, hpd2);
- 
 
 2589 
	WREG32(DC_HPD3_INT_CONTROL, hpd3);
- 
 
 2590 
	WREG32(DC_HPD4_INT_CONTROL, hpd4);
- 
 
 2591 
	WREG32(DC_HPD5_INT_CONTROL, hpd5);
- 
 
 2592 
	WREG32(DC_HPD6_INT_CONTROL, hpd6);
- 
 
 2593 
 
- 
 
 2594 
	return 0;
- 
 
 2595 
}
- 
 
 2596 
 
- 
 
 2597 
static inline void evergreen_irq_ack(struct radeon_device *rdev)
- 
 
 2598 
{
- 
 
 2599 
	u32 tmp;
- 
 
 2600 
 
- 
 
 2601 
	rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
- 
 
 2602 
	rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
- 
 
 2603 
	rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
- 
 
 2604 
	rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
- 
 
 2605 
	rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
- 
 
 2606 
	rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
- 
 
 2607 
	rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
- 
 
 2608 
	rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
- 
 
 2609 
	if (rdev->num_crtc >= 4) {
- 
 
 2610 
		rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
- 
 
 2611 
		rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
- 
 
 2612 
	}
- 
 
 2613 
	if (rdev->num_crtc >= 6) {
- 
 
 2614 
		rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
- 
 
 2615 
		rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
- 
 
 2616 
	}
- 
 
 2617 
 
- 
 
 2618 
	if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
- 
 
 2619 
		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- 
 
 2620 
	if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
- 
 
 2621 
		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- 
 
 2622 
	if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
- 
 
 2623 
		WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
- 
 
 2624 
	if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
- 
 
 2625 
		WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
- 
 
 2626 
	if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
- 
 
 2627 
		WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
- 
 
 2628 
	if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
- 
 
 2629 
		WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
- 
 
 2630 
 
- 
 
 2631 
	if (rdev->num_crtc >= 4) {
- 
 
 2632 
		if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
- 
 
 2633 
			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- 
 
 2634 
		if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
- 
 
 2635 
			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- 
 
 2636 
		if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
- 
 
 2637 
			WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
- 
 
 2638 
		if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
- 
 
 2639 
			WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
- 
 
 2640 
		if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
- 
 
 2641 
			WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
- 
 
 2642 
		if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
- 
 
 2643 
			WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
- 
 
 2644 
	}
- 
 
 2645 
 
- 
 
 2646 
	if (rdev->num_crtc >= 6) {
- 
 
 2647 
		if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
- 
 
 2648 
			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- 
 
 2649 
		if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
- 
 
 2650 
			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
- 
 
 2651 
		if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
- 
 
 2652 
			WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
- 
 
 2653 
		if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
- 
 
 2654 
			WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
- 
 
 2655 
		if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
- 
 
 2656 
			WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
- 
 
 2657 
		if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
- 
 
 2658 
			WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
- 
 
 2659 
	}
- 
 
 2660 
 
- 
 
 2661 
	if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
- 
 
 2662 
		tmp = RREG32(DC_HPD1_INT_CONTROL);
- 
 
 2663 
		tmp |= DC_HPDx_INT_ACK;
- 
 
 2664 
		WREG32(DC_HPD1_INT_CONTROL, tmp);
- 
 
 2665 
	}
- 
 
 2666 
	if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
- 
 
 2667 
		tmp = RREG32(DC_HPD2_INT_CONTROL);
- 
 
 2668 
		tmp |= DC_HPDx_INT_ACK;
- 
 
 2669 
		WREG32(DC_HPD2_INT_CONTROL, tmp);
- 
 
 2670 
	}
- 
 
 2671 
	if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
- 
 
 2672 
		tmp = RREG32(DC_HPD3_INT_CONTROL);
- 
 
 2673 
		tmp |= DC_HPDx_INT_ACK;
- 
 
 2674 
		WREG32(DC_HPD3_INT_CONTROL, tmp);
- 
 
 2675 
	}
- 
 
 2676 
	if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
- 
 
 2677 
		tmp = RREG32(DC_HPD4_INT_CONTROL);
- 
 
 2678 
		tmp |= DC_HPDx_INT_ACK;
- 
 
 2679 
		WREG32(DC_HPD4_INT_CONTROL, tmp);
- 
 
 2680 
	}
- 
 
 2681 
	if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
- 
 
 2682 
		tmp = RREG32(DC_HPD5_INT_CONTROL);
- 
 
 2683 
		tmp |= DC_HPDx_INT_ACK;
- 
 
 2684 
		WREG32(DC_HPD5_INT_CONTROL, tmp);
- 
 
 2685 
	}
- 
 
 2686 
	if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
- 
 
 2687 
		tmp = RREG32(DC_HPD5_INT_CONTROL);
- 
 
 2688 
		tmp |= DC_HPDx_INT_ACK;
- 
 
 2689 
		WREG32(DC_HPD6_INT_CONTROL, tmp);
- 
 
 2690 
	}
- 
 
 2691 
}
- 
 
 2692 
static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
- 
 
 2693 
{
- 
 
 2694 
	u32 wptr, tmp;
- 
 
 2695 
 
- 
 
 2696 
	if (rdev->wb.enabled)
- 
 
 2697 
		wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
- 
 
 2698 
	else
- 
 
 2699 
		wptr = RREG32(IH_RB_WPTR);
- 
 
 2700 
 
- 
 
 2701 
	if (wptr & RB_OVERFLOW) {
- 
 
 2702 
		/* When a ring buffer overflow happen start parsing interrupt
- 
 
 2703 
		 * from the last not overwritten vector (wptr + 16). Hopefully
- 
 
 2704 
		 * this should allow us to catchup.
- 
 
 2705 
		 */
- 
 
 2706 
		dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
- 
 
 2707 
			wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
- 
 
 2708 
		rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
- 
 
 2709 
		tmp = RREG32(IH_RB_CNTL);
- 
 
 2710 
		tmp |= IH_WPTR_OVERFLOW_CLEAR;
- 
 
 2711 
		WREG32(IH_RB_CNTL, tmp);
- 
 
 2712 
	}
- 
 
 2713 
	return (wptr & rdev->ih.ptr_mask);
- 
 
 2714 
}
- 
 
 2715 
 
- 
 
 2716 
int evergreen_irq_process(struct radeon_device *rdev)
- 
 
 2717 
{
- 
 
 2718 
	u32 wptr;
- 
 
 2719 
	u32 rptr;
- 
 
 2720 
	u32 src_id, src_data;
- 
 
 2721 
	u32 ring_index;
- 
 
 2722 
	unsigned long flags;
- 
 
 2723 
	bool queue_hotplug = false;
- 
 
 2724 
 
- 
 
 2725 
	if (!rdev->ih.enabled || rdev->shutdown)
- 
 
 2726 
		return IRQ_NONE;
- 
 
 2727 
 
- 
 
 2728 
	wptr = evergreen_get_ih_wptr(rdev);
- 
 
 2729 
	rptr = rdev->ih.rptr;
- 
 
 2730 
	DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
- 
 
 2731 
 
- 
 
 2732 
	spin_lock_irqsave(&rdev->ih.lock, flags);
- 
 
 2733 
	if (rptr == wptr) {
- 
 
 2734 
		spin_unlock_irqrestore(&rdev->ih.lock, flags);
- 
 
 2735 
		return IRQ_NONE;
- 
 
 2736 
	}
- 
 
 2737 
restart_ih:
- 
 
 2738 
	/* display interrupts */
- 
 
 2739 
	evergreen_irq_ack(rdev);
- 
 
 2740 
 
- 
 
 2741 
	rdev->ih.wptr = wptr;
- 
 
 2742 
	while (rptr != wptr) {
- 
 
 2743 
		/* wptr/rptr are in bytes! */
- 
 
 2744 
		ring_index = rptr / 4;
- 
 
 2745 
		src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
- 
 
 2746 
		src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
- 
 
 2747 
 
- 
 
 2748 
		switch (src_id) {
- 
 
 2749 
		case 1: /* D1 vblank/vline */
- 
 
 2750 
			switch (src_data) {
- 
 
 2751 
			case 0: /* D1 vblank */
- 
 
 2752 
				if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
- 
 
 2753 
					if (rdev->irq.crtc_vblank_int[0]) {
- 
 
 2754 
				//		drm_handle_vblank(rdev->ddev, 0);
- 
 
 2755 
						rdev->pm.vblank_sync = true;
- 
 
 2756 
				//		wake_up(&rdev->irq.vblank_queue);
- 
 
 2757 
					}
- 
 
 2758 
				//	if (rdev->irq.pflip[0])
- 
 
 2759 
				//		radeon_crtc_handle_flip(rdev, 0);
- 
 
 2760 
					rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
- 
 
 2761 
					DRM_DEBUG("IH: D1 vblank\n");
- 
 
 2762 
				}
- 
 
 2763 
				break;
- 
 
 2764 
			case 1: /* D1 vline */
- 
 
 2765 
				if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
- 
 
 2766 
					rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
- 
 
 2767 
					DRM_DEBUG("IH: D1 vline\n");
- 
 
 2768 
				}
- 
 
 2769 
				break;
- 
 
 2770 
			default:
- 
 
 2771 
				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
- 
 
 2772 
				break;
- 
 
 2773 
			}
- 
 
 2774 
			break;
- 
 
 2775 
		case 2: /* D2 vblank/vline */
- 
 
 2776 
			switch (src_data) {
- 
 
 2777 
			case 0: /* D2 vblank */
- 
 
 2778 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
- 
 
 2779 
					if (rdev->irq.crtc_vblank_int[1]) {
- 
 
 2780 
				//		drm_handle_vblank(rdev->ddev, 1);
- 
 
 2781 
						rdev->pm.vblank_sync = true;
- 
 
 2782 
				//		wake_up(&rdev->irq.vblank_queue);
- 
 
 2783 
					}
- 
 
 2784 
			//		if (rdev->irq.pflip[1])
- 
 
 2785 
			//			radeon_crtc_handle_flip(rdev, 1);
- 
 
 2786 
					rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
- 
 
 2787 
					DRM_DEBUG("IH: D2 vblank\n");
- 
 
 2788 
				}
- 
 
 2789 
				break;
- 
 
 2790 
			case 1: /* D2 vline */
- 
 
 2791 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
- 
 
 2792 
					rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
- 
 
 2793 
					DRM_DEBUG("IH: D2 vline\n");
- 
 
 2794 
				}
- 
 
 2795 
				break;
- 
 
 2796 
			default:
- 
 
 2797 
				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
- 
 
 2798 
				break;
- 
 
 2799 
			}
- 
 
 2800 
			break;
- 
 
 2801 
		case 3: /* D3 vblank/vline */
- 
 
 2802 
			switch (src_data) {
- 
 
 2803 
			case 0: /* D3 vblank */
- 
 
 2804 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
- 
 
 2805 
					if (rdev->irq.crtc_vblank_int[2]) {
- 
 
 2806 
				//		drm_handle_vblank(rdev->ddev, 2);
- 
 
 2807 
						rdev->pm.vblank_sync = true;
- 
 
 2808 
				//		wake_up(&rdev->irq.vblank_queue);
- 
 
 2809 
					}
- 
 
 2810 
				//	if (rdev->irq.pflip[2])
- 
 
 2811 
				//		radeon_crtc_handle_flip(rdev, 2);
- 
 
 2812 
					rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
- 
 
 2813 
					DRM_DEBUG("IH: D3 vblank\n");
- 
 
 2814 
				}
- 
 
 2815 
				break;
- 
 
 2816 
			case 1: /* D3 vline */
- 
 
 2817 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
- 
 
 2818 
					rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
- 
 
 2819 
					DRM_DEBUG("IH: D3 vline\n");
- 
 
 2820 
				}
- 
 
 2821 
				break;
- 
 
 2822 
			default:
- 
 
 2823 
				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
- 
 
 2824 
				break;
- 
 
 2825 
			}
- 
 
 2826 
			break;
- 
 
 2827 
		case 4: /* D4 vblank/vline */
- 
 
 2828 
			switch (src_data) {
- 
 
 2829 
			case 0: /* D4 vblank */
- 
 
 2830 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
- 
 
 2831 
					if (rdev->irq.crtc_vblank_int[3]) {
- 
 
 2832 
					//	drm_handle_vblank(rdev->ddev, 3);
- 
 
 2833 
						rdev->pm.vblank_sync = true;
- 
 
 2834 
					//	wake_up(&rdev->irq.vblank_queue);
- 
 
 2835 
					}
- 
 
 2836 
		//			if (rdev->irq.pflip[3])
- 
 
 2837 
		//				radeon_crtc_handle_flip(rdev, 3);
- 
 
 2838 
					rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
- 
 
 2839 
					DRM_DEBUG("IH: D4 vblank\n");
- 
 
 2840 
				}
- 
 
 2841 
				break;
- 
 
 2842 
			case 1: /* D4 vline */
- 
 
 2843 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
- 
 
 2844 
					rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
- 
 
 2845 
					DRM_DEBUG("IH: D4 vline\n");
- 
 
 2846 
				}
- 
 
 2847 
				break;
- 
 
 2848 
			default:
- 
 
 2849 
				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
- 
 
 2850 
				break;
- 
 
 2851 
			}
- 
 
 2852 
			break;
- 
 
 2853 
		case 5: /* D5 vblank/vline */
- 
 
 2854 
			switch (src_data) {
- 
 
 2855 
			case 0: /* D5 vblank */
- 
 
 2856 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
- 
 
 2857 
					if (rdev->irq.crtc_vblank_int[4]) {
- 
 
 2858 
//						drm_handle_vblank(rdev->ddev, 4);
- 
 
 2859 
						rdev->pm.vblank_sync = true;
- 
 
 2860 
//						wake_up(&rdev->irq.vblank_queue);
- 
 
 2861 
					}
- 
 
 2862 
//					if (rdev->irq.pflip[4])
- 
 
 2863 
//						radeon_crtc_handle_flip(rdev, 4);
- 
 
 2864 
					rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
- 
 
 2865 
					DRM_DEBUG("IH: D5 vblank\n");
- 
 
 2866 
				}
- 
 
 2867 
				break;
- 
 
 2868 
			case 1: /* D5 vline */
- 
 
 2869 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
- 
 
 2870 
					rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
- 
 
 2871 
					DRM_DEBUG("IH: D5 vline\n");
- 
 
 2872 
				}
- 
 
 2873 
				break;
- 
 
 2874 
			default:
- 
 
 2875 
				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
- 
 
 2876 
				break;
- 
 
 2877 
			}
- 
 
 2878 
			break;
- 
 
 2879 
		case 6: /* D6 vblank/vline */
- 
 
 2880 
			switch (src_data) {
- 
 
 2881 
			case 0: /* D6 vblank */
- 
 
 2882 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
- 
 
 2883 
					if (rdev->irq.crtc_vblank_int[5]) {
- 
 
 2884 
				//		drm_handle_vblank(rdev->ddev, 5);
- 
 
 2885 
						rdev->pm.vblank_sync = true;
- 
 
 2886 
				//		wake_up(&rdev->irq.vblank_queue);
- 
 
 2887 
					}
- 
 
 2888 
			//		if (rdev->irq.pflip[5])
- 
 
 2889 
			//			radeon_crtc_handle_flip(rdev, 5);
- 
 
 2890 
					rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
- 
 
 2891 
					DRM_DEBUG("IH: D6 vblank\n");
- 
 
 2892 
				}
- 
 
 2893 
				break;
- 
 
 2894 
			case 1: /* D6 vline */
- 
 
 2895 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
- 
 
 2896 
					rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
- 
 
 2897 
					DRM_DEBUG("IH: D6 vline\n");
- 
 
 2898 
				}
- 
 
 2899 
				break;
- 
 
 2900 
			default:
- 
 
 2901 
				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
- 
 
 2902 
				break;
- 
 
 2903 
			}
- 
 
 2904 
			break;
- 
 
 2905 
		case 42: /* HPD hotplug */
- 
 
 2906 
			switch (src_data) {
- 
 
 2907 
			case 0:
- 
 
 2908 
				if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
- 
 
 2909 
					rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
- 
 
 2910 
					queue_hotplug = true;
- 
 
 2911 
					DRM_DEBUG("IH: HPD1\n");
- 
 
 2912 
				}
- 
 
 2913 
				break;
- 
 
 2914 
			case 1:
- 
 
 2915 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
- 
 
 2916 
					rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
- 
 
 2917 
					queue_hotplug = true;
- 
 
 2918 
					DRM_DEBUG("IH: HPD2\n");
- 
 
 2919 
				}
- 
 
 2920 
				break;
- 
 
 2921 
			case 2:
- 
 
 2922 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
- 
 
 2923 
					rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
- 
 
 2924 
					queue_hotplug = true;
- 
 
 2925 
					DRM_DEBUG("IH: HPD3\n");
- 
 
 2926 
				}
- 
 
 2927 
				break;
- 
 
 2928 
			case 3:
- 
 
 2929 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
- 
 
 2930 
					rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
- 
 
 2931 
					queue_hotplug = true;
- 
 
 2932 
					DRM_DEBUG("IH: HPD4\n");
- 
 
 2933 
				}
- 
 
 2934 
				break;
- 
 
 2935 
			case 4:
- 
 
 2936 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
- 
 
 2937 
					rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
- 
 
 2938 
					queue_hotplug = true;
- 
 
 2939 
					DRM_DEBUG("IH: HPD5\n");
- 
 
 2940 
				}
- 
 
 2941 
				break;
- 
 
 2942 
			case 5:
- 
 
 2943 
				if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
- 
 
 2944 
					rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
- 
 
 2945 
					queue_hotplug = true;
- 
 
 2946 
					DRM_DEBUG("IH: HPD6\n");
- 
 
 2947 
				}
- 
 
 2948 
				break;
- 
 
 2949 
			default:
- 
 
 2950 
				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
- 
 
 2951 
				break;
- 
 
 2952 
			}
- 
 
 2953 
			break;
- 
 
 2954 
		case 176: /* CP_INT in ring buffer */
- 
 
 2955 
		case 177: /* CP_INT in IB1 */
- 
 
 2956 
		case 178: /* CP_INT in IB2 */
- 
 
 2957 
			DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
- 
 
 2958 
			radeon_fence_process(rdev);
- 
 
 2959 
			break;
- 
 
 2960 
		case 181: /* CP EOP event */
- 
 
 2961 
			DRM_DEBUG("IH: CP EOP\n");
- 
 
 2962 
			radeon_fence_process(rdev);
- 
 
 2963 
			break;
- 
 
 2964 
		case 233: /* GUI IDLE */
- 
 
 2965 
			DRM_DEBUG("IH: GUI idle\n");
- 
 
 2966 
			rdev->pm.gui_idle = true;
- 
 
 2967 
//			wake_up(&rdev->irq.idle_queue);
- 
 
 2968 
			break;
- 
 
 2969 
		default:
- 
 
 2970 
			DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
- 
 
 2971 
			break;
- 
 
 2972 
		}
- 
 
 2973 
 
- 
 
 2974 
		/* wptr/rptr are in bytes! */
- 
 
 2975 
		rptr += 16;
- 
 
 2976 
		rptr &= rdev->ih.ptr_mask;
- 
 
 2977 
	}
- 
 
 2978 
	/* make sure wptr hasn't changed while processing */
- 
 
 2979 
	wptr = evergreen_get_ih_wptr(rdev);
- 
 
 2980 
	if (wptr != rdev->ih.wptr)
- 
 
 2981 
		goto restart_ih;
- 
 
 2982 
//	if (queue_hotplug)
- 
 
 2983 
//		schedule_work(&rdev->hotplug_work);
- 
 
 2984 
	rdev->ih.rptr = rptr;
- 
 
 2985 
	WREG32(IH_RB_RPTR, rdev->ih.rptr);
- 
 
 2986 
	spin_unlock_irqrestore(&rdev->ih.lock, flags);
- 
 
 2987 
	return IRQ_HANDLED;
- 
 
 2988 
}
2445 
}
 2989 
 
2446 
static int evergreen_startup(struct radeon_device *rdev)
 2990 
static int evergreen_startup(struct radeon_device *rdev)
2447 
{
 2991 
{
Line 2448... Line 2992...
2448 
	int r;
 2992 
	int r;
Line 2481... Line 3025...
2481 
		r = evergreen_pcie_gart_enable(rdev);
 3025 
		r = evergreen_pcie_gart_enable(rdev);
2482 
		if (r)
 3026 
		if (r)
2483 
			return r;
 3027 
			return r;
2484 
	}
 3028 
	}
2485 
	evergreen_gpu_init(rdev);
 3029 
	evergreen_gpu_init(rdev);
2486 
#if 0
 3030 
 
2487 
	r = evergreen_blit_init(rdev);
 3031 
	r = evergreen_blit_init(rdev);
2488 
	if (r) {
 3032 
	if (r) {
2489 
		evergreen_blit_fini(rdev);
 3033 
		evergreen_blit_fini(rdev);
2490 
		rdev->asic->copy = NULL;
 3034 
		rdev->asic->copy = NULL;
2491 
		dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
 3035 
		dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
Line 2493... Line 3037...
2493 
 
 3037 
 
2494 
	/* allocate wb buffer */
 3038 
	/* allocate wb buffer */
2495 
	r = radeon_wb_init(rdev);
 3039 
	r = radeon_wb_init(rdev);
2496 
	if (r)
 3040 
	if (r)
2497 
		return r;
 - 
 
Line 2498... Line 3041...
2498 
#endif
 3041 
		return r;
- 
 
 3042 
 
- 
 
 3043 
	/* Enable IRQ */
- 
 
 3044 
	r = r600_irq_init(rdev);
- 
 
 3045 
	if (r) {
- 
 
 3046 
		DRM_ERROR("radeon: IH init failed (%d).\n", r);
- 
 
 3047 
//		radeon_irq_kms_fini(rdev);
- 
 
 3048 
		return r;
Line 2499... Line 3049...
2499 
 
 3049 
	}
2500 
	/* Enable IRQ */
 3050 
	evergreen_irq_set(rdev);
2501 
 
 3051 
 
2502 
    r = radeon_ring_init(rdev, rdev->cp.ring_size);
 3052 
    r = radeon_ring_init(rdev, rdev->cp.ring_size);
Line -... Line 3064...
- 
 
 3064 
 
- 
 
 3065 
 
- 
 
 3066 
 
- 
 
 3067 
 
- 
 
 3068 
 
Line -... Line 3069...
- 
 
 3069 
int evergreen_copy_blit(struct radeon_device *rdev,
- 
 
 3070 
			uint64_t src_offset, uint64_t dst_offset,
- 
 
 3071 
			unsigned num_pages, struct radeon_fence *fence)
- 
 
 3072 
{
- 
 
 3073 
	int r;
- 
 
 3074 
 
- 
 
 3075 
	mutex_lock(&rdev->r600_blit.mutex);
- 
 
 3076 
	rdev->r600_blit.vb_ib = NULL;
- 
 
 3077 
	r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
- 
 
 3078 
	if (r) {
- 
 
 3079 
		if (rdev->r600_blit.vb_ib)
- 
 
 3080 
			radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
- 
 
 3081 
		mutex_unlock(&rdev->r600_blit.mutex);
- 
 
 3082 
		return r;
Line 2514... Line 3083...
2514 
 
 3083 
	}
2515 
 
 3084 
	evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2516 
 
 3085 
	evergreen_blit_done_copy(rdev, fence);
2517 
 
 3086 
	mutex_unlock(&rdev->r600_blit.mutex);
Line 2564... Line 3133...
2564 
	/* Initialize surface registers */
 3133 
	/* Initialize surface registers */
2565 
	radeon_surface_init(rdev);
 3134 
	radeon_surface_init(rdev);
2566 
	/* Initialize clocks */
 3135 
	/* Initialize clocks */
2567 
	radeon_get_clock_info(rdev->ddev);
 3136 
	radeon_get_clock_info(rdev->ddev);
2568 
	/* Fence driver */
 3137 
	/* Fence driver */
- 
 
 3138 
	r = radeon_fence_driver_init(rdev);
- 
 
 3139 
	if (r)
- 
 
 3140 
		return r;
2569 
    /* initialize AGP */
 3141 
    /* initialize AGP */
2570 
	if (rdev->flags & RADEON_IS_AGP) {
 3142 
	if (rdev->flags & RADEON_IS_AGP) {
2571 
		r = radeon_agp_init(rdev);
 3143 
		r = radeon_agp_init(rdev);
2572 
		if (r)
 3144 
		if (r)
2573 
			radeon_agp_disable(rdev);
 3145 
			radeon_agp_disable(rdev);
Line 2579... Line 3151...
2579 
	/* Memory manager */
 3151 
	/* Memory manager */
2580 
	r = radeon_bo_init(rdev);
 3152 
	r = radeon_bo_init(rdev);
2581 
	if (r)
 3153 
	if (r)
2582 
		return r;
 3154 
		return r;
Line -... Line 3155...
- 
 
 3155 
 
- 
 
 3156 
	r = radeon_irq_kms_init(rdev);
- 
 
 3157 
	if (r)
Line 2583... Line 3158...
2583 
 
 3158 
		return r;
2584 
 
 3159 
 
Line 2585... Line 3160...
2585 
	rdev->cp.ring_obj = NULL;
 3160 
	rdev->cp.ring_obj = NULL;
2586 
	r600_ring_init(rdev, 1024 * 1024);
 3161 
	r600_ring_init(rdev, 1024 * 1024);
Line 2587... Line 3162...
2587 
 
 3162 
 
2588 
//   rdev->ih.ring_obj = NULL;
 3163 
	rdev->ih.ring_obj = NULL;
2589 
//   r600_ih_ring_init(rdev, 64 * 1024);
 3164 
	r600_ih_ring_init(rdev, 64 * 1024);
Line 2597... Line 3172...
2597 
	if (r) {
 3172 
	if (r) {
2598 
		dev_err(rdev->dev, "disabling GPU acceleration\n");
 3173 
		dev_err(rdev->dev, "disabling GPU acceleration\n");
2599 
		rdev->accel_working = false;
 3174 
		rdev->accel_working = false;
2600 
	}
 3175 
	}
2601 
	if (rdev->accel_working) {
 3176 
	if (rdev->accel_working) {
- 
 
 3177 
		r = radeon_ib_pool_init(rdev);
- 
 
 3178 
		if (r) {
- 
 
 3179 
			DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
- 
 
 3180 
			rdev->accel_working = false;
- 
 
 3181 
		}
- 
 
 3182 
		r = r600_ib_test(rdev);
- 
 
 3183 
		if (r) {
- 
 
 3184 
			DRM_ERROR("radeon: failed testing IB (%d).\n", r);
- 
 
 3185 
			rdev->accel_working = false;
- 
 
 3186 
		}
2602 
	}
 3187 
	}
2603 
	return 0;
 3188 
	return 0;
2604 
}
 3189 
}