Rev 6104 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 6104 | Rev 6321 | ||
|---|---|---|---|
| Line 299... | Line 299... | ||
| 299 | /* Express [24MHz / target pixel clock] as an exact rational |
299 | /* Express [24MHz / target pixel clock] as an exact rational |
| 300 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
300 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
| 301 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
301 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
| 302 | */ |
302 | */ |
| 303 | if (ASIC_IS_DCE8(rdev)) { |
303 | if (ASIC_IS_DCE8(rdev)) { |
| - | 304 | unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) & |
|
| - | 305 | DENTIST_DPREFCLK_WDIVIDER_MASK) >> |
|
| - | 306 | DENTIST_DPREFCLK_WDIVIDER_SHIFT; |
|
| - | 307 | div = radeon_audio_decode_dfs_div(div); |
|
| - | 308 | ||
| - | 309 | if (div) |
|
| - | 310 | clock = clock * 100 / div; |
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| - | 311 | ||
| 304 | WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000); |
312 | WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000); |
| 305 | WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); |
313 | WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); |
| 306 | } else { |
314 | } else { |
| 307 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); |
315 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); |
| 308 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); |
316 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); |