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#define		SOFT_RESET_TST				(1 << 21)

#define		SOFT_RESET_TST				(1 << 21)

#define		SOFT_RESET_REGBB		       	(1 << 22)

#define		SOFT_RESET_REGBB		       	(1 << 22)

#define		SOFT_RESET_ORB				(1 << 23)

#define		SOFT_RESET_ORB				(1 << 23)

#define		SOFT_RESET_VCE				(1 << 24)

#define		SOFT_RESET_VCE				(1 << 24)

#define VM_L2_CNTL					0x1400

#define VM_L2_CNTL					0x1400

#define		ENABLE_L2_CACHE					(1 << 0)

#define		ENABLE_L2_CACHE					(1 << 0)

#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)

#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)

#define		L2_CACHE_PTE_ENDIAN_SWAP_MODE(x)		((x) << 2)

#define		L2_CACHE_PTE_ENDIAN_SWAP_MODE(x)		((x) << 2)

#define CP_INT_CNTL_RING0                               0xC1A8

#define CP_INT_CNTL_RING0                               0xC1A8

#       define CNTX_BUSY_INT_ENABLE                     (1 << 19)

#       define CNTX_BUSY_INT_ENABLE                     (1 << 19)

#       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)

#       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)

#       define PRIV_INSTR_INT_ENABLE                    (1 << 22)

#       define PRIV_INSTR_INT_ENABLE                    (1 << 22)

#       define PRIV_REG_INT_ENABLE                      (1 << 23)

#       define PRIV_REG_INT_ENABLE                      (1 << 23)

#       define TIME_STAMP_INT_ENABLE                    (1 << 26)

#       define TIME_STAMP_INT_ENABLE                    (1 << 26)

#       define CP_RINGID2_INT_ENABLE                    (1 << 29)

#       define CP_RINGID2_INT_ENABLE                    (1 << 29)

#       define CP_RINGID1_INT_ENABLE                    (1 << 30)

#       define CP_RINGID1_INT_ENABLE                    (1 << 30)

#       define CP_RINGID0_INT_ENABLE                    (1 << 31)

#       define CP_RINGID0_INT_ENABLE                    (1 << 31)

#	define CG_DT(x)					((x) << 2)

#	define CG_DT(x)					((x) << 2)

#	define CG_DT_MASK				(0xf << 2)

#	define CG_DT_MASK				(0xf << 2)

#	define CLK_OD(x)				((x) << 6)

#	define CLK_OD(x)				((x) << 6)

#	define CLK_OD_MASK				(0x1f << 6)

#	define CLK_OD_MASK				(0x1f << 6)

/* UVD clocks */

/* UVD clocks */

#define CG_DCLK_CNTL			0xC050009C

#define CG_DCLK_CNTL			0xC050009C

#	define CLOCK_OFF_DELAY_MASK	(0xff << 4)

#	define CLOCK_OFF_DELAY_MASK	(0xff << 4)

#	define CLOCK_OFF_DELAY(x)	((x) << 4)

#	define CLOCK_OFF_DELAY(x)	((x) << 4)

#define VCE_UENC_REG_CLOCK_GATING	0x207c0

#define VCE_UENC_REG_CLOCK_GATING	0x207c0

#define VCE_SYS_INT_EN			0x21300

#define VCE_SYS_INT_EN			0x21300

#	define VCE_SYS_INT_TRAP_INTERRUPT_EN	(1 << 3)

#	define VCE_SYS_INT_TRAP_INTERRUPT_EN	(1 << 3)

#define VCE_LMI_CTRL2			0x21474

#define VCE_LMI_CTRL2			0x21474

#define VCE_LMI_CTRL			0x21498

#define VCE_LMI_CTRL			0x21498

#define VCE_LMI_VM_CTRL			0x214a0

#define VCE_LMI_VM_CTRL			0x214a0

#define VCE_LMI_SWAP_CNTL		0x214b4

#define VCE_LMI_SWAP_CNTL		0x214b4

#define VCE_LMI_SWAP_CNTL1		0x214b8

#define VCE_LMI_SWAP_CNTL1		0x214b8

#define VCE_CMD_FENCE		0x00000003

#define VCE_CMD_FENCE		0x00000003

#define VCE_CMD_TRAP		0x00000004

#define VCE_CMD_TRAP		0x00000004

#define VCE_CMD_IB_AUTO		0x00000005

#define VCE_CMD_IB_AUTO		0x00000005

#define VCE_CMD_SEMAPHORE	0x00000006

#define VCE_CMD_SEMAPHORE	0x00000006

#define ATC_VMID0_PASID_MAPPING					0x339Cu

#define	ATC_VMID_PASID_MAPPING_VALID				(1U << 31)

#define ATC_VMID_PASID_MAPPING_VALID_SHIFT		31

#define ATC_VM_APERTURE0_CNTL					0x3310u

#define ATC_VM_APERTURE0_CNTL					0x3310u

#define ATC_VM_APERTURE1_CNTL					0x3314u

#define ATC_VM_APERTURE1_CNTL					0x3314u

#define ATC_VM_APERTURE1_CNTL2					0x331Cu

#define ATC_VM_APERTURE1_CNTL2					0x331Cu

#define ATC_VM_APERTURE1_HIGH_ADDR				0x330Cu

#define ATC_VM_APERTURE1_HIGH_ADDR				0x330Cu

#define ATC_VM_APERTURE1_LOW_ADDR				0x3304u

#define ATC_VM_APERTURE1_LOW_ADDR				0x3304u