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Rev 5078 | Rev 5271 | ||
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Line 28... | Line 28... | ||
28 | #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 |
28 | #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 |
Line 29... | Line 29... | ||
29 | 29 | ||
30 | #define CIK_RB_BITMAP_WIDTH_PER_SH 2 |
30 | #define CIK_RB_BITMAP_WIDTH_PER_SH 2 |
Line -... | Line 31... | ||
- | 31 | #define HAWAII_RB_BITMAP_WIDTH_PER_SH 4 |
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- | 32 | ||
31 | #define HAWAII_RB_BITMAP_WIDTH_PER_SH 4 |
33 | #define RADEON_NUM_OF_VMIDS 8 |
32 | 34 | ||
33 | /* DIDT IND registers */ |
35 | /* DIDT IND registers */ |
34 | #define DIDT_SQ_CTRL0 0x0 |
36 | #define DIDT_SQ_CTRL0 0x0 |
35 | # define DIDT_CTRL_EN (1 << 0) |
37 | # define DIDT_CTRL_EN (1 << 0) |
Line 182... | Line 184... | ||
182 | #define DPM_EVENT_SRC(x) ((x) << 0) |
184 | #define DPM_EVENT_SRC(x) ((x) << 0) |
183 | #define DPM_EVENT_SRC_MASK (7 << 0) |
185 | #define DPM_EVENT_SRC_MASK (7 << 0) |
184 | #define DIG_THERM_DPM(x) ((x) << 14) |
186 | #define DIG_THERM_DPM(x) ((x) << 14) |
185 | #define DIG_THERM_DPM_MASK 0x003FC000 |
187 | #define DIG_THERM_DPM_MASK 0x003FC000 |
186 | #define DIG_THERM_DPM_SHIFT 14 |
188 | #define DIG_THERM_DPM_SHIFT 14 |
187 | - | ||
- | 189 | #define CG_THERMAL_STATUS 0xC0300008 |
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- | 190 | #define FDO_PWM_DUTY(x) ((x) << 9) |
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- | 191 | #define FDO_PWM_DUTY_MASK (0xff << 9) |
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- | 192 | #define FDO_PWM_DUTY_SHIFT 9 |
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188 | #define CG_THERMAL_INT 0xC030000C |
193 | #define CG_THERMAL_INT 0xC030000C |
189 | #define CI_DIG_THERM_INTH(x) ((x) << 8) |
194 | #define CI_DIG_THERM_INTH(x) ((x) << 8) |
190 | #define CI_DIG_THERM_INTH_MASK 0x0000FF00 |
195 | #define CI_DIG_THERM_INTH_MASK 0x0000FF00 |
191 | #define CI_DIG_THERM_INTH_SHIFT 8 |
196 | #define CI_DIG_THERM_INTH_SHIFT 8 |
192 | #define CI_DIG_THERM_INTL(x) ((x) << 16) |
197 | #define CI_DIG_THERM_INTL(x) ((x) << 16) |
193 | #define CI_DIG_THERM_INTL_MASK 0x00FF0000 |
198 | #define CI_DIG_THERM_INTL_MASK 0x00FF0000 |
194 | #define CI_DIG_THERM_INTL_SHIFT 16 |
199 | #define CI_DIG_THERM_INTL_SHIFT 16 |
195 | #define THERM_INT_MASK_HIGH (1 << 24) |
200 | #define THERM_INT_MASK_HIGH (1 << 24) |
196 | #define THERM_INT_MASK_LOW (1 << 25) |
201 | #define THERM_INT_MASK_LOW (1 << 25) |
197 | - | ||
- | 202 | #define CG_MULT_THERMAL_CTRL 0xC0300010 |
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- | 203 | #define TEMP_SEL(x) ((x) << 20) |
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- | 204 | #define TEMP_SEL_MASK (0xff << 20) |
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- | 205 | #define TEMP_SEL_SHIFT 20 |
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198 | #define CG_MULT_THERMAL_STATUS 0xC0300014 |
206 | #define CG_MULT_THERMAL_STATUS 0xC0300014 |
199 | #define ASIC_MAX_TEMP(x) ((x) << 0) |
207 | #define ASIC_MAX_TEMP(x) ((x) << 0) |
200 | #define ASIC_MAX_TEMP_MASK 0x000001ff |
208 | #define ASIC_MAX_TEMP_MASK 0x000001ff |
201 | #define ASIC_MAX_TEMP_SHIFT 0 |
209 | #define ASIC_MAX_TEMP_SHIFT 0 |
202 | #define CTF_TEMP(x) ((x) << 9) |
210 | #define CTF_TEMP(x) ((x) << 9) |
203 | #define CTF_TEMP_MASK 0x0003fe00 |
211 | #define CTF_TEMP_MASK 0x0003fe00 |
204 | #define CTF_TEMP_SHIFT 9 |
212 | #define CTF_TEMP_SHIFT 9 |
Line -... | Line 213... | ||
- | 213 | ||
- | 214 | #define CG_FDO_CTRL0 0xC0300064 |
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- | 215 | #define FDO_STATIC_DUTY(x) ((x) << 0) |
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- | 216 | #define FDO_STATIC_DUTY_MASK 0x000000FF |
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- | 217 | #define FDO_STATIC_DUTY_SHIFT 0 |
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- | 218 | #define CG_FDO_CTRL1 0xC0300068 |
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- | 219 | #define FMAX_DUTY100(x) ((x) << 0) |
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- | 220 | #define FMAX_DUTY100_MASK 0x000000FF |
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- | 221 | #define FMAX_DUTY100_SHIFT 0 |
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- | 222 | #define CG_FDO_CTRL2 0xC030006C |
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- | 223 | #define TMIN(x) ((x) << 0) |
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- | 224 | #define TMIN_MASK 0x000000FF |
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- | 225 | #define TMIN_SHIFT 0 |
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- | 226 | #define FDO_PWM_MODE(x) ((x) << 11) |
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- | 227 | #define FDO_PWM_MODE_MASK (7 << 11) |
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- | 228 | #define FDO_PWM_MODE_SHIFT 11 |
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- | 229 | #define TACH_PWM_RESP_RATE(x) ((x) << 25) |
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- | 230 | #define TACH_PWM_RESP_RATE_MASK (0x7f << 25) |
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- | 231 | #define TACH_PWM_RESP_RATE_SHIFT 25 |
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- | 232 | #define CG_TACH_CTRL 0xC0300070 |
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- | 233 | # define EDGE_PER_REV(x) ((x) << 0) |
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- | 234 | # define EDGE_PER_REV_MASK (0x7 << 0) |
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- | 235 | # define EDGE_PER_REV_SHIFT 0 |
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- | 236 | # define TARGET_PERIOD(x) ((x) << 3) |
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- | 237 | # define TARGET_PERIOD_MASK 0xfffffff8 |
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- | 238 | # define TARGET_PERIOD_SHIFT 3 |
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- | 239 | #define CG_TACH_STATUS 0xC0300074 |
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- | 240 | # define TACH_PERIOD(x) ((x) << 0) |
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- | 241 | # define TACH_PERIOD_MASK 0xffffffff |
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- | 242 | # define TACH_PERIOD_SHIFT 0 |
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205 | 243 | ||
206 | #define CG_ECLK_CNTL 0xC05000AC |
244 | #define CG_ECLK_CNTL 0xC05000AC |
207 | # define ECLK_DIVIDER_MASK 0x7f |
245 | # define ECLK_DIVIDER_MASK 0x7f |
208 | # define ECLK_DIR_CNTL_EN (1 << 8) |
246 | # define ECLK_DIR_CNTL_EN (1 << 8) |
209 | #define CG_ECLK_STATUS 0xC05000B0 |
247 | #define CG_ECLK_STATUS 0xC05000B0 |
Line 1135... | Line 1173... | ||
1135 | #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 |
1173 | #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 |
1136 | #define SH_MEM_ALIGNMENT_MODE_STRICT 2 |
1174 | #define SH_MEM_ALIGNMENT_MODE_STRICT 2 |
1137 | #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 |
1175 | #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 |
1138 | #define DEFAULT_MTYPE(x) ((x) << 4) |
1176 | #define DEFAULT_MTYPE(x) ((x) << 4) |
1139 | #define APE1_MTYPE(x) ((x) << 7) |
1177 | #define APE1_MTYPE(x) ((x) << 7) |
- | 1178 | /* valid for both DEFAULT_MTYPE and APE1_MTYPE */ |
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- | 1179 | #define MTYPE_CACHED 0 |
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- | 1180 | #define MTYPE_NONCACHED 3 |
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Line 1140... | Line 1181... | ||
1140 | 1181 | ||
Line 1141... | Line 1182... | ||
1141 | #define SX_DEBUG_1 0x9060 |
1182 | #define SX_DEBUG_1 0x9060 |
Line 1445... | Line 1486... | ||
1445 | #define CP_MQD_BASE_ADDR 0xC914 |
1486 | #define CP_MQD_BASE_ADDR 0xC914 |
1446 | #define CP_MQD_BASE_ADDR_HI 0xC918 |
1487 | #define CP_MQD_BASE_ADDR_HI 0xC918 |
1447 | #define CP_HQD_ACTIVE 0xC91C |
1488 | #define CP_HQD_ACTIVE 0xC91C |
1448 | #define CP_HQD_VMID 0xC920 |
1489 | #define CP_HQD_VMID 0xC920 |
Line -... | Line 1490... | ||
- | 1490 | ||
- | 1491 | #define CP_HQD_PERSISTENT_STATE 0xC924u |
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- | 1492 | #define DEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8) |
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- | 1493 | ||
- | 1494 | #define CP_HQD_PIPE_PRIORITY 0xC928u |
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- | 1495 | #define CP_HQD_QUEUE_PRIORITY 0xC92Cu |
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- | 1496 | #define CP_HQD_QUANTUM 0xC930u |
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- | 1497 | #define QUANTUM_EN 1U |
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- | 1498 | #define QUANTUM_SCALE_1MS (1U << 4) |
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- | 1499 | #define QUANTUM_DURATION(x) ((x) << 8) |
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1449 | 1500 | ||
1450 | #define CP_HQD_PQ_BASE 0xC934 |
1501 | #define CP_HQD_PQ_BASE 0xC934 |
1451 | #define CP_HQD_PQ_BASE_HI 0xC938 |
1502 | #define CP_HQD_PQ_BASE_HI 0xC938 |
1452 | #define CP_HQD_PQ_RPTR 0xC93C |
1503 | #define CP_HQD_PQ_RPTR 0xC93C |
1453 | #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 |
1504 | #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 |
Line 1472... | Line 1523... | ||
1472 | #define UNORD_DISPATCH (1 << 28) |
1523 | #define UNORD_DISPATCH (1 << 28) |
1473 | #define ROQ_PQ_IB_FLIP (1 << 29) |
1524 | #define ROQ_PQ_IB_FLIP (1 << 29) |
1474 | #define PRIV_STATE (1 << 30) |
1525 | #define PRIV_STATE (1 << 30) |
1475 | #define KMD_QUEUE (1 << 31) |
1526 | #define KMD_QUEUE (1 << 31) |
Line -... | Line 1527... | ||
- | 1527 | ||
- | 1528 | #define CP_HQD_IB_BASE_ADDR 0xC95Cu |
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- | 1529 | #define CP_HQD_IB_BASE_ADDR_HI 0xC960u |
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- | 1530 | #define CP_HQD_IB_RPTR 0xC964u |
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- | 1531 | #define CP_HQD_IB_CONTROL 0xC968u |
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- | 1532 | #define IB_ATC_EN (1U << 23) |
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- | 1533 | #define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20) |
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1476 | 1534 | ||
- | 1535 | #define CP_HQD_DEQUEUE_REQUEST 0xC974 |
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- | 1536 | #define DEQUEUE_REQUEST_DRAIN 1 |
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Line 1477... | Line 1537... | ||
1477 | #define CP_HQD_DEQUEUE_REQUEST 0xC974 |
1537 | #define DEQUEUE_REQUEST_RESET 2 |
1478 | 1538 | ||
1479 | #define CP_MQD_CONTROL 0xC99C |
1539 | #define CP_MQD_CONTROL 0xC99C |
Line -... | Line 1540... | ||
- | 1540 | #define MQD_VMID(x) ((x) << 0) |
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- | 1541 | #define MQD_VMID_MASK (0xf << 0) |
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- | 1542 | ||
- | 1543 | #define CP_HQD_SEMA_CMD 0xC97Cu |
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- | 1544 | #define CP_HQD_MSG_TYPE 0xC980u |
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- | 1545 | #define CP_HQD_ATOMIC0_PREOP_LO 0xC984u |
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- | 1546 | #define CP_HQD_ATOMIC0_PREOP_HI 0xC988u |
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- | 1547 | #define CP_HQD_ATOMIC1_PREOP_LO 0xC98Cu |
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- | 1548 | #define CP_HQD_ATOMIC1_PREOP_HI 0xC990u |
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- | 1549 | #define CP_HQD_HQ_SCHEDULER0 0xC994u |
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- | 1550 | #define CP_HQD_HQ_SCHEDULER1 0xC998u |
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1480 | #define MQD_VMID(x) ((x) << 0) |
1551 | |
Line 1481... | Line 1552... | ||
1481 | #define MQD_VMID_MASK (0xf << 0) |
1552 | #define SH_STATIC_MEM_CONFIG 0x9604u |
1482 | 1553 | ||
1483 | #define DB_RENDER_CONTROL 0x28000 |
1554 | #define DB_RENDER_CONTROL 0x28000 |
Line 2067... | Line 2138... | ||
2067 | #define VCE_CMD_FENCE 0x00000003 |
2138 | #define VCE_CMD_FENCE 0x00000003 |
2068 | #define VCE_CMD_TRAP 0x00000004 |
2139 | #define VCE_CMD_TRAP 0x00000004 |
2069 | #define VCE_CMD_IB_AUTO 0x00000005 |
2140 | #define VCE_CMD_IB_AUTO 0x00000005 |
2070 | #define VCE_CMD_SEMAPHORE 0x00000006 |
2141 | #define VCE_CMD_SEMAPHORE 0x00000006 |
Line -... | Line 2142... | ||
- | 2142 | ||
- | 2143 | #define ATC_VMID0_PASID_MAPPING 0x339Cu |
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- | 2144 | #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x3398u |
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- | 2145 | #define ATC_VMID_PASID_MAPPING_VALID (1U << 31) |
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- | 2146 | ||
- | 2147 | #define ATC_VM_APERTURE0_CNTL 0x3310u |
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- | 2148 | #define ATS_ACCESS_MODE_NEVER 0 |
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- | 2149 | #define ATS_ACCESS_MODE_ALWAYS 1 |
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- | 2150 | ||
- | 2151 | #define ATC_VM_APERTURE0_CNTL2 0x3318u |
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- | 2152 | #define ATC_VM_APERTURE0_HIGH_ADDR 0x3308u |
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- | 2153 | #define ATC_VM_APERTURE0_LOW_ADDR 0x3300u |
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- | 2154 | #define ATC_VM_APERTURE1_CNTL 0x3314u |
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- | 2155 | #define ATC_VM_APERTURE1_CNTL2 0x331Cu |
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- | 2156 | #define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu |
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- | 2157 | #define ATC_VM_APERTURE1_LOW_ADDR 0x3304u |
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2071 | 2158 |