Rev 5179 | Rev 6104 | Go to most recent revision | Only display areas with differences | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 5179 | Rev 5271 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
12 | * all copies or substantial portions of the Software. |
13 | * |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
21 | * |
22 | * Authors: Alex Deucher |
22 | * Authors: Alex Deucher |
23 | */ |
23 | */ |
24 | #include |
24 | #include |
25 | #include |
25 | #include |
26 | #include "radeon.h" |
26 | #include "radeon.h" |
27 | #include "radeon_ucode.h" |
27 | #include "radeon_ucode.h" |
28 | #include "radeon_asic.h" |
28 | #include "radeon_asic.h" |
29 | #include "radeon_trace.h" |
29 | #include "radeon_trace.h" |
30 | #include "cikd.h" |
30 | #include "cikd.h" |
31 | 31 | ||
32 | /* sdma */ |
32 | /* sdma */ |
33 | #define CIK_SDMA_UCODE_SIZE 1050 |
33 | #define CIK_SDMA_UCODE_SIZE 1050 |
34 | #define CIK_SDMA_UCODE_VERSION 64 |
34 | #define CIK_SDMA_UCODE_VERSION 64 |
35 | 35 | ||
36 | u32 cik_gpu_check_soft_reset(struct radeon_device *rdev); |
36 | u32 cik_gpu_check_soft_reset(struct radeon_device *rdev); |
37 | 37 | ||
38 | /* |
38 | /* |
39 | * sDMA - System DMA |
39 | * sDMA - System DMA |
40 | * Starting with CIK, the GPU has new asynchronous |
40 | * Starting with CIK, the GPU has new asynchronous |
41 | * DMA engines. These engines are used for compute |
41 | * DMA engines. These engines are used for compute |
42 | * and gfx. There are two DMA engines (SDMA0, SDMA1) |
42 | * and gfx. There are two DMA engines (SDMA0, SDMA1) |
43 | * and each one supports 1 ring buffer used for gfx |
43 | * and each one supports 1 ring buffer used for gfx |
44 | * and 2 queues used for compute. |
44 | * and 2 queues used for compute. |
45 | * |
45 | * |
46 | * The programming model is very similar to the CP |
46 | * The programming model is very similar to the CP |
47 | * (ring buffer, IBs, etc.), but sDMA has it's own |
47 | * (ring buffer, IBs, etc.), but sDMA has it's own |
48 | * packet format that is different from the PM4 format |
48 | * packet format that is different from the PM4 format |
49 | * used by the CP. sDMA supports copying data, writing |
49 | * used by the CP. sDMA supports copying data, writing |
50 | * embedded data, solid fills, and a number of other |
50 | * embedded data, solid fills, and a number of other |
51 | * things. It also has support for tiling/detiling of |
51 | * things. It also has support for tiling/detiling of |
52 | * buffers. |
52 | * buffers. |
53 | */ |
53 | */ |
54 | 54 | ||
55 | /** |
55 | /** |
56 | * cik_sdma_get_rptr - get the current read pointer |
56 | * cik_sdma_get_rptr - get the current read pointer |
57 | * |
57 | * |
58 | * @rdev: radeon_device pointer |
58 | * @rdev: radeon_device pointer |
59 | * @ring: radeon ring pointer |
59 | * @ring: radeon ring pointer |
60 | * |
60 | * |
61 | * Get the current rptr from the hardware (CIK+). |
61 | * Get the current rptr from the hardware (CIK+). |
62 | */ |
62 | */ |
63 | uint32_t cik_sdma_get_rptr(struct radeon_device *rdev, |
63 | uint32_t cik_sdma_get_rptr(struct radeon_device *rdev, |
64 | struct radeon_ring *ring) |
64 | struct radeon_ring *ring) |
65 | { |
65 | { |
66 | u32 rptr, reg; |
66 | u32 rptr, reg; |
67 | 67 | ||
68 | if (rdev->wb.enabled) { |
68 | if (rdev->wb.enabled) { |
69 | rptr = rdev->wb.wb[ring->rptr_offs/4]; |
69 | rptr = rdev->wb.wb[ring->rptr_offs/4]; |
70 | } else { |
70 | } else { |
71 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
71 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
72 | reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; |
72 | reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; |
73 | else |
73 | else |
74 | reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; |
74 | reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; |
75 | 75 | ||
76 | rptr = RREG32(reg); |
76 | rptr = RREG32(reg); |
77 | } |
77 | } |
78 | 78 | ||
79 | return (rptr & 0x3fffc) >> 2; |
79 | return (rptr & 0x3fffc) >> 2; |
80 | } |
80 | } |
81 | 81 | ||
82 | /** |
82 | /** |
83 | * cik_sdma_get_wptr - get the current write pointer |
83 | * cik_sdma_get_wptr - get the current write pointer |
84 | * |
84 | * |
85 | * @rdev: radeon_device pointer |
85 | * @rdev: radeon_device pointer |
86 | * @ring: radeon ring pointer |
86 | * @ring: radeon ring pointer |
87 | * |
87 | * |
88 | * Get the current wptr from the hardware (CIK+). |
88 | * Get the current wptr from the hardware (CIK+). |
89 | */ |
89 | */ |
90 | uint32_t cik_sdma_get_wptr(struct radeon_device *rdev, |
90 | uint32_t cik_sdma_get_wptr(struct radeon_device *rdev, |
91 | struct radeon_ring *ring) |
91 | struct radeon_ring *ring) |
92 | { |
92 | { |
93 | u32 reg; |
93 | u32 reg; |
94 | 94 | ||
95 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
95 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
96 | reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; |
96 | reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; |
97 | else |
97 | else |
98 | reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; |
98 | reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; |
99 | 99 | ||
100 | return (RREG32(reg) & 0x3fffc) >> 2; |
100 | return (RREG32(reg) & 0x3fffc) >> 2; |
101 | } |
101 | } |
102 | 102 | ||
103 | /** |
103 | /** |
104 | * cik_sdma_set_wptr - commit the write pointer |
104 | * cik_sdma_set_wptr - commit the write pointer |
105 | * |
105 | * |
106 | * @rdev: radeon_device pointer |
106 | * @rdev: radeon_device pointer |
107 | * @ring: radeon ring pointer |
107 | * @ring: radeon ring pointer |
108 | * |
108 | * |
109 | * Write the wptr back to the hardware (CIK+). |
109 | * Write the wptr back to the hardware (CIK+). |
110 | */ |
110 | */ |
111 | void cik_sdma_set_wptr(struct radeon_device *rdev, |
111 | void cik_sdma_set_wptr(struct radeon_device *rdev, |
112 | struct radeon_ring *ring) |
112 | struct radeon_ring *ring) |
113 | { |
113 | { |
114 | u32 reg; |
114 | u32 reg; |
115 | 115 | ||
116 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
116 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
117 | reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; |
117 | reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; |
118 | else |
118 | else |
119 | reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; |
119 | reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; |
120 | 120 | ||
121 | WREG32(reg, (ring->wptr << 2) & 0x3fffc); |
121 | WREG32(reg, (ring->wptr << 2) & 0x3fffc); |
122 | (void)RREG32(reg); |
122 | (void)RREG32(reg); |
123 | } |
123 | } |
124 | 124 | ||
125 | /** |
125 | /** |
126 | * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine |
126 | * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine |
127 | * |
127 | * |
128 | * @rdev: radeon_device pointer |
128 | * @rdev: radeon_device pointer |
129 | * @ib: IB object to schedule |
129 | * @ib: IB object to schedule |
130 | * |
130 | * |
131 | * Schedule an IB in the DMA ring (CIK). |
131 | * Schedule an IB in the DMA ring (CIK). |
132 | */ |
132 | */ |
133 | void cik_sdma_ring_ib_execute(struct radeon_device *rdev, |
133 | void cik_sdma_ring_ib_execute(struct radeon_device *rdev, |
134 | struct radeon_ib *ib) |
134 | struct radeon_ib *ib) |
135 | { |
135 | { |
136 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
136 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
137 | u32 extra_bits = (ib->vm ? ib->vm->id : 0) & 0xf; |
137 | u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf; |
138 | 138 | ||
139 | if (rdev->wb.enabled) { |
139 | if (rdev->wb.enabled) { |
140 | u32 next_rptr = ring->wptr + 5; |
140 | u32 next_rptr = ring->wptr + 5; |
141 | while ((next_rptr & 7) != 4) |
141 | while ((next_rptr & 7) != 4) |
142 | next_rptr++; |
142 | next_rptr++; |
143 | next_rptr += 4; |
143 | next_rptr += 4; |
144 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); |
144 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); |
145 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); |
145 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); |
146 | radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); |
146 | radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); |
147 | radeon_ring_write(ring, 1); /* number of DWs to follow */ |
147 | radeon_ring_write(ring, 1); /* number of DWs to follow */ |
148 | radeon_ring_write(ring, next_rptr); |
148 | radeon_ring_write(ring, next_rptr); |
149 | } |
149 | } |
150 | 150 | ||
151 | /* IB packet must end on a 8 DW boundary */ |
151 | /* IB packet must end on a 8 DW boundary */ |
152 | while ((ring->wptr & 7) != 4) |
152 | while ((ring->wptr & 7) != 4) |
153 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); |
153 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); |
154 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); |
154 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); |
155 | radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ |
155 | radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ |
156 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); |
156 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); |
157 | radeon_ring_write(ring, ib->length_dw); |
157 | radeon_ring_write(ring, ib->length_dw); |
158 | 158 | ||
159 | } |
159 | } |
160 | 160 | ||
161 | /** |
161 | /** |
162 | * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring |
162 | * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring |
163 | * |
163 | * |
164 | * @rdev: radeon_device pointer |
164 | * @rdev: radeon_device pointer |
165 | * @ridx: radeon ring index |
165 | * @ridx: radeon ring index |
166 | * |
166 | * |
167 | * Emit an hdp flush packet on the requested DMA ring. |
167 | * Emit an hdp flush packet on the requested DMA ring. |
168 | */ |
168 | */ |
169 | static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev, |
169 | static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev, |
170 | int ridx) |
170 | int ridx) |
171 | { |
171 | { |
172 | struct radeon_ring *ring = &rdev->ring[ridx]; |
172 | struct radeon_ring *ring = &rdev->ring[ridx]; |
173 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | |
173 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | |
174 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ |
174 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ |
175 | u32 ref_and_mask; |
175 | u32 ref_and_mask; |
176 | 176 | ||
177 | if (ridx == R600_RING_TYPE_DMA_INDEX) |
177 | if (ridx == R600_RING_TYPE_DMA_INDEX) |
178 | ref_and_mask = SDMA0; |
178 | ref_and_mask = SDMA0; |
179 | else |
179 | else |
180 | ref_and_mask = SDMA1; |
180 | ref_and_mask = SDMA1; |
181 | 181 | ||
182 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); |
182 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); |
183 | radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); |
183 | radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); |
184 | radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); |
184 | radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); |
185 | radeon_ring_write(ring, ref_and_mask); /* reference */ |
185 | radeon_ring_write(ring, ref_and_mask); /* reference */ |
186 | radeon_ring_write(ring, ref_and_mask); /* mask */ |
186 | radeon_ring_write(ring, ref_and_mask); /* mask */ |
187 | radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ |
187 | radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ |
188 | } |
188 | } |
189 | 189 | ||
190 | /** |
190 | /** |
191 | * cik_sdma_fence_ring_emit - emit a fence on the DMA ring |
191 | * cik_sdma_fence_ring_emit - emit a fence on the DMA ring |
192 | * |
192 | * |
193 | * @rdev: radeon_device pointer |
193 | * @rdev: radeon_device pointer |
194 | * @fence: radeon fence object |
194 | * @fence: radeon fence object |
195 | * |
195 | * |
196 | * Add a DMA fence packet to the ring to write |
196 | * Add a DMA fence packet to the ring to write |
197 | * the fence seq number and DMA trap packet to generate |
197 | * the fence seq number and DMA trap packet to generate |
198 | * an interrupt if needed (CIK). |
198 | * an interrupt if needed (CIK). |
199 | */ |
199 | */ |
200 | void cik_sdma_fence_ring_emit(struct radeon_device *rdev, |
200 | void cik_sdma_fence_ring_emit(struct radeon_device *rdev, |
201 | struct radeon_fence *fence) |
201 | struct radeon_fence *fence) |
202 | { |
202 | { |
203 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
203 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
204 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
204 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
205 | 205 | ||
206 | /* write the fence */ |
206 | /* write the fence */ |
207 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); |
207 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); |
208 | radeon_ring_write(ring, lower_32_bits(addr)); |
208 | radeon_ring_write(ring, lower_32_bits(addr)); |
209 | radeon_ring_write(ring, upper_32_bits(addr)); |
209 | radeon_ring_write(ring, upper_32_bits(addr)); |
210 | radeon_ring_write(ring, fence->seq); |
210 | radeon_ring_write(ring, fence->seq); |
211 | /* generate an interrupt */ |
211 | /* generate an interrupt */ |
212 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); |
212 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); |
213 | /* flush HDP */ |
213 | /* flush HDP */ |
214 | cik_sdma_hdp_flush_ring_emit(rdev, fence->ring); |
214 | cik_sdma_hdp_flush_ring_emit(rdev, fence->ring); |
215 | } |
215 | } |
216 | 216 | ||
217 | /** |
217 | /** |
218 | * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring |
218 | * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring |
219 | * |
219 | * |
220 | * @rdev: radeon_device pointer |
220 | * @rdev: radeon_device pointer |
221 | * @ring: radeon_ring structure holding ring information |
221 | * @ring: radeon_ring structure holding ring information |
222 | * @semaphore: radeon semaphore object |
222 | * @semaphore: radeon semaphore object |
223 | * @emit_wait: wait or signal semaphore |
223 | * @emit_wait: wait or signal semaphore |
224 | * |
224 | * |
225 | * Add a DMA semaphore packet to the ring wait on or signal |
225 | * Add a DMA semaphore packet to the ring wait on or signal |
226 | * other rings (CIK). |
226 | * other rings (CIK). |
227 | */ |
227 | */ |
228 | bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, |
228 | bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, |
229 | struct radeon_ring *ring, |
229 | struct radeon_ring *ring, |
230 | struct radeon_semaphore *semaphore, |
230 | struct radeon_semaphore *semaphore, |
231 | bool emit_wait) |
231 | bool emit_wait) |
232 | { |
232 | { |
233 | u64 addr = semaphore->gpu_addr; |
233 | u64 addr = semaphore->gpu_addr; |
234 | u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S; |
234 | u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S; |
235 | 235 | ||
236 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); |
236 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); |
237 | radeon_ring_write(ring, addr & 0xfffffff8); |
237 | radeon_ring_write(ring, addr & 0xfffffff8); |
238 | radeon_ring_write(ring, upper_32_bits(addr)); |
238 | radeon_ring_write(ring, upper_32_bits(addr)); |
239 | 239 | ||
240 | return true; |
240 | return true; |
241 | } |
241 | } |
242 | 242 | ||
243 | /** |
243 | /** |
244 | * cik_sdma_gfx_stop - stop the gfx async dma engines |
244 | * cik_sdma_gfx_stop - stop the gfx async dma engines |
245 | * |
245 | * |
246 | * @rdev: radeon_device pointer |
246 | * @rdev: radeon_device pointer |
247 | * |
247 | * |
248 | * Stop the gfx async dma ring buffers (CIK). |
248 | * Stop the gfx async dma ring buffers (CIK). |
249 | */ |
249 | */ |
250 | static void cik_sdma_gfx_stop(struct radeon_device *rdev) |
250 | static void cik_sdma_gfx_stop(struct radeon_device *rdev) |
251 | { |
251 | { |
252 | u32 rb_cntl, reg_offset; |
252 | u32 rb_cntl, reg_offset; |
253 | int i; |
253 | int i; |
254 | 254 | ||
255 | if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || |
255 | if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || |
256 | (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) |
256 | (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) |
257 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
257 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
258 | 258 | ||
259 | for (i = 0; i < 2; i++) { |
259 | for (i = 0; i < 2; i++) { |
260 | if (i == 0) |
260 | if (i == 0) |
261 | reg_offset = SDMA0_REGISTER_OFFSET; |
261 | reg_offset = SDMA0_REGISTER_OFFSET; |
262 | else |
262 | else |
263 | reg_offset = SDMA1_REGISTER_OFFSET; |
263 | reg_offset = SDMA1_REGISTER_OFFSET; |
264 | rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); |
264 | rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); |
265 | rb_cntl &= ~SDMA_RB_ENABLE; |
265 | rb_cntl &= ~SDMA_RB_ENABLE; |
266 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); |
266 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); |
267 | WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); |
267 | WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); |
268 | } |
268 | } |
269 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; |
269 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; |
270 | rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false; |
270 | rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false; |
271 | } |
271 | } |
272 | 272 | ||
273 | /** |
273 | /** |
274 | * cik_sdma_rlc_stop - stop the compute async dma engines |
274 | * cik_sdma_rlc_stop - stop the compute async dma engines |
275 | * |
275 | * |
276 | * @rdev: radeon_device pointer |
276 | * @rdev: radeon_device pointer |
277 | * |
277 | * |
278 | * Stop the compute async dma queues (CIK). |
278 | * Stop the compute async dma queues (CIK). |
279 | */ |
279 | */ |
280 | static void cik_sdma_rlc_stop(struct radeon_device *rdev) |
280 | static void cik_sdma_rlc_stop(struct radeon_device *rdev) |
281 | { |
281 | { |
282 | /* XXX todo */ |
282 | /* XXX todo */ |
283 | } |
283 | } |
284 | 284 | ||
285 | /** |
285 | /** |
286 | * cik_sdma_enable - stop the async dma engines |
286 | * cik_sdma_enable - stop the async dma engines |
287 | * |
287 | * |
288 | * @rdev: radeon_device pointer |
288 | * @rdev: radeon_device pointer |
289 | * @enable: enable/disable the DMA MEs. |
289 | * @enable: enable/disable the DMA MEs. |
290 | * |
290 | * |
291 | * Halt or unhalt the async dma engines (CIK). |
291 | * Halt or unhalt the async dma engines (CIK). |
292 | */ |
292 | */ |
293 | void cik_sdma_enable(struct radeon_device *rdev, bool enable) |
293 | void cik_sdma_enable(struct radeon_device *rdev, bool enable) |
294 | { |
294 | { |
295 | u32 me_cntl, reg_offset; |
295 | u32 me_cntl, reg_offset; |
296 | int i; |
296 | int i; |
297 | 297 | ||
298 | if (enable == false) { |
298 | if (enable == false) { |
299 | cik_sdma_gfx_stop(rdev); |
299 | cik_sdma_gfx_stop(rdev); |
300 | cik_sdma_rlc_stop(rdev); |
300 | cik_sdma_rlc_stop(rdev); |
301 | } |
301 | } |
302 | 302 | ||
303 | for (i = 0; i < 2; i++) { |
303 | for (i = 0; i < 2; i++) { |
304 | if (i == 0) |
304 | if (i == 0) |
305 | reg_offset = SDMA0_REGISTER_OFFSET; |
305 | reg_offset = SDMA0_REGISTER_OFFSET; |
306 | else |
306 | else |
307 | reg_offset = SDMA1_REGISTER_OFFSET; |
307 | reg_offset = SDMA1_REGISTER_OFFSET; |
308 | me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); |
308 | me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); |
309 | if (enable) |
309 | if (enable) |
310 | me_cntl &= ~SDMA_HALT; |
310 | me_cntl &= ~SDMA_HALT; |
311 | else |
311 | else |
312 | me_cntl |= SDMA_HALT; |
312 | me_cntl |= SDMA_HALT; |
313 | WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); |
313 | WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); |
314 | } |
314 | } |
315 | } |
315 | } |
316 | 316 | ||
317 | /** |
317 | /** |
318 | * cik_sdma_gfx_resume - setup and start the async dma engines |
318 | * cik_sdma_gfx_resume - setup and start the async dma engines |
319 | * |
319 | * |
320 | * @rdev: radeon_device pointer |
320 | * @rdev: radeon_device pointer |
321 | * |
321 | * |
322 | * Set up the gfx DMA ring buffers and enable them (CIK). |
322 | * Set up the gfx DMA ring buffers and enable them (CIK). |
323 | * Returns 0 for success, error for failure. |
323 | * Returns 0 for success, error for failure. |
324 | */ |
324 | */ |
325 | static int cik_sdma_gfx_resume(struct radeon_device *rdev) |
325 | static int cik_sdma_gfx_resume(struct radeon_device *rdev) |
326 | { |
326 | { |
327 | struct radeon_ring *ring; |
327 | struct radeon_ring *ring; |
328 | u32 rb_cntl, ib_cntl; |
328 | u32 rb_cntl, ib_cntl; |
329 | u32 rb_bufsz; |
329 | u32 rb_bufsz; |
330 | u32 reg_offset, wb_offset; |
330 | u32 reg_offset, wb_offset; |
331 | int i, r; |
331 | int i, r; |
332 | 332 | ||
333 | for (i = 0; i < 2; i++) { |
333 | for (i = 0; i < 2; i++) { |
334 | if (i == 0) { |
334 | if (i == 0) { |
335 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
335 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
336 | reg_offset = SDMA0_REGISTER_OFFSET; |
336 | reg_offset = SDMA0_REGISTER_OFFSET; |
337 | wb_offset = R600_WB_DMA_RPTR_OFFSET; |
337 | wb_offset = R600_WB_DMA_RPTR_OFFSET; |
338 | } else { |
338 | } else { |
339 | ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; |
339 | ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; |
340 | reg_offset = SDMA1_REGISTER_OFFSET; |
340 | reg_offset = SDMA1_REGISTER_OFFSET; |
341 | wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET; |
341 | wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET; |
342 | } |
342 | } |
343 | 343 | ||
344 | WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); |
344 | WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); |
345 | WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); |
345 | WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); |
346 | 346 | ||
347 | /* Set ring buffer size in dwords */ |
347 | /* Set ring buffer size in dwords */ |
348 | rb_bufsz = order_base_2(ring->ring_size / 4); |
348 | rb_bufsz = order_base_2(ring->ring_size / 4); |
349 | rb_cntl = rb_bufsz << 1; |
349 | rb_cntl = rb_bufsz << 1; |
350 | #ifdef __BIG_ENDIAN |
350 | #ifdef __BIG_ENDIAN |
351 | rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; |
351 | rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; |
352 | #endif |
352 | #endif |
353 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); |
353 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); |
354 | 354 | ||
355 | /* Initialize the ring buffer's read and write pointers */ |
355 | /* Initialize the ring buffer's read and write pointers */ |
356 | WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0); |
356 | WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0); |
357 | WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0); |
357 | WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0); |
358 | 358 | ||
359 | /* set the wb address whether it's enabled or not */ |
359 | /* set the wb address whether it's enabled or not */ |
360 | WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset, |
360 | WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset, |
361 | upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); |
361 | upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); |
362 | WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset, |
362 | WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset, |
363 | ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); |
363 | ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); |
364 | 364 | ||
365 | if (rdev->wb.enabled) |
365 | if (rdev->wb.enabled) |
366 | rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; |
366 | rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; |
367 | 367 | ||
368 | WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); |
368 | WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); |
369 | WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); |
369 | WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); |
370 | 370 | ||
371 | ring->wptr = 0; |
371 | ring->wptr = 0; |
372 | WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); |
372 | WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); |
373 | 373 | ||
374 | /* enable DMA RB */ |
374 | /* enable DMA RB */ |
375 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); |
375 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); |
376 | 376 | ||
377 | ib_cntl = SDMA_IB_ENABLE; |
377 | ib_cntl = SDMA_IB_ENABLE; |
378 | #ifdef __BIG_ENDIAN |
378 | #ifdef __BIG_ENDIAN |
379 | ib_cntl |= SDMA_IB_SWAP_ENABLE; |
379 | ib_cntl |= SDMA_IB_SWAP_ENABLE; |
380 | #endif |
380 | #endif |
381 | /* enable DMA IBs */ |
381 | /* enable DMA IBs */ |
382 | WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl); |
382 | WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl); |
383 | 383 | ||
384 | ring->ready = true; |
384 | ring->ready = true; |
385 | 385 | ||
386 | r = radeon_ring_test(rdev, ring->idx, ring); |
386 | r = radeon_ring_test(rdev, ring->idx, ring); |
387 | if (r) { |
387 | if (r) { |
388 | ring->ready = false; |
388 | ring->ready = false; |
389 | return r; |
389 | return r; |
390 | } |
390 | } |
391 | } |
391 | } |
392 | 392 | ||
393 | if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || |
393 | if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || |
394 | (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) |
394 | (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) |
395 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
395 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
396 | 396 | ||
397 | return 0; |
397 | return 0; |
398 | } |
398 | } |
399 | 399 | ||
400 | /** |
400 | /** |
401 | * cik_sdma_rlc_resume - setup and start the async dma engines |
401 | * cik_sdma_rlc_resume - setup and start the async dma engines |
402 | * |
402 | * |
403 | * @rdev: radeon_device pointer |
403 | * @rdev: radeon_device pointer |
404 | * |
404 | * |
405 | * Set up the compute DMA queues and enable them (CIK). |
405 | * Set up the compute DMA queues and enable them (CIK). |
406 | * Returns 0 for success, error for failure. |
406 | * Returns 0 for success, error for failure. |
407 | */ |
407 | */ |
408 | static int cik_sdma_rlc_resume(struct radeon_device *rdev) |
408 | static int cik_sdma_rlc_resume(struct radeon_device *rdev) |
409 | { |
409 | { |
410 | /* XXX todo */ |
410 | /* XXX todo */ |
411 | return 0; |
411 | return 0; |
412 | } |
412 | } |
413 | 413 | ||
414 | /** |
414 | /** |
415 | * cik_sdma_load_microcode - load the sDMA ME ucode |
415 | * cik_sdma_load_microcode - load the sDMA ME ucode |
416 | * |
416 | * |
417 | * @rdev: radeon_device pointer |
417 | * @rdev: radeon_device pointer |
418 | * |
418 | * |
419 | * Loads the sDMA0/1 ucode. |
419 | * Loads the sDMA0/1 ucode. |
420 | * Returns 0 for success, -EINVAL if the ucode is not available. |
420 | * Returns 0 for success, -EINVAL if the ucode is not available. |
421 | */ |
421 | */ |
422 | static int cik_sdma_load_microcode(struct radeon_device *rdev) |
422 | static int cik_sdma_load_microcode(struct radeon_device *rdev) |
423 | { |
423 | { |
424 | int i; |
424 | int i; |
425 | 425 | ||
426 | if (!rdev->sdma_fw) |
426 | if (!rdev->sdma_fw) |
427 | return -EINVAL; |
427 | return -EINVAL; |
428 | 428 | ||
429 | /* halt the MEs */ |
429 | /* halt the MEs */ |
430 | cik_sdma_enable(rdev, false); |
430 | cik_sdma_enable(rdev, false); |
431 | 431 | ||
432 | if (rdev->new_fw) { |
432 | if (rdev->new_fw) { |
433 | const struct sdma_firmware_header_v1_0 *hdr = |
433 | const struct sdma_firmware_header_v1_0 *hdr = |
434 | (const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data; |
434 | (const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data; |
435 | const __le32 *fw_data; |
435 | const __le32 *fw_data; |
436 | u32 fw_size; |
436 | u32 fw_size; |
437 | 437 | ||
438 | radeon_ucode_print_sdma_hdr(&hdr->header); |
438 | radeon_ucode_print_sdma_hdr(&hdr->header); |
439 | 439 | ||
440 | /* sdma0 */ |
440 | /* sdma0 */ |
441 | fw_data = (const __le32 *) |
441 | fw_data = (const __le32 *) |
442 | (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
442 | (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
443 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; |
443 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; |
444 | WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); |
444 | WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); |
445 | for (i = 0; i < fw_size; i++) |
445 | for (i = 0; i < fw_size; i++) |
446 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++)); |
446 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++)); |
447 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); |
447 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); |
448 | 448 | ||
449 | /* sdma1 */ |
449 | /* sdma1 */ |
450 | fw_data = (const __le32 *) |
450 | fw_data = (const __le32 *) |
451 | (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
451 | (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
452 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; |
452 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; |
453 | WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); |
453 | WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); |
454 | for (i = 0; i < fw_size; i++) |
454 | for (i = 0; i < fw_size; i++) |
455 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++)); |
455 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++)); |
456 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); |
456 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); |
457 | } else { |
457 | } else { |
458 | const __be32 *fw_data; |
458 | const __be32 *fw_data; |
459 | 459 | ||
460 | /* sdma0 */ |
460 | /* sdma0 */ |
461 | fw_data = (const __be32 *)rdev->sdma_fw->data; |
461 | fw_data = (const __be32 *)rdev->sdma_fw->data; |
462 | WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); |
462 | WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); |
463 | for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) |
463 | for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) |
464 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++)); |
464 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++)); |
465 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); |
465 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); |
466 | 466 | ||
467 | /* sdma1 */ |
467 | /* sdma1 */ |
468 | fw_data = (const __be32 *)rdev->sdma_fw->data; |
468 | fw_data = (const __be32 *)rdev->sdma_fw->data; |
469 | WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); |
469 | WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); |
470 | for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) |
470 | for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) |
471 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++)); |
471 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++)); |
472 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); |
472 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); |
473 | } |
473 | } |
474 | 474 | ||
475 | WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); |
475 | WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); |
476 | WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); |
476 | WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); |
477 | return 0; |
477 | return 0; |
478 | } |
478 | } |
479 | 479 | ||
480 | /** |
480 | /** |
481 | * cik_sdma_resume - setup and start the async dma engines |
481 | * cik_sdma_resume - setup and start the async dma engines |
482 | * |
482 | * |
483 | * @rdev: radeon_device pointer |
483 | * @rdev: radeon_device pointer |
484 | * |
484 | * |
485 | * Set up the DMA engines and enable them (CIK). |
485 | * Set up the DMA engines and enable them (CIK). |
486 | * Returns 0 for success, error for failure. |
486 | * Returns 0 for success, error for failure. |
487 | */ |
487 | */ |
488 | int cik_sdma_resume(struct radeon_device *rdev) |
488 | int cik_sdma_resume(struct radeon_device *rdev) |
489 | { |
489 | { |
490 | int r; |
490 | int r; |
491 | 491 | ||
492 | r = cik_sdma_load_microcode(rdev); |
492 | r = cik_sdma_load_microcode(rdev); |
493 | if (r) |
493 | if (r) |
494 | return r; |
494 | return r; |
495 | 495 | ||
496 | /* unhalt the MEs */ |
496 | /* unhalt the MEs */ |
497 | cik_sdma_enable(rdev, true); |
497 | cik_sdma_enable(rdev, true); |
498 | 498 | ||
499 | /* start the gfx rings and rlc compute queues */ |
499 | /* start the gfx rings and rlc compute queues */ |
500 | r = cik_sdma_gfx_resume(rdev); |
500 | r = cik_sdma_gfx_resume(rdev); |
501 | if (r) |
501 | if (r) |
502 | return r; |
502 | return r; |
503 | r = cik_sdma_rlc_resume(rdev); |
503 | r = cik_sdma_rlc_resume(rdev); |
504 | if (r) |
504 | if (r) |
505 | return r; |
505 | return r; |
506 | 506 | ||
507 | return 0; |
507 | return 0; |
508 | } |
508 | } |
509 | 509 | ||
510 | /** |
510 | /** |
511 | * cik_sdma_fini - tear down the async dma engines |
511 | * cik_sdma_fini - tear down the async dma engines |
512 | * |
512 | * |
513 | * @rdev: radeon_device pointer |
513 | * @rdev: radeon_device pointer |
514 | * |
514 | * |
515 | * Stop the async dma engines and free the rings (CIK). |
515 | * Stop the async dma engines and free the rings (CIK). |
516 | */ |
516 | */ |
517 | void cik_sdma_fini(struct radeon_device *rdev) |
517 | void cik_sdma_fini(struct radeon_device *rdev) |
518 | { |
518 | { |
519 | /* halt the MEs */ |
519 | /* halt the MEs */ |
520 | cik_sdma_enable(rdev, false); |
520 | cik_sdma_enable(rdev, false); |
521 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); |
521 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); |
522 | radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); |
522 | radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); |
523 | /* XXX - compute dma queue tear down */ |
523 | /* XXX - compute dma queue tear down */ |
524 | } |
524 | } |
525 | 525 | ||
526 | /** |
526 | /** |
527 | * cik_copy_dma - copy pages using the DMA engine |
527 | * cik_copy_dma - copy pages using the DMA engine |
528 | * |
528 | * |
529 | * @rdev: radeon_device pointer |
529 | * @rdev: radeon_device pointer |
530 | * @src_offset: src GPU address |
530 | * @src_offset: src GPU address |
531 | * @dst_offset: dst GPU address |
531 | * @dst_offset: dst GPU address |
532 | * @num_gpu_pages: number of GPU pages to xfer |
532 | * @num_gpu_pages: number of GPU pages to xfer |
533 | * @fence: radeon fence object |
533 | * @resv: reservation object to sync to |
534 | * |
534 | * |
535 | * Copy GPU paging using the DMA engine (CIK). |
535 | * Copy GPU paging using the DMA engine (CIK). |
536 | * Used by the radeon ttm implementation to move pages if |
536 | * Used by the radeon ttm implementation to move pages if |
537 | * registered as the asic copy callback. |
537 | * registered as the asic copy callback. |
538 | */ |
538 | */ |
539 | int cik_copy_dma(struct radeon_device *rdev, |
539 | struct radeon_fence *cik_copy_dma(struct radeon_device *rdev, |
540 | uint64_t src_offset, uint64_t dst_offset, |
540 | uint64_t src_offset, uint64_t dst_offset, |
541 | unsigned num_gpu_pages, |
541 | unsigned num_gpu_pages, |
542 | struct radeon_fence **fence) |
542 | struct reservation_object *resv) |
543 | { |
543 | { |
544 | struct radeon_semaphore *sem = NULL; |
544 | struct radeon_fence *fence; |
- | 545 | struct radeon_sync sync; |
|
545 | int ring_index = rdev->asic->copy.dma_ring_index; |
546 | int ring_index = rdev->asic->copy.dma_ring_index; |
546 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
547 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
547 | u32 size_in_bytes, cur_size_in_bytes; |
548 | u32 size_in_bytes, cur_size_in_bytes; |
548 | int i, num_loops; |
549 | int i, num_loops; |
549 | int r = 0; |
550 | int r = 0; |
550 | 551 | ||
551 | r = radeon_semaphore_create(rdev, &sem); |
- | |
552 | if (r) { |
- | |
553 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
- | |
554 | return r; |
- | |
555 | } |
552 | radeon_sync_create(&sync); |
556 | 553 | ||
557 | size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); |
554 | size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); |
558 | num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); |
555 | num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); |
559 | r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14); |
556 | r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14); |
560 | if (r) { |
557 | if (r) { |
561 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
558 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
562 | radeon_semaphore_free(rdev, &sem, NULL); |
559 | radeon_sync_free(rdev, &sync, NULL); |
563 | return r; |
560 | return ERR_PTR(r); |
564 | } |
561 | } |
565 | 562 | ||
566 | radeon_semaphore_sync_to(sem, *fence); |
563 | radeon_sync_resv(rdev, &sync, resv, false); |
567 | radeon_semaphore_sync_rings(rdev, sem, ring->idx); |
564 | radeon_sync_rings(rdev, &sync, ring->idx); |
568 | 565 | ||
569 | for (i = 0; i < num_loops; i++) { |
566 | for (i = 0; i < num_loops; i++) { |
570 | cur_size_in_bytes = size_in_bytes; |
567 | cur_size_in_bytes = size_in_bytes; |
571 | if (cur_size_in_bytes > 0x1fffff) |
568 | if (cur_size_in_bytes > 0x1fffff) |
572 | cur_size_in_bytes = 0x1fffff; |
569 | cur_size_in_bytes = 0x1fffff; |
573 | size_in_bytes -= cur_size_in_bytes; |
570 | size_in_bytes -= cur_size_in_bytes; |
574 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); |
571 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); |
575 | radeon_ring_write(ring, cur_size_in_bytes); |
572 | radeon_ring_write(ring, cur_size_in_bytes); |
576 | radeon_ring_write(ring, 0); /* src/dst endian swap */ |
573 | radeon_ring_write(ring, 0); /* src/dst endian swap */ |
577 | radeon_ring_write(ring, lower_32_bits(src_offset)); |
574 | radeon_ring_write(ring, lower_32_bits(src_offset)); |
578 | radeon_ring_write(ring, upper_32_bits(src_offset)); |
575 | radeon_ring_write(ring, upper_32_bits(src_offset)); |
579 | radeon_ring_write(ring, lower_32_bits(dst_offset)); |
576 | radeon_ring_write(ring, lower_32_bits(dst_offset)); |
580 | radeon_ring_write(ring, upper_32_bits(dst_offset)); |
577 | radeon_ring_write(ring, upper_32_bits(dst_offset)); |
581 | src_offset += cur_size_in_bytes; |
578 | src_offset += cur_size_in_bytes; |
582 | dst_offset += cur_size_in_bytes; |
579 | dst_offset += cur_size_in_bytes; |
583 | } |
580 | } |
584 | 581 | ||
585 | r = radeon_fence_emit(rdev, fence, ring->idx); |
582 | r = radeon_fence_emit(rdev, &fence, ring->idx); |
586 | if (r) { |
583 | if (r) { |
587 | radeon_ring_unlock_undo(rdev, ring); |
584 | radeon_ring_unlock_undo(rdev, ring); |
588 | radeon_semaphore_free(rdev, &sem, NULL); |
585 | radeon_sync_free(rdev, &sync, NULL); |
589 | return r; |
586 | return ERR_PTR(r); |
590 | } |
587 | } |
591 | 588 | ||
592 | radeon_ring_unlock_commit(rdev, ring, false); |
589 | radeon_ring_unlock_commit(rdev, ring, false); |
593 | radeon_semaphore_free(rdev, &sem, *fence); |
590 | radeon_sync_free(rdev, &sync, fence); |
594 | 591 | ||
595 | return r; |
592 | return fence; |
596 | } |
593 | } |
597 | 594 | ||
598 | /** |
595 | /** |
599 | * cik_sdma_ring_test - simple async dma engine test |
596 | * cik_sdma_ring_test - simple async dma engine test |
600 | * |
597 | * |
601 | * @rdev: radeon_device pointer |
598 | * @rdev: radeon_device pointer |
602 | * @ring: radeon_ring structure holding ring information |
599 | * @ring: radeon_ring structure holding ring information |
603 | * |
600 | * |
604 | * Test the DMA engine by writing using it to write an |
601 | * Test the DMA engine by writing using it to write an |
605 | * value to memory. (CIK). |
602 | * value to memory. (CIK). |
606 | * Returns 0 for success, error for failure. |
603 | * Returns 0 for success, error for failure. |
607 | */ |
604 | */ |
608 | int cik_sdma_ring_test(struct radeon_device *rdev, |
605 | int cik_sdma_ring_test(struct radeon_device *rdev, |
609 | struct radeon_ring *ring) |
606 | struct radeon_ring *ring) |
610 | { |
607 | { |
611 | unsigned i; |
608 | unsigned i; |
612 | int r; |
609 | int r; |
613 | unsigned index; |
610 | unsigned index; |
614 | u32 tmp; |
611 | u32 tmp; |
615 | u64 gpu_addr; |
612 | u64 gpu_addr; |
616 | 613 | ||
617 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
614 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
618 | index = R600_WB_DMA_RING_TEST_OFFSET; |
615 | index = R600_WB_DMA_RING_TEST_OFFSET; |
619 | else |
616 | else |
620 | index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; |
617 | index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; |
621 | 618 | ||
622 | gpu_addr = rdev->wb.gpu_addr + index; |
619 | gpu_addr = rdev->wb.gpu_addr + index; |
623 | 620 | ||
624 | tmp = 0xCAFEDEAD; |
621 | tmp = 0xCAFEDEAD; |
625 | rdev->wb.wb[index/4] = cpu_to_le32(tmp); |
622 | rdev->wb.wb[index/4] = cpu_to_le32(tmp); |
626 | 623 | ||
627 | r = radeon_ring_lock(rdev, ring, 5); |
624 | r = radeon_ring_lock(rdev, ring, 5); |
628 | if (r) { |
625 | if (r) { |
629 | DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); |
626 | DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); |
630 | return r; |
627 | return r; |
631 | } |
628 | } |
632 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); |
629 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); |
633 | radeon_ring_write(ring, lower_32_bits(gpu_addr)); |
630 | radeon_ring_write(ring, lower_32_bits(gpu_addr)); |
634 | radeon_ring_write(ring, upper_32_bits(gpu_addr)); |
631 | radeon_ring_write(ring, upper_32_bits(gpu_addr)); |
635 | radeon_ring_write(ring, 1); /* number of DWs to follow */ |
632 | radeon_ring_write(ring, 1); /* number of DWs to follow */ |
636 | radeon_ring_write(ring, 0xDEADBEEF); |
633 | radeon_ring_write(ring, 0xDEADBEEF); |
637 | radeon_ring_unlock_commit(rdev, ring, false); |
634 | radeon_ring_unlock_commit(rdev, ring, false); |
638 | 635 | ||
639 | for (i = 0; i < rdev->usec_timeout; i++) { |
636 | for (i = 0; i < rdev->usec_timeout; i++) { |
640 | tmp = le32_to_cpu(rdev->wb.wb[index/4]); |
637 | tmp = le32_to_cpu(rdev->wb.wb[index/4]); |
641 | if (tmp == 0xDEADBEEF) |
638 | if (tmp == 0xDEADBEEF) |
642 | break; |
639 | break; |
643 | DRM_UDELAY(1); |
640 | DRM_UDELAY(1); |
644 | } |
641 | } |
645 | 642 | ||
646 | if (i < rdev->usec_timeout) { |
643 | if (i < rdev->usec_timeout) { |
647 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); |
644 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); |
648 | } else { |
645 | } else { |
649 | DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", |
646 | DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", |
650 | ring->idx, tmp); |
647 | ring->idx, tmp); |
651 | r = -EINVAL; |
648 | r = -EINVAL; |
652 | } |
649 | } |
653 | return r; |
650 | return r; |
654 | } |
651 | } |
655 | 652 | ||
656 | /** |
653 | /** |
657 | * cik_sdma_ib_test - test an IB on the DMA engine |
654 | * cik_sdma_ib_test - test an IB on the DMA engine |
658 | * |
655 | * |
659 | * @rdev: radeon_device pointer |
656 | * @rdev: radeon_device pointer |
660 | * @ring: radeon_ring structure holding ring information |
657 | * @ring: radeon_ring structure holding ring information |
661 | * |
658 | * |
662 | * Test a simple IB in the DMA ring (CIK). |
659 | * Test a simple IB in the DMA ring (CIK). |
663 | * Returns 0 on success, error on failure. |
660 | * Returns 0 on success, error on failure. |
664 | */ |
661 | */ |
665 | int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
662 | int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
666 | { |
663 | { |
667 | struct radeon_ib ib; |
664 | struct radeon_ib ib; |
668 | unsigned i; |
665 | unsigned i; |
- | 666 | unsigned index; |
|
669 | int r; |
667 | int r; |
670 | void __iomem *ptr = (void *)rdev->vram_scratch.ptr; |
- | |
671 | u32 tmp = 0; |
668 | u32 tmp = 0; |
- | 669 | u64 gpu_addr; |
|
672 | 670 | ||
673 | if (!ptr) { |
671 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
- | 672 | index = R600_WB_DMA_RING_TEST_OFFSET; |
|
674 | DRM_ERROR("invalid vram scratch pointer\n"); |
673 | else |
675 | return -EINVAL; |
674 | index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; |
- | 675 | ||
676 | } |
676 | gpu_addr = rdev->wb.gpu_addr + index; |
677 | 677 | ||
678 | tmp = 0xCAFEDEAD; |
678 | tmp = 0xCAFEDEAD; |
679 | writel(tmp, ptr); |
679 | rdev->wb.wb[index/4] = cpu_to_le32(tmp); |
680 | 680 | ||
681 | r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); |
681 | r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); |
682 | if (r) { |
682 | if (r) { |
683 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
683 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
684 | return r; |
684 | return r; |
685 | } |
685 | } |
686 | 686 | ||
687 | ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); |
687 | ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); |
688 | ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; |
688 | ib.ptr[1] = lower_32_bits(gpu_addr); |
689 | ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr); |
689 | ib.ptr[2] = upper_32_bits(gpu_addr); |
690 | ib.ptr[3] = 1; |
690 | ib.ptr[3] = 1; |
691 | ib.ptr[4] = 0xDEADBEEF; |
691 | ib.ptr[4] = 0xDEADBEEF; |
692 | ib.length_dw = 5; |
692 | ib.length_dw = 5; |
693 | 693 | ||
694 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
694 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
695 | if (r) { |
695 | if (r) { |
696 | radeon_ib_free(rdev, &ib); |
696 | radeon_ib_free(rdev, &ib); |
697 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
697 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
698 | return r; |
698 | return r; |
699 | } |
699 | } |
700 | r = radeon_fence_wait(ib.fence, false); |
700 | r = radeon_fence_wait(ib.fence, false); |
701 | if (r) { |
701 | if (r) { |
702 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
702 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
703 | return r; |
703 | return r; |
704 | } |
704 | } |
705 | for (i = 0; i < rdev->usec_timeout; i++) { |
705 | for (i = 0; i < rdev->usec_timeout; i++) { |
706 | tmp = readl(ptr); |
706 | tmp = le32_to_cpu(rdev->wb.wb[index/4]); |
707 | if (tmp == 0xDEADBEEF) |
707 | if (tmp == 0xDEADBEEF) |
708 | break; |
708 | break; |
709 | DRM_UDELAY(1); |
709 | DRM_UDELAY(1); |
710 | } |
710 | } |
711 | if (i < rdev->usec_timeout) { |
711 | if (i < rdev->usec_timeout) { |
712 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); |
712 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); |
713 | } else { |
713 | } else { |
714 | DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); |
714 | DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); |
715 | r = -EINVAL; |
715 | r = -EINVAL; |
716 | } |
716 | } |
717 | radeon_ib_free(rdev, &ib); |
717 | radeon_ib_free(rdev, &ib); |
718 | return r; |
718 | return r; |
719 | } |
719 | } |
720 | 720 | ||
721 | /** |
721 | /** |
722 | * cik_sdma_is_lockup - Check if the DMA engine is locked up |
722 | * cik_sdma_is_lockup - Check if the DMA engine is locked up |
723 | * |
723 | * |
724 | * @rdev: radeon_device pointer |
724 | * @rdev: radeon_device pointer |
725 | * @ring: radeon_ring structure holding ring information |
725 | * @ring: radeon_ring structure holding ring information |
726 | * |
726 | * |
727 | * Check if the async DMA engine is locked up (CIK). |
727 | * Check if the async DMA engine is locked up (CIK). |
728 | * Returns true if the engine appears to be locked up, false if not. |
728 | * Returns true if the engine appears to be locked up, false if not. |
729 | */ |
729 | */ |
730 | bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
730 | bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
731 | { |
731 | { |
732 | u32 reset_mask = cik_gpu_check_soft_reset(rdev); |
732 | u32 reset_mask = cik_gpu_check_soft_reset(rdev); |
733 | u32 mask; |
733 | u32 mask; |
734 | 734 | ||
735 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
735 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
736 | mask = RADEON_RESET_DMA; |
736 | mask = RADEON_RESET_DMA; |
737 | else |
737 | else |
738 | mask = RADEON_RESET_DMA1; |
738 | mask = RADEON_RESET_DMA1; |
739 | 739 | ||
740 | if (!(reset_mask & mask)) { |
740 | if (!(reset_mask & mask)) { |
741 | radeon_ring_lockup_update(rdev, ring); |
741 | radeon_ring_lockup_update(rdev, ring); |
742 | return false; |
742 | return false; |
743 | } |
743 | } |
744 | return radeon_ring_test_lockup(rdev, ring); |
744 | return radeon_ring_test_lockup(rdev, ring); |
745 | } |
745 | } |
746 | 746 | ||
747 | /** |
747 | /** |
748 | * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART |
748 | * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART |
749 | * |
749 | * |
750 | * @rdev: radeon_device pointer |
750 | * @rdev: radeon_device pointer |
751 | * @ib: indirect buffer to fill with commands |
751 | * @ib: indirect buffer to fill with commands |
752 | * @pe: addr of the page entry |
752 | * @pe: addr of the page entry |
753 | * @src: src addr to copy from |
753 | * @src: src addr to copy from |
754 | * @count: number of page entries to update |
754 | * @count: number of page entries to update |
755 | * |
755 | * |
756 | * Update PTEs by copying them from the GART using sDMA (CIK). |
756 | * Update PTEs by copying them from the GART using sDMA (CIK). |
757 | */ |
757 | */ |
758 | void cik_sdma_vm_copy_pages(struct radeon_device *rdev, |
758 | void cik_sdma_vm_copy_pages(struct radeon_device *rdev, |
759 | struct radeon_ib *ib, |
759 | struct radeon_ib *ib, |
760 | uint64_t pe, uint64_t src, |
760 | uint64_t pe, uint64_t src, |
761 | unsigned count) |
761 | unsigned count) |
762 | { |
762 | { |
763 | while (count) { |
763 | while (count) { |
764 | unsigned bytes = count * 8; |
764 | unsigned bytes = count * 8; |
765 | if (bytes > 0x1FFFF8) |
765 | if (bytes > 0x1FFFF8) |
766 | bytes = 0x1FFFF8; |
766 | bytes = 0x1FFFF8; |
767 | 767 | ||
768 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, |
768 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, |
769 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); |
769 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); |
770 | ib->ptr[ib->length_dw++] = bytes; |
770 | ib->ptr[ib->length_dw++] = bytes; |
771 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ |
771 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ |
772 | ib->ptr[ib->length_dw++] = lower_32_bits(src); |
772 | ib->ptr[ib->length_dw++] = lower_32_bits(src); |
773 | ib->ptr[ib->length_dw++] = upper_32_bits(src); |
773 | ib->ptr[ib->length_dw++] = upper_32_bits(src); |
774 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); |
774 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); |
775 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); |
775 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); |
776 | 776 | ||
777 | pe += bytes; |
777 | pe += bytes; |
778 | src += bytes; |
778 | src += bytes; |
779 | count -= bytes / 8; |
779 | count -= bytes / 8; |
780 | } |
780 | } |
781 | } |
781 | } |
782 | 782 | ||
783 | /** |
783 | /** |
784 | * cik_sdma_vm_write_pages - update PTEs by writing them manually |
784 | * cik_sdma_vm_write_pages - update PTEs by writing them manually |
785 | * |
785 | * |
786 | * @rdev: radeon_device pointer |
786 | * @rdev: radeon_device pointer |
787 | * @ib: indirect buffer to fill with commands |
787 | * @ib: indirect buffer to fill with commands |
788 | * @pe: addr of the page entry |
788 | * @pe: addr of the page entry |
789 | * @addr: dst addr to write into pe |
789 | * @addr: dst addr to write into pe |
790 | * @count: number of page entries to update |
790 | * @count: number of page entries to update |
791 | * @incr: increase next addr by incr bytes |
791 | * @incr: increase next addr by incr bytes |
792 | * @flags: access flags |
792 | * @flags: access flags |
793 | * |
793 | * |
794 | * Update PTEs by writing them manually using sDMA (CIK). |
794 | * Update PTEs by writing them manually using sDMA (CIK). |
795 | */ |
795 | */ |
796 | void cik_sdma_vm_write_pages(struct radeon_device *rdev, |
796 | void cik_sdma_vm_write_pages(struct radeon_device *rdev, |
797 | struct radeon_ib *ib, |
797 | struct radeon_ib *ib, |
798 | uint64_t pe, |
798 | uint64_t pe, |
799 | uint64_t addr, unsigned count, |
799 | uint64_t addr, unsigned count, |
800 | uint32_t incr, uint32_t flags) |
800 | uint32_t incr, uint32_t flags) |
801 | { |
801 | { |
802 | uint64_t value; |
802 | uint64_t value; |
803 | unsigned ndw; |
803 | unsigned ndw; |
804 | 804 | ||
805 | while (count) { |
805 | while (count) { |
806 | ndw = count * 2; |
806 | ndw = count * 2; |
807 | if (ndw > 0xFFFFE) |
807 | if (ndw > 0xFFFFE) |
808 | ndw = 0xFFFFE; |
808 | ndw = 0xFFFFE; |
809 | 809 | ||
810 | /* for non-physically contiguous pages (system) */ |
810 | /* for non-physically contiguous pages (system) */ |
811 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, |
811 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, |
812 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); |
812 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); |
813 | ib->ptr[ib->length_dw++] = pe; |
813 | ib->ptr[ib->length_dw++] = pe; |
814 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); |
814 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); |
815 | ib->ptr[ib->length_dw++] = ndw; |
815 | ib->ptr[ib->length_dw++] = ndw; |
816 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { |
816 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { |
817 | if (flags & R600_PTE_SYSTEM) { |
817 | if (flags & R600_PTE_SYSTEM) { |
818 | value = radeon_vm_map_gart(rdev, addr); |
818 | value = radeon_vm_map_gart(rdev, addr); |
819 | value &= 0xFFFFFFFFFFFFF000ULL; |
819 | value &= 0xFFFFFFFFFFFFF000ULL; |
820 | } else if (flags & R600_PTE_VALID) { |
820 | } else if (flags & R600_PTE_VALID) { |
821 | value = addr; |
821 | value = addr; |
822 | } else { |
822 | } else { |
823 | value = 0; |
823 | value = 0; |
824 | } |
824 | } |
825 | addr += incr; |
825 | addr += incr; |
826 | value |= flags; |
826 | value |= flags; |
827 | ib->ptr[ib->length_dw++] = value; |
827 | ib->ptr[ib->length_dw++] = value; |
828 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
828 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
829 | } |
829 | } |
830 | } |
830 | } |
831 | } |
831 | } |
832 | 832 | ||
833 | /** |
833 | /** |
834 | * cik_sdma_vm_set_pages - update the page tables using sDMA |
834 | * cik_sdma_vm_set_pages - update the page tables using sDMA |
835 | * |
835 | * |
836 | * @rdev: radeon_device pointer |
836 | * @rdev: radeon_device pointer |
837 | * @ib: indirect buffer to fill with commands |
837 | * @ib: indirect buffer to fill with commands |
838 | * @pe: addr of the page entry |
838 | * @pe: addr of the page entry |
839 | * @addr: dst addr to write into pe |
839 | * @addr: dst addr to write into pe |
840 | * @count: number of page entries to update |
840 | * @count: number of page entries to update |
841 | * @incr: increase next addr by incr bytes |
841 | * @incr: increase next addr by incr bytes |
842 | * @flags: access flags |
842 | * @flags: access flags |
843 | * |
843 | * |
844 | * Update the page tables using sDMA (CIK). |
844 | * Update the page tables using sDMA (CIK). |
845 | */ |
845 | */ |
846 | void cik_sdma_vm_set_pages(struct radeon_device *rdev, |
846 | void cik_sdma_vm_set_pages(struct radeon_device *rdev, |
847 | struct radeon_ib *ib, |
847 | struct radeon_ib *ib, |
848 | uint64_t pe, |
848 | uint64_t pe, |
849 | uint64_t addr, unsigned count, |
849 | uint64_t addr, unsigned count, |
850 | uint32_t incr, uint32_t flags) |
850 | uint32_t incr, uint32_t flags) |
851 | { |
851 | { |
852 | uint64_t value; |
852 | uint64_t value; |
853 | unsigned ndw; |
853 | unsigned ndw; |
854 | 854 | ||
855 | while (count) { |
855 | while (count) { |
856 | ndw = count; |
856 | ndw = count; |
857 | if (ndw > 0x7FFFF) |
857 | if (ndw > 0x7FFFF) |
858 | ndw = 0x7FFFF; |
858 | ndw = 0x7FFFF; |
859 | 859 | ||
860 | if (flags & R600_PTE_VALID) |
860 | if (flags & R600_PTE_VALID) |
861 | value = addr; |
861 | value = addr; |
862 | else |
862 | else |
863 | value = 0; |
863 | value = 0; |
864 | 864 | ||
865 | /* for physically contiguous pages (vram) */ |
865 | /* for physically contiguous pages (vram) */ |
866 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); |
866 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); |
867 | ib->ptr[ib->length_dw++] = pe; /* dst addr */ |
867 | ib->ptr[ib->length_dw++] = pe; /* dst addr */ |
868 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); |
868 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); |
869 | ib->ptr[ib->length_dw++] = flags; /* mask */ |
869 | ib->ptr[ib->length_dw++] = flags; /* mask */ |
870 | ib->ptr[ib->length_dw++] = 0; |
870 | ib->ptr[ib->length_dw++] = 0; |
871 | ib->ptr[ib->length_dw++] = value; /* value */ |
871 | ib->ptr[ib->length_dw++] = value; /* value */ |
872 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
872 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
873 | ib->ptr[ib->length_dw++] = incr; /* increment size */ |
873 | ib->ptr[ib->length_dw++] = incr; /* increment size */ |
874 | ib->ptr[ib->length_dw++] = 0; |
874 | ib->ptr[ib->length_dw++] = 0; |
875 | ib->ptr[ib->length_dw++] = ndw; /* number of entries */ |
875 | ib->ptr[ib->length_dw++] = ndw; /* number of entries */ |
876 | 876 | ||
877 | pe += ndw * 8; |
877 | pe += ndw * 8; |
878 | addr += ndw * incr; |
878 | addr += ndw * incr; |
879 | count -= ndw; |
879 | count -= ndw; |
880 | } |
880 | } |
881 | } |
881 | } |
882 | 882 | ||
883 | /** |
883 | /** |
884 | * cik_sdma_vm_pad_ib - pad the IB to the required number of dw |
884 | * cik_sdma_vm_pad_ib - pad the IB to the required number of dw |
885 | * |
885 | * |
886 | * @ib: indirect buffer to fill with padding |
886 | * @ib: indirect buffer to fill with padding |
887 | * |
887 | * |
888 | */ |
888 | */ |
889 | void cik_sdma_vm_pad_ib(struct radeon_ib *ib) |
889 | void cik_sdma_vm_pad_ib(struct radeon_ib *ib) |
890 | { |
890 | { |
891 | while (ib->length_dw & 0x7) |
891 | while (ib->length_dw & 0x7) |
892 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); |
892 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); |
893 | } |
893 | } |
894 | 894 | ||
895 | /** |
895 | /** |
896 | * cik_dma_vm_flush - cik vm flush using sDMA |
896 | * cik_dma_vm_flush - cik vm flush using sDMA |
897 | * |
897 | * |
898 | * @rdev: radeon_device pointer |
898 | * @rdev: radeon_device pointer |
899 | * |
899 | * |
900 | * Update the page table base and flush the VM TLB |
900 | * Update the page table base and flush the VM TLB |
901 | * using sDMA (CIK). |
901 | * using sDMA (CIK). |
902 | */ |
902 | */ |
903 | void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) |
903 | void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
- | 904 | unsigned vm_id, uint64_t pd_addr) |
|
904 | { |
905 | { |
905 | struct radeon_ring *ring = &rdev->ring[ridx]; |
- | |
906 | - | ||
907 | if (vm == NULL) |
- | |
908 | return; |
- | |
909 | - | ||
910 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
906 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
911 | if (vm->id < 8) { |
907 | if (vm_id < 8) { |
912 | radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); |
908 | radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2); |
913 | } else { |
909 | } else { |
914 | radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2); |
910 | radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2); |
915 | } |
911 | } |
916 | radeon_ring_write(ring, vm->pd_gpu_addr >> 12); |
912 | radeon_ring_write(ring, pd_addr >> 12); |
917 | 913 | ||
918 | /* update SH_MEM_* regs */ |
914 | /* update SH_MEM_* regs */ |
919 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
915 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
920 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); |
916 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); |
921 | radeon_ring_write(ring, VMID(vm->id)); |
917 | radeon_ring_write(ring, VMID(vm_id)); |
922 | 918 | ||
923 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
919 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
924 | radeon_ring_write(ring, SH_MEM_BASES >> 2); |
920 | radeon_ring_write(ring, SH_MEM_BASES >> 2); |
925 | radeon_ring_write(ring, 0); |
921 | radeon_ring_write(ring, 0); |
926 | 922 | ||
927 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
923 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
928 | radeon_ring_write(ring, SH_MEM_CONFIG >> 2); |
924 | radeon_ring_write(ring, SH_MEM_CONFIG >> 2); |
929 | radeon_ring_write(ring, 0); |
925 | radeon_ring_write(ring, 0); |
930 | 926 | ||
931 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
927 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
932 | radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2); |
928 | radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2); |
933 | radeon_ring_write(ring, 1); |
929 | radeon_ring_write(ring, 1); |
934 | 930 | ||
935 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
931 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
936 | radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2); |
932 | radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2); |
937 | radeon_ring_write(ring, 0); |
933 | radeon_ring_write(ring, 0); |
938 | 934 | ||
939 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
935 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
940 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); |
936 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); |
941 | radeon_ring_write(ring, VMID(0)); |
937 | radeon_ring_write(ring, VMID(0)); |
942 | 938 | ||
943 | /* flush HDP */ |
939 | /* flush HDP */ |
944 | cik_sdma_hdp_flush_ring_emit(rdev, ridx); |
940 | cik_sdma_hdp_flush_ring_emit(rdev, ring->idx); |
945 | 941 | ||
946 | /* flush TLB */ |
942 | /* flush TLB */ |
947 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
943 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
948 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
944 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
949 | radeon_ring_write(ring, 1 << vm->id); |
945 | radeon_ring_write(ring, 1 << vm_id); |
950 | }><>><>><>>>>>>>><>>>>>><>><>>>>><>><> |
946 | }><>><>><>>>>>>>><>>>>>><>><>>>>><>><> |