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Rev 5271 Rev 6104
Line 145... Line 145...
145 
#define CIK_LB_DATA_FORMAT                        0x6b00
 145 
#define CIK_LB_DATA_FORMAT                        0x6b00
146 
#       define CIK_INTERLEAVE_EN                  (1 << 3)
 146 
#       define CIK_INTERLEAVE_EN                  (1 << 3)
Line 147... Line 147...
147 
 
 147 
 
Line -... Line 148...
- 
 
 148 
#define CIK_LB_DESKTOP_HEIGHT                     0x6b0c
- 
 
 149 
 
- 
 
 150 
#define KFD_CIK_SDMA_QUEUE_OFFSET		0x200
- 
 
 151 
 
- 
 
 152 
#define SQ_IND_INDEX					0x8DE0
- 
 
 153 
#define SQ_CMD						0x8DEC
- 
 
 154 
#define SQ_IND_DATA					0x8DE4
- 
 
 155 
 
- 
 
 156 
/*
- 
 
 157 
 * The TCP_WATCHx_xxxx addresses that are shown here are in dwords,
- 
 
 158 
 * and that's why they are multiplied by 4
- 
 
 159 
 */
- 
 
 160 
#define TCP_WATCH0_ADDR_H				(0x32A0*4)
- 
 
 161 
#define TCP_WATCH1_ADDR_H				(0x32A3*4)
- 
 
 162 
#define TCP_WATCH2_ADDR_H				(0x32A6*4)
- 
 
 163 
#define TCP_WATCH3_ADDR_H				(0x32A9*4)
- 
 
 164 
#define TCP_WATCH0_ADDR_L				(0x32A1*4)
- 
 
 165 
#define TCP_WATCH1_ADDR_L				(0x32A4*4)
- 
 
 166 
#define TCP_WATCH2_ADDR_L				(0x32A7*4)
- 
 
 167 
#define TCP_WATCH3_ADDR_L				(0x32AA*4)
- 
 
 168 
#define TCP_WATCH0_CNTL					(0x32A2*4)
- 
 
 169 
#define TCP_WATCH1_CNTL					(0x32A5*4)
- 
 
 170 
#define TCP_WATCH2_CNTL					(0x32A8*4)
- 
 
 171 
#define TCP_WATCH3_CNTL					(0x32AB*4)
- 
 
 172 
 
148 
#define CIK_LB_DESKTOP_HEIGHT                     0x6b0c
 173 
#define CPC_INT_CNTL					0xC2D0
- 
 
 174 
 
- 
 
 175 
#define CP_HQD_IQ_RPTR					0xC970u
- 
 
 176 
#define SDMA0_RLC0_RB_CNTL				0xD400u
- 
 
 177 
#define	SDMA_RB_VMID(x)					(x << 24)
- 
 
 178 
#define	SDMA0_RLC0_RB_BASE				0xD404u
- 
 
 179 
#define	SDMA0_RLC0_RB_BASE_HI				0xD408u
- 
 
 180 
#define	SDMA0_RLC0_RB_RPTR				0xD40Cu
- 
 
 181 
#define	SDMA0_RLC0_RB_WPTR				0xD410u
- 
 
 182 
#define	SDMA0_RLC0_RB_WPTR_POLL_CNTL			0xD414u
- 
 
 183 
#define	SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI			0xD418u
- 
 
 184 
#define	SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO			0xD41Cu
- 
 
 185 
#define	SDMA0_RLC0_RB_RPTR_ADDR_HI			0xD420u
- 
 
 186 
#define	SDMA0_RLC0_RB_RPTR_ADDR_LO			0xD424u
- 
 
 187 
#define	SDMA0_RLC0_IB_CNTL				0xD428u
- 
 
 188 
#define	SDMA0_RLC0_IB_RPTR				0xD42Cu
- 
 
 189 
#define	SDMA0_RLC0_IB_OFFSET				0xD430u
- 
 
 190 
#define	SDMA0_RLC0_IB_BASE_LO				0xD434u
- 
 
 191 
#define	SDMA0_RLC0_IB_BASE_HI				0xD438u
- 
 
 192 
#define	SDMA0_RLC0_IB_SIZE				0xD43Cu
- 
 
 193 
#define	SDMA0_RLC0_SKIP_CNTL				0xD440u
- 
 
 194 
#define	SDMA0_RLC0_CONTEXT_STATUS			0xD444u
- 
 
 195 
#define	SDMA_RLC_IDLE					(1 << 2)
149 
 
 196 
#define	SDMA0_RLC0_DOORBELL				0xD448u
- 
 
 197 
#define	SDMA_OFFSET(x)					(x << 0)
- 
 
 198 
#define	SDMA_DB_ENABLE					(1 << 28)
- 
 
 199 
#define	SDMA0_RLC0_VIRTUAL_ADDR				0xD49Cu
- 
 
 200 
#define	SDMA_ATC					(1 << 0)
- 
 
 201 
#define	SDMA_VA_PTR32					(1 << 4)
- 
 
 202 
#define	SDMA_VA_SHARED_BASE(x)				(x << 8)
- 
 
 203 
#define	SDMA0_RLC0_APE1_CNTL				0xD4A0u
- 
 
 204 
#define	SDMA0_RLC0_DOORBELL_LOG				0xD4A4u
- 
 
 205 
#define	SDMA0_RLC0_WATERMARK				0xD4A8u
Line -... Line 206...
- 
 
 206 
#define	SDMA0_CNTL					0xD010
- 
 
 207 
#define	SDMA1_CNTL					0xD810
150 
#define CP_HQD_IQ_RPTR					0xC970u
 208 
 
- 
 
 209 
enum {
- 
 
 210 
	MAX_TRAPID = 8,		/* 3 bits in the bitfield.  */
- 
 
 211 
	MAX_WATCH_ADDRESSES = 4
- 
 
 212 
};
- 
 
 213 
 
- 
 
 214 
enum {
- 
 
 215 
	ADDRESS_WATCH_REG_ADDR_HI = 0,
- 
 
 216 
	ADDRESS_WATCH_REG_ADDR_LO,
- 
 
 217 
	ADDRESS_WATCH_REG_CNTL,
- 
 
 218 
	ADDRESS_WATCH_REG_MAX
- 
 
 219 
};
- 
 
 220 
 
- 
 
 221 
enum {				/*  not defined in the CI/KV reg file  */
- 
 
 222 
	ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
- 
 
 223 
	ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
- 
 
 224 
	ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
- 
 
 225 
	/* extend the mask to 26 bits in order to match the low address field */
Line 151... Line 226...
151 
#define AQL_ENABLE					(1U << 0)
 226 
	ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
152 
 
 227 
	ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
153 
#define IDLE					(1 << 2)
 - 
 
154 
 
 - 
 
155 
struct cik_mqd {
 - 
 
156 
	uint32_t header;
 228 
};
157 
	uint32_t compute_dispatch_initiator;
 - 
 
158 
	uint32_t compute_dim_x;
 - 
 
159 
	uint32_t compute_dim_y;
 - 
 
160 
	uint32_t compute_dim_z;
 - 
 
161 
	uint32_t compute_start_x;
 - 
 
162 
	uint32_t compute_start_y;
 - 
 
163 
	uint32_t compute_start_z;
 - 
 
164 
	uint32_t compute_num_thread_x;
 - 
 
165 
	uint32_t compute_num_thread_y;
 - 
 
166 
	uint32_t compute_num_thread_z;
 - 
 
167 
	uint32_t compute_pipelinestat_enable;
 - 
 
168 
	uint32_t compute_perfcount_enable;
 - 
 
169 
	uint32_t compute_pgm_lo;
 - 
 
170 
	uint32_t compute_pgm_hi;
 - 
 
171 
	uint32_t compute_tba_lo;
 - 
 
172 
	uint32_t compute_tba_hi;
 - 
 
173 
	uint32_t compute_tma_lo;
 229 
 
174 
	uint32_t compute_tma_hi;
 - 
 
175 
	uint32_t compute_pgm_rsrc1;
 - 
 
176 
	uint32_t compute_pgm_rsrc2;
 - 
 
177 
	uint32_t compute_vmid;
 - 
 
178 
	uint32_t compute_resource_limits;
 - 
 
179 
	uint32_t compute_static_thread_mgmt_se0;
 - 
 
180 
	uint32_t compute_static_thread_mgmt_se1;
 - 
 
181 
	uint32_t compute_tmpring_size;
 - 
 
182 
	uint32_t compute_static_thread_mgmt_se2;
 - 
 
183 
	uint32_t compute_static_thread_mgmt_se3;
 - 
 
184 
	uint32_t compute_restart_x;
 - 
 
185 
	uint32_t compute_restart_y;
 - 
 
186 
	uint32_t compute_restart_z;
 - 
 
187 
	uint32_t compute_thread_trace_enable;
 - 
 
188 
	uint32_t compute_misc_reserved;
 - 
 
189 
	uint32_t compute_user_data_0;
 - 
 
190 
	uint32_t compute_user_data_1;
 - 
 
191 
	uint32_t compute_user_data_2;
 - 
 
192 
	uint32_t compute_user_data_3;
 - 
 
193 
	uint32_t compute_user_data_4;
 - 
 
194 
	uint32_t compute_user_data_5;
 - 
 
195 
	uint32_t compute_user_data_6;
 - 
 
196 
	uint32_t compute_user_data_7;
 - 
 
197 
	uint32_t compute_user_data_8;
 - 
 
198 
	uint32_t compute_user_data_9;
 - 
 
199 
	uint32_t compute_user_data_10;
 - 
 
200 
	uint32_t compute_user_data_11;
 - 
 
201 
	uint32_t compute_user_data_12;
 - 
 
202 
	uint32_t compute_user_data_13;
 - 
 
203 
	uint32_t compute_user_data_14;
 - 
 
204 
	uint32_t compute_user_data_15;
 - 
 
205 
	uint32_t cp_compute_csinvoc_count_lo;
 230 
union TCP_WATCH_CNTL_BITS {
206 
	uint32_t cp_compute_csinvoc_count_hi;
 231 
	struct {
207 
	uint32_t cp_mqd_base_addr_lo;
 - 
 
208 
	uint32_t cp_mqd_base_addr_hi;
 - 
 
209 
	uint32_t cp_hqd_active;
 - 
 
210 
	uint32_t cp_hqd_vmid;
 - 
 
211 
	uint32_t cp_hqd_persistent_state;
 - 
 
212 
	uint32_t cp_hqd_pipe_priority;
 - 
 
213 
	uint32_t cp_hqd_queue_priority;
 - 
 
214 
	uint32_t cp_hqd_quantum;
 - 
 
215 
	uint32_t cp_hqd_pq_base_lo;
 - 
 
216 
	uint32_t cp_hqd_pq_base_hi;
 - 
 
217 
	uint32_t cp_hqd_pq_rptr;
 - 
 
218 
	uint32_t cp_hqd_pq_rptr_report_addr_lo;
 - 
 
219 
	uint32_t cp_hqd_pq_rptr_report_addr_hi;
 - 
 
220 
	uint32_t cp_hqd_pq_wptr_poll_addr_lo;
 - 
 
221 
	uint32_t cp_hqd_pq_wptr_poll_addr_hi;
 - 
 
222 
	uint32_t cp_hqd_pq_doorbell_control;
 - 
 
223 
	uint32_t cp_hqd_pq_wptr;
 - 
 
224 
	uint32_t cp_hqd_pq_control;
 - 
 
225 
	uint32_t cp_hqd_ib_base_addr_lo;
 - 
 
226 
	uint32_t cp_hqd_ib_base_addr_hi;
 - 
 
227 
	uint32_t cp_hqd_ib_rptr;
 - 
 
228 
	uint32_t cp_hqd_ib_control;
 - 
 
229 
	uint32_t cp_hqd_iq_timer;
 - 
 
230 
	uint32_t cp_hqd_iq_rptr;
 - 
 
231 
	uint32_t cp_hqd_dequeue_request;
 - 
 
232 
	uint32_t cp_hqd_dma_offload;
 - 
 
233 
	uint32_t cp_hqd_sema_cmd;
 - 
 
234 
	uint32_t cp_hqd_msg_type;
 - 
 
235 
	uint32_t cp_hqd_atomic0_preop_lo;
 - 
 
236 
	uint32_t cp_hqd_atomic0_preop_hi;
 - 
 
237 
	uint32_t cp_hqd_atomic1_preop_lo;
 - 
 
238 
	uint32_t cp_hqd_atomic1_preop_hi;
 - 
 
239 
	uint32_t cp_hqd_hq_status0;
 - 
 
240 
	uint32_t cp_hqd_hq_control0;
 - 
 
241 
	uint32_t cp_mqd_control;
 - 
 
242 
	uint32_t cp_mqd_query_time_lo;
 - 
 
243 
	uint32_t cp_mqd_query_time_hi;
 - 
 
244 
	uint32_t cp_mqd_connect_start_time_lo;
 - 
 
245 
	uint32_t cp_mqd_connect_start_time_hi;
 - 
 
246 
	uint32_t cp_mqd_connect_end_time_lo;
 - 
 
247 
	uint32_t cp_mqd_connect_end_time_hi;
 - 
 
248 
	uint32_t cp_mqd_connect_end_wf_count;
 232 
		uint32_t mask:24;
249 
	uint32_t cp_mqd_connect_end_pq_rptr;
 233 
		uint32_t vmid:4;
250 
	uint32_t cp_mqd_connect_end_pq_wptr;
 234 
		uint32_t atc:1;
251 
	uint32_t cp_mqd_connect_end_ib_rptr;
 235 
		uint32_t mode:2;
252 
	uint32_t reserved_96;
 - 
 
253 
	uint32_t reserved_97;
 - 
 
254 
	uint32_t reserved_98;
 - 
 
255 
	uint32_t reserved_99;
 - 
 
256 
	uint32_t iqtimer_pkt_header;
 - 
 
257 
	uint32_t iqtimer_pkt_dw0;
 - 
 
258 
	uint32_t iqtimer_pkt_dw1;
 - 
 
259 
	uint32_t iqtimer_pkt_dw2;
 - 
 
260 
	uint32_t iqtimer_pkt_dw3;
 - 
 
261 
	uint32_t iqtimer_pkt_dw4;
 - 
 
262 
	uint32_t iqtimer_pkt_dw5;
 - 
 
263 
	uint32_t iqtimer_pkt_dw6;
 236 
		uint32_t valid:1;
264 
	uint32_t reserved_108;
 - 
 
265 
	uint32_t reserved_109;
 - 
 
266 
	uint32_t reserved_110;
 - 
 
267 
	uint32_t reserved_111;
 - 
 
268 
	uint32_t queue_doorbell_id0;
 - 
 
269 
	uint32_t queue_doorbell_id1;
 - 
 
270 
	uint32_t queue_doorbell_id2;
 - 
 
271 
	uint32_t queue_doorbell_id3;
 - 
 
272 
	uint32_t queue_doorbell_id4;
 - 
 
273 
	uint32_t queue_doorbell_id5;
 - 
 
274 
	uint32_t queue_doorbell_id6;
 - 
 
275 
	uint32_t queue_doorbell_id7;
 - 
 
276 
	uint32_t queue_doorbell_id8;
 - 
 
277 
	uint32_t queue_doorbell_id9;
 - 
 
278 
	uint32_t queue_doorbell_id10;
 - 
 
279 
	uint32_t queue_doorbell_id11;
 - 
 
280 
	uint32_t queue_doorbell_id12;
 237 
	} bitfields, bits;
Line 281... Line 238...
281 
	uint32_t queue_doorbell_id13;
 238 
	uint32_t u32All;