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Rev 6938 Rev 7146
Line 2341... Line 2341...
2341 
 * which index in the tiling table we want to use, and the
 2341 
 * which index in the tiling table we want to use, and the
2342 
 * surface uses those parameters (CIK).
 2342 
 * surface uses those parameters (CIK).
2343 
 */
 2343 
 */
2344 
static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 2344 
static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2345 
{
 2345 
{
- 
 
 2346 
	u32 *tile = rdev->config.cik.tile_mode_array;
- 
 
 2347 
	u32 *macrotile = rdev->config.cik.macrotile_mode_array;
2346 
	const u32 num_tile_mode_states = 32;
 2348 
	const u32 num_tile_mode_states =
- 
 
 2349 
			ARRAY_SIZE(rdev->config.cik.tile_mode_array);
2347 
	const u32 num_secondary_tile_mode_states = 16;
 2350 
	const u32 num_secondary_tile_mode_states =
- 
 
 2351 
			ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);
2348 
	u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
 2352 
	u32 reg_offset, split_equal_to_row_size;
2349 
	u32 num_pipe_configs;
 2353 
	u32 num_pipe_configs;
2350 
	u32 num_rbs = rdev->config.cik.max_backends_per_se *
 2354 
	u32 num_rbs = rdev->config.cik.max_backends_per_se *
2351 
		rdev->config.cik.max_shader_engines;
 2355 
		rdev->config.cik.max_shader_engines;
Line 2352... Line 2356...
2352 
 
 2356 
 
Line 2365... Line 2369...
2365 
 
 2369 
 
2366 
	num_pipe_configs = rdev->config.cik.max_tile_pipes;
 2370 
	num_pipe_configs = rdev->config.cik.max_tile_pipes;
2367 
	if (num_pipe_configs > 8)
 2371 
	if (num_pipe_configs > 8)
Line -... Line 2372...
- 
 
 2372 
		num_pipe_configs = 16;
2368 
		num_pipe_configs = 16;
 2373 
 
2369 
 
 2374 
	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2370 
	if (num_pipe_configs == 16) {
 2375 
		tile[reg_offset] = 0;
- 
 
 2376 
	for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
- 
 
 2377 
		macrotile[reg_offset] = 0;
2371 
		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 2378 
 
2372 
			switch (reg_offset) {
 2379 
	switch(num_pipe_configs) {
2373 
			case 0:
 2380 
	case 16:
2374 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2381 
		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2375 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2382 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2376 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2377 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
 - 
 
2378 
				break;
 2383 
			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2379 
			case 1:
 2384 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2380 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2385 
		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2381 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2386 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2382 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2383 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
 - 
 
2384 
				break;
 2387 
			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2385 
			case 2:
 2388 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2386 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2389 
		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2387 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2390 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2388 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2389 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 - 
 
2390 
				break;
 2391 
			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2391 
			case 3:
 2392 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2392 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2393 
		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2393 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2394 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2394 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2395 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
 - 
 
2396 
				break;
 2395 
			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2397 
			case 4:
 2396 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2398 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2397 
		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2399 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2398 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2400 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2401 
						 TILE_SPLIT(split_equal_to_row_size));
 - 
 
2402 
				break;
 2399 
			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2403 
			case 5:
 2400 
			   TILE_SPLIT(split_equal_to_row_size));
2404 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2401 
		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2405 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2406 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 - 
 
2407 
				break;
 2402 
			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2408 
			case 6:
 2403 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2409 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2404 
		tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2410 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2405 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2411 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2412 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 - 
 
2413 
				break;
 2406 
			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2414 
			case 7:
 2407 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2415 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2408 
		tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2416 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2409 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2417 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2418 
						 TILE_SPLIT(split_equal_to_row_size));
 - 
 
2419 
				break;
 2410 
			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2420 
			case 8:
 2411 
			   TILE_SPLIT(split_equal_to_row_size));
2421 
				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 - 
 
2422 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
 - 
 
2423 
				break;
 2412 
		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2424 
			case 9:
 2413 
			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2425 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2414 
		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2426 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2427 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 - 
 
2428 
				break;
 2415 
			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2429 
			case 10:
 2416 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2430 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2417 
		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2431 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2418 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2432 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2433 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2434 
				break;
 2419 
			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2435 
			case 11:
 2420 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2436 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2421 
		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2437 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2422 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2438 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
 - 
 
2439 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2440 
				break;
 2423 
			    PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2441 
			case 12:
 2424 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2442 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2425 
		tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2443 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2426 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2444 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2445 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2446 
				break;
 2427 
			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2447 
			case 13:
 2428 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2448 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2429 
		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2449 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2450 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 - 
 
2451 
				break;
 2430 
			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2452 
			case 14:
 2431 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2453 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2432 
		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2454 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2433 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2455 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2456 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2457 
				break;
 2434 
			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2458 
			case 16:
 2435 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2459 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2436 
		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2460 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2437 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2461 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
 - 
 
2462 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2463 
				break;
 2438 
			    PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2464 
			case 17:
 2439 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2465 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2440 
		tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2466 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2441 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2467 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2468 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2469 
				break;
 2442 
			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2470 
			case 27:
 2443 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2471 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2444 
		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2472 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2473 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 - 
 
2474 
				break;
 2445 
			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2475 
			case 28:
 2446 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2476 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2447 
		tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2477 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2448 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2478 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2479 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2480 
				break;
 2449 
			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2481 
			case 29:
 2450 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2482 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2451 
		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2483 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2452 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2484 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
 - 
 
2485 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2486 
				break;
 2453 
			    PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2487 
			case 30:
 2454 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2488 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2455 
		tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2489 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2456 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2490 
						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 - 
 
2491 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2492 
				break;
 - 
 
2493 
			default:
 - 
 
2494 
				gb_tile_moden = 0;
 - 
 
2495 
				break;
 - 
 
2496 
			}
 - 
 
2497 
			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
 2457 
			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2498 
			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 - 
 
2499 
		}
 - 
 
2500 
		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
 - 
 
2501 
			switch (reg_offset) {
 2458 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2502 
			case 0:
 2459 
 
2503 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2460 
		macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2504 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2461 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2505 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
2506 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2507 
				break;
 2462 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2508 
			case 1:
 2463 
			   NUM_BANKS(ADDR_SURF_16_BANK));
2509 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2464 
		macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2510 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2465 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2511 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
2512 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2513 
				break;
 2466 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2514 
			case 2:
 2467 
			   NUM_BANKS(ADDR_SURF_16_BANK));
2515 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2468 
		macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2516 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2469 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2517 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2518 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2519 
				break;
 2470 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2520 
			case 3:
 2471 
			   NUM_BANKS(ADDR_SURF_16_BANK));
2521 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2472 
		macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2522 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2473 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2523 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2524 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2525 
				break;
 2474 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2526 
			case 4:
 2475 
			   NUM_BANKS(ADDR_SURF_16_BANK));
2527 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2476 
		macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2528 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2477 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2529 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2530 
						 NUM_BANKS(ADDR_SURF_8_BANK));
 - 
 
2531 
				break;
 2478 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2532 
			case 5:
 2479 
			   NUM_BANKS(ADDR_SURF_8_BANK));
2533 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2480 
		macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2534 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2481 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2535 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2536 
						 NUM_BANKS(ADDR_SURF_4_BANK));
 - 
 
2537 
				break;
 2482 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2538 
			case 6:
 2483 
			   NUM_BANKS(ADDR_SURF_4_BANK));
2539 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2484 
		macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2540 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2485 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2541 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2542 
						 NUM_BANKS(ADDR_SURF_2_BANK));
 - 
 
2543 
				break;
 2486 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2544 
			case 8:
 2487 
			   NUM_BANKS(ADDR_SURF_2_BANK));
2545 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2488 
		macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2546 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2489 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2547 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
2548 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2549 
				break;
 2490 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2550 
			case 9:
 2491 
			   NUM_BANKS(ADDR_SURF_16_BANK));
2551 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2492 
		macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2552 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2493 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2553 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
2554 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2555 
				break;
 2494 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2556 
			case 10:
 2495 
			   NUM_BANKS(ADDR_SURF_16_BANK));
2557 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2496 
		macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2558 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2497 
			    BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2559 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2560 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2561 
				break;
 2498 
			    MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2562 
			case 11:
 2499 
			    NUM_BANKS(ADDR_SURF_16_BANK));
2563 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2500 
		macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2564 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2501 
			    BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2565 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2566 
						 NUM_BANKS(ADDR_SURF_8_BANK));
 - 
 
2567 
				break;
 2502 
			    MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2568 
			case 12:
 2503 
			    NUM_BANKS(ADDR_SURF_8_BANK));
2569 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2504 
		macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2570 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2505 
			    BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2571 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2572 
						 NUM_BANKS(ADDR_SURF_4_BANK));
 - 
 
2573 
				break;
 2506 
			    MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2574 
			case 13:
 2507 
			    NUM_BANKS(ADDR_SURF_4_BANK));
2575 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2508 
		macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2576 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2509 
			    BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2577 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2578 
						 NUM_BANKS(ADDR_SURF_2_BANK));
 - 
 
2579 
				break;
 2510 
			    MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2580 
			case 14:
 2511 
			    NUM_BANKS(ADDR_SURF_2_BANK));
2581 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2512 
		macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2582 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2513 
			    BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- 
 
 2514 
			    MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- 
 
 2515 
			    NUM_BANKS(ADDR_SURF_2_BANK));
- 
 
 2516 
 
- 
 
 2517 
		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
- 
 
 2518 
			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2583 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 2519 
		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2584 
						 NUM_BANKS(ADDR_SURF_2_BANK));
 - 
 
2585 
				break;
 - 
 
2586 
			default:
 - 
 
2587 
				gb_tile_moden = 0;
 - 
 
2588 
				break;
 - 
 
2589 
			}
 - 
 
2590 
			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
 2520 
			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2591 
			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 - 
 
2592 
		}
 - 
 
2593 
	} else if (num_pipe_configs == 8) {
 - 
 
2594 
		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 2521 
		break;
2595 
			switch (reg_offset) {
 2522 
 
2596 
			case 0:
 2523 
	case 8:
2597 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2524 
		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2598 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2525 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2599 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2600 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
 - 
 
2601 
				break;
 2526 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2602 
			case 1:
 2527 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2603 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2528 
		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2604 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2529 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2605 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2606 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
 - 
 
2607 
				break;
 2530 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2608 
			case 2:
 2531 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2609 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2532 
		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2610 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2533 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2611 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2612 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 - 
 
2613 
				break;
 2534 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2614 
			case 3:
 2535 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2615 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2536 
		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2616 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2537 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2617 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2618 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
 - 
 
2619 
				break;
 2538 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2620 
			case 4:
 2539 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2621 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2540 
		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2622 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2541 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2623 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2624 
						 TILE_SPLIT(split_equal_to_row_size));
 - 
 
2625 
				break;
 2542 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2626 
			case 5:
 2543 
			   TILE_SPLIT(split_equal_to_row_size));
2627 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2544 
		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2628 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2629 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 - 
 
2630 
				break;
 2545 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2631 
			case 6:
 2546 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2632 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2547 
		tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2633 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2548 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2634 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2635 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 - 
 
2636 
				break;
 2549 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2637 
			case 7:
 2550 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2638 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2551 
		tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2639 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2552 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2640 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2641 
						 TILE_SPLIT(split_equal_to_row_size));
 - 
 
2642 
				break;
 2553 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2643 
			case 8:
 2554 
			   TILE_SPLIT(split_equal_to_row_size));
2644 
				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 - 
 
2645 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
 - 
 
2646 
				break;
 2555 
		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2647 
			case 9:
 2556 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2648 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2557 
		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2649 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2650 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 - 
 
2651 
				break;
 2558 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2652 
			case 10:
 2559 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2653 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2560 
		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2654 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2561 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2655 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2656 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2657 
				break;
 2562 
			    PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2658 
			case 11:
 2563 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2659 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2564 
		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2660 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2565 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2661 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 - 
 
2662 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2663 
				break;
 2566 
			    PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2664 
			case 12:
 2567 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2665 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2568 
		tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2666 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2569 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2667 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2668 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2669 
				break;
 2570 
			    PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2670 
			case 13:
 2571 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2671 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2572 
		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2672 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2673 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 - 
 
2674 
				break;
 2573 
			    PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2675 
			case 14:
 2574 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2676 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2575 
		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2677 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2576 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2678 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2679 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2680 
				break;
 2577 
			    PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2681 
			case 16:
 2578 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2682 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2579 
		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2683 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2580 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2684 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 - 
 
2685 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2686 
				break;
 2581 
			    PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2687 
			case 17:
 2582 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2688 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2583 
		tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2689 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2584 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2690 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2691 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2692 
				break;
 2585 
			    PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2693 
			case 27:
 2586 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2694 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2587 
		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2695 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2696 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 - 
 
2697 
				break;
 2588 
			    PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2698 
			case 28:
 2589 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2699 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2590 
		tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2700 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2591 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2701 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2702 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2703 
				break;
 2592 
			    PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2704 
			case 29:
 2593 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2705 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2594 
		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2706 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2595 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2707 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 - 
 
2708 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2709 
				break;
 2596 
			    PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2710 
			case 30:
 2597 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2711 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2598 
		tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2712 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2599 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2713 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 - 
 
2714 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2715 
				break;
 - 
 
2716 
			default:
 - 
 
2717 
				gb_tile_moden = 0;
 - 
 
2718 
				break;
 - 
 
2719 
			}
 - 
 
2720 
			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
 2600 
			    PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2721 
			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 - 
 
2722 
		}
 - 
 
2723 
		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
 - 
 
2724 
			switch (reg_offset) {
 2601 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2725 
			case 0:
 2602 
 
2726 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2603 
		macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2727 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2604 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2728 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
2729 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2730 
				break;
 2605 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2731 
			case 1:
 2606 
				NUM_BANKS(ADDR_SURF_16_BANK));
2732 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2607 
		macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2733 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2608 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2734 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
2735 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2736 
				break;
 2609 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2737 
			case 2:
 2610 
				NUM_BANKS(ADDR_SURF_16_BANK));
2738 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2611 
		macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2739 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2612 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2740 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
2741 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2742 
				break;
 2613 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2743 
			case 3:
 2614 
				NUM_BANKS(ADDR_SURF_16_BANK));
2744 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2615 
		macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2745 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2616 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2746 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
2747 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2748 
				break;
 2617 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2749 
			case 4:
 2618 
				NUM_BANKS(ADDR_SURF_16_BANK));
2750 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2619 
		macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2751 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2620 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2752 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2753 
						 NUM_BANKS(ADDR_SURF_8_BANK));
 - 
 
2754 
				break;
 2621 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2755 
			case 5:
 2622 
				NUM_BANKS(ADDR_SURF_8_BANK));
2756 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2623 
		macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2757 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2624 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2758 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2759 
						 NUM_BANKS(ADDR_SURF_4_BANK));
 - 
 
2760 
				break;
 2625 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2761 
			case 6:
 2626 
				NUM_BANKS(ADDR_SURF_4_BANK));
2762 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2627 
		macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2763 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2628 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2764 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2765 
						 NUM_BANKS(ADDR_SURF_2_BANK));
 - 
 
2766 
				break;
 2629 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2767 
			case 8:
 2630 
				NUM_BANKS(ADDR_SURF_2_BANK));
2768 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2631 
		macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2769 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
 2632 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2770 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
2771 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2772 
				break;
 2633 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2773 
			case 9:
 2634 
				NUM_BANKS(ADDR_SURF_16_BANK));
2774 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2635 
		macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2775 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2636 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2776 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
2777 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2778 
				break;
 2637 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2779 
			case 10:
 2638 
				NUM_BANKS(ADDR_SURF_16_BANK));
2780 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2639 
		macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2781 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2640 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2782 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
2783 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2784 
				break;
 2641 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2785 
			case 11:
 2642 
				NUM_BANKS(ADDR_SURF_16_BANK));
2786 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2643 
		macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2787 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2644 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2788 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
2789 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
2790 
				break;
 2645 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2791 
			case 12:
 2646 
				NUM_BANKS(ADDR_SURF_16_BANK));
2792 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2647 
		macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2793 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2648 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2794 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2795 
						 NUM_BANKS(ADDR_SURF_8_BANK));
 - 
 
2796 
				break;
 2649 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2797 
			case 13:
 2650 
				NUM_BANKS(ADDR_SURF_8_BANK));
2798 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2651 
		macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2799 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2652 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2800 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
2801 
						 NUM_BANKS(ADDR_SURF_4_BANK));
 - 
 
2802 
				break;
 2653 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2803 
			case 14:
 2654 
				NUM_BANKS(ADDR_SURF_4_BANK));
2804 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2655 
		macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2805 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2656 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- 
 
 2657 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- 
 
 2658 
				NUM_BANKS(ADDR_SURF_2_BANK));
- 
 
 2659 
 
- 
 
 2660 
		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
- 
 
 2661 
			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2806 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 2662 
		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2807 
						 NUM_BANKS(ADDR_SURF_2_BANK));
 - 
 
2808 
				break;
 - 
 
2809 
			default:
 - 
 
2810 
				gb_tile_moden = 0;
 2663 
			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2811 
				break;
 - 
 
2812 
			}
 - 
 
2813 
			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
 2664 
		break;
2814 
			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 - 
 
2815 
		}
 2665 
 
2816 
	} else if (num_pipe_configs == 4) {
 - 
 
2817 
		if (num_rbs == 4) {
 - 
 
2818 
			for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 - 
 
2819 
				switch (reg_offset) {
 2666 
	case 4:
2820 
				case 0:
 2667 
		if (num_rbs == 4) {
2821 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2668 
		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2822 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2669 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2823 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2824 
							 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
 - 
 
2825 
					break;
 2670 
			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2826 
				case 1:
 2671 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2827 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2672 
		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2828 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2673 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2829 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2830 
							 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
 - 
 
2831 
					break;
 2674 
			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2832 
				case 2:
 2675 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2833 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2676 
		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2834 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2677 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2835 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2836 
							 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 - 
 
2837 
					break;
 2678 
			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2838 
				case 3:
 2679 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2839 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2680 
		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2840 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2681 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2841 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2842 
							 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
 - 
 
2843 
					break;
 2682 
			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2844 
				case 4:
 2683 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2845 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2684 
		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2846 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2685 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2847 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2848 
							 TILE_SPLIT(split_equal_to_row_size));
 - 
 
2849 
					break;
 2686 
			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2850 
				case 5:
 2687 
			   TILE_SPLIT(split_equal_to_row_size));
2851 
					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2688 
		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2852 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2853 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 - 
 
2854 
					break;
 2689 
			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2855 
				case 6:
 2690 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2856 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2691 
		tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2857 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2692 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2858 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2859 
							 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 - 
 
2860 
					break;
 2693 
			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2861 
				case 7:
 2694 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2862 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2695 
		tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2863 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2696 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2864 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2865 
							 TILE_SPLIT(split_equal_to_row_size));
 - 
 
2866 
					break;
 2697 
			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2867 
				case 8:
 2698 
			   TILE_SPLIT(split_equal_to_row_size));
2868 
					gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 - 
 
2869 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16));
 - 
 
2870 
					break;
 2699 
		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2871 
				case 9:
 2700 
			   PIPE_CONFIG(ADDR_SURF_P4_16x16));
2872 
					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2701 
		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2873 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2874 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 - 
 
2875 
					break;
 2702 
			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2876 
				case 10:
 2703 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2877 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2704 
		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2878 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2705 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2879 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2880 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2881 
					break;
 2706 
			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2882 
				case 11:
 2707 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2883 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2708 
		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2884 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2709 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2885 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
2886 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2887 
					break;
 2710 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2888 
				case 12:
 2711 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2889 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2712 
		tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2890 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2713 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2891 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2892 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2893 
					break;
 2714 
			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2894 
				case 13:
 2715 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2895 
					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2716 
		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2896 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2897 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 - 
 
2898 
					break;
 2717 
			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2899 
				case 14:
 2718 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2900 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2719 
		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2901 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2720 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2902 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2903 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2904 
					break;
 2721 
			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2905 
				case 16:
 2722 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2906 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2723 
		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2907 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2724 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2908 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
2909 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2910 
					break;
 2725 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2911 
				case 17:
 2726 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2912 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2727 
		tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2913 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2728 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2914 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2915 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2916 
					break;
 2729 
			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2917 
				case 27:
 2730 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2918 
					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2731 
		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2919 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2920 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 - 
 
2921 
					break;
 2732 
			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2922 
				case 28:
 2733 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2923 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2734 
		tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2924 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2735 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2925 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2926 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2927 
					break;
 2736 
			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2928 
				case 29:
 2737 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2929 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2738 
		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2930 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2739 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2931 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
2932 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2933 
					break;
 2740 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2934 
				case 30:
 2741 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2935 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2742 
		tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2936 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2743 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2937 
							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 - 
 
2938 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
2939 
					break;
 - 
 
2940 
				default:
 - 
 
2941 
					gb_tile_moden = 0;
 - 
 
2942 
					break;
 - 
 
2943 
				}
 - 
 
2944 
				rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
 2744 
			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2945 
				WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 2745 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2946 
			}
 - 
 
2947 
		} else if (num_rbs < 4) {
 - 
 
2948 
			for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 - 
 
2949 
				switch (reg_offset) {
 2746 
 
2950 
				case 0:
 2747 
		} else if (num_rbs < 4) {
2951 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2748 
		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2952 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2749 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2953 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
2954 
							 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
 - 
 
2955 
					break;
 2750 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2956 
				case 1:
 2751 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2957 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2752 
		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2958 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2753 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2959 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
2960 
							 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
 - 
 
2961 
					break;
 2754 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2962 
				case 2:
 2755 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2963 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2756 
		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2964 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2757 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2965 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
2966 
							 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 - 
 
2967 
					break;
 2758 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2968 
				case 3:
 2759 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2969 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2760 
		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2970 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2761 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2971 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
2972 
							 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
 - 
 
2973 
					break;
 2762 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2974 
				case 4:
 2763 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2975 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2764 
		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2976 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2765 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2977 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
2978 
							 TILE_SPLIT(split_equal_to_row_size));
 - 
 
2979 
					break;
 2766 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2980 
				case 5:
 2767 
			   TILE_SPLIT(split_equal_to_row_size));
2981 
					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2768 
		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2982 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
2983 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 - 
 
2984 
					break;
 2769 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2985 
				case 6:
 2770 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2986 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2771 
		tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2987 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2772 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2988 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
2989 
							 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 - 
 
2990 
					break;
 2773 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2991 
				case 7:
 2774 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2992 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2775 
		tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2993 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2776 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2994 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
2995 
							 TILE_SPLIT(split_equal_to_row_size));
 - 
 
2996 
					break;
 2777 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2997 
				case 8:
 2778 
			   TILE_SPLIT(split_equal_to_row_size));
2998 
					gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 - 
 
2999 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16));
 - 
 
3000 
					break;
 2779 
		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3001 
				case 9:
 2780 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16));
3002 
					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2781 
		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3003 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
3004 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 - 
 
3005 
					break;
 2782 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3006 
				case 10:
 2783 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
3007 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2784 
		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3008 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2785 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3009 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
3010 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3011 
					break;
 2786 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3012 
				case 11:
 2787 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3013 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2788 
		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3014 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2789 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3015 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
3016 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3017 
					break;
 2790 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3018 
				case 12:
 2791 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3019 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2792 
		tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3020 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2793 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3021 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
3022 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3023 
					break;
 2794 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3024 
				case 13:
 2795 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3025 
					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2796 
		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3026 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
3027 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 - 
 
3028 
					break;
 2797 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3029 
				case 14:
 2798 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
3030 
					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2799 
		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3031 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2800 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3032 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
3033 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3034 
					break;
 2801 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3035 
				case 16:
 2802 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3036 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2803 
		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3037 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2804 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3038 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
3039 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3040 
					break;
 2805 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3041 
				case 17:
 2806 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3042 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2807 
		tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3043 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2808 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3044 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
3045 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3046 
					break;
 2809 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3047 
				case 27:
 2810 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3048 
					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2811 
		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3049 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
3050 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 - 
 
3051 
					break;
 2812 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3052 
				case 28:
 2813 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
3053 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2814 
		tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3054 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2815 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3055 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
3056 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3057 
					break;
 2816 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3058 
				case 29:
 2817 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3059 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2818 
		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3060 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2819 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3061 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
3062 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3063 
					break;
 2820 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3064 
				case 30:
 2821 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3065 
					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2822 
		tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3066 
							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2823 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3067 
							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 - 
 
3068 
							 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3069 
					break;
 - 
 
3070 
				default:
 - 
 
3071 
					gb_tile_moden = 0;
 - 
 
3072 
					break;
 - 
 
3073 
				}
 - 
 
3074 
				rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
 2824 
			    PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3075 
				WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 2825 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3076 
			}
 - 
 
3077 
		}
 - 
 
3078 
		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
 - 
 
3079 
			switch (reg_offset) {
 2826 
		}
3080 
			case 0:
 2827 
 
3081 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2828 
		macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3082 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2829 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3083 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3084 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3085 
				break;
 2830 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3086 
			case 1:
 2831 
				NUM_BANKS(ADDR_SURF_16_BANK));
3087 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2832 
		macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3088 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2833 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3089 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3090 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3091 
				break;
 2834 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3092 
			case 2:
 2835 
				NUM_BANKS(ADDR_SURF_16_BANK));
3093 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2836 
		macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3094 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2837 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3095 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
3096 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3097 
				break;
 2838 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3098 
			case 3:
 2839 
				NUM_BANKS(ADDR_SURF_16_BANK));
3099 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2840 
		macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3100 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2841 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3101 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
3102 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3103 
				break;
 2842 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3104 
			case 4:
 2843 
				NUM_BANKS(ADDR_SURF_16_BANK));
3105 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2844 
		macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3106 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2845 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3107 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
3108 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3109 
				break;
 2846 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3110 
			case 5:
 2847 
				NUM_BANKS(ADDR_SURF_16_BANK));
3111 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2848 
		macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3112 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2849 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3113 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
3114 
						 NUM_BANKS(ADDR_SURF_8_BANK));
 - 
 
3115 
				break;
 2850 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3116 
			case 6:
 2851 
				NUM_BANKS(ADDR_SURF_8_BANK));
3117 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2852 
		macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3118 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2853 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3119 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 - 
 
3120 
						 NUM_BANKS(ADDR_SURF_4_BANK));
 - 
 
3121 
				break;
 2854 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3122 
			case 8:
 2855 
				NUM_BANKS(ADDR_SURF_4_BANK));
3123 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 2856 
		macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3124 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
 2857 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3125 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3126 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3127 
				break;
 2858 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3128 
			case 9:
 2859 
				NUM_BANKS(ADDR_SURF_16_BANK));
3129 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 2860 
		macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3130 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2861 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3131 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3132 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3133 
				break;
 2862 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3134 
			case 10:
 2863 
				NUM_BANKS(ADDR_SURF_16_BANK));
3135 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2864 
		macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3136 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2865 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3137 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3138 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3139 
				break;
 2866 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3140 
			case 11:
 2867 
				NUM_BANKS(ADDR_SURF_16_BANK));
3141 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2868 
		macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3142 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2869 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3143 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3144 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3145 
				break;
 2870 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3146 
			case 12:
 2871 
				NUM_BANKS(ADDR_SURF_16_BANK));
3147 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2872 
		macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3148 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2873 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3149 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
3150 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3151 
				break;
 2874 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3152 
			case 13:
 2875 
				NUM_BANKS(ADDR_SURF_16_BANK));
3153 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2876 
		macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3154 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2877 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3155 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
3156 
						 NUM_BANKS(ADDR_SURF_8_BANK));
 - 
 
3157 
				break;
 2878 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3158 
			case 14:
 2879 
				NUM_BANKS(ADDR_SURF_8_BANK));
3159 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2880 
		macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3160 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2881 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- 
 
 2882 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- 
 
 2883 
				NUM_BANKS(ADDR_SURF_4_BANK));
- 
 
 2884 
 
- 
 
 2885 
		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
- 
 
 2886 
			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
3161 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 2887 
		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3162 
						 NUM_BANKS(ADDR_SURF_4_BANK));
 - 
 
3163 
				break;
 - 
 
3164 
			default:
 - 
 
3165 
				gb_tile_moden = 0;
 - 
 
3166 
				break;
 - 
 
3167 
			}
 - 
 
3168 
			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
 2888 
			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
3169 
			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 - 
 
3170 
		}
 - 
 
3171 
	} else if (num_pipe_configs == 2) {
 - 
 
3172 
		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 2889 
		break;
3173 
			switch (reg_offset) {
 2890 
 
3174 
			case 0:
 2891 
	case 2:
3175 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2892 
		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3176 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2893 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3177 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3178 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
 - 
 
3179 
				break;
 2894 
			   PIPE_CONFIG(ADDR_SURF_P2) |
3180 
			case 1:
 2895 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
3181 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2896 
		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3182 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2897 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3183 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3184 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
 - 
 
3185 
				break;
 2898 
			   PIPE_CONFIG(ADDR_SURF_P2) |
3186 
			case 2:
 2899 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
3187 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2900 
		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3188 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2901 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3189 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3190 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 - 
 
3191 
				break;
 2902 
			   PIPE_CONFIG(ADDR_SURF_P2) |
3192 
			case 3:
 2903 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
3193 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2904 
		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3194 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2905 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3195 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3196 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
 - 
 
3197 
				break;
 2906 
			   PIPE_CONFIG(ADDR_SURF_P2) |
3198 
			case 4:
 2907 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
3199 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2908 
		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3200 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2909 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3201 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3202 
						 TILE_SPLIT(split_equal_to_row_size));
 - 
 
3203 
				break;
 2910 
			   PIPE_CONFIG(ADDR_SURF_P2) |
3204 
			case 5:
 2911 
			   TILE_SPLIT(split_equal_to_row_size));
3205 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2912 
		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3206 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3207 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 - 
 
3208 
				break;
 2913 
			   PIPE_CONFIG(ADDR_SURF_P2) |
3209 
			case 6:
 2914 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3210 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2915 
		tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3211 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2916 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3212 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3213 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 - 
 
3214 
				break;
 2917 
			   PIPE_CONFIG(ADDR_SURF_P2) |
3215 
			case 7:
 2918 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
3216 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2919 
		tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3217 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 2920 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3218 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3219 
						 TILE_SPLIT(split_equal_to_row_size));
 - 
 
3220 
				break;
 2921 
			   PIPE_CONFIG(ADDR_SURF_P2) |
3221 
			case 8:
 2922 
			   TILE_SPLIT(split_equal_to_row_size));
3222 
				gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 - 
 
3223 
						PIPE_CONFIG(ADDR_SURF_P2);
 - 
 
3224 
				break;
 2923 
		tile[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3225 
			case 9:
 2924 
			   PIPE_CONFIG(ADDR_SURF_P2);
3226 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2925 
		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3227 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 - 
 
3228 
						 PIPE_CONFIG(ADDR_SURF_P2));
 - 
 
3229 
				break;
 2926 
			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3230 
			case 10:
 2927 
			   PIPE_CONFIG(ADDR_SURF_P2));
3231 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2928 
		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3232 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2929 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3233 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3234 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3235 
				break;
 2930 
			    PIPE_CONFIG(ADDR_SURF_P2) |
3236 
			case 11:
 2931 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3237 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2932 
		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3238 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2933 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3239 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3240 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3241 
				break;
 2934 
			    PIPE_CONFIG(ADDR_SURF_P2) |
3242 
			case 12:
 2935 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3243 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2936 
		tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3244 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2937 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3245 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3246 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3247 
				break;
 2938 
			    PIPE_CONFIG(ADDR_SURF_P2) |
3248 
			case 13:
 2939 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3249 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2940 
		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3250 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3251 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 - 
 
3252 
				break;
 2941 
			    PIPE_CONFIG(ADDR_SURF_P2) |
3253 
			case 14:
 2942 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
3254 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2943 
		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3255 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2944 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3256 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3257 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3258 
				break;
 2945 
			    PIPE_CONFIG(ADDR_SURF_P2) |
3259 
			case 16:
 2946 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3260 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2947 
		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3261 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2948 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3262 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3263 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3264 
				break;
 2949 
			    PIPE_CONFIG(ADDR_SURF_P2) |
3265 
			case 17:
 2950 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3266 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2951 
		tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3267 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 2952 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3268 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3269 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3270 
				break;
 2953 
			    PIPE_CONFIG(ADDR_SURF_P2) |
3271 
			case 27:
 2954 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3272 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2955 
		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3273 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 - 
 
3274 
						 PIPE_CONFIG(ADDR_SURF_P2));
 - 
 
3275 
				break;
 2956 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3276 
			case 28:
 2957 
			    PIPE_CONFIG(ADDR_SURF_P2));
3277 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2958 
		tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3278 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2959 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3279 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3280 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3281 
				break;
 2960 
			    PIPE_CONFIG(ADDR_SURF_P2) |
3282 
			case 29:
 2961 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3283 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 2962 
		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3284 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2963 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3285 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3286 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3287 
				break;
 2964 
			    PIPE_CONFIG(ADDR_SURF_P2) |
3288 
			case 30:
 2965 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3289 
				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 2966 
		tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3290 
						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 2967 
			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3291 
						 PIPE_CONFIG(ADDR_SURF_P2) |
 - 
 
3292 
						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 - 
 
3293 
				break;
 - 
 
3294 
			default:
 - 
 
3295 
				gb_tile_moden = 0;
 - 
 
3296 
				break;
 - 
 
3297 
			}
 - 
 
3298 
			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
 2968 
			    PIPE_CONFIG(ADDR_SURF_P2) |
3299 
			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 - 
 
3300 
		}
 - 
 
3301 
		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
 - 
 
3302 
			switch (reg_offset) {
 2969 
			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3303 
			case 0:
 2970 
 
3304 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 2971 
		macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3305 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2972 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3306 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3307 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3308 
				break;
 2973 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3309 
			case 1:
 2974 
				NUM_BANKS(ADDR_SURF_16_BANK));
3310 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 2975 
		macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3311 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2976 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3312 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3313 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3314 
				break;
 2977 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3315 
			case 2:
 2978 
				NUM_BANKS(ADDR_SURF_16_BANK));
3316 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2979 
		macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3317 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2980 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3318 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3319 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3320 
				break;
 2981 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3321 
			case 3:
 2982 
				NUM_BANKS(ADDR_SURF_16_BANK));
3322 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2983 
		macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3323 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2984 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3324 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3325 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3326 
				break;
 2985 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3327 
			case 4:
 2986 
				NUM_BANKS(ADDR_SURF_16_BANK));
3328 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2987 
		macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3329 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2988 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3330 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3331 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3332 
				break;
 2989 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3333 
			case 5:
 2990 
				NUM_BANKS(ADDR_SURF_16_BANK));
3334 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2991 
		macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3335 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2992 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3336 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3337 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3338 
				break;
 2993 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3339 
			case 6:
 2994 
				NUM_BANKS(ADDR_SURF_16_BANK));
3340 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2995 
		macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3341 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2996 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3342 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 - 
 
3343 
						 NUM_BANKS(ADDR_SURF_8_BANK));
 - 
 
3344 
				break;
 2997 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3345 
			case 8:
 2998 
				NUM_BANKS(ADDR_SURF_8_BANK));
3346 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
 2999 
		macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3347 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
 3000 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3348 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3349 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3350 
				break;
 3001 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3351 
			case 9:
 3002 
				NUM_BANKS(ADDR_SURF_16_BANK));
3352 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
 3003 
		macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3353 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 3004 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3354 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3355 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3356 
				break;
 3005 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3357 
			case 10:
 3006 
				NUM_BANKS(ADDR_SURF_16_BANK));
3358 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 3007 
		macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3359 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 3008 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3360 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3361 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3362 
				break;
 3009 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3363 
			case 11:
 3010 
				NUM_BANKS(ADDR_SURF_16_BANK));
3364 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 3011 
		macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3365 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 3012 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3366 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3367 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3368 
				break;
 3013 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3369 
			case 12:
 3014 
				NUM_BANKS(ADDR_SURF_16_BANK));
3370 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 3015 
		macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3371 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 3016 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3372 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3373 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3374 
				break;
 3017 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3375 
			case 13:
 3018 
				NUM_BANKS(ADDR_SURF_16_BANK));
3376 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 3019 
		macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3377 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 3020 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3378 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 - 
 
3379 
						 NUM_BANKS(ADDR_SURF_16_BANK));
 - 
 
3380 
				break;
 3021 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3381 
			case 14:
 3022 
				NUM_BANKS(ADDR_SURF_16_BANK));
3382 
				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 3023 
		macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3383 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 3024 
				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- 
 
 3025 
				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- 
 
 3026 
				NUM_BANKS(ADDR_SURF_8_BANK));
- 
 
 3027 
 
- 
 
 3028 
		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
- 
 
 3029 
			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
3384 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 3030 
		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
- 
 
 3031 
			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
3385 
						 NUM_BANKS(ADDR_SURF_8_BANK));
 3032 
		break;
3386 
				break;
 - 
 
3387 
			default:
 - 
 
3388 
				gb_tile_moden = 0;
 - 
 
3389 
				break;
 - 
 
3390 
			}
 - 
 
3391 
			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
 - 
 
3392 
			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 - 
 
3393 
		}
 3033 
 
3394 
	} else
 3034 
	default:
- 
 
 3035 
		DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
Line 3395... Line 3036...
3395 
		DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
 3036 
	}
3396 
}
 3037 
}
3397 
 
 3038 
 
3398 
/**
 3039 
/**
Line 4217... Line 3858...
4217 
		radeon_scratch_free(rdev, scratch);
 3858 
		radeon_scratch_free(rdev, scratch);
4218 
		radeon_ib_free(rdev, &ib);
 3859 
		radeon_ib_free(rdev, &ib);
4219 
		DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
 3860 
		DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
4220 
		return r;
 3861 
		return r;
4221 
	}
 3862 
	}
4222 
	r = radeon_fence_wait(ib.fence, false);
 3863 
	r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
- 
 
 3864 
		RADEON_USEC_IB_TEST_TIMEOUT));
4223 
	if (r) {
 3865 
	if (r < 0) {
4224 
		DRM_ERROR("radeon: fence wait failed (%d).\n", r);
 3866 
		DRM_ERROR("radeon: fence wait failed (%d).\n", r);
4225 
		radeon_scratch_free(rdev, scratch);
 3867 
		radeon_scratch_free(rdev, scratch);
4226 
		radeon_ib_free(rdev, &ib);
 3868 
		radeon_ib_free(rdev, &ib);
4227 
		return r;
 3869 
		return r;
- 
 
 3870 
	} else if (r == 0) {
- 
 
 3871 
		DRM_ERROR("radeon: fence wait timed out.\n");
- 
 
 3872 
		radeon_scratch_free(rdev, scratch);
- 
 
 3873 
		radeon_ib_free(rdev, &ib);
- 
 
 3874 
		return -ETIMEDOUT;
4228 
	}
 3875 
	}
- 
 
 3876 
	r = 0;
4229 
	for (i = 0; i < rdev->usec_timeout; i++) {
 3877 
	for (i = 0; i < rdev->usec_timeout; i++) {
4230 
		tmp = RREG32(scratch);
 3878 
		tmp = RREG32(scratch);
4231 
		if (tmp == 0xDEADBEEF)
 3879 
		if (tmp == 0xDEADBEEF)
4232 
			break;
 3880 
			break;
4233 
		DRM_UDELAY(1);
 3881 
		DRM_UDELAY(1);