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| Rev 5078 | Rev 5271 | ||
|---|---|---|---|
| Line 31... | Line 31... | ||
| 31 | #define SMU__NUM_PCIE_DPM_LEVELS 8 |
31 | #define SMU__NUM_PCIE_DPM_LEVELS 8 |
| 32 | #include "smu7_discrete.h" |
32 | #include "smu7_discrete.h" |
| Line 33... | Line 33... | ||
| 33 | 33 | ||
| Line -... | Line 34... | ||
| - | 34 | #define CISLANDS_MAX_HARDWARE_POWERLEVELS 2 |
|
| - | 35 | ||
| 34 | #define CISLANDS_MAX_HARDWARE_POWERLEVELS 2 |
36 | #define CISLANDS_UNUSED_GPIO_PIN 0x7F |
| 35 | 37 | ||
| 36 | struct ci_pl { |
38 | struct ci_pl { |
| 37 | u32 mclk; |
39 | u32 mclk; |
| 38 | u32 sclk; |
40 | u32 sclk; |
| Line 235... | Line 237... | ||
| 235 | struct ci_dpm_level_enable_mask dpm_level_enable_mask; |
237 | struct ci_dpm_level_enable_mask dpm_level_enable_mask; |
| 236 | u32 need_update_smu7_dpm_table; |
238 | u32 need_update_smu7_dpm_table; |
| 237 | u32 sclk_dpm_key_disabled; |
239 | u32 sclk_dpm_key_disabled; |
| 238 | u32 mclk_dpm_key_disabled; |
240 | u32 mclk_dpm_key_disabled; |
| 239 | u32 pcie_dpm_key_disabled; |
241 | u32 pcie_dpm_key_disabled; |
| - | 242 | u32 thermal_sclk_dpm_enabled; |
|
| 240 | struct ci_pcie_perf_range pcie_gen_performance; |
243 | struct ci_pcie_perf_range pcie_gen_performance; |
| 241 | struct ci_pcie_perf_range pcie_lane_performance; |
244 | struct ci_pcie_perf_range pcie_lane_performance; |
| 242 | struct ci_pcie_perf_range pcie_gen_powersaving; |
245 | struct ci_pcie_perf_range pcie_gen_powersaving; |
| 243 | struct ci_pcie_perf_range pcie_lane_powersaving; |
246 | struct ci_pcie_perf_range pcie_lane_powersaving; |
| 244 | u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS]; |
247 | u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS]; |
| Line 262... | Line 265... | ||
| 262 | bool caps_samu_dpm; |
265 | bool caps_samu_dpm; |
| 263 | bool caps_acp_dpm; |
266 | bool caps_acp_dpm; |
| 264 | bool caps_automatic_dc_transition; |
267 | bool caps_automatic_dc_transition; |
| 265 | bool caps_sclk_throttle_low_notification; |
268 | bool caps_sclk_throttle_low_notification; |
| 266 | bool caps_dynamic_ac_timing; |
269 | bool caps_dynamic_ac_timing; |
| - | 270 | bool caps_od_fuzzy_fan_control_support; |
|
| 267 | /* flags */ |
271 | /* flags */ |
| 268 | bool thermal_protection; |
272 | bool thermal_protection; |
| 269 | bool pcie_performance_request; |
273 | bool pcie_performance_request; |
| 270 | bool dynamic_ss; |
274 | bool dynamic_ss; |
| 271 | bool dll_default_on; |
275 | bool dll_default_on; |
| Line 283... | Line 287... | ||
| 283 | /* driver states */ |
287 | /* driver states */ |
| 284 | struct radeon_ps current_rps; |
288 | struct radeon_ps current_rps; |
| 285 | struct ci_ps current_ps; |
289 | struct ci_ps current_ps; |
| 286 | struct radeon_ps requested_rps; |
290 | struct radeon_ps requested_rps; |
| 287 | struct ci_ps requested_ps; |
291 | struct ci_ps requested_ps; |
| - | 292 | /* fan control */ |
|
| - | 293 | bool fan_ctrl_is_in_default_mode; |
|
| - | 294 | u32 t_min; |
|
| - | 295 | u32 fan_ctrl_default_mode; |
|
| 288 | }; |
296 | }; |
| Line 289... | Line 297... | ||
| 289 | 297 | ||
| 290 | #define CISLANDS_VOLTAGE_CONTROL_NONE 0x0 |
298 | #define CISLANDS_VOLTAGE_CONTROL_NONE 0x0 |
| 291 | #define CISLANDS_VOLTAGE_CONTROL_BY_GPIO 0x1 |
299 | #define CISLANDS_VOLTAGE_CONTROL_BY_GPIO 0x1 |