Rev 6104 | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 6104 | Rev 7146 | ||
|---|---|---|---|
| Line 1161... | Line 1161... | ||
| 1161 | 55000, 60000, 65000, 70000, 75000, 80000, 85000, 90000, 95000, 100000, |
1161 | 55000, 60000, 65000, 70000, 75000, 80000, 85000, 90000, 95000, 100000, |
| 1162 | 105000, 110000, 11500, 120000, 125000, 130000, 135000, 140000, 145000, 150000, |
1162 | 105000, 110000, 11500, 120000, 125000, 130000, 135000, 140000, 145000, 150000, |
| 1163 | 155000, 160000, 165000, 170000, 175000, 180000, 185000, 190000, 195000, 200000 |
1163 | 155000, 160000, 165000, 170000, 175000, 180000, 185000, 190000, 195000, 200000 |
| 1164 | }; |
1164 | }; |
| Line 1165... | Line 1165... | ||
| 1165 | 1165 | ||
| 1166 | static const struct radeon_blacklist_clocks btc_blacklist_clocks[] = |
- | |
| 1167 | { |
1166 | static const struct radeon_blacklist_clocks btc_blacklist_clocks[] = { |
| 1168 | { 10000, 30000, RADEON_SCLK_UP }, |
1167 | { 10000, 30000, RADEON_SCLK_UP }, |
| 1169 | { 15000, 30000, RADEON_SCLK_UP }, |
1168 | { 15000, 30000, RADEON_SCLK_UP }, |
| 1170 | { 20000, 30000, RADEON_SCLK_UP }, |
1169 | { 20000, 30000, RADEON_SCLK_UP }, |
| 1171 | { 25000, 30000, RADEON_SCLK_UP } |
1170 | { 25000, 30000, RADEON_SCLK_UP } |
| Line 1172... | Line 1171... | ||
| 1172 | }; |
1171 | }; |
| 1173 | 1172 | ||
| 1174 | void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table, |
1173 | void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table, |
| Line 1635... | Line 1634... | ||
| 1635 | memset(table, 0, sizeof(RV770_SMC_STATETABLE)); |
1634 | memset(table, 0, sizeof(RV770_SMC_STATETABLE)); |
| Line 1636... | Line 1635... | ||
| 1636 | 1635 | ||
| Line 1637... | Line 1636... | ||
| 1637 | cypress_populate_smc_voltage_tables(rdev, table); |
1636 | cypress_populate_smc_voltage_tables(rdev, table); |
| 1638 | 1637 | ||
| 1639 | switch (rdev->pm.int_thermal_type) { |
1638 | switch (rdev->pm.int_thermal_type) { |
| 1640 | case THERMAL_TYPE_EVERGREEN: |
1639 | case THERMAL_TYPE_EVERGREEN: |
| 1641 | case THERMAL_TYPE_EMC2103_WITH_INTERNAL: |
1640 | case THERMAL_TYPE_EMC2103_WITH_INTERNAL: |
| 1642 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; |
1641 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; |
| 1643 | break; |
1642 | break; |
| 1644 | case THERMAL_TYPE_NONE: |
1643 | case THERMAL_TYPE_NONE: |
| 1645 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; |
1644 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; |
| 1646 | break; |
1645 | break; |
| 1647 | default: |
1646 | default: |
| 1648 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; |
1647 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; |
| Line 1649... | Line 1648... | ||
| 1649 | break; |
1648 | break; |
| Line 1858... | Line 1857... | ||
| 1858 | 1857 | ||
| 1859 | switch (in_reg) { |
1858 | switch (in_reg) { |
| 1860 | case MC_SEQ_RAS_TIMING >> 2: |
1859 | case MC_SEQ_RAS_TIMING >> 2: |
| 1861 | *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; |
1860 | *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; |
| 1862 | break; |
1861 | break; |
| 1863 | case MC_SEQ_CAS_TIMING >> 2: |
1862 | case MC_SEQ_CAS_TIMING >> 2: |
| 1864 | *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; |
1863 | *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; |
| 1865 | break; |
1864 | break; |
| 1866 | case MC_SEQ_MISC_TIMING >> 2: |
1865 | case MC_SEQ_MISC_TIMING >> 2: |
| 1867 | *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; |
1866 | *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; |
| 1868 | break; |
1867 | break; |
| 1869 | case MC_SEQ_MISC_TIMING2 >> 2: |
1868 | case MC_SEQ_MISC_TIMING2 >> 2: |
| 1870 | *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; |
1869 | *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; |
| 1871 | break; |
1870 | break; |
| 1872 | case MC_SEQ_RD_CTL_D0 >> 2: |
1871 | case MC_SEQ_RD_CTL_D0 >> 2: |
| 1873 | *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; |
1872 | *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; |
| 1874 | break; |
1873 | break; |
| 1875 | case MC_SEQ_RD_CTL_D1 >> 2: |
1874 | case MC_SEQ_RD_CTL_D1 >> 2: |
| 1876 | *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; |
1875 | *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; |
| 1877 | break; |
1876 | break; |
| 1878 | case MC_SEQ_WR_CTL_D0 >> 2: |
1877 | case MC_SEQ_WR_CTL_D0 >> 2: |
| 1879 | *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; |
1878 | *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; |
| 1880 | break; |
1879 | break; |
| 1881 | case MC_SEQ_WR_CTL_D1 >> 2: |
1880 | case MC_SEQ_WR_CTL_D1 >> 2: |
| 1882 | *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; |
1881 | *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; |
| 1883 | break; |
1882 | break; |
| 1884 | case MC_PMG_CMD_EMRS >> 2: |
1883 | case MC_PMG_CMD_EMRS >> 2: |
| 1885 | *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; |
1884 | *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; |
| 1886 | break; |
1885 | break; |
| 1887 | case MC_PMG_CMD_MRS >> 2: |
1886 | case MC_PMG_CMD_MRS >> 2: |
| 1888 | *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; |
1887 | *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; |
| 1889 | break; |
1888 | break; |
| 1890 | case MC_PMG_CMD_MRS1 >> 2: |
1889 | case MC_PMG_CMD_MRS1 >> 2: |
| 1891 | *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; |
1890 | *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; |
| 1892 | break; |
1891 | break; |
| 1893 | default: |
1892 | default: |
| 1894 | result = false; |
1893 | result = false; |
| 1895 | break; |
1894 | break; |
| Line 1896... | Line 1895... | ||
| 1896 | } |
1895 | } |