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1 | /* |
1 | /* |
2 | * Copyright 2007-11 Advanced Micro Devices, Inc. |
2 | * Copyright 2007-11 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
13 | * all copies or substantial portions of the Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: Dave Airlie |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
24 | * Alex Deucher |
25 | */ |
25 | */ |
26 | #include |
26 | #include |
27 | #include |
27 | #include |
28 | #include |
28 | #include |
29 | #include "radeon.h" |
29 | #include "radeon.h" |
30 | #include "atom.h" |
30 | #include "atom.h" |
31 | #include |
31 | #include |
32 | 32 | ||
33 | extern int atom_debug; |
33 | extern int atom_debug; |
34 | 34 | ||
35 | static u8 |
35 | static u8 |
36 | radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) |
36 | radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) |
37 | { |
37 | { |
38 | u8 backlight_level; |
38 | u8 backlight_level; |
39 | u32 bios_2_scratch; |
39 | u32 bios_2_scratch; |
40 | 40 | ||
41 | if (rdev->family >= CHIP_R600) |
41 | if (rdev->family >= CHIP_R600) |
42 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
42 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
43 | else |
43 | else |
44 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
44 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
45 | 45 | ||
46 | backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> |
46 | backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> |
47 | ATOM_S2_CURRENT_BL_LEVEL_SHIFT); |
47 | ATOM_S2_CURRENT_BL_LEVEL_SHIFT); |
48 | 48 | ||
49 | return backlight_level; |
49 | return backlight_level; |
50 | } |
50 | } |
51 | 51 | ||
52 | static void |
52 | static void |
53 | radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, |
53 | radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, |
54 | u8 backlight_level) |
54 | u8 backlight_level) |
55 | { |
55 | { |
56 | u32 bios_2_scratch; |
56 | u32 bios_2_scratch; |
57 | 57 | ||
58 | if (rdev->family >= CHIP_R600) |
58 | if (rdev->family >= CHIP_R600) |
59 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
59 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
60 | else |
60 | else |
61 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
61 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
62 | 62 | ||
63 | bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; |
63 | bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; |
64 | bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & |
64 | bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & |
65 | ATOM_S2_CURRENT_BL_LEVEL_MASK); |
65 | ATOM_S2_CURRENT_BL_LEVEL_MASK); |
66 | 66 | ||
67 | if (rdev->family >= CHIP_R600) |
67 | if (rdev->family >= CHIP_R600) |
68 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); |
68 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); |
69 | else |
69 | else |
70 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); |
70 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); |
71 | } |
71 | } |
72 | 72 | ||
73 | u8 |
73 | u8 |
74 | atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) |
74 | atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) |
75 | { |
75 | { |
76 | struct drm_device *dev = radeon_encoder->base.dev; |
76 | struct drm_device *dev = radeon_encoder->base.dev; |
77 | struct radeon_device *rdev = dev->dev_private; |
77 | struct radeon_device *rdev = dev->dev_private; |
78 | 78 | ||
79 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
79 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
80 | return 0; |
80 | return 0; |
81 | 81 | ||
82 | return radeon_atom_get_backlight_level_from_reg(rdev); |
82 | return radeon_atom_get_backlight_level_from_reg(rdev); |
83 | } |
83 | } |
84 | 84 | ||
85 | void |
85 | void |
86 | atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) |
86 | atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) |
87 | { |
87 | { |
88 | struct drm_encoder *encoder = &radeon_encoder->base; |
88 | struct drm_encoder *encoder = &radeon_encoder->base; |
89 | struct drm_device *dev = radeon_encoder->base.dev; |
89 | struct drm_device *dev = radeon_encoder->base.dev; |
90 | struct radeon_device *rdev = dev->dev_private; |
90 | struct radeon_device *rdev = dev->dev_private; |
91 | struct radeon_encoder_atom_dig *dig; |
91 | struct radeon_encoder_atom_dig *dig; |
92 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
92 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
93 | int index; |
93 | int index; |
94 | 94 | ||
95 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
95 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
96 | return; |
96 | return; |
97 | 97 | ||
98 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && |
98 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && |
99 | radeon_encoder->enc_priv) { |
99 | radeon_encoder->enc_priv) { |
100 | dig = radeon_encoder->enc_priv; |
100 | dig = radeon_encoder->enc_priv; |
101 | dig->backlight_level = level; |
101 | dig->backlight_level = level; |
102 | radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); |
102 | radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); |
103 | 103 | ||
104 | switch (radeon_encoder->encoder_id) { |
104 | switch (radeon_encoder->encoder_id) { |
105 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
105 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
106 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
106 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
107 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
107 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
108 | if (dig->backlight_level == 0) { |
108 | if (dig->backlight_level == 0) { |
109 | args.ucAction = ATOM_LCD_BLOFF; |
109 | args.ucAction = ATOM_LCD_BLOFF; |
110 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
110 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
111 | } else { |
111 | } else { |
112 | args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; |
112 | args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; |
113 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
113 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
114 | args.ucAction = ATOM_LCD_BLON; |
114 | args.ucAction = ATOM_LCD_BLON; |
115 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
115 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
116 | } |
116 | } |
117 | break; |
117 | break; |
118 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
118 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
119 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
119 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
120 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
120 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
121 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
121 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
122 | if (dig->backlight_level == 0) |
122 | if (dig->backlight_level == 0) |
123 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); |
123 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); |
124 | else { |
124 | else { |
125 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); |
125 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); |
126 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); |
126 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); |
127 | } |
127 | } |
128 | break; |
128 | break; |
129 | default: |
129 | default: |
130 | break; |
130 | break; |
131 | } |
131 | } |
132 | } |
132 | } |
133 | } |
133 | } |
134 | 134 | ||
135 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
135 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
136 | 136 | ||
137 | static u8 radeon_atom_bl_level(struct backlight_device *bd) |
137 | static u8 radeon_atom_bl_level(struct backlight_device *bd) |
138 | { |
138 | { |
139 | u8 level; |
139 | u8 level; |
140 | 140 | ||
141 | /* Convert brightness to hardware level */ |
141 | /* Convert brightness to hardware level */ |
142 | if (bd->props.brightness < 0) |
142 | if (bd->props.brightness < 0) |
143 | level = 0; |
143 | level = 0; |
144 | else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) |
144 | else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) |
145 | level = RADEON_MAX_BL_LEVEL; |
145 | level = RADEON_MAX_BL_LEVEL; |
146 | else |
146 | else |
147 | level = bd->props.brightness; |
147 | level = bd->props.brightness; |
148 | 148 | ||
149 | return level; |
149 | return level; |
150 | } |
150 | } |
151 | 151 | ||
152 | static int radeon_atom_backlight_update_status(struct backlight_device *bd) |
152 | static int radeon_atom_backlight_update_status(struct backlight_device *bd) |
153 | { |
153 | { |
154 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); |
154 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); |
155 | struct radeon_encoder *radeon_encoder = pdata->encoder; |
155 | struct radeon_encoder *radeon_encoder = pdata->encoder; |
156 | 156 | ||
157 | atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); |
157 | atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); |
158 | 158 | ||
159 | return 0; |
159 | return 0; |
160 | } |
160 | } |
161 | 161 | ||
162 | static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) |
162 | static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) |
163 | { |
163 | { |
164 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); |
164 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); |
165 | struct radeon_encoder *radeon_encoder = pdata->encoder; |
165 | struct radeon_encoder *radeon_encoder = pdata->encoder; |
166 | struct drm_device *dev = radeon_encoder->base.dev; |
166 | struct drm_device *dev = radeon_encoder->base.dev; |
167 | struct radeon_device *rdev = dev->dev_private; |
167 | struct radeon_device *rdev = dev->dev_private; |
168 | 168 | ||
169 | return radeon_atom_get_backlight_level_from_reg(rdev); |
169 | return radeon_atom_get_backlight_level_from_reg(rdev); |
170 | } |
170 | } |
171 | 171 | ||
172 | static const struct backlight_ops radeon_atom_backlight_ops = { |
172 | static const struct backlight_ops radeon_atom_backlight_ops = { |
173 | .get_brightness = radeon_atom_backlight_get_brightness, |
173 | .get_brightness = radeon_atom_backlight_get_brightness, |
174 | .update_status = radeon_atom_backlight_update_status, |
174 | .update_status = radeon_atom_backlight_update_status, |
175 | }; |
175 | }; |
176 | 176 | ||
177 | void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, |
177 | void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, |
178 | struct drm_connector *drm_connector) |
178 | struct drm_connector *drm_connector) |
179 | { |
179 | { |
180 | struct drm_device *dev = radeon_encoder->base.dev; |
180 | struct drm_device *dev = radeon_encoder->base.dev; |
181 | struct radeon_device *rdev = dev->dev_private; |
181 | struct radeon_device *rdev = dev->dev_private; |
182 | struct backlight_device *bd; |
182 | struct backlight_device *bd; |
183 | struct backlight_properties props; |
183 | struct backlight_properties props; |
184 | struct radeon_backlight_privdata *pdata; |
184 | struct radeon_backlight_privdata *pdata; |
185 | struct radeon_encoder_atom_dig *dig; |
185 | struct radeon_encoder_atom_dig *dig; |
186 | char bl_name[16]; |
186 | char bl_name[16]; |
187 | 187 | ||
188 | /* Mac laptops with multiple GPUs use the gmux driver for backlight |
188 | /* Mac laptops with multiple GPUs use the gmux driver for backlight |
189 | * so don't register a backlight device |
189 | * so don't register a backlight device |
190 | */ |
190 | */ |
191 | if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && |
191 | if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && |
192 | (rdev->pdev->device == 0x6741)) |
192 | (rdev->pdev->device == 0x6741)) |
193 | return; |
193 | return; |
194 | 194 | ||
195 | if (!radeon_encoder->enc_priv) |
195 | if (!radeon_encoder->enc_priv) |
196 | return; |
196 | return; |
197 | 197 | ||
198 | if (!rdev->is_atom_bios) |
198 | if (!rdev->is_atom_bios) |
199 | return; |
199 | return; |
200 | 200 | ||
201 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
201 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
202 | return; |
202 | return; |
203 | 203 | ||
204 | pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); |
204 | pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); |
205 | if (!pdata) { |
205 | if (!pdata) { |
206 | DRM_ERROR("Memory allocation failed\n"); |
206 | DRM_ERROR("Memory allocation failed\n"); |
207 | goto error; |
207 | goto error; |
208 | } |
208 | } |
209 | 209 | ||
210 | memset(&props, 0, sizeof(props)); |
210 | memset(&props, 0, sizeof(props)); |
211 | props.max_brightness = RADEON_MAX_BL_LEVEL; |
211 | props.max_brightness = RADEON_MAX_BL_LEVEL; |
212 | props.type = BACKLIGHT_RAW; |
212 | props.type = BACKLIGHT_RAW; |
213 | snprintf(bl_name, sizeof(bl_name), |
213 | snprintf(bl_name, sizeof(bl_name), |
214 | "radeon_bl%d", dev->primary->index); |
214 | "radeon_bl%d", dev->primary->index); |
215 | bd = backlight_device_register(bl_name, drm_connector->kdev, |
215 | bd = backlight_device_register(bl_name, drm_connector->kdev, |
216 | pdata, &radeon_atom_backlight_ops, &props); |
216 | pdata, &radeon_atom_backlight_ops, &props); |
217 | if (IS_ERR(bd)) { |
217 | if (IS_ERR(bd)) { |
218 | DRM_ERROR("Backlight registration failed\n"); |
218 | DRM_ERROR("Backlight registration failed\n"); |
219 | goto error; |
219 | goto error; |
220 | } |
220 | } |
221 | 221 | ||
222 | pdata->encoder = radeon_encoder; |
222 | pdata->encoder = radeon_encoder; |
223 | 223 | ||
224 | dig = radeon_encoder->enc_priv; |
224 | dig = radeon_encoder->enc_priv; |
225 | dig->bl_dev = bd; |
225 | dig->bl_dev = bd; |
226 | 226 | ||
227 | bd->props.brightness = radeon_atom_backlight_get_brightness(bd); |
227 | bd->props.brightness = radeon_atom_backlight_get_brightness(bd); |
228 | /* Set a reasonable default here if the level is 0 otherwise |
228 | /* Set a reasonable default here if the level is 0 otherwise |
229 | * fbdev will attempt to turn the backlight on after console |
229 | * fbdev will attempt to turn the backlight on after console |
230 | * unblanking and it will try and restore 0 which turns the backlight |
230 | * unblanking and it will try and restore 0 which turns the backlight |
231 | * off again. |
231 | * off again. |
232 | */ |
232 | */ |
233 | if (bd->props.brightness == 0) |
233 | if (bd->props.brightness == 0) |
234 | bd->props.brightness = RADEON_MAX_BL_LEVEL; |
234 | bd->props.brightness = RADEON_MAX_BL_LEVEL; |
235 | bd->props.power = FB_BLANK_UNBLANK; |
235 | bd->props.power = FB_BLANK_UNBLANK; |
236 | backlight_update_status(bd); |
236 | backlight_update_status(bd); |
237 | 237 | ||
238 | DRM_INFO("radeon atom DIG backlight initialized\n"); |
238 | DRM_INFO("radeon atom DIG backlight initialized\n"); |
239 | 239 | ||
240 | return; |
240 | return; |
241 | 241 | ||
242 | error: |
242 | error: |
243 | kfree(pdata); |
243 | kfree(pdata); |
244 | return; |
244 | return; |
245 | } |
245 | } |
246 | 246 | ||
247 | static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) |
247 | static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) |
248 | { |
248 | { |
249 | struct drm_device *dev = radeon_encoder->base.dev; |
249 | struct drm_device *dev = radeon_encoder->base.dev; |
250 | struct radeon_device *rdev = dev->dev_private; |
250 | struct radeon_device *rdev = dev->dev_private; |
251 | struct backlight_device *bd = NULL; |
251 | struct backlight_device *bd = NULL; |
252 | struct radeon_encoder_atom_dig *dig; |
252 | struct radeon_encoder_atom_dig *dig; |
253 | 253 | ||
254 | if (!radeon_encoder->enc_priv) |
254 | if (!radeon_encoder->enc_priv) |
255 | return; |
255 | return; |
256 | 256 | ||
257 | if (!rdev->is_atom_bios) |
257 | if (!rdev->is_atom_bios) |
258 | return; |
258 | return; |
259 | 259 | ||
260 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
260 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
261 | return; |
261 | return; |
262 | 262 | ||
263 | dig = radeon_encoder->enc_priv; |
263 | dig = radeon_encoder->enc_priv; |
264 | bd = dig->bl_dev; |
264 | bd = dig->bl_dev; |
265 | dig->bl_dev = NULL; |
265 | dig->bl_dev = NULL; |
266 | 266 | ||
267 | if (bd) { |
267 | if (bd) { |
268 | struct radeon_legacy_backlight_privdata *pdata; |
268 | struct radeon_legacy_backlight_privdata *pdata; |
269 | 269 | ||
270 | pdata = bl_get_data(bd); |
270 | pdata = bl_get_data(bd); |
271 | backlight_device_unregister(bd); |
271 | backlight_device_unregister(bd); |
272 | kfree(pdata); |
272 | kfree(pdata); |
273 | 273 | ||
274 | DRM_INFO("radeon atom LVDS backlight unloaded\n"); |
274 | DRM_INFO("radeon atom LVDS backlight unloaded\n"); |
275 | } |
275 | } |
276 | } |
276 | } |
277 | 277 | ||
278 | #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ |
278 | #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ |
279 | 279 | ||
280 | void radeon_atom_backlight_init(struct radeon_encoder *encoder) |
280 | void radeon_atom_backlight_init(struct radeon_encoder *encoder) |
281 | { |
281 | { |
282 | } |
282 | } |
283 | 283 | ||
284 | static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) |
284 | static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) |
285 | { |
285 | { |
286 | } |
286 | } |
287 | 287 | ||
288 | #endif |
288 | #endif |
289 | 289 | ||
290 | /* evil but including atombios.h is much worse */ |
290 | /* evil but including atombios.h is much worse */ |
291 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
291 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
292 | struct drm_display_mode *mode); |
292 | struct drm_display_mode *mode); |
293 | - | ||
294 | - | ||
295 | static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) |
- | |
296 | { |
- | |
297 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
- | |
298 | switch (radeon_encoder->encoder_id) { |
- | |
299 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
- | |
300 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
- | |
301 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
- | |
302 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
- | |
303 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
- | |
304 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
- | |
305 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
- | |
306 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
- | |
307 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
- | |
308 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
- | |
309 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
- | |
310 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
- | |
311 | return true; |
- | |
312 | default: |
- | |
313 | return false; |
- | |
314 | } |
- | |
315 | } |
- | |
316 | 293 | ||
317 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
294 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
318 | const struct drm_display_mode *mode, |
295 | const struct drm_display_mode *mode, |
319 | struct drm_display_mode *adjusted_mode) |
296 | struct drm_display_mode *adjusted_mode) |
320 | { |
297 | { |
321 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
298 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
322 | struct drm_device *dev = encoder->dev; |
299 | struct drm_device *dev = encoder->dev; |
323 | struct radeon_device *rdev = dev->dev_private; |
300 | struct radeon_device *rdev = dev->dev_private; |
324 | 301 | ||
325 | /* set the active encoder to connector routing */ |
302 | /* set the active encoder to connector routing */ |
326 | radeon_encoder_set_active_device(encoder); |
303 | radeon_encoder_set_active_device(encoder); |
327 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
304 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
328 | 305 | ||
329 | /* hw bug */ |
306 | /* hw bug */ |
330 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
307 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
331 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
308 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
332 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
309 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
333 | 310 | ||
334 | /* get the native mode for scaling */ |
311 | /* get the native mode for scaling */ |
335 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT|ATOM_DEVICE_DFP_SUPPORT)) { |
312 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT|ATOM_DEVICE_DFP_SUPPORT)) { |
336 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
313 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
337 | } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
314 | } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
338 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
315 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
339 | if (tv_dac) { |
316 | if (tv_dac) { |
340 | if (tv_dac->tv_std == TV_STD_NTSC || |
317 | if (tv_dac->tv_std == TV_STD_NTSC || |
341 | tv_dac->tv_std == TV_STD_NTSC_J || |
318 | tv_dac->tv_std == TV_STD_NTSC_J || |
342 | tv_dac->tv_std == TV_STD_PAL_M) |
319 | tv_dac->tv_std == TV_STD_PAL_M) |
343 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); |
320 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); |
344 | else |
321 | else |
345 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); |
322 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); |
346 | } |
323 | } |
347 | } else if (radeon_encoder->rmx_type != RMX_OFF) { |
324 | } else if (radeon_encoder->rmx_type != RMX_OFF) { |
348 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
325 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
349 | } |
326 | } |
350 | 327 | ||
351 | if (ASIC_IS_DCE3(rdev) && |
328 | if (ASIC_IS_DCE3(rdev) && |
352 | ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || |
329 | ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || |
353 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { |
330 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { |
354 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
331 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
355 | radeon_dp_set_link_config(connector, adjusted_mode); |
332 | radeon_dp_set_link_config(connector, adjusted_mode); |
356 | } |
333 | } |
357 | 334 | ||
358 | return true; |
335 | return true; |
359 | } |
336 | } |
360 | 337 | ||
361 | static void |
338 | static void |
362 | atombios_dac_setup(struct drm_encoder *encoder, int action) |
339 | atombios_dac_setup(struct drm_encoder *encoder, int action) |
363 | { |
340 | { |
364 | struct drm_device *dev = encoder->dev; |
341 | struct drm_device *dev = encoder->dev; |
365 | struct radeon_device *rdev = dev->dev_private; |
342 | struct radeon_device *rdev = dev->dev_private; |
366 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
343 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
367 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; |
344 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; |
368 | int index = 0; |
345 | int index = 0; |
369 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
346 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
370 | 347 | ||
371 | memset(&args, 0, sizeof(args)); |
348 | memset(&args, 0, sizeof(args)); |
372 | 349 | ||
373 | switch (radeon_encoder->encoder_id) { |
350 | switch (radeon_encoder->encoder_id) { |
374 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
351 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
375 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
352 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
376 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); |
353 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); |
377 | break; |
354 | break; |
378 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
355 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
379 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
356 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
380 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); |
357 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); |
381 | break; |
358 | break; |
382 | } |
359 | } |
383 | 360 | ||
384 | args.ucAction = action; |
361 | args.ucAction = action; |
385 | 362 | ||
386 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
363 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
387 | args.ucDacStandard = ATOM_DAC1_PS2; |
364 | args.ucDacStandard = ATOM_DAC1_PS2; |
388 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
365 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
389 | args.ucDacStandard = ATOM_DAC1_CV; |
366 | args.ucDacStandard = ATOM_DAC1_CV; |
390 | else { |
367 | else { |
391 | switch (dac_info->tv_std) { |
368 | switch (dac_info->tv_std) { |
392 | case TV_STD_PAL: |
369 | case TV_STD_PAL: |
393 | case TV_STD_PAL_M: |
370 | case TV_STD_PAL_M: |
394 | case TV_STD_SCART_PAL: |
371 | case TV_STD_SCART_PAL: |
395 | case TV_STD_SECAM: |
372 | case TV_STD_SECAM: |
396 | case TV_STD_PAL_CN: |
373 | case TV_STD_PAL_CN: |
397 | args.ucDacStandard = ATOM_DAC1_PAL; |
374 | args.ucDacStandard = ATOM_DAC1_PAL; |
398 | break; |
375 | break; |
399 | case TV_STD_NTSC: |
376 | case TV_STD_NTSC: |
400 | case TV_STD_NTSC_J: |
377 | case TV_STD_NTSC_J: |
401 | case TV_STD_PAL_60: |
378 | case TV_STD_PAL_60: |
402 | default: |
379 | default: |
403 | args.ucDacStandard = ATOM_DAC1_NTSC; |
380 | args.ucDacStandard = ATOM_DAC1_NTSC; |
404 | break; |
381 | break; |
405 | } |
382 | } |
406 | } |
383 | } |
407 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
384 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
408 | 385 | ||
409 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
386 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
410 | 387 | ||
411 | } |
388 | } |
412 | 389 | ||
413 | static void |
390 | static void |
414 | atombios_tv_setup(struct drm_encoder *encoder, int action) |
391 | atombios_tv_setup(struct drm_encoder *encoder, int action) |
415 | { |
392 | { |
416 | struct drm_device *dev = encoder->dev; |
393 | struct drm_device *dev = encoder->dev; |
417 | struct radeon_device *rdev = dev->dev_private; |
394 | struct radeon_device *rdev = dev->dev_private; |
418 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
395 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
419 | TV_ENCODER_CONTROL_PS_ALLOCATION args; |
396 | TV_ENCODER_CONTROL_PS_ALLOCATION args; |
420 | int index = 0; |
397 | int index = 0; |
421 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
398 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
422 | 399 | ||
423 | memset(&args, 0, sizeof(args)); |
400 | memset(&args, 0, sizeof(args)); |
424 | 401 | ||
425 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); |
402 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); |
426 | 403 | ||
427 | args.sTVEncoder.ucAction = action; |
404 | args.sTVEncoder.ucAction = action; |
428 | 405 | ||
429 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
406 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
430 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
407 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
431 | else { |
408 | else { |
432 | switch (dac_info->tv_std) { |
409 | switch (dac_info->tv_std) { |
433 | case TV_STD_NTSC: |
410 | case TV_STD_NTSC: |
434 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
411 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
435 | break; |
412 | break; |
436 | case TV_STD_PAL: |
413 | case TV_STD_PAL: |
437 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; |
414 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; |
438 | break; |
415 | break; |
439 | case TV_STD_PAL_M: |
416 | case TV_STD_PAL_M: |
440 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; |
417 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; |
441 | break; |
418 | break; |
442 | case TV_STD_PAL_60: |
419 | case TV_STD_PAL_60: |
443 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; |
420 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; |
444 | break; |
421 | break; |
445 | case TV_STD_NTSC_J: |
422 | case TV_STD_NTSC_J: |
446 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; |
423 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; |
447 | break; |
424 | break; |
448 | case TV_STD_SCART_PAL: |
425 | case TV_STD_SCART_PAL: |
449 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ |
426 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ |
450 | break; |
427 | break; |
451 | case TV_STD_SECAM: |
428 | case TV_STD_SECAM: |
452 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; |
429 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; |
453 | break; |
430 | break; |
454 | case TV_STD_PAL_CN: |
431 | case TV_STD_PAL_CN: |
455 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; |
432 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; |
456 | break; |
433 | break; |
457 | default: |
434 | default: |
458 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
435 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
459 | break; |
436 | break; |
460 | } |
437 | } |
461 | } |
438 | } |
462 | 439 | ||
463 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
440 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
464 | 441 | ||
465 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
442 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
466 | 443 | ||
467 | } |
444 | } |
468 | 445 | ||
469 | static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) |
446 | static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) |
470 | { |
447 | { |
471 | int bpc = 8; |
448 | int bpc = 8; |
472 | 449 | ||
473 | if (encoder->crtc) { |
450 | if (encoder->crtc) { |
474 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
451 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
475 | bpc = radeon_crtc->bpc; |
452 | bpc = radeon_crtc->bpc; |
476 | } |
453 | } |
477 | 454 | ||
478 | switch (bpc) { |
455 | switch (bpc) { |
479 | case 0: |
456 | case 0: |
480 | return PANEL_BPC_UNDEFINE; |
457 | return PANEL_BPC_UNDEFINE; |
481 | case 6: |
458 | case 6: |
482 | return PANEL_6BIT_PER_COLOR; |
459 | return PANEL_6BIT_PER_COLOR; |
483 | case 8: |
460 | case 8: |
484 | default: |
461 | default: |
485 | return PANEL_8BIT_PER_COLOR; |
462 | return PANEL_8BIT_PER_COLOR; |
486 | case 10: |
463 | case 10: |
487 | return PANEL_10BIT_PER_COLOR; |
464 | return PANEL_10BIT_PER_COLOR; |
488 | case 12: |
465 | case 12: |
489 | return PANEL_12BIT_PER_COLOR; |
466 | return PANEL_12BIT_PER_COLOR; |
490 | case 16: |
467 | case 16: |
491 | return PANEL_16BIT_PER_COLOR; |
468 | return PANEL_16BIT_PER_COLOR; |
492 | } |
469 | } |
493 | } |
470 | } |
494 | 471 | ||
495 | union dvo_encoder_control { |
472 | union dvo_encoder_control { |
496 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; |
473 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; |
497 | DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; |
474 | DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; |
498 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; |
475 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; |
499 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; |
476 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; |
500 | }; |
477 | }; |
501 | 478 | ||
502 | void |
479 | void |
503 | atombios_dvo_setup(struct drm_encoder *encoder, int action) |
480 | atombios_dvo_setup(struct drm_encoder *encoder, int action) |
504 | { |
481 | { |
505 | struct drm_device *dev = encoder->dev; |
482 | struct drm_device *dev = encoder->dev; |
506 | struct radeon_device *rdev = dev->dev_private; |
483 | struct radeon_device *rdev = dev->dev_private; |
507 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
484 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
508 | union dvo_encoder_control args; |
485 | union dvo_encoder_control args; |
509 | int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
486 | int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
510 | uint8_t frev, crev; |
487 | uint8_t frev, crev; |
511 | 488 | ||
512 | memset(&args, 0, sizeof(args)); |
489 | memset(&args, 0, sizeof(args)); |
513 | 490 | ||
514 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
491 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
515 | return; |
492 | return; |
516 | 493 | ||
517 | /* some R4xx chips have the wrong frev */ |
494 | /* some R4xx chips have the wrong frev */ |
518 | if (rdev->family <= CHIP_RV410) |
495 | if (rdev->family <= CHIP_RV410) |
519 | frev = 1; |
496 | frev = 1; |
520 | 497 | ||
521 | switch (frev) { |
498 | switch (frev) { |
522 | case 1: |
499 | case 1: |
523 | switch (crev) { |
500 | switch (crev) { |
524 | case 1: |
501 | case 1: |
525 | /* R4xx, R5xx */ |
502 | /* R4xx, R5xx */ |
526 | args.ext_tmds.sXTmdsEncoder.ucEnable = action; |
503 | args.ext_tmds.sXTmdsEncoder.ucEnable = action; |
527 | 504 | ||
528 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
505 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
529 | args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
506 | args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
530 | 507 | ||
531 | args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; |
508 | args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; |
532 | break; |
509 | break; |
533 | case 2: |
510 | case 2: |
534 | /* RS600/690/740 */ |
511 | /* RS600/690/740 */ |
535 | args.dvo.sDVOEncoder.ucAction = action; |
512 | args.dvo.sDVOEncoder.ucAction = action; |
536 | args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
513 | args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
537 | /* DFP1, CRT1, TV1 depending on the type of port */ |
514 | /* DFP1, CRT1, TV1 depending on the type of port */ |
538 | args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; |
515 | args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; |
539 | 516 | ||
540 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
517 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
541 | args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; |
518 | args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; |
542 | break; |
519 | break; |
543 | case 3: |
520 | case 3: |
544 | /* R6xx */ |
521 | /* R6xx */ |
545 | args.dvo_v3.ucAction = action; |
522 | args.dvo_v3.ucAction = action; |
546 | args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
523 | args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
547 | args.dvo_v3.ucDVOConfig = 0; /* XXX */ |
524 | args.dvo_v3.ucDVOConfig = 0; /* XXX */ |
548 | break; |
525 | break; |
549 | case 4: |
526 | case 4: |
550 | /* DCE8 */ |
527 | /* DCE8 */ |
551 | args.dvo_v4.ucAction = action; |
528 | args.dvo_v4.ucAction = action; |
552 | args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
529 | args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
553 | args.dvo_v4.ucDVOConfig = 0; /* XXX */ |
530 | args.dvo_v4.ucDVOConfig = 0; /* XXX */ |
554 | args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); |
531 | args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); |
555 | break; |
532 | break; |
556 | default: |
533 | default: |
557 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
534 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
558 | break; |
535 | break; |
559 | } |
536 | } |
560 | break; |
537 | break; |
561 | default: |
538 | default: |
562 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
539 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
563 | break; |
540 | break; |
564 | } |
541 | } |
565 | 542 | ||
566 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
543 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
567 | } |
544 | } |
568 | 545 | ||
569 | union lvds_encoder_control { |
546 | union lvds_encoder_control { |
570 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; |
547 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; |
571 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; |
548 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; |
572 | }; |
549 | }; |
573 | 550 | ||
574 | void |
551 | void |
575 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
552 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
576 | { |
553 | { |
577 | struct drm_device *dev = encoder->dev; |
554 | struct drm_device *dev = encoder->dev; |
578 | struct radeon_device *rdev = dev->dev_private; |
555 | struct radeon_device *rdev = dev->dev_private; |
579 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
556 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
580 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
557 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
581 | union lvds_encoder_control args; |
558 | union lvds_encoder_control args; |
582 | int index = 0; |
559 | int index = 0; |
583 | int hdmi_detected = 0; |
560 | int hdmi_detected = 0; |
584 | uint8_t frev, crev; |
561 | uint8_t frev, crev; |
585 | 562 | ||
586 | if (!dig) |
563 | if (!dig) |
587 | return; |
564 | return; |
588 | 565 | ||
589 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
566 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
590 | hdmi_detected = 1; |
567 | hdmi_detected = 1; |
591 | 568 | ||
592 | memset(&args, 0, sizeof(args)); |
569 | memset(&args, 0, sizeof(args)); |
593 | 570 | ||
594 | switch (radeon_encoder->encoder_id) { |
571 | switch (radeon_encoder->encoder_id) { |
595 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
572 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
596 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
573 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
597 | break; |
574 | break; |
598 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
575 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
599 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
576 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
600 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); |
577 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); |
601 | break; |
578 | break; |
602 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
579 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
603 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
580 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
604 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
581 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
605 | else |
582 | else |
606 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); |
583 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); |
607 | break; |
584 | break; |
608 | } |
585 | } |
609 | 586 | ||
610 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
587 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
611 | return; |
588 | return; |
612 | 589 | ||
613 | switch (frev) { |
590 | switch (frev) { |
614 | case 1: |
591 | case 1: |
615 | case 2: |
592 | case 2: |
616 | switch (crev) { |
593 | switch (crev) { |
617 | case 1: |
594 | case 1: |
618 | args.v1.ucMisc = 0; |
595 | args.v1.ucMisc = 0; |
619 | args.v1.ucAction = action; |
596 | args.v1.ucAction = action; |
620 | if (hdmi_detected) |
597 | if (hdmi_detected) |
621 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
598 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
622 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
599 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
623 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
600 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
624 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
601 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
625 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
602 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
626 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
603 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
627 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
604 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
628 | } else { |
605 | } else { |
629 | if (dig->linkb) |
606 | if (dig->linkb) |
630 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
607 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
631 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
608 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
632 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
609 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
633 | /*if (pScrn->rgbBits == 8) */ |
610 | /*if (pScrn->rgbBits == 8) */ |
634 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
611 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
635 | } |
612 | } |
636 | break; |
613 | break; |
637 | case 2: |
614 | case 2: |
638 | case 3: |
615 | case 3: |
639 | args.v2.ucMisc = 0; |
616 | args.v2.ucMisc = 0; |
640 | args.v2.ucAction = action; |
617 | args.v2.ucAction = action; |
641 | if (crev == 3) { |
618 | if (crev == 3) { |
642 | if (dig->coherent_mode) |
619 | if (dig->coherent_mode) |
643 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; |
620 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; |
644 | } |
621 | } |
645 | if (hdmi_detected) |
622 | if (hdmi_detected) |
646 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
623 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
647 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
624 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
648 | args.v2.ucTruncate = 0; |
625 | args.v2.ucTruncate = 0; |
649 | args.v2.ucSpatial = 0; |
626 | args.v2.ucSpatial = 0; |
650 | args.v2.ucTemporal = 0; |
627 | args.v2.ucTemporal = 0; |
651 | args.v2.ucFRC = 0; |
628 | args.v2.ucFRC = 0; |
652 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
629 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
653 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
630 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
654 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
631 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
655 | if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { |
632 | if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { |
656 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; |
633 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; |
657 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
634 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
658 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; |
635 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; |
659 | } |
636 | } |
660 | if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { |
637 | if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { |
661 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; |
638 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; |
662 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
639 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
663 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; |
640 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; |
664 | if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) |
641 | if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) |
665 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
642 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
666 | } |
643 | } |
667 | } else { |
644 | } else { |
668 | if (dig->linkb) |
645 | if (dig->linkb) |
669 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
646 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
670 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
647 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
671 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
648 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
672 | } |
649 | } |
673 | break; |
650 | break; |
674 | default: |
651 | default: |
675 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
652 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
676 | break; |
653 | break; |
677 | } |
654 | } |
678 | break; |
655 | break; |
679 | default: |
656 | default: |
680 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
657 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
681 | break; |
658 | break; |
682 | } |
659 | } |
683 | 660 | ||
684 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
661 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
685 | } |
662 | } |
686 | 663 | ||
687 | int |
664 | int |
688 | atombios_get_encoder_mode(struct drm_encoder *encoder) |
665 | atombios_get_encoder_mode(struct drm_encoder *encoder) |
689 | { |
666 | { |
690 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
667 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
691 | struct drm_connector *connector; |
668 | struct drm_connector *connector; |
692 | struct radeon_connector *radeon_connector; |
669 | struct radeon_connector *radeon_connector; |
693 | struct radeon_connector_atom_dig *dig_connector; |
670 | struct radeon_connector_atom_dig *dig_connector; |
694 | 671 | ||
695 | /* dp bridges are always DP */ |
672 | /* dp bridges are always DP */ |
696 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) |
673 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) |
697 | return ATOM_ENCODER_MODE_DP; |
674 | return ATOM_ENCODER_MODE_DP; |
698 | 675 | ||
699 | /* DVO is always DVO */ |
676 | /* DVO is always DVO */ |
700 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || |
677 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || |
701 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) |
678 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) |
702 | return ATOM_ENCODER_MODE_DVO; |
679 | return ATOM_ENCODER_MODE_DVO; |
703 | 680 | ||
704 | connector = radeon_get_connector_for_encoder(encoder); |
681 | connector = radeon_get_connector_for_encoder(encoder); |
705 | /* if we don't have an active device yet, just use one of |
682 | /* if we don't have an active device yet, just use one of |
706 | * the connectors tied to the encoder. |
683 | * the connectors tied to the encoder. |
707 | */ |
684 | */ |
708 | if (!connector) |
685 | if (!connector) |
709 | connector = radeon_get_connector_for_encoder_init(encoder); |
686 | connector = radeon_get_connector_for_encoder_init(encoder); |
710 | radeon_connector = to_radeon_connector(connector); |
687 | radeon_connector = to_radeon_connector(connector); |
711 | 688 | ||
712 | switch (connector->connector_type) { |
689 | switch (connector->connector_type) { |
713 | case DRM_MODE_CONNECTOR_DVII: |
690 | case DRM_MODE_CONNECTOR_DVII: |
714 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
691 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
715 | if (radeon_audio != 0) { |
692 | if (radeon_audio != 0) { |
716 | if (radeon_connector->use_digital && |
693 | if (radeon_connector->use_digital && |
717 | (radeon_connector->audio == RADEON_AUDIO_ENABLE)) |
694 | (radeon_connector->audio == RADEON_AUDIO_ENABLE)) |
718 | return ATOM_ENCODER_MODE_HDMI; |
695 | return ATOM_ENCODER_MODE_HDMI; |
719 | else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
696 | else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
720 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
697 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
721 | return ATOM_ENCODER_MODE_HDMI; |
698 | return ATOM_ENCODER_MODE_HDMI; |
722 | else if (radeon_connector->use_digital) |
699 | else if (radeon_connector->use_digital) |
723 | return ATOM_ENCODER_MODE_DVI; |
700 | return ATOM_ENCODER_MODE_DVI; |
724 | else |
701 | else |
725 | return ATOM_ENCODER_MODE_CRT; |
702 | return ATOM_ENCODER_MODE_CRT; |
726 | } else if (radeon_connector->use_digital) { |
703 | } else if (radeon_connector->use_digital) { |
727 | return ATOM_ENCODER_MODE_DVI; |
704 | return ATOM_ENCODER_MODE_DVI; |
728 | } else { |
705 | } else { |
729 | return ATOM_ENCODER_MODE_CRT; |
706 | return ATOM_ENCODER_MODE_CRT; |
730 | } |
707 | } |
731 | break; |
708 | break; |
732 | case DRM_MODE_CONNECTOR_DVID: |
709 | case DRM_MODE_CONNECTOR_DVID: |
733 | case DRM_MODE_CONNECTOR_HDMIA: |
710 | case DRM_MODE_CONNECTOR_HDMIA: |
734 | default: |
711 | default: |
735 | if (radeon_audio != 0) { |
712 | if (radeon_audio != 0) { |
736 | if (radeon_connector->audio == RADEON_AUDIO_ENABLE) |
713 | if (radeon_connector->audio == RADEON_AUDIO_ENABLE) |
737 | return ATOM_ENCODER_MODE_HDMI; |
714 | return ATOM_ENCODER_MODE_HDMI; |
738 | else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
715 | else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
739 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
716 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
740 | return ATOM_ENCODER_MODE_HDMI; |
717 | return ATOM_ENCODER_MODE_HDMI; |
741 | else |
718 | else |
742 | return ATOM_ENCODER_MODE_DVI; |
719 | return ATOM_ENCODER_MODE_DVI; |
743 | } else { |
720 | } else { |
744 | return ATOM_ENCODER_MODE_DVI; |
721 | return ATOM_ENCODER_MODE_DVI; |
745 | } |
722 | } |
746 | break; |
723 | break; |
747 | case DRM_MODE_CONNECTOR_LVDS: |
724 | case DRM_MODE_CONNECTOR_LVDS: |
748 | return ATOM_ENCODER_MODE_LVDS; |
725 | return ATOM_ENCODER_MODE_LVDS; |
749 | break; |
726 | break; |
750 | case DRM_MODE_CONNECTOR_DisplayPort: |
727 | case DRM_MODE_CONNECTOR_DisplayPort: |
751 | dig_connector = radeon_connector->con_priv; |
728 | dig_connector = radeon_connector->con_priv; |
752 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
729 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
753 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
730 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
754 | return ATOM_ENCODER_MODE_DP; |
731 | return ATOM_ENCODER_MODE_DP; |
755 | } else if (radeon_audio != 0) { |
732 | } else if (radeon_audio != 0) { |
756 | if (radeon_connector->audio == RADEON_AUDIO_ENABLE) |
733 | if (radeon_connector->audio == RADEON_AUDIO_ENABLE) |
757 | return ATOM_ENCODER_MODE_HDMI; |
734 | return ATOM_ENCODER_MODE_HDMI; |
758 | else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
735 | else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
759 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
736 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
760 | return ATOM_ENCODER_MODE_HDMI; |
737 | return ATOM_ENCODER_MODE_HDMI; |
761 | else |
738 | else |
762 | return ATOM_ENCODER_MODE_DVI; |
739 | return ATOM_ENCODER_MODE_DVI; |
763 | } else { |
740 | } else { |
764 | return ATOM_ENCODER_MODE_DVI; |
741 | return ATOM_ENCODER_MODE_DVI; |
765 | } |
742 | } |
766 | break; |
743 | break; |
767 | case DRM_MODE_CONNECTOR_eDP: |
744 | case DRM_MODE_CONNECTOR_eDP: |
768 | return ATOM_ENCODER_MODE_DP; |
745 | return ATOM_ENCODER_MODE_DP; |
769 | case DRM_MODE_CONNECTOR_DVIA: |
746 | case DRM_MODE_CONNECTOR_DVIA: |
770 | case DRM_MODE_CONNECTOR_VGA: |
747 | case DRM_MODE_CONNECTOR_VGA: |
771 | return ATOM_ENCODER_MODE_CRT; |
748 | return ATOM_ENCODER_MODE_CRT; |
772 | break; |
749 | break; |
773 | case DRM_MODE_CONNECTOR_Composite: |
750 | case DRM_MODE_CONNECTOR_Composite: |
774 | case DRM_MODE_CONNECTOR_SVIDEO: |
751 | case DRM_MODE_CONNECTOR_SVIDEO: |
775 | case DRM_MODE_CONNECTOR_9PinDIN: |
752 | case DRM_MODE_CONNECTOR_9PinDIN: |
776 | /* fix me */ |
753 | /* fix me */ |
777 | return ATOM_ENCODER_MODE_TV; |
754 | return ATOM_ENCODER_MODE_TV; |
778 | /*return ATOM_ENCODER_MODE_CV;*/ |
755 | /*return ATOM_ENCODER_MODE_CV;*/ |
779 | break; |
756 | break; |
780 | } |
757 | } |
781 | } |
758 | } |
782 | 759 | ||
783 | /* |
760 | /* |
784 | * DIG Encoder/Transmitter Setup |
761 | * DIG Encoder/Transmitter Setup |
785 | * |
762 | * |
786 | * DCE 3.0/3.1 |
763 | * DCE 3.0/3.1 |
787 | * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. |
764 | * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. |
788 | * Supports up to 3 digital outputs |
765 | * Supports up to 3 digital outputs |
789 | * - 2 DIG encoder blocks. |
766 | * - 2 DIG encoder blocks. |
790 | * DIG1 can drive UNIPHY link A or link B |
767 | * DIG1 can drive UNIPHY link A or link B |
791 | * DIG2 can drive UNIPHY link B or LVTMA |
768 | * DIG2 can drive UNIPHY link B or LVTMA |
792 | * |
769 | * |
793 | * DCE 3.2 |
770 | * DCE 3.2 |
794 | * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). |
771 | * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). |
795 | * Supports up to 5 digital outputs |
772 | * Supports up to 5 digital outputs |
796 | * - 2 DIG encoder blocks. |
773 | * - 2 DIG encoder blocks. |
797 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
774 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
798 | * |
775 | * |
799 | * DCE 4.0/5.0/6.0 |
776 | * DCE 4.0/5.0/6.0 |
800 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
777 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
801 | * Supports up to 6 digital outputs |
778 | * Supports up to 6 digital outputs |
802 | * - 6 DIG encoder blocks. |
779 | * - 6 DIG encoder blocks. |
803 | * - DIG to PHY mapping is hardcoded |
780 | * - DIG to PHY mapping is hardcoded |
804 | * DIG1 drives UNIPHY0 link A, A+B |
781 | * DIG1 drives UNIPHY0 link A, A+B |
805 | * DIG2 drives UNIPHY0 link B |
782 | * DIG2 drives UNIPHY0 link B |
806 | * DIG3 drives UNIPHY1 link A, A+B |
783 | * DIG3 drives UNIPHY1 link A, A+B |
807 | * DIG4 drives UNIPHY1 link B |
784 | * DIG4 drives UNIPHY1 link B |
808 | * DIG5 drives UNIPHY2 link A, A+B |
785 | * DIG5 drives UNIPHY2 link A, A+B |
809 | * DIG6 drives UNIPHY2 link B |
786 | * DIG6 drives UNIPHY2 link B |
810 | * |
787 | * |
811 | * DCE 4.1 |
788 | * DCE 4.1 |
812 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
789 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
813 | * Supports up to 6 digital outputs |
790 | * Supports up to 6 digital outputs |
814 | * - 2 DIG encoder blocks. |
791 | * - 2 DIG encoder blocks. |
815 | * llano |
792 | * llano |
816 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
793 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
817 | * ontario |
794 | * ontario |
818 | * DIG1 drives UNIPHY0/1/2 link A |
795 | * DIG1 drives UNIPHY0/1/2 link A |
819 | * DIG2 drives UNIPHY0/1/2 link B |
796 | * DIG2 drives UNIPHY0/1/2 link B |
820 | * |
797 | * |
821 | * Routing |
798 | * Routing |
822 | * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) |
799 | * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) |
823 | * Examples: |
800 | * Examples: |
824 | * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI |
801 | * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI |
825 | * crtc1 -> dig1 -> UNIPHY0 link B -> DP |
802 | * crtc1 -> dig1 -> UNIPHY0 link B -> DP |
826 | * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS |
803 | * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS |
827 | * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI |
804 | * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI |
828 | */ |
805 | */ |
829 | 806 | ||
830 | union dig_encoder_control { |
807 | union dig_encoder_control { |
831 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; |
808 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; |
832 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; |
809 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; |
833 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; |
810 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; |
834 | DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; |
811 | DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; |
835 | }; |
812 | }; |
836 | 813 | ||
837 | void |
814 | void |
838 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) |
815 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) |
839 | { |
816 | { |
840 | struct drm_device *dev = encoder->dev; |
817 | struct drm_device *dev = encoder->dev; |
841 | struct radeon_device *rdev = dev->dev_private; |
818 | struct radeon_device *rdev = dev->dev_private; |
842 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
819 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
843 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
820 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
844 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
821 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
845 | union dig_encoder_control args; |
822 | union dig_encoder_control args; |
846 | int index = 0; |
823 | int index = 0; |
847 | uint8_t frev, crev; |
824 | uint8_t frev, crev; |
848 | int dp_clock = 0; |
825 | int dp_clock = 0; |
849 | int dp_lane_count = 0; |
826 | int dp_lane_count = 0; |
850 | int hpd_id = RADEON_HPD_NONE; |
827 | int hpd_id = RADEON_HPD_NONE; |
851 | 828 | ||
852 | if (connector) { |
829 | if (connector) { |
853 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
830 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
854 | struct radeon_connector_atom_dig *dig_connector = |
831 | struct radeon_connector_atom_dig *dig_connector = |
855 | radeon_connector->con_priv; |
832 | radeon_connector->con_priv; |
856 | 833 | ||
857 | dp_clock = dig_connector->dp_clock; |
834 | dp_clock = dig_connector->dp_clock; |
858 | dp_lane_count = dig_connector->dp_lane_count; |
835 | dp_lane_count = dig_connector->dp_lane_count; |
859 | hpd_id = radeon_connector->hpd.hpd; |
836 | hpd_id = radeon_connector->hpd.hpd; |
860 | } |
837 | } |
861 | 838 | ||
862 | /* no dig encoder assigned */ |
839 | /* no dig encoder assigned */ |
863 | if (dig->dig_encoder == -1) |
840 | if (dig->dig_encoder == -1) |
864 | return; |
841 | return; |
865 | 842 | ||
866 | memset(&args, 0, sizeof(args)); |
843 | memset(&args, 0, sizeof(args)); |
867 | 844 | ||
868 | if (ASIC_IS_DCE4(rdev)) |
845 | if (ASIC_IS_DCE4(rdev)) |
869 | index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); |
846 | index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); |
870 | else { |
847 | else { |
871 | if (dig->dig_encoder) |
848 | if (dig->dig_encoder) |
872 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
849 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
873 | else |
850 | else |
874 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); |
851 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); |
875 | } |
852 | } |
876 | 853 | ||
877 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
854 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
878 | return; |
855 | return; |
879 | 856 | ||
880 | switch (frev) { |
857 | switch (frev) { |
881 | case 1: |
858 | case 1: |
882 | switch (crev) { |
859 | switch (crev) { |
883 | case 1: |
860 | case 1: |
884 | args.v1.ucAction = action; |
861 | args.v1.ucAction = action; |
885 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
862 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
886 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) |
863 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) |
887 | args.v3.ucPanelMode = panel_mode; |
864 | args.v3.ucPanelMode = panel_mode; |
888 | else |
865 | else |
889 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); |
866 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); |
890 | 867 | ||
891 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) |
868 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) |
892 | args.v1.ucLaneNum = dp_lane_count; |
869 | args.v1.ucLaneNum = dp_lane_count; |
893 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
870 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
894 | args.v1.ucLaneNum = 8; |
871 | args.v1.ucLaneNum = 8; |
895 | else |
872 | else |
896 | args.v1.ucLaneNum = 4; |
873 | args.v1.ucLaneNum = 4; |
897 | 874 | ||
898 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) |
875 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) |
899 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
876 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
900 | switch (radeon_encoder->encoder_id) { |
877 | switch (radeon_encoder->encoder_id) { |
901 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
878 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
902 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
879 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
903 | break; |
880 | break; |
904 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
881 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
905 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
882 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
906 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; |
883 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; |
907 | break; |
884 | break; |
908 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
885 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
909 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
886 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
910 | break; |
887 | break; |
911 | } |
888 | } |
912 | if (dig->linkb) |
889 | if (dig->linkb) |
913 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; |
890 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; |
914 | else |
891 | else |
915 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; |
892 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; |
916 | break; |
893 | break; |
917 | case 2: |
894 | case 2: |
918 | case 3: |
895 | case 3: |
919 | args.v3.ucAction = action; |
896 | args.v3.ucAction = action; |
920 | args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
897 | args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
921 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) |
898 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) |
922 | args.v3.ucPanelMode = panel_mode; |
899 | args.v3.ucPanelMode = panel_mode; |
923 | else |
900 | else |
924 | args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); |
901 | args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); |
925 | 902 | ||
926 | if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) |
903 | if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) |
927 | args.v3.ucLaneNum = dp_lane_count; |
904 | args.v3.ucLaneNum = dp_lane_count; |
928 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
905 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
929 | args.v3.ucLaneNum = 8; |
906 | args.v3.ucLaneNum = 8; |
930 | else |
907 | else |
931 | args.v3.ucLaneNum = 4; |
908 | args.v3.ucLaneNum = 4; |
932 | 909 | ||
933 | if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) |
910 | if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) |
934 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
911 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
935 | args.v3.acConfig.ucDigSel = dig->dig_encoder; |
912 | args.v3.acConfig.ucDigSel = dig->dig_encoder; |
936 | args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); |
913 | args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); |
937 | break; |
914 | break; |
938 | case 4: |
915 | case 4: |
939 | args.v4.ucAction = action; |
916 | args.v4.ucAction = action; |
940 | args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
917 | args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
941 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) |
918 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) |
942 | args.v4.ucPanelMode = panel_mode; |
919 | args.v4.ucPanelMode = panel_mode; |
943 | else |
920 | else |
944 | args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); |
921 | args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); |
945 | 922 | ||
946 | if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) |
923 | if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) |
947 | args.v4.ucLaneNum = dp_lane_count; |
924 | args.v4.ucLaneNum = dp_lane_count; |
948 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
925 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
949 | args.v4.ucLaneNum = 8; |
926 | args.v4.ucLaneNum = 8; |
950 | else |
927 | else |
951 | args.v4.ucLaneNum = 4; |
928 | args.v4.ucLaneNum = 4; |
952 | 929 | ||
953 | if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { |
930 | if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { |
954 | if (dp_clock == 540000) |
931 | if (dp_clock == 540000) |
955 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; |
932 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; |
956 | else if (dp_clock == 324000) |
933 | else if (dp_clock == 324000) |
957 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; |
934 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; |
958 | else if (dp_clock == 270000) |
935 | else if (dp_clock == 270000) |
959 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; |
936 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; |
960 | else |
937 | else |
961 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; |
938 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; |
962 | } |
939 | } |
963 | args.v4.acConfig.ucDigSel = dig->dig_encoder; |
940 | args.v4.acConfig.ucDigSel = dig->dig_encoder; |
964 | args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); |
941 | args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); |
965 | if (hpd_id == RADEON_HPD_NONE) |
942 | if (hpd_id == RADEON_HPD_NONE) |
966 | args.v4.ucHPD_ID = 0; |
943 | args.v4.ucHPD_ID = 0; |
967 | else |
944 | else |
968 | args.v4.ucHPD_ID = hpd_id + 1; |
945 | args.v4.ucHPD_ID = hpd_id + 1; |
969 | break; |
946 | break; |
970 | default: |
947 | default: |
971 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
948 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
972 | break; |
949 | break; |
973 | } |
950 | } |
974 | break; |
951 | break; |
975 | default: |
952 | default: |
976 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
953 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
977 | break; |
954 | break; |
978 | } |
955 | } |
979 | 956 | ||
980 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
957 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
981 | 958 | ||
982 | } |
959 | } |
983 | 960 | ||
984 | union dig_transmitter_control { |
961 | union dig_transmitter_control { |
985 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; |
962 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; |
986 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; |
963 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; |
987 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; |
964 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; |
988 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; |
965 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; |
989 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; |
966 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; |
990 | }; |
967 | }; |
991 | 968 | ||
992 | void |
969 | void |
993 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) |
970 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) |
994 | { |
971 | { |
995 | struct drm_device *dev = encoder->dev; |
972 | struct drm_device *dev = encoder->dev; |
996 | struct radeon_device *rdev = dev->dev_private; |
973 | struct radeon_device *rdev = dev->dev_private; |
997 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
974 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
998 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
975 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
999 | struct drm_connector *connector; |
976 | struct drm_connector *connector; |
1000 | union dig_transmitter_control args; |
977 | union dig_transmitter_control args; |
1001 | int index = 0; |
978 | int index = 0; |
1002 | uint8_t frev, crev; |
979 | uint8_t frev, crev; |
1003 | bool is_dp = false; |
980 | bool is_dp = false; |
1004 | int pll_id = 0; |
981 | int pll_id = 0; |
1005 | int dp_clock = 0; |
982 | int dp_clock = 0; |
1006 | int dp_lane_count = 0; |
983 | int dp_lane_count = 0; |
1007 | int connector_object_id = 0; |
984 | int connector_object_id = 0; |
1008 | int igp_lane_info = 0; |
985 | int igp_lane_info = 0; |
1009 | int dig_encoder = dig->dig_encoder; |
986 | int dig_encoder = dig->dig_encoder; |
1010 | int hpd_id = RADEON_HPD_NONE; |
987 | int hpd_id = RADEON_HPD_NONE; |
1011 | 988 | ||
1012 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
989 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
1013 | connector = radeon_get_connector_for_encoder_init(encoder); |
990 | connector = radeon_get_connector_for_encoder_init(encoder); |
1014 | /* just needed to avoid bailing in the encoder check. the encoder |
991 | /* just needed to avoid bailing in the encoder check. the encoder |
1015 | * isn't used for init |
992 | * isn't used for init |
1016 | */ |
993 | */ |
1017 | dig_encoder = 0; |
994 | dig_encoder = 0; |
1018 | } else |
995 | } else |
1019 | connector = radeon_get_connector_for_encoder(encoder); |
996 | connector = radeon_get_connector_for_encoder(encoder); |
1020 | 997 | ||
1021 | if (connector) { |
998 | if (connector) { |
1022 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
999 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1023 | struct radeon_connector_atom_dig *dig_connector = |
1000 | struct radeon_connector_atom_dig *dig_connector = |
1024 | radeon_connector->con_priv; |
1001 | radeon_connector->con_priv; |
1025 | 1002 | ||
1026 | hpd_id = radeon_connector->hpd.hpd; |
1003 | hpd_id = radeon_connector->hpd.hpd; |
1027 | dp_clock = dig_connector->dp_clock; |
1004 | dp_clock = dig_connector->dp_clock; |
1028 | dp_lane_count = dig_connector->dp_lane_count; |
1005 | dp_lane_count = dig_connector->dp_lane_count; |
1029 | connector_object_id = |
1006 | connector_object_id = |
1030 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
1007 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
1031 | igp_lane_info = dig_connector->igp_lane_info; |
1008 | igp_lane_info = dig_connector->igp_lane_info; |
1032 | } |
1009 | } |
1033 | 1010 | ||
1034 | if (encoder->crtc) { |
1011 | if (encoder->crtc) { |
1035 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1012 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1036 | pll_id = radeon_crtc->pll_id; |
1013 | pll_id = radeon_crtc->pll_id; |
1037 | } |
1014 | } |
1038 | 1015 | ||
1039 | /* no dig encoder assigned */ |
1016 | /* no dig encoder assigned */ |
1040 | if (dig_encoder == -1) |
1017 | if (dig_encoder == -1) |
1041 | return; |
1018 | return; |
1042 | 1019 | ||
1043 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) |
1020 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) |
1044 | is_dp = true; |
1021 | is_dp = true; |
1045 | 1022 | ||
1046 | memset(&args, 0, sizeof(args)); |
1023 | memset(&args, 0, sizeof(args)); |
1047 | 1024 | ||
1048 | switch (radeon_encoder->encoder_id) { |
1025 | switch (radeon_encoder->encoder_id) { |
1049 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1026 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1050 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
1027 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
1051 | break; |
1028 | break; |
1052 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1029 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1053 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1030 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1054 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1031 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1055 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
1032 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
1056 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
1033 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
1057 | break; |
1034 | break; |
1058 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1035 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1059 | index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); |
1036 | index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); |
1060 | break; |
1037 | break; |
1061 | } |
1038 | } |
1062 | 1039 | ||
1063 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1040 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1064 | return; |
1041 | return; |
1065 | 1042 | ||
1066 | switch (frev) { |
1043 | switch (frev) { |
1067 | case 1: |
1044 | case 1: |
1068 | switch (crev) { |
1045 | switch (crev) { |
1069 | case 1: |
1046 | case 1: |
1070 | args.v1.ucAction = action; |
1047 | args.v1.ucAction = action; |
1071 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
1048 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
1072 | args.v1.usInitInfo = cpu_to_le16(connector_object_id); |
1049 | args.v1.usInitInfo = cpu_to_le16(connector_object_id); |
1073 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
1050 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
1074 | args.v1.asMode.ucLaneSel = lane_num; |
1051 | args.v1.asMode.ucLaneSel = lane_num; |
1075 | args.v1.asMode.ucLaneSet = lane_set; |
1052 | args.v1.asMode.ucLaneSet = lane_set; |
1076 | } else { |
1053 | } else { |
1077 | if (is_dp) |
1054 | if (is_dp) |
1078 | args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); |
1055 | args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); |
1079 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1056 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1080 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1057 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1081 | else |
1058 | else |
1082 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1059 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1083 | } |
1060 | } |
1084 | 1061 | ||
1085 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
1062 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
1086 | 1063 | ||
1087 | if (dig_encoder) |
1064 | if (dig_encoder) |
1088 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; |
1065 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; |
1089 | else |
1066 | else |
1090 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; |
1067 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; |
1091 | 1068 | ||
1092 | if ((rdev->flags & RADEON_IS_IGP) && |
1069 | if ((rdev->flags & RADEON_IS_IGP) && |
1093 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { |
1070 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { |
1094 | if (is_dp || |
1071 | if (is_dp || |
1095 | !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { |
1072 | !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { |
1096 | if (igp_lane_info & 0x1) |
1073 | if (igp_lane_info & 0x1) |
1097 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
1074 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
1098 | else if (igp_lane_info & 0x2) |
1075 | else if (igp_lane_info & 0x2) |
1099 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; |
1076 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; |
1100 | else if (igp_lane_info & 0x4) |
1077 | else if (igp_lane_info & 0x4) |
1101 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; |
1078 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; |
1102 | else if (igp_lane_info & 0x8) |
1079 | else if (igp_lane_info & 0x8) |
1103 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; |
1080 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; |
1104 | } else { |
1081 | } else { |
1105 | if (igp_lane_info & 0x3) |
1082 | if (igp_lane_info & 0x3) |
1106 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; |
1083 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; |
1107 | else if (igp_lane_info & 0xc) |
1084 | else if (igp_lane_info & 0xc) |
1108 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; |
1085 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; |
1109 | } |
1086 | } |
1110 | } |
1087 | } |
1111 | 1088 | ||
1112 | if (dig->linkb) |
1089 | if (dig->linkb) |
1113 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; |
1090 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; |
1114 | else |
1091 | else |
1115 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; |
1092 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; |
1116 | 1093 | ||
1117 | if (is_dp) |
1094 | if (is_dp) |
1118 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
1095 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
1119 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1096 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1120 | if (dig->coherent_mode) |
1097 | if (dig->coherent_mode) |
1121 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
1098 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
1122 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1099 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1123 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; |
1100 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; |
1124 | } |
1101 | } |
1125 | break; |
1102 | break; |
1126 | case 2: |
1103 | case 2: |
1127 | args.v2.ucAction = action; |
1104 | args.v2.ucAction = action; |
1128 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
1105 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
1129 | args.v2.usInitInfo = cpu_to_le16(connector_object_id); |
1106 | args.v2.usInitInfo = cpu_to_le16(connector_object_id); |
1130 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
1107 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
1131 | args.v2.asMode.ucLaneSel = lane_num; |
1108 | args.v2.asMode.ucLaneSel = lane_num; |
1132 | args.v2.asMode.ucLaneSet = lane_set; |
1109 | args.v2.asMode.ucLaneSet = lane_set; |
1133 | } else { |
1110 | } else { |
1134 | if (is_dp) |
1111 | if (is_dp) |
1135 | args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); |
1112 | args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); |
1136 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1113 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1137 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1114 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1138 | else |
1115 | else |
1139 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1116 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1140 | } |
1117 | } |
1141 | 1118 | ||
1142 | args.v2.acConfig.ucEncoderSel = dig_encoder; |
1119 | args.v2.acConfig.ucEncoderSel = dig_encoder; |
1143 | if (dig->linkb) |
1120 | if (dig->linkb) |
1144 | args.v2.acConfig.ucLinkSel = 1; |
1121 | args.v2.acConfig.ucLinkSel = 1; |
1145 | 1122 | ||
1146 | switch (radeon_encoder->encoder_id) { |
1123 | switch (radeon_encoder->encoder_id) { |
1147 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1124 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1148 | args.v2.acConfig.ucTransmitterSel = 0; |
1125 | args.v2.acConfig.ucTransmitterSel = 0; |
1149 | break; |
1126 | break; |
1150 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1127 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1151 | args.v2.acConfig.ucTransmitterSel = 1; |
1128 | args.v2.acConfig.ucTransmitterSel = 1; |
1152 | break; |
1129 | break; |
1153 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1130 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1154 | args.v2.acConfig.ucTransmitterSel = 2; |
1131 | args.v2.acConfig.ucTransmitterSel = 2; |
1155 | break; |
1132 | break; |
1156 | } |
1133 | } |
1157 | 1134 | ||
1158 | if (is_dp) { |
1135 | if (is_dp) { |
1159 | args.v2.acConfig.fCoherentMode = 1; |
1136 | args.v2.acConfig.fCoherentMode = 1; |
1160 | args.v2.acConfig.fDPConnector = 1; |
1137 | args.v2.acConfig.fDPConnector = 1; |
1161 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1138 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1162 | if (dig->coherent_mode) |
1139 | if (dig->coherent_mode) |
1163 | args.v2.acConfig.fCoherentMode = 1; |
1140 | args.v2.acConfig.fCoherentMode = 1; |
1164 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1141 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1165 | args.v2.acConfig.fDualLinkConnector = 1; |
1142 | args.v2.acConfig.fDualLinkConnector = 1; |
1166 | } |
1143 | } |
1167 | break; |
1144 | break; |
1168 | case 3: |
1145 | case 3: |
1169 | args.v3.ucAction = action; |
1146 | args.v3.ucAction = action; |
1170 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
1147 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
1171 | args.v3.usInitInfo = cpu_to_le16(connector_object_id); |
1148 | args.v3.usInitInfo = cpu_to_le16(connector_object_id); |
1172 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
1149 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
1173 | args.v3.asMode.ucLaneSel = lane_num; |
1150 | args.v3.asMode.ucLaneSel = lane_num; |
1174 | args.v3.asMode.ucLaneSet = lane_set; |
1151 | args.v3.asMode.ucLaneSet = lane_set; |
1175 | } else { |
1152 | } else { |
1176 | if (is_dp) |
1153 | if (is_dp) |
1177 | args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); |
1154 | args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); |
1178 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1155 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1179 | args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1156 | args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1180 | else |
1157 | else |
1181 | args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1158 | args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1182 | } |
1159 | } |
1183 | 1160 | ||
1184 | if (is_dp) |
1161 | if (is_dp) |
1185 | args.v3.ucLaneNum = dp_lane_count; |
1162 | args.v3.ucLaneNum = dp_lane_count; |
1186 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1163 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1187 | args.v3.ucLaneNum = 8; |
1164 | args.v3.ucLaneNum = 8; |
1188 | else |
1165 | else |
1189 | args.v3.ucLaneNum = 4; |
1166 | args.v3.ucLaneNum = 4; |
1190 | 1167 | ||
1191 | if (dig->linkb) |
1168 | if (dig->linkb) |
1192 | args.v3.acConfig.ucLinkSel = 1; |
1169 | args.v3.acConfig.ucLinkSel = 1; |
1193 | if (dig_encoder & 1) |
1170 | if (dig_encoder & 1) |
1194 | args.v3.acConfig.ucEncoderSel = 1; |
1171 | args.v3.acConfig.ucEncoderSel = 1; |
1195 | 1172 | ||
1196 | /* Select the PLL for the PHY |
1173 | /* Select the PLL for the PHY |
1197 | * DP PHY should be clocked from external src if there is |
1174 | * DP PHY should be clocked from external src if there is |
1198 | * one. |
1175 | * one. |
1199 | */ |
1176 | */ |
1200 | /* On DCE4, if there is an external clock, it generates the DP ref clock */ |
1177 | /* On DCE4, if there is an external clock, it generates the DP ref clock */ |
1201 | if (is_dp && rdev->clock.dp_extclk) |
1178 | if (is_dp && rdev->clock.dp_extclk) |
1202 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ |
1179 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ |
1203 | else |
1180 | else |
1204 | args.v3.acConfig.ucRefClkSource = pll_id; |
1181 | args.v3.acConfig.ucRefClkSource = pll_id; |
1205 | 1182 | ||
1206 | switch (radeon_encoder->encoder_id) { |
1183 | switch (radeon_encoder->encoder_id) { |
1207 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1184 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1208 | args.v3.acConfig.ucTransmitterSel = 0; |
1185 | args.v3.acConfig.ucTransmitterSel = 0; |
1209 | break; |
1186 | break; |
1210 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1187 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1211 | args.v3.acConfig.ucTransmitterSel = 1; |
1188 | args.v3.acConfig.ucTransmitterSel = 1; |
1212 | break; |
1189 | break; |
1213 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1190 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1214 | args.v3.acConfig.ucTransmitterSel = 2; |
1191 | args.v3.acConfig.ucTransmitterSel = 2; |
1215 | break; |
1192 | break; |
1216 | } |
1193 | } |
1217 | 1194 | ||
1218 | if (is_dp) |
1195 | if (is_dp) |
1219 | args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ |
1196 | args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ |
1220 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1197 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1221 | if (dig->coherent_mode) |
1198 | if (dig->coherent_mode) |
1222 | args.v3.acConfig.fCoherentMode = 1; |
1199 | args.v3.acConfig.fCoherentMode = 1; |
1223 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1200 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1224 | args.v3.acConfig.fDualLinkConnector = 1; |
1201 | args.v3.acConfig.fDualLinkConnector = 1; |
1225 | } |
1202 | } |
1226 | break; |
1203 | break; |
1227 | case 4: |
1204 | case 4: |
1228 | args.v4.ucAction = action; |
1205 | args.v4.ucAction = action; |
1229 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
1206 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
1230 | args.v4.usInitInfo = cpu_to_le16(connector_object_id); |
1207 | args.v4.usInitInfo = cpu_to_le16(connector_object_id); |
1231 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
1208 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
1232 | args.v4.asMode.ucLaneSel = lane_num; |
1209 | args.v4.asMode.ucLaneSel = lane_num; |
1233 | args.v4.asMode.ucLaneSet = lane_set; |
1210 | args.v4.asMode.ucLaneSet = lane_set; |
1234 | } else { |
1211 | } else { |
1235 | if (is_dp) |
1212 | if (is_dp) |
1236 | args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); |
1213 | args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); |
1237 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1214 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1238 | args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1215 | args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1239 | else |
1216 | else |
1240 | args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1217 | args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1241 | } |
1218 | } |
1242 | 1219 | ||
1243 | if (is_dp) |
1220 | if (is_dp) |
1244 | args.v4.ucLaneNum = dp_lane_count; |
1221 | args.v4.ucLaneNum = dp_lane_count; |
1245 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1222 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1246 | args.v4.ucLaneNum = 8; |
1223 | args.v4.ucLaneNum = 8; |
1247 | else |
1224 | else |
1248 | args.v4.ucLaneNum = 4; |
1225 | args.v4.ucLaneNum = 4; |
1249 | 1226 | ||
1250 | if (dig->linkb) |
1227 | if (dig->linkb) |
1251 | args.v4.acConfig.ucLinkSel = 1; |
1228 | args.v4.acConfig.ucLinkSel = 1; |
1252 | if (dig_encoder & 1) |
1229 | if (dig_encoder & 1) |
1253 | args.v4.acConfig.ucEncoderSel = 1; |
1230 | args.v4.acConfig.ucEncoderSel = 1; |
1254 | 1231 | ||
1255 | /* Select the PLL for the PHY |
1232 | /* Select the PLL for the PHY |
1256 | * DP PHY should be clocked from external src if there is |
1233 | * DP PHY should be clocked from external src if there is |
1257 | * one. |
1234 | * one. |
1258 | */ |
1235 | */ |
1259 | /* On DCE5 DCPLL usually generates the DP ref clock */ |
1236 | /* On DCE5 DCPLL usually generates the DP ref clock */ |
1260 | if (is_dp) { |
1237 | if (is_dp) { |
1261 | if (rdev->clock.dp_extclk) |
1238 | if (rdev->clock.dp_extclk) |
1262 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; |
1239 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; |
1263 | else |
1240 | else |
1264 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; |
1241 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; |
1265 | } else |
1242 | } else |
1266 | args.v4.acConfig.ucRefClkSource = pll_id; |
1243 | args.v4.acConfig.ucRefClkSource = pll_id; |
1267 | 1244 | ||
1268 | switch (radeon_encoder->encoder_id) { |
1245 | switch (radeon_encoder->encoder_id) { |
1269 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1246 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1270 | args.v4.acConfig.ucTransmitterSel = 0; |
1247 | args.v4.acConfig.ucTransmitterSel = 0; |
1271 | break; |
1248 | break; |
1272 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1249 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1273 | args.v4.acConfig.ucTransmitterSel = 1; |
1250 | args.v4.acConfig.ucTransmitterSel = 1; |
1274 | break; |
1251 | break; |
1275 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1252 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1276 | args.v4.acConfig.ucTransmitterSel = 2; |
1253 | args.v4.acConfig.ucTransmitterSel = 2; |
1277 | break; |
1254 | break; |
1278 | } |
1255 | } |
1279 | 1256 | ||
1280 | if (is_dp) |
1257 | if (is_dp) |
1281 | args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ |
1258 | args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ |
1282 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1259 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1283 | if (dig->coherent_mode) |
1260 | if (dig->coherent_mode) |
1284 | args.v4.acConfig.fCoherentMode = 1; |
1261 | args.v4.acConfig.fCoherentMode = 1; |
1285 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1262 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1286 | args.v4.acConfig.fDualLinkConnector = 1; |
1263 | args.v4.acConfig.fDualLinkConnector = 1; |
1287 | } |
1264 | } |
1288 | break; |
1265 | break; |
1289 | case 5: |
1266 | case 5: |
1290 | args.v5.ucAction = action; |
1267 | args.v5.ucAction = action; |
1291 | if (is_dp) |
1268 | if (is_dp) |
1292 | args.v5.usSymClock = cpu_to_le16(dp_clock / 10); |
1269 | args.v5.usSymClock = cpu_to_le16(dp_clock / 10); |
1293 | else |
1270 | else |
1294 | args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1271 | args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1295 | 1272 | ||
1296 | switch (radeon_encoder->encoder_id) { |
1273 | switch (radeon_encoder->encoder_id) { |
1297 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1274 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1298 | if (dig->linkb) |
1275 | if (dig->linkb) |
1299 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; |
1276 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; |
1300 | else |
1277 | else |
1301 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; |
1278 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; |
1302 | break; |
1279 | break; |
1303 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1280 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1304 | if (dig->linkb) |
1281 | if (dig->linkb) |
1305 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; |
1282 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; |
1306 | else |
1283 | else |
1307 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; |
1284 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; |
1308 | break; |
1285 | break; |
1309 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1286 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1310 | if (dig->linkb) |
1287 | if (dig->linkb) |
1311 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; |
1288 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; |
1312 | else |
1289 | else |
1313 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; |
1290 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; |
1314 | break; |
1291 | break; |
1315 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
1292 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
1316 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; |
1293 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; |
1317 | break; |
1294 | break; |
1318 | } |
1295 | } |
1319 | if (is_dp) |
1296 | if (is_dp) |
1320 | args.v5.ucLaneNum = dp_lane_count; |
1297 | args.v5.ucLaneNum = dp_lane_count; |
1321 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1298 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1322 | args.v5.ucLaneNum = 8; |
1299 | args.v5.ucLaneNum = 8; |
1323 | else |
1300 | else |
1324 | args.v5.ucLaneNum = 4; |
1301 | args.v5.ucLaneNum = 4; |
1325 | args.v5.ucConnObjId = connector_object_id; |
1302 | args.v5.ucConnObjId = connector_object_id; |
1326 | args.v5.ucDigMode = atombios_get_encoder_mode(encoder); |
1303 | args.v5.ucDigMode = atombios_get_encoder_mode(encoder); |
1327 | 1304 | ||
1328 | if (is_dp && rdev->clock.dp_extclk) |
1305 | if (is_dp && rdev->clock.dp_extclk) |
1329 | args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; |
1306 | args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; |
1330 | else |
1307 | else |
1331 | args.v5.asConfig.ucPhyClkSrcId = pll_id; |
1308 | args.v5.asConfig.ucPhyClkSrcId = pll_id; |
1332 | 1309 | ||
1333 | if (is_dp) |
1310 | if (is_dp) |
1334 | args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ |
1311 | args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ |
1335 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1312 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
1336 | if (dig->coherent_mode) |
1313 | if (dig->coherent_mode) |
1337 | args.v5.asConfig.ucCoherentMode = 1; |
1314 | args.v5.asConfig.ucCoherentMode = 1; |
1338 | } |
1315 | } |
1339 | if (hpd_id == RADEON_HPD_NONE) |
1316 | if (hpd_id == RADEON_HPD_NONE) |
1340 | args.v5.asConfig.ucHPDSel = 0; |
1317 | args.v5.asConfig.ucHPDSel = 0; |
1341 | else |
1318 | else |
1342 | args.v5.asConfig.ucHPDSel = hpd_id + 1; |
1319 | args.v5.asConfig.ucHPDSel = hpd_id + 1; |
1343 | args.v5.ucDigEncoderSel = 1 << dig_encoder; |
1320 | args.v5.ucDigEncoderSel = 1 << dig_encoder; |
1344 | args.v5.ucDPLaneSet = lane_set; |
1321 | args.v5.ucDPLaneSet = lane_set; |
1345 | break; |
1322 | break; |
1346 | default: |
1323 | default: |
1347 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
1324 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
1348 | break; |
1325 | break; |
1349 | } |
1326 | } |
1350 | break; |
1327 | break; |
1351 | default: |
1328 | default: |
1352 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
1329 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
1353 | break; |
1330 | break; |
1354 | } |
1331 | } |
1355 | 1332 | ||
1356 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1333 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1357 | } |
1334 | } |
1358 | 1335 | ||
1359 | bool |
1336 | bool |
1360 | atombios_set_edp_panel_power(struct drm_connector *connector, int action) |
1337 | atombios_set_edp_panel_power(struct drm_connector *connector, int action) |
1361 | { |
1338 | { |
1362 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1339 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1363 | struct drm_device *dev = radeon_connector->base.dev; |
1340 | struct drm_device *dev = radeon_connector->base.dev; |
1364 | struct radeon_device *rdev = dev->dev_private; |
1341 | struct radeon_device *rdev = dev->dev_private; |
1365 | union dig_transmitter_control args; |
1342 | union dig_transmitter_control args; |
1366 | int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
1343 | int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
1367 | uint8_t frev, crev; |
1344 | uint8_t frev, crev; |
1368 | 1345 | ||
1369 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) |
1346 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) |
1370 | goto done; |
1347 | goto done; |
1371 | 1348 | ||
1372 | if (!ASIC_IS_DCE4(rdev)) |
1349 | if (!ASIC_IS_DCE4(rdev)) |
1373 | goto done; |
1350 | goto done; |
1374 | 1351 | ||
1375 | if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && |
1352 | if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && |
1376 | (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) |
1353 | (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) |
1377 | goto done; |
1354 | goto done; |
1378 | 1355 | ||
1379 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1356 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1380 | goto done; |
1357 | goto done; |
1381 | 1358 | ||
1382 | memset(&args, 0, sizeof(args)); |
1359 | memset(&args, 0, sizeof(args)); |
1383 | 1360 | ||
1384 | args.v1.ucAction = action; |
1361 | args.v1.ucAction = action; |
1385 | 1362 | ||
1386 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1363 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1387 | 1364 | ||
1388 | /* wait for the panel to power up */ |
1365 | /* wait for the panel to power up */ |
1389 | if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { |
1366 | if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { |
1390 | int i; |
1367 | int i; |
1391 | 1368 | ||
1392 | for (i = 0; i < 300; i++) { |
1369 | for (i = 0; i < 300; i++) { |
1393 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) |
1370 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) |
1394 | return true; |
1371 | return true; |
1395 | mdelay(1); |
1372 | mdelay(1); |
1396 | } |
1373 | } |
1397 | return false; |
1374 | return false; |
1398 | } |
1375 | } |
1399 | done: |
1376 | done: |
1400 | return true; |
1377 | return true; |
1401 | } |
1378 | } |
1402 | 1379 | ||
1403 | union external_encoder_control { |
1380 | union external_encoder_control { |
1404 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; |
1381 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; |
1405 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; |
1382 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; |
1406 | }; |
1383 | }; |
1407 | 1384 | ||
1408 | static void |
1385 | static void |
1409 | atombios_external_encoder_setup(struct drm_encoder *encoder, |
1386 | atombios_external_encoder_setup(struct drm_encoder *encoder, |
1410 | struct drm_encoder *ext_encoder, |
1387 | struct drm_encoder *ext_encoder, |
1411 | int action) |
1388 | int action) |
1412 | { |
1389 | { |
1413 | struct drm_device *dev = encoder->dev; |
1390 | struct drm_device *dev = encoder->dev; |
1414 | struct radeon_device *rdev = dev->dev_private; |
1391 | struct radeon_device *rdev = dev->dev_private; |
1415 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1392 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1416 | struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); |
1393 | struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); |
1417 | union external_encoder_control args; |
1394 | union external_encoder_control args; |
1418 | struct drm_connector *connector; |
1395 | struct drm_connector *connector; |
1419 | int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); |
1396 | int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); |
1420 | u8 frev, crev; |
1397 | u8 frev, crev; |
1421 | int dp_clock = 0; |
1398 | int dp_clock = 0; |
1422 | int dp_lane_count = 0; |
1399 | int dp_lane_count = 0; |
1423 | int connector_object_id = 0; |
1400 | int connector_object_id = 0; |
1424 | u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
1401 | u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
1425 | 1402 | ||
1426 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) |
1403 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) |
1427 | connector = radeon_get_connector_for_encoder_init(encoder); |
1404 | connector = radeon_get_connector_for_encoder_init(encoder); |
1428 | else |
1405 | else |
1429 | connector = radeon_get_connector_for_encoder(encoder); |
1406 | connector = radeon_get_connector_for_encoder(encoder); |
1430 | 1407 | ||
1431 | if (connector) { |
1408 | if (connector) { |
1432 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1409 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1433 | struct radeon_connector_atom_dig *dig_connector = |
1410 | struct radeon_connector_atom_dig *dig_connector = |
1434 | radeon_connector->con_priv; |
1411 | radeon_connector->con_priv; |
1435 | 1412 | ||
1436 | dp_clock = dig_connector->dp_clock; |
1413 | dp_clock = dig_connector->dp_clock; |
1437 | dp_lane_count = dig_connector->dp_lane_count; |
1414 | dp_lane_count = dig_connector->dp_lane_count; |
1438 | connector_object_id = |
1415 | connector_object_id = |
1439 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
1416 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
1440 | } |
1417 | } |
1441 | 1418 | ||
1442 | memset(&args, 0, sizeof(args)); |
1419 | memset(&args, 0, sizeof(args)); |
1443 | 1420 | ||
1444 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1421 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1445 | return; |
1422 | return; |
1446 | 1423 | ||
1447 | switch (frev) { |
1424 | switch (frev) { |
1448 | case 1: |
1425 | case 1: |
1449 | /* no params on frev 1 */ |
1426 | /* no params on frev 1 */ |
1450 | break; |
1427 | break; |
1451 | case 2: |
1428 | case 2: |
1452 | switch (crev) { |
1429 | switch (crev) { |
1453 | case 1: |
1430 | case 1: |
1454 | case 2: |
1431 | case 2: |
1455 | args.v1.sDigEncoder.ucAction = action; |
1432 | args.v1.sDigEncoder.ucAction = action; |
1456 | args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1433 | args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1457 | args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); |
1434 | args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); |
1458 | 1435 | ||
1459 | if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { |
1436 | if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { |
1460 | if (dp_clock == 270000) |
1437 | if (dp_clock == 270000) |
1461 | args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
1438 | args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
1462 | args.v1.sDigEncoder.ucLaneNum = dp_lane_count; |
1439 | args.v1.sDigEncoder.ucLaneNum = dp_lane_count; |
1463 | } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1440 | } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1464 | args.v1.sDigEncoder.ucLaneNum = 8; |
1441 | args.v1.sDigEncoder.ucLaneNum = 8; |
1465 | else |
1442 | else |
1466 | args.v1.sDigEncoder.ucLaneNum = 4; |
1443 | args.v1.sDigEncoder.ucLaneNum = 4; |
1467 | break; |
1444 | break; |
1468 | case 3: |
1445 | case 3: |
1469 | args.v3.sExtEncoder.ucAction = action; |
1446 | args.v3.sExtEncoder.ucAction = action; |
1470 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) |
1447 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) |
1471 | args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); |
1448 | args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); |
1472 | else |
1449 | else |
1473 | args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1450 | args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1474 | args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); |
1451 | args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); |
1475 | 1452 | ||
1476 | if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { |
1453 | if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { |
1477 | if (dp_clock == 270000) |
1454 | if (dp_clock == 270000) |
1478 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
1455 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
1479 | else if (dp_clock == 540000) |
1456 | else if (dp_clock == 540000) |
1480 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; |
1457 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; |
1481 | args.v3.sExtEncoder.ucLaneNum = dp_lane_count; |
1458 | args.v3.sExtEncoder.ucLaneNum = dp_lane_count; |
1482 | } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1459 | } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1483 | args.v3.sExtEncoder.ucLaneNum = 8; |
1460 | args.v3.sExtEncoder.ucLaneNum = 8; |
1484 | else |
1461 | else |
1485 | args.v3.sExtEncoder.ucLaneNum = 4; |
1462 | args.v3.sExtEncoder.ucLaneNum = 4; |
1486 | switch (ext_enum) { |
1463 | switch (ext_enum) { |
1487 | case GRAPH_OBJECT_ENUM_ID1: |
1464 | case GRAPH_OBJECT_ENUM_ID1: |
1488 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; |
1465 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; |
1489 | break; |
1466 | break; |
1490 | case GRAPH_OBJECT_ENUM_ID2: |
1467 | case GRAPH_OBJECT_ENUM_ID2: |
1491 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; |
1468 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; |
1492 | break; |
1469 | break; |
1493 | case GRAPH_OBJECT_ENUM_ID3: |
1470 | case GRAPH_OBJECT_ENUM_ID3: |
1494 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; |
1471 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; |
1495 | break; |
1472 | break; |
1496 | } |
1473 | } |
1497 | args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); |
1474 | args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); |
1498 | break; |
1475 | break; |
1499 | default: |
1476 | default: |
1500 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1477 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1501 | return; |
1478 | return; |
1502 | } |
1479 | } |
1503 | break; |
1480 | break; |
1504 | default: |
1481 | default: |
1505 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1482 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1506 | return; |
1483 | return; |
1507 | } |
1484 | } |
1508 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1485 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1509 | } |
1486 | } |
1510 | 1487 | ||
1511 | static void |
1488 | static void |
1512 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) |
1489 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) |
1513 | { |
1490 | { |
1514 | struct drm_device *dev = encoder->dev; |
1491 | struct drm_device *dev = encoder->dev; |
1515 | struct radeon_device *rdev = dev->dev_private; |
1492 | struct radeon_device *rdev = dev->dev_private; |
1516 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1493 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1517 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1494 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1518 | ENABLE_YUV_PS_ALLOCATION args; |
1495 | ENABLE_YUV_PS_ALLOCATION args; |
1519 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); |
1496 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); |
1520 | uint32_t temp, reg; |
1497 | uint32_t temp, reg; |
1521 | 1498 | ||
1522 | memset(&args, 0, sizeof(args)); |
1499 | memset(&args, 0, sizeof(args)); |
1523 | 1500 | ||
1524 | if (rdev->family >= CHIP_R600) |
1501 | if (rdev->family >= CHIP_R600) |
1525 | reg = R600_BIOS_3_SCRATCH; |
1502 | reg = R600_BIOS_3_SCRATCH; |
1526 | else |
1503 | else |
1527 | reg = RADEON_BIOS_3_SCRATCH; |
1504 | reg = RADEON_BIOS_3_SCRATCH; |
1528 | 1505 | ||
1529 | /* XXX: fix up scratch reg handling */ |
1506 | /* XXX: fix up scratch reg handling */ |
1530 | temp = RREG32(reg); |
1507 | temp = RREG32(reg); |
1531 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1508 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1532 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
1509 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
1533 | (radeon_crtc->crtc_id << 18))); |
1510 | (radeon_crtc->crtc_id << 18))); |
1534 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1511 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1535 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
1512 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
1536 | else |
1513 | else |
1537 | WREG32(reg, 0); |
1514 | WREG32(reg, 0); |
1538 | 1515 | ||
1539 | if (enable) |
1516 | if (enable) |
1540 | args.ucEnable = ATOM_ENABLE; |
1517 | args.ucEnable = ATOM_ENABLE; |
1541 | args.ucCRTC = radeon_crtc->crtc_id; |
1518 | args.ucCRTC = radeon_crtc->crtc_id; |
1542 | 1519 | ||
1543 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1520 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1544 | 1521 | ||
1545 | WREG32(reg, temp); |
1522 | WREG32(reg, temp); |
1546 | } |
1523 | } |
1547 | 1524 | ||
1548 | static void |
1525 | static void |
1549 | radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) |
1526 | radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) |
1550 | { |
1527 | { |
1551 | struct drm_device *dev = encoder->dev; |
1528 | struct drm_device *dev = encoder->dev; |
1552 | struct radeon_device *rdev = dev->dev_private; |
1529 | struct radeon_device *rdev = dev->dev_private; |
1553 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1530 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1554 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
1531 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
1555 | int index = 0; |
1532 | int index = 0; |
1556 | 1533 | ||
1557 | memset(&args, 0, sizeof(args)); |
1534 | memset(&args, 0, sizeof(args)); |
1558 | 1535 | ||
1559 | switch (radeon_encoder->encoder_id) { |
1536 | switch (radeon_encoder->encoder_id) { |
1560 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1537 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1561 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1538 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1562 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); |
1539 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); |
1563 | break; |
1540 | break; |
1564 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1541 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1565 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1542 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1566 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1543 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1567 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
1544 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
1568 | break; |
1545 | break; |
1569 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1546 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1570 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
1547 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
1571 | break; |
1548 | break; |
1572 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1549 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1573 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1550 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1574 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
1551 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
1575 | else |
1552 | else |
1576 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
1553 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
1577 | break; |
1554 | break; |
1578 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1555 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1579 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1556 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1580 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1557 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1581 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
1558 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
1582 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1559 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1583 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1560 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1584 | else |
1561 | else |
1585 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
1562 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
1586 | break; |
1563 | break; |
1587 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1564 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1588 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1565 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1589 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1566 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1590 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
1567 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
1591 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1568 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1592 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1569 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1593 | else |
1570 | else |
1594 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
1571 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
1595 | break; |
1572 | break; |
1596 | default: |
1573 | default: |
1597 | return; |
1574 | return; |
1598 | } |
1575 | } |
1599 | 1576 | ||
1600 | switch (mode) { |
1577 | switch (mode) { |
1601 | case DRM_MODE_DPMS_ON: |
1578 | case DRM_MODE_DPMS_ON: |
1602 | args.ucAction = ATOM_ENABLE; |
1579 | args.ucAction = ATOM_ENABLE; |
1603 | /* workaround for DVOOutputControl on some RS690 systems */ |
1580 | /* workaround for DVOOutputControl on some RS690 systems */ |
1604 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { |
1581 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { |
1605 | u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); |
1582 | u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); |
1606 | WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); |
1583 | WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); |
1607 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1584 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1608 | WREG32(RADEON_BIOS_3_SCRATCH, reg); |
1585 | WREG32(RADEON_BIOS_3_SCRATCH, reg); |
1609 | } else |
1586 | } else |
1610 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1587 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1611 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1588 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1612 | args.ucAction = ATOM_LCD_BLON; |
1589 | args.ucAction = ATOM_LCD_BLON; |
1613 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1590 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1614 | } |
1591 | } |
1615 | break; |
1592 | break; |
1616 | case DRM_MODE_DPMS_STANDBY: |
1593 | case DRM_MODE_DPMS_STANDBY: |
1617 | case DRM_MODE_DPMS_SUSPEND: |
1594 | case DRM_MODE_DPMS_SUSPEND: |
1618 | case DRM_MODE_DPMS_OFF: |
1595 | case DRM_MODE_DPMS_OFF: |
1619 | args.ucAction = ATOM_DISABLE; |
1596 | args.ucAction = ATOM_DISABLE; |
1620 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1597 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1621 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1598 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1622 | args.ucAction = ATOM_LCD_BLOFF; |
1599 | args.ucAction = ATOM_LCD_BLOFF; |
1623 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1600 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1624 | } |
1601 | } |
1625 | break; |
1602 | break; |
1626 | } |
1603 | } |
1627 | } |
1604 | } |
1628 | 1605 | ||
1629 | static void |
1606 | static void |
1630 | radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) |
1607 | radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) |
1631 | { |
1608 | { |
1632 | struct drm_device *dev = encoder->dev; |
1609 | struct drm_device *dev = encoder->dev; |
1633 | struct radeon_device *rdev = dev->dev_private; |
1610 | struct radeon_device *rdev = dev->dev_private; |
1634 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1611 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1635 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
1612 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
1636 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
1613 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
1637 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1614 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1638 | struct radeon_connector *radeon_connector = NULL; |
1615 | struct radeon_connector *radeon_connector = NULL; |
1639 | struct radeon_connector_atom_dig *radeon_dig_connector = NULL; |
1616 | struct radeon_connector_atom_dig *radeon_dig_connector = NULL; |
1640 | bool travis_quirk = false; |
1617 | bool travis_quirk = false; |
1641 | 1618 | ||
1642 | if (connector) { |
1619 | if (connector) { |
1643 | radeon_connector = to_radeon_connector(connector); |
1620 | radeon_connector = to_radeon_connector(connector); |
1644 | radeon_dig_connector = radeon_connector->con_priv; |
1621 | radeon_dig_connector = radeon_connector->con_priv; |
1645 | if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
1622 | if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
1646 | ENCODER_OBJECT_ID_TRAVIS) && |
1623 | ENCODER_OBJECT_ID_TRAVIS) && |
1647 | (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && |
1624 | (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && |
1648 | !ASIC_IS_DCE5(rdev)) |
1625 | !ASIC_IS_DCE5(rdev)) |
1649 | travis_quirk = true; |
1626 | travis_quirk = true; |
1650 | } |
1627 | } |
1651 | 1628 | ||
1652 | switch (mode) { |
1629 | switch (mode) { |
1653 | case DRM_MODE_DPMS_ON: |
1630 | case DRM_MODE_DPMS_ON: |
1654 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { |
1631 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { |
1655 | if (!connector) |
1632 | if (!connector) |
1656 | dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
1633 | dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
1657 | else |
1634 | else |
1658 | dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); |
1635 | dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); |
1659 | 1636 | ||
1660 | /* setup and enable the encoder */ |
1637 | /* setup and enable the encoder */ |
1661 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); |
1638 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); |
1662 | atombios_dig_encoder_setup(encoder, |
1639 | atombios_dig_encoder_setup(encoder, |
1663 | ATOM_ENCODER_CMD_SETUP_PANEL_MODE, |
1640 | ATOM_ENCODER_CMD_SETUP_PANEL_MODE, |
1664 | dig->panel_mode); |
1641 | dig->panel_mode); |
1665 | if (ext_encoder) { |
1642 | if (ext_encoder) { |
1666 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) |
1643 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) |
1667 | atombios_external_encoder_setup(encoder, ext_encoder, |
1644 | atombios_external_encoder_setup(encoder, ext_encoder, |
1668 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); |
1645 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); |
1669 | } |
1646 | } |
1670 | } else if (ASIC_IS_DCE4(rdev)) { |
1647 | } else if (ASIC_IS_DCE4(rdev)) { |
1671 | /* setup and enable the encoder */ |
1648 | /* setup and enable the encoder */ |
1672 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); |
1649 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); |
1673 | } else { |
1650 | } else { |
1674 | /* setup and enable the encoder and transmitter */ |
1651 | /* setup and enable the encoder and transmitter */ |
1675 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); |
1652 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); |
1676 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); |
1653 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); |
1677 | } |
1654 | } |
1678 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1655 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1679 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
1656 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
1680 | atombios_set_edp_panel_power(connector, |
1657 | atombios_set_edp_panel_power(connector, |
1681 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
1658 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
1682 | radeon_dig_connector->edp_on = true; |
1659 | radeon_dig_connector->edp_on = true; |
1683 | } |
1660 | } |
1684 | } |
1661 | } |
1685 | /* enable the transmitter */ |
1662 | /* enable the transmitter */ |
1686 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
1663 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
1687 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1664 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1688 | /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ |
1665 | /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ |
1689 | radeon_dp_link_train(encoder, connector); |
1666 | radeon_dp_link_train(encoder, connector); |
1690 | if (ASIC_IS_DCE4(rdev)) |
1667 | if (ASIC_IS_DCE4(rdev)) |
1691 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); |
1668 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); |
1692 | } |
1669 | } |
1693 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1670 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1694 | atombios_dig_transmitter_setup(encoder, |
1671 | atombios_dig_transmitter_setup(encoder, |
1695 | ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); |
1672 | ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); |
1696 | if (ext_encoder) |
1673 | if (ext_encoder) |
1697 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); |
1674 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); |
1698 | break; |
1675 | break; |
1699 | case DRM_MODE_DPMS_STANDBY: |
1676 | case DRM_MODE_DPMS_STANDBY: |
1700 | case DRM_MODE_DPMS_SUSPEND: |
1677 | case DRM_MODE_DPMS_SUSPEND: |
1701 | case DRM_MODE_DPMS_OFF: |
1678 | case DRM_MODE_DPMS_OFF: |
1702 | if (ASIC_IS_DCE4(rdev)) { |
1679 | if (ASIC_IS_DCE4(rdev)) { |
1703 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) |
1680 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) |
1704 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
1681 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
1705 | } |
1682 | } |
1706 | if (ext_encoder) |
1683 | if (ext_encoder) |
1707 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); |
1684 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); |
1708 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1685 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1709 | atombios_dig_transmitter_setup(encoder, |
1686 | atombios_dig_transmitter_setup(encoder, |
1710 | ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); |
1687 | ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); |
1711 | 1688 | ||
1712 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && |
1689 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && |
1713 | connector && !travis_quirk) |
1690 | connector && !travis_quirk) |
1714 | radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); |
1691 | radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); |
1715 | if (ASIC_IS_DCE4(rdev)) { |
1692 | if (ASIC_IS_DCE4(rdev)) { |
1716 | /* disable the transmitter */ |
1693 | /* disable the transmitter */ |
1717 | atombios_dig_transmitter_setup(encoder, |
1694 | atombios_dig_transmitter_setup(encoder, |
1718 | ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1695 | ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1719 | } else { |
1696 | } else { |
1720 | /* disable the encoder and transmitter */ |
1697 | /* disable the encoder and transmitter */ |
1721 | atombios_dig_transmitter_setup(encoder, |
1698 | atombios_dig_transmitter_setup(encoder, |
1722 | ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1699 | ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1723 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); |
1700 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); |
1724 | } |
1701 | } |
1725 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1702 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1726 | if (travis_quirk) |
1703 | if (travis_quirk) |
1727 | radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); |
1704 | radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); |
1728 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
1705 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
1729 | atombios_set_edp_panel_power(connector, |
1706 | atombios_set_edp_panel_power(connector, |
1730 | ATOM_TRANSMITTER_ACTION_POWER_OFF); |
1707 | ATOM_TRANSMITTER_ACTION_POWER_OFF); |
1731 | radeon_dig_connector->edp_on = false; |
1708 | radeon_dig_connector->edp_on = false; |
1732 | } |
1709 | } |
1733 | } |
1710 | } |
1734 | break; |
1711 | break; |
1735 | } |
1712 | } |
1736 | } |
1713 | } |
1737 | 1714 | ||
1738 | static void |
1715 | static void |
1739 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
1716 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
1740 | { |
1717 | { |
1741 | struct drm_device *dev = encoder->dev; |
1718 | struct drm_device *dev = encoder->dev; |
1742 | struct radeon_device *rdev = dev->dev_private; |
1719 | struct radeon_device *rdev = dev->dev_private; |
1743 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1720 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1744 | 1721 | ||
1745 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
1722 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
1746 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
1723 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
1747 | radeon_encoder->active_device); |
1724 | radeon_encoder->active_device); |
1748 | switch (radeon_encoder->encoder_id) { |
1725 | switch (radeon_encoder->encoder_id) { |
1749 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1726 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1750 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1727 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1751 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1728 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1752 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1729 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1753 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1730 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1754 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1731 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1755 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1732 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1756 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1733 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1757 | radeon_atom_encoder_dpms_avivo(encoder, mode); |
1734 | radeon_atom_encoder_dpms_avivo(encoder, mode); |
1758 | break; |
1735 | break; |
1759 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1736 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1760 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1737 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1761 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1738 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1762 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
1739 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
1763 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1740 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1764 | radeon_atom_encoder_dpms_dig(encoder, mode); |
1741 | radeon_atom_encoder_dpms_dig(encoder, mode); |
1765 | break; |
1742 | break; |
1766 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1743 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1767 | if (ASIC_IS_DCE5(rdev)) { |
1744 | if (ASIC_IS_DCE5(rdev)) { |
1768 | switch (mode) { |
1745 | switch (mode) { |
1769 | case DRM_MODE_DPMS_ON: |
1746 | case DRM_MODE_DPMS_ON: |
1770 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
1747 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
1771 | break; |
1748 | break; |
1772 | case DRM_MODE_DPMS_STANDBY: |
1749 | case DRM_MODE_DPMS_STANDBY: |
1773 | case DRM_MODE_DPMS_SUSPEND: |
1750 | case DRM_MODE_DPMS_SUSPEND: |
1774 | case DRM_MODE_DPMS_OFF: |
1751 | case DRM_MODE_DPMS_OFF: |
1775 | atombios_dvo_setup(encoder, ATOM_DISABLE); |
1752 | atombios_dvo_setup(encoder, ATOM_DISABLE); |
1776 | break; |
1753 | break; |
1777 | } |
1754 | } |
1778 | } else if (ASIC_IS_DCE3(rdev)) |
1755 | } else if (ASIC_IS_DCE3(rdev)) |
1779 | radeon_atom_encoder_dpms_dig(encoder, mode); |
1756 | radeon_atom_encoder_dpms_dig(encoder, mode); |
1780 | else |
1757 | else |
1781 | radeon_atom_encoder_dpms_avivo(encoder, mode); |
1758 | radeon_atom_encoder_dpms_avivo(encoder, mode); |
1782 | break; |
1759 | break; |
1783 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1760 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1784 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1761 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1785 | if (ASIC_IS_DCE5(rdev)) { |
1762 | if (ASIC_IS_DCE5(rdev)) { |
1786 | switch (mode) { |
1763 | switch (mode) { |
1787 | case DRM_MODE_DPMS_ON: |
1764 | case DRM_MODE_DPMS_ON: |
1788 | atombios_dac_setup(encoder, ATOM_ENABLE); |
1765 | atombios_dac_setup(encoder, ATOM_ENABLE); |
1789 | break; |
1766 | break; |
1790 | case DRM_MODE_DPMS_STANDBY: |
1767 | case DRM_MODE_DPMS_STANDBY: |
1791 | case DRM_MODE_DPMS_SUSPEND: |
1768 | case DRM_MODE_DPMS_SUSPEND: |
1792 | case DRM_MODE_DPMS_OFF: |
1769 | case DRM_MODE_DPMS_OFF: |
1793 | atombios_dac_setup(encoder, ATOM_DISABLE); |
1770 | atombios_dac_setup(encoder, ATOM_DISABLE); |
1794 | break; |
1771 | break; |
1795 | } |
1772 | } |
1796 | } else |
1773 | } else |
1797 | radeon_atom_encoder_dpms_avivo(encoder, mode); |
1774 | radeon_atom_encoder_dpms_avivo(encoder, mode); |
1798 | break; |
1775 | break; |
1799 | default: |
1776 | default: |
1800 | return; |
1777 | return; |
1801 | } |
1778 | } |
1802 | 1779 | ||
1803 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
1780 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
1804 | 1781 | ||
1805 | } |
1782 | } |
1806 | 1783 | ||
1807 | union crtc_source_param { |
1784 | union crtc_source_param { |
1808 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; |
1785 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; |
1809 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; |
1786 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; |
1810 | }; |
1787 | }; |
1811 | 1788 | ||
1812 | static void |
1789 | static void |
1813 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) |
1790 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) |
1814 | { |
1791 | { |
1815 | struct drm_device *dev = encoder->dev; |
1792 | struct drm_device *dev = encoder->dev; |
1816 | struct radeon_device *rdev = dev->dev_private; |
1793 | struct radeon_device *rdev = dev->dev_private; |
1817 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1794 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1818 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1795 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1819 | union crtc_source_param args; |
1796 | union crtc_source_param args; |
1820 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); |
1797 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); |
1821 | uint8_t frev, crev; |
1798 | uint8_t frev, crev; |
1822 | struct radeon_encoder_atom_dig *dig; |
1799 | struct radeon_encoder_atom_dig *dig; |
1823 | 1800 | ||
1824 | memset(&args, 0, sizeof(args)); |
1801 | memset(&args, 0, sizeof(args)); |
1825 | 1802 | ||
1826 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1803 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1827 | return; |
1804 | return; |
1828 | 1805 | ||
1829 | switch (frev) { |
1806 | switch (frev) { |
1830 | case 1: |
1807 | case 1: |
1831 | switch (crev) { |
1808 | switch (crev) { |
1832 | case 1: |
1809 | case 1: |
1833 | default: |
1810 | default: |
1834 | if (ASIC_IS_AVIVO(rdev)) |
1811 | if (ASIC_IS_AVIVO(rdev)) |
1835 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
1812 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
1836 | else { |
1813 | else { |
1837 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { |
1814 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { |
1838 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
1815 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
1839 | } else { |
1816 | } else { |
1840 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; |
1817 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; |
1841 | } |
1818 | } |
1842 | } |
1819 | } |
1843 | switch (radeon_encoder->encoder_id) { |
1820 | switch (radeon_encoder->encoder_id) { |
1844 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1821 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1845 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1822 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
1846 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; |
1823 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; |
1847 | break; |
1824 | break; |
1848 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1825 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1849 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1826 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
1850 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) |
1827 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) |
1851 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; |
1828 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; |
1852 | else |
1829 | else |
1853 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; |
1830 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; |
1854 | break; |
1831 | break; |
1855 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1832 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1856 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1833 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1857 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1834 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1858 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; |
1835 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; |
1859 | break; |
1836 | break; |
1860 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1837 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1861 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1838 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1862 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1839 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1863 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1840 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1864 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1841 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1865 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1842 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1866 | else |
1843 | else |
1867 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; |
1844 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; |
1868 | break; |
1845 | break; |
1869 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1846 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1870 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1847 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1871 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1848 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1872 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1849 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1873 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1850 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1874 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1851 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1875 | else |
1852 | else |
1876 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; |
1853 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; |
1877 | break; |
1854 | break; |
1878 | } |
1855 | } |
1879 | break; |
1856 | break; |
1880 | case 2: |
1857 | case 2: |
1881 | args.v2.ucCRTC = radeon_crtc->crtc_id; |
1858 | args.v2.ucCRTC = radeon_crtc->crtc_id; |
1882 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { |
1859 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { |
1883 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1860 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1884 | 1861 | ||
1885 | if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) |
1862 | if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) |
1886 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; |
1863 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; |
1887 | else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) |
1864 | else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) |
1888 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; |
1865 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; |
1889 | else |
1866 | else |
1890 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
1867 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
1891 | } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1868 | } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1892 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; |
1869 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; |
1893 | } else { |
1870 | } else { |
1894 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
1871 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
1895 | } |
1872 | } |
1896 | switch (radeon_encoder->encoder_id) { |
1873 | switch (radeon_encoder->encoder_id) { |
1897 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1874 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1898 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1875 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1899 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1876 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1900 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
1877 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
1901 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1878 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1902 | dig = radeon_encoder->enc_priv; |
1879 | dig = radeon_encoder->enc_priv; |
1903 | switch (dig->dig_encoder) { |
1880 | switch (dig->dig_encoder) { |
1904 | case 0: |
1881 | case 0: |
1905 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
1882 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
1906 | break; |
1883 | break; |
1907 | case 1: |
1884 | case 1: |
1908 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
1885 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
1909 | break; |
1886 | break; |
1910 | case 2: |
1887 | case 2: |
1911 | args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; |
1888 | args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; |
1912 | break; |
1889 | break; |
1913 | case 3: |
1890 | case 3: |
1914 | args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; |
1891 | args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; |
1915 | break; |
1892 | break; |
1916 | case 4: |
1893 | case 4: |
1917 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; |
1894 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; |
1918 | break; |
1895 | break; |
1919 | case 5: |
1896 | case 5: |
1920 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; |
1897 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; |
1921 | break; |
1898 | break; |
1922 | case 6: |
1899 | case 6: |
1923 | args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; |
1900 | args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; |
1924 | break; |
1901 | break; |
1925 | } |
1902 | } |
1926 | break; |
1903 | break; |
1927 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1904 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1928 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; |
1905 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; |
1929 | break; |
1906 | break; |
1930 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1907 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1931 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1908 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1932 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1909 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1933 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1910 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1934 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1911 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1935 | else |
1912 | else |
1936 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; |
1913 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; |
1937 | break; |
1914 | break; |
1938 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1915 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1939 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1916 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1940 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1917 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1941 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1918 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
1942 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1919 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1943 | else |
1920 | else |
1944 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; |
1921 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; |
1945 | break; |
1922 | break; |
1946 | } |
1923 | } |
1947 | break; |
1924 | break; |
1948 | } |
1925 | } |
1949 | break; |
1926 | break; |
1950 | default: |
1927 | default: |
1951 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1928 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
1952 | return; |
1929 | return; |
1953 | } |
1930 | } |
1954 | 1931 | ||
1955 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1932 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1956 | 1933 | ||
1957 | /* update scratch regs with new routing */ |
1934 | /* update scratch regs with new routing */ |
1958 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
1935 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
1959 | } |
1936 | } |
1960 | 1937 | ||
1961 | static void |
1938 | static void |
1962 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, |
1939 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, |
1963 | struct drm_display_mode *mode) |
1940 | struct drm_display_mode *mode) |
1964 | { |
1941 | { |
1965 | struct drm_device *dev = encoder->dev; |
1942 | struct drm_device *dev = encoder->dev; |
1966 | struct radeon_device *rdev = dev->dev_private; |
1943 | struct radeon_device *rdev = dev->dev_private; |
1967 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1944 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1968 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1945 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1969 | 1946 | ||
1970 | /* Funky macbooks */ |
1947 | /* Funky macbooks */ |
1971 | if ((dev->pdev->device == 0x71C5) && |
1948 | if ((dev->pdev->device == 0x71C5) && |
1972 | (dev->pdev->subsystem_vendor == 0x106b) && |
1949 | (dev->pdev->subsystem_vendor == 0x106b) && |
1973 | (dev->pdev->subsystem_device == 0x0080)) { |
1950 | (dev->pdev->subsystem_device == 0x0080)) { |
1974 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
1951 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
1975 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); |
1952 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); |
1976 | 1953 | ||
1977 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
1954 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
1978 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
1955 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
1979 | 1956 | ||
1980 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); |
1957 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); |
1981 | } |
1958 | } |
1982 | } |
1959 | } |
1983 | 1960 | ||
1984 | /* set scaler clears this on some chips */ |
1961 | /* set scaler clears this on some chips */ |
1985 | if (ASIC_IS_AVIVO(rdev) && |
1962 | if (ASIC_IS_AVIVO(rdev) && |
1986 | (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { |
1963 | (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { |
1987 | if (ASIC_IS_DCE8(rdev)) { |
1964 | if (ASIC_IS_DCE8(rdev)) { |
1988 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1965 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1989 | WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, |
1966 | WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, |
1990 | CIK_INTERLEAVE_EN); |
1967 | CIK_INTERLEAVE_EN); |
1991 | else |
1968 | else |
1992 | WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
1969 | WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
1993 | } else if (ASIC_IS_DCE4(rdev)) { |
1970 | } else if (ASIC_IS_DCE4(rdev)) { |
1994 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1971 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1995 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, |
1972 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, |
1996 | EVERGREEN_INTERLEAVE_EN); |
1973 | EVERGREEN_INTERLEAVE_EN); |
1997 | else |
1974 | else |
1998 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
1975 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
1999 | } else { |
1976 | } else { |
2000 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1977 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
2001 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
1978 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
2002 | AVIVO_D1MODE_INTERLEAVE_EN); |
1979 | AVIVO_D1MODE_INTERLEAVE_EN); |
2003 | else |
1980 | else |
2004 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
1981 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
2005 | } |
1982 | } |
2006 | } |
1983 | } |
2007 | } |
1984 | } |
2008 | 1985 | ||
2009 | static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) |
1986 | static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) |
2010 | { |
1987 | { |
2011 | struct drm_device *dev = encoder->dev; |
1988 | struct drm_device *dev = encoder->dev; |
2012 | struct radeon_device *rdev = dev->dev_private; |
1989 | struct radeon_device *rdev = dev->dev_private; |
2013 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
1990 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
2014 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1991 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2015 | struct drm_encoder *test_encoder; |
1992 | struct drm_encoder *test_encoder; |
2016 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
1993 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
2017 | uint32_t dig_enc_in_use = 0; |
1994 | uint32_t dig_enc_in_use = 0; |
2018 | 1995 | ||
2019 | if (ASIC_IS_DCE6(rdev)) { |
1996 | if (ASIC_IS_DCE6(rdev)) { |
2020 | /* DCE6 */ |
1997 | /* DCE6 */ |
2021 | switch (radeon_encoder->encoder_id) { |
1998 | switch (radeon_encoder->encoder_id) { |
2022 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1999 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2023 | if (dig->linkb) |
2000 | if (dig->linkb) |
2024 | return 1; |
2001 | return 1; |
2025 | else |
2002 | else |
2026 | return 0; |
2003 | return 0; |
2027 | break; |
2004 | break; |
2028 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2005 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2029 | if (dig->linkb) |
2006 | if (dig->linkb) |
2030 | return 3; |
2007 | return 3; |
2031 | else |
2008 | else |
2032 | return 2; |
2009 | return 2; |
2033 | break; |
2010 | break; |
2034 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2011 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2035 | if (dig->linkb) |
2012 | if (dig->linkb) |
2036 | return 5; |
2013 | return 5; |
2037 | else |
2014 | else |
2038 | return 4; |
2015 | return 4; |
2039 | break; |
2016 | break; |
2040 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
2017 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
2041 | return 6; |
2018 | return 6; |
2042 | break; |
2019 | break; |
2043 | } |
2020 | } |
2044 | } else if (ASIC_IS_DCE4(rdev)) { |
2021 | } else if (ASIC_IS_DCE4(rdev)) { |
2045 | /* DCE4/5 */ |
2022 | /* DCE4/5 */ |
2046 | if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { |
2023 | if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { |
2047 | /* ontario follows DCE4 */ |
2024 | /* ontario follows DCE4 */ |
2048 | if (rdev->family == CHIP_PALM) { |
2025 | if (rdev->family == CHIP_PALM) { |
2049 | if (dig->linkb) |
2026 | if (dig->linkb) |
2050 | return 1; |
2027 | return 1; |
2051 | else |
2028 | else |
2052 | return 0; |
2029 | return 0; |
2053 | } else |
2030 | } else |
2054 | /* llano follows DCE3.2 */ |
2031 | /* llano follows DCE3.2 */ |
2055 | return radeon_crtc->crtc_id; |
2032 | return radeon_crtc->crtc_id; |
2056 | } else { |
2033 | } else { |
2057 | switch (radeon_encoder->encoder_id) { |
2034 | switch (radeon_encoder->encoder_id) { |
2058 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2035 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2059 | if (dig->linkb) |
2036 | if (dig->linkb) |
2060 | return 1; |
2037 | return 1; |
2061 | else |
2038 | else |
2062 | return 0; |
2039 | return 0; |
2063 | break; |
2040 | break; |
2064 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2041 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2065 | if (dig->linkb) |
2042 | if (dig->linkb) |
2066 | return 3; |
2043 | return 3; |
2067 | else |
2044 | else |
2068 | return 2; |
2045 | return 2; |
2069 | break; |
2046 | break; |
2070 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2047 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2071 | if (dig->linkb) |
2048 | if (dig->linkb) |
2072 | return 5; |
2049 | return 5; |
2073 | else |
2050 | else |
2074 | return 4; |
2051 | return 4; |
2075 | break; |
2052 | break; |
2076 | } |
2053 | } |
2077 | } |
2054 | } |
2078 | } |
2055 | } |
2079 | 2056 | ||
2080 | /* on DCE32 and encoder can driver any block so just crtc id */ |
2057 | /* on DCE32 and encoder can driver any block so just crtc id */ |
2081 | if (ASIC_IS_DCE32(rdev)) { |
2058 | if (ASIC_IS_DCE32(rdev)) { |
2082 | return radeon_crtc->crtc_id; |
2059 | return radeon_crtc->crtc_id; |
2083 | } |
2060 | } |
2084 | 2061 | ||
2085 | /* on DCE3 - LVTMA can only be driven by DIGB */ |
2062 | /* on DCE3 - LVTMA can only be driven by DIGB */ |
2086 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
2063 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
2087 | struct radeon_encoder *radeon_test_encoder; |
2064 | struct radeon_encoder *radeon_test_encoder; |
2088 | 2065 | ||
2089 | if (encoder == test_encoder) |
2066 | if (encoder == test_encoder) |
2090 | continue; |
2067 | continue; |
2091 | 2068 | ||
2092 | if (!radeon_encoder_is_digital(test_encoder)) |
2069 | if (!radeon_encoder_is_digital(test_encoder)) |
2093 | continue; |
2070 | continue; |
2094 | 2071 | ||
2095 | radeon_test_encoder = to_radeon_encoder(test_encoder); |
2072 | radeon_test_encoder = to_radeon_encoder(test_encoder); |
2096 | dig = radeon_test_encoder->enc_priv; |
2073 | dig = radeon_test_encoder->enc_priv; |
2097 | 2074 | ||
2098 | if (dig->dig_encoder >= 0) |
2075 | if (dig->dig_encoder >= 0) |
2099 | dig_enc_in_use |= (1 << dig->dig_encoder); |
2076 | dig_enc_in_use |= (1 << dig->dig_encoder); |
2100 | } |
2077 | } |
2101 | 2078 | ||
2102 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { |
2079 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { |
2103 | if (dig_enc_in_use & 0x2) |
2080 | if (dig_enc_in_use & 0x2) |
2104 | DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); |
2081 | DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); |
2105 | return 1; |
2082 | return 1; |
2106 | } |
2083 | } |
2107 | if (!(dig_enc_in_use & 1)) |
2084 | if (!(dig_enc_in_use & 1)) |
2108 | return 0; |
2085 | return 0; |
2109 | return 1; |
2086 | return 1; |
2110 | } |
2087 | } |
2111 | 2088 | ||
2112 | /* This only needs to be called once at startup */ |
2089 | /* This only needs to be called once at startup */ |
2113 | void |
2090 | void |
2114 | radeon_atom_encoder_init(struct radeon_device *rdev) |
2091 | radeon_atom_encoder_init(struct radeon_device *rdev) |
2115 | { |
2092 | { |
2116 | struct drm_device *dev = rdev->ddev; |
2093 | struct drm_device *dev = rdev->ddev; |
2117 | struct drm_encoder *encoder; |
2094 | struct drm_encoder *encoder; |
2118 | 2095 | ||
2119 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
2096 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
2120 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2097 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2121 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
2098 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
2122 | 2099 | ||
2123 | switch (radeon_encoder->encoder_id) { |
2100 | switch (radeon_encoder->encoder_id) { |
2124 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2101 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2125 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2102 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2126 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2103 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2127 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
2104 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
2128 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2105 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2129 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); |
2106 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); |
2130 | break; |
2107 | break; |
2131 | default: |
2108 | default: |
2132 | break; |
2109 | break; |
2133 | } |
2110 | } |
2134 | 2111 | ||
2135 | if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) |
2112 | if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) |
2136 | atombios_external_encoder_setup(encoder, ext_encoder, |
2113 | atombios_external_encoder_setup(encoder, ext_encoder, |
2137 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); |
2114 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); |
2138 | } |
2115 | } |
2139 | } |
2116 | } |
2140 | 2117 | ||
2141 | static void |
2118 | static void |
2142 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, |
2119 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, |
2143 | struct drm_display_mode *mode, |
2120 | struct drm_display_mode *mode, |
2144 | struct drm_display_mode *adjusted_mode) |
2121 | struct drm_display_mode *adjusted_mode) |
2145 | { |
2122 | { |
2146 | struct drm_device *dev = encoder->dev; |
2123 | struct drm_device *dev = encoder->dev; |
2147 | struct radeon_device *rdev = dev->dev_private; |
2124 | struct radeon_device *rdev = dev->dev_private; |
2148 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2125 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2149 | 2126 | ||
2150 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
2127 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
2151 | 2128 | ||
2152 | /* need to call this here rather than in prepare() since we need some crtc info */ |
2129 | /* need to call this here rather than in prepare() since we need some crtc info */ |
2153 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
2130 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
2154 | 2131 | ||
2155 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { |
2132 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { |
2156 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
2133 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
2157 | atombios_yuv_setup(encoder, true); |
2134 | atombios_yuv_setup(encoder, true); |
2158 | else |
2135 | else |
2159 | atombios_yuv_setup(encoder, false); |
2136 | atombios_yuv_setup(encoder, false); |
2160 | } |
2137 | } |
2161 | 2138 | ||
2162 | switch (radeon_encoder->encoder_id) { |
2139 | switch (radeon_encoder->encoder_id) { |
2163 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
2140 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
2164 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
2141 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
2165 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
2142 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
2166 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
2143 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
2167 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
2144 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
2168 | break; |
2145 | break; |
2169 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2146 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2170 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2147 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2171 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2148 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2172 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
2149 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
2173 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2150 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2174 | /* handled in dpms */ |
2151 | /* handled in dpms */ |
2175 | break; |
2152 | break; |
2176 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2153 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2177 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
2154 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
2178 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
2155 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
2179 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
2156 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
2180 | break; |
2157 | break; |
2181 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
2158 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
2182 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
2159 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
2183 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
2160 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
2184 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
2161 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
2185 | atombios_dac_setup(encoder, ATOM_ENABLE); |
2162 | atombios_dac_setup(encoder, ATOM_ENABLE); |
2186 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { |
2163 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { |
2187 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
2164 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
2188 | atombios_tv_setup(encoder, ATOM_ENABLE); |
2165 | atombios_tv_setup(encoder, ATOM_ENABLE); |
2189 | else |
2166 | else |
2190 | atombios_tv_setup(encoder, ATOM_DISABLE); |
2167 | atombios_tv_setup(encoder, ATOM_DISABLE); |
2191 | } |
2168 | } |
2192 | break; |
2169 | break; |
2193 | } |
2170 | } |
2194 | 2171 | ||
2195 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
2172 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
2196 | 2173 | ||
2197 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
2174 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
2198 | if (rdev->asic->display.hdmi_enable) |
2175 | if (rdev->asic->display.hdmi_enable) |
2199 | radeon_hdmi_enable(rdev, encoder, true); |
2176 | radeon_hdmi_enable(rdev, encoder, true); |
2200 | if (rdev->asic->display.hdmi_setmode) |
2177 | if (rdev->asic->display.hdmi_setmode) |
2201 | radeon_hdmi_setmode(rdev, encoder, adjusted_mode); |
2178 | radeon_hdmi_setmode(rdev, encoder, adjusted_mode); |
2202 | } |
2179 | } |
2203 | } |
2180 | } |
2204 | 2181 | ||
2205 | static bool |
2182 | static bool |
2206 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
2183 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
2207 | { |
2184 | { |
2208 | struct drm_device *dev = encoder->dev; |
2185 | struct drm_device *dev = encoder->dev; |
2209 | struct radeon_device *rdev = dev->dev_private; |
2186 | struct radeon_device *rdev = dev->dev_private; |
2210 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2187 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2211 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
2188 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
2212 | 2189 | ||
2213 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | |
2190 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | |
2214 | ATOM_DEVICE_CV_SUPPORT | |
2191 | ATOM_DEVICE_CV_SUPPORT | |
2215 | ATOM_DEVICE_CRT_SUPPORT)) { |
2192 | ATOM_DEVICE_CRT_SUPPORT)) { |
2216 | DAC_LOAD_DETECTION_PS_ALLOCATION args; |
2193 | DAC_LOAD_DETECTION_PS_ALLOCATION args; |
2217 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); |
2194 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); |
2218 | uint8_t frev, crev; |
2195 | uint8_t frev, crev; |
2219 | 2196 | ||
2220 | memset(&args, 0, sizeof(args)); |
2197 | memset(&args, 0, sizeof(args)); |
2221 | 2198 | ||
2222 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
2199 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
2223 | return false; |
2200 | return false; |
2224 | 2201 | ||
2225 | args.sDacload.ucMisc = 0; |
2202 | args.sDacload.ucMisc = 0; |
2226 | 2203 | ||
2227 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || |
2204 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || |
2228 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) |
2205 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) |
2229 | args.sDacload.ucDacType = ATOM_DAC_A; |
2206 | args.sDacload.ucDacType = ATOM_DAC_A; |
2230 | else |
2207 | else |
2231 | args.sDacload.ucDacType = ATOM_DAC_B; |
2208 | args.sDacload.ucDacType = ATOM_DAC_B; |
2232 | 2209 | ||
2233 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
2210 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
2234 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
2211 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
2235 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
2212 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
2236 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
2213 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
2237 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
2214 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
2238 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
2215 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
2239 | if (crev >= 3) |
2216 | if (crev >= 3) |
2240 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
2217 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
2241 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
2218 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
2242 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
2219 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
2243 | if (crev >= 3) |
2220 | if (crev >= 3) |
2244 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
2221 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
2245 | } |
2222 | } |
2246 | 2223 | ||
2247 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
2224 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
2248 | 2225 | ||
2249 | return true; |
2226 | return true; |
2250 | } else |
2227 | } else |
2251 | return false; |
2228 | return false; |
2252 | } |
2229 | } |
2253 | 2230 | ||
2254 | static enum drm_connector_status |
2231 | static enum drm_connector_status |
2255 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
2232 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
2256 | { |
2233 | { |
2257 | struct drm_device *dev = encoder->dev; |
2234 | struct drm_device *dev = encoder->dev; |
2258 | struct radeon_device *rdev = dev->dev_private; |
2235 | struct radeon_device *rdev = dev->dev_private; |
2259 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2236 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2260 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
2237 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
2261 | uint32_t bios_0_scratch; |
2238 | uint32_t bios_0_scratch; |
2262 | 2239 | ||
2263 | if (!atombios_dac_load_detect(encoder, connector)) { |
2240 | if (!atombios_dac_load_detect(encoder, connector)) { |
2264 | DRM_DEBUG_KMS("detect returned false \n"); |
2241 | DRM_DEBUG_KMS("detect returned false \n"); |
2265 | return connector_status_unknown; |
2242 | return connector_status_unknown; |
2266 | } |
2243 | } |
2267 | 2244 | ||
2268 | if (rdev->family >= CHIP_R600) |
2245 | if (rdev->family >= CHIP_R600) |
2269 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
2246 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
2270 | else |
2247 | else |
2271 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
2248 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
2272 | 2249 | ||
2273 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
2250 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
2274 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
2251 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
2275 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
2252 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
2276 | return connector_status_connected; |
2253 | return connector_status_connected; |
2277 | } |
2254 | } |
2278 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
2255 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
2279 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
2256 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
2280 | return connector_status_connected; |
2257 | return connector_status_connected; |
2281 | } |
2258 | } |
2282 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
2259 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
2283 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
2260 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
2284 | return connector_status_connected; |
2261 | return connector_status_connected; |
2285 | } |
2262 | } |
2286 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
2263 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
2287 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
2264 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
2288 | return connector_status_connected; /* CTV */ |
2265 | return connector_status_connected; /* CTV */ |
2289 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
2266 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
2290 | return connector_status_connected; /* STV */ |
2267 | return connector_status_connected; /* STV */ |
2291 | } |
2268 | } |
2292 | return connector_status_disconnected; |
2269 | return connector_status_disconnected; |
2293 | } |
2270 | } |
2294 | 2271 | ||
2295 | static enum drm_connector_status |
2272 | static enum drm_connector_status |
2296 | radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
2273 | radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
2297 | { |
2274 | { |
2298 | struct drm_device *dev = encoder->dev; |
2275 | struct drm_device *dev = encoder->dev; |
2299 | struct radeon_device *rdev = dev->dev_private; |
2276 | struct radeon_device *rdev = dev->dev_private; |
2300 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2277 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2301 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
2278 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
2302 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
2279 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
2303 | u32 bios_0_scratch; |
2280 | u32 bios_0_scratch; |
2304 | 2281 | ||
2305 | if (!ASIC_IS_DCE4(rdev)) |
2282 | if (!ASIC_IS_DCE4(rdev)) |
2306 | return connector_status_unknown; |
2283 | return connector_status_unknown; |
2307 | 2284 | ||
2308 | if (!ext_encoder) |
2285 | if (!ext_encoder) |
2309 | return connector_status_unknown; |
2286 | return connector_status_unknown; |
2310 | 2287 | ||
2311 | if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) |
2288 | if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) |
2312 | return connector_status_unknown; |
2289 | return connector_status_unknown; |
2313 | 2290 | ||
2314 | /* load detect on the dp bridge */ |
2291 | /* load detect on the dp bridge */ |
2315 | atombios_external_encoder_setup(encoder, ext_encoder, |
2292 | atombios_external_encoder_setup(encoder, ext_encoder, |
2316 | EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); |
2293 | EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); |
2317 | 2294 | ||
2318 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
2295 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
2319 | 2296 | ||
2320 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
2297 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
2321 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
2298 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
2322 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
2299 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
2323 | return connector_status_connected; |
2300 | return connector_status_connected; |
2324 | } |
2301 | } |
2325 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
2302 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
2326 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
2303 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
2327 | return connector_status_connected; |
2304 | return connector_status_connected; |
2328 | } |
2305 | } |
2329 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
2306 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
2330 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
2307 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
2331 | return connector_status_connected; |
2308 | return connector_status_connected; |
2332 | } |
2309 | } |
2333 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
2310 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
2334 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
2311 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
2335 | return connector_status_connected; /* CTV */ |
2312 | return connector_status_connected; /* CTV */ |
2336 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
2313 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
2337 | return connector_status_connected; /* STV */ |
2314 | return connector_status_connected; /* STV */ |
2338 | } |
2315 | } |
2339 | return connector_status_disconnected; |
2316 | return connector_status_disconnected; |
2340 | } |
2317 | } |
2341 | 2318 | ||
2342 | void |
2319 | void |
2343 | radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) |
2320 | radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) |
2344 | { |
2321 | { |
2345 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
2322 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
2346 | 2323 | ||
2347 | if (ext_encoder) |
2324 | if (ext_encoder) |
2348 | /* ddc_setup on the dp bridge */ |
2325 | /* ddc_setup on the dp bridge */ |
2349 | atombios_external_encoder_setup(encoder, ext_encoder, |
2326 | atombios_external_encoder_setup(encoder, ext_encoder, |
2350 | EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); |
2327 | EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); |
2351 | 2328 | ||
2352 | } |
2329 | } |
2353 | 2330 | ||
2354 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
2331 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
2355 | { |
2332 | { |
2356 | struct radeon_device *rdev = encoder->dev->dev_private; |
2333 | struct radeon_device *rdev = encoder->dev->dev_private; |
2357 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2334 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2358 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
2335 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
2359 | 2336 | ||
2360 | if ((radeon_encoder->active_device & |
2337 | if ((radeon_encoder->active_device & |
2361 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || |
2338 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || |
2362 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != |
2339 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != |
2363 | ENCODER_OBJECT_ID_NONE)) { |
2340 | ENCODER_OBJECT_ID_NONE)) { |
2364 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
2341 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
2365 | if (dig) { |
2342 | if (dig) { |
2366 | dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); |
2343 | dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); |
2367 | if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { |
2344 | if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { |
2368 | if (rdev->family >= CHIP_R600) |
2345 | if (rdev->family >= CHIP_R600) |
2369 | dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; |
2346 | dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; |
2370 | else |
2347 | else |
2371 | /* RS600/690/740 have only 1 afmt block */ |
2348 | /* RS600/690/740 have only 1 afmt block */ |
2372 | dig->afmt = rdev->mode_info.afmt[0]; |
2349 | dig->afmt = rdev->mode_info.afmt[0]; |
2373 | } |
2350 | } |
2374 | } |
2351 | } |
2375 | } |
2352 | } |
2376 | 2353 | ||
2377 | radeon_atom_output_lock(encoder, true); |
2354 | radeon_atom_output_lock(encoder, true); |
2378 | 2355 | ||
2379 | if (connector) { |
2356 | if (connector) { |
2380 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
2357 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
2381 | 2358 | ||
2382 | /* select the clock/data port if it uses a router */ |
2359 | /* select the clock/data port if it uses a router */ |
2383 | if (radeon_connector->router.cd_valid) |
2360 | if (radeon_connector->router.cd_valid) |
2384 | radeon_router_select_cd_port(radeon_connector); |
2361 | radeon_router_select_cd_port(radeon_connector); |
2385 | 2362 | ||
2386 | /* turn eDP panel on for mode set */ |
2363 | /* turn eDP panel on for mode set */ |
2387 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
2364 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
2388 | atombios_set_edp_panel_power(connector, |
2365 | atombios_set_edp_panel_power(connector, |
2389 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
2366 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
2390 | } |
2367 | } |
2391 | 2368 | ||
2392 | /* this is needed for the pll/ss setup to work correctly in some cases */ |
2369 | /* this is needed for the pll/ss setup to work correctly in some cases */ |
2393 | atombios_set_encoder_crtc_source(encoder); |
2370 | atombios_set_encoder_crtc_source(encoder); |
2394 | /* set up the FMT blocks */ |
2371 | /* set up the FMT blocks */ |
2395 | if (ASIC_IS_DCE8(rdev)) |
2372 | if (ASIC_IS_DCE8(rdev)) |
2396 | dce8_program_fmt(encoder); |
2373 | dce8_program_fmt(encoder); |
2397 | else if (ASIC_IS_DCE4(rdev)) |
2374 | else if (ASIC_IS_DCE4(rdev)) |
2398 | dce4_program_fmt(encoder); |
2375 | dce4_program_fmt(encoder); |
2399 | else if (ASIC_IS_DCE3(rdev)) |
2376 | else if (ASIC_IS_DCE3(rdev)) |
2400 | dce3_program_fmt(encoder); |
2377 | dce3_program_fmt(encoder); |
2401 | else if (ASIC_IS_AVIVO(rdev)) |
2378 | else if (ASIC_IS_AVIVO(rdev)) |
2402 | avivo_program_fmt(encoder); |
2379 | avivo_program_fmt(encoder); |
2403 | } |
2380 | } |
2404 | 2381 | ||
2405 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
2382 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
2406 | { |
2383 | { |
2407 | /* need to call this here as we need the crtc set up */ |
2384 | /* need to call this here as we need the crtc set up */ |
2408 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
2385 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
2409 | radeon_atom_output_lock(encoder, false); |
2386 | radeon_atom_output_lock(encoder, false); |
2410 | } |
2387 | } |
2411 | 2388 | ||
2412 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
2389 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
2413 | { |
2390 | { |
2414 | struct drm_device *dev = encoder->dev; |
2391 | struct drm_device *dev = encoder->dev; |
2415 | struct radeon_device *rdev = dev->dev_private; |
2392 | struct radeon_device *rdev = dev->dev_private; |
2416 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2393 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2417 | struct radeon_encoder_atom_dig *dig; |
2394 | struct radeon_encoder_atom_dig *dig; |
2418 | 2395 | ||
2419 | /* check for pre-DCE3 cards with shared encoders; |
2396 | /* check for pre-DCE3 cards with shared encoders; |
2420 | * can't really use the links individually, so don't disable |
2397 | * can't really use the links individually, so don't disable |
2421 | * the encoder if it's in use by another connector |
2398 | * the encoder if it's in use by another connector |
2422 | */ |
2399 | */ |
2423 | if (!ASIC_IS_DCE3(rdev)) { |
2400 | if (!ASIC_IS_DCE3(rdev)) { |
2424 | struct drm_encoder *other_encoder; |
2401 | struct drm_encoder *other_encoder; |
2425 | struct radeon_encoder *other_radeon_encoder; |
2402 | struct radeon_encoder *other_radeon_encoder; |
2426 | 2403 | ||
2427 | list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { |
2404 | list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { |
2428 | other_radeon_encoder = to_radeon_encoder(other_encoder); |
2405 | other_radeon_encoder = to_radeon_encoder(other_encoder); |
2429 | if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && |
2406 | if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && |
2430 | drm_helper_encoder_in_use(other_encoder)) |
2407 | drm_helper_encoder_in_use(other_encoder)) |
2431 | goto disable_done; |
2408 | goto disable_done; |
2432 | } |
2409 | } |
2433 | } |
2410 | } |
2434 | 2411 | ||
2435 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
2412 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
2436 | 2413 | ||
2437 | switch (radeon_encoder->encoder_id) { |
2414 | switch (radeon_encoder->encoder_id) { |
2438 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
2415 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
2439 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
2416 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
2440 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
2417 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
2441 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
2418 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
2442 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); |
2419 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); |
2443 | break; |
2420 | break; |
2444 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2421 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2445 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2422 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2446 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2423 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2447 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
2424 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
2448 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2425 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2449 | /* handled in dpms */ |
2426 | /* handled in dpms */ |
2450 | break; |
2427 | break; |
2451 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2428 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2452 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
2429 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
2453 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
2430 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
2454 | atombios_dvo_setup(encoder, ATOM_DISABLE); |
2431 | atombios_dvo_setup(encoder, ATOM_DISABLE); |
2455 | break; |
2432 | break; |
2456 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
2433 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
2457 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
2434 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
2458 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
2435 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
2459 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
2436 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
2460 | atombios_dac_setup(encoder, ATOM_DISABLE); |
2437 | atombios_dac_setup(encoder, ATOM_DISABLE); |
2461 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
2438 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
2462 | atombios_tv_setup(encoder, ATOM_DISABLE); |
2439 | atombios_tv_setup(encoder, ATOM_DISABLE); |
2463 | break; |
2440 | break; |
2464 | } |
2441 | } |
2465 | 2442 | ||
2466 | disable_done: |
2443 | disable_done: |
2467 | if (radeon_encoder_is_digital(encoder)) { |
2444 | if (radeon_encoder_is_digital(encoder)) { |
2468 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
2445 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
2469 | if (rdev->asic->display.hdmi_enable) |
2446 | if (rdev->asic->display.hdmi_enable) |
2470 | radeon_hdmi_enable(rdev, encoder, false); |
2447 | radeon_hdmi_enable(rdev, encoder, false); |
2471 | } |
2448 | } |
2472 | dig = radeon_encoder->enc_priv; |
2449 | dig = radeon_encoder->enc_priv; |
2473 | dig->dig_encoder = -1; |
2450 | dig->dig_encoder = -1; |
2474 | } |
2451 | } |
2475 | radeon_encoder->active_device = 0; |
2452 | radeon_encoder->active_device = 0; |
2476 | } |
2453 | } |
2477 | 2454 | ||
2478 | /* these are handled by the primary encoders */ |
2455 | /* these are handled by the primary encoders */ |
2479 | static void radeon_atom_ext_prepare(struct drm_encoder *encoder) |
2456 | static void radeon_atom_ext_prepare(struct drm_encoder *encoder) |
2480 | { |
2457 | { |
2481 | 2458 | ||
2482 | } |
2459 | } |
2483 | 2460 | ||
2484 | static void radeon_atom_ext_commit(struct drm_encoder *encoder) |
2461 | static void radeon_atom_ext_commit(struct drm_encoder *encoder) |
2485 | { |
2462 | { |
2486 | 2463 | ||
2487 | } |
2464 | } |
2488 | 2465 | ||
2489 | static void |
2466 | static void |
2490 | radeon_atom_ext_mode_set(struct drm_encoder *encoder, |
2467 | radeon_atom_ext_mode_set(struct drm_encoder *encoder, |
2491 | struct drm_display_mode *mode, |
2468 | struct drm_display_mode *mode, |
2492 | struct drm_display_mode *adjusted_mode) |
2469 | struct drm_display_mode *adjusted_mode) |
2493 | { |
2470 | { |
2494 | 2471 | ||
2495 | } |
2472 | } |
2496 | 2473 | ||
2497 | static void radeon_atom_ext_disable(struct drm_encoder *encoder) |
2474 | static void radeon_atom_ext_disable(struct drm_encoder *encoder) |
2498 | { |
2475 | { |
2499 | 2476 | ||
2500 | } |
2477 | } |
2501 | 2478 | ||
2502 | static void |
2479 | static void |
2503 | radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) |
2480 | radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) |
2504 | { |
2481 | { |
2505 | 2482 | ||
2506 | } |
2483 | } |
2507 | 2484 | ||
2508 | static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, |
2485 | static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, |
2509 | const struct drm_display_mode *mode, |
2486 | const struct drm_display_mode *mode, |
2510 | struct drm_display_mode *adjusted_mode) |
2487 | struct drm_display_mode *adjusted_mode) |
2511 | { |
2488 | { |
2512 | return true; |
2489 | return true; |
2513 | } |
2490 | } |
2514 | 2491 | ||
2515 | static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { |
2492 | static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { |
2516 | .dpms = radeon_atom_ext_dpms, |
2493 | .dpms = radeon_atom_ext_dpms, |
2517 | .mode_fixup = radeon_atom_ext_mode_fixup, |
2494 | .mode_fixup = radeon_atom_ext_mode_fixup, |
2518 | .prepare = radeon_atom_ext_prepare, |
2495 | .prepare = radeon_atom_ext_prepare, |
2519 | .mode_set = radeon_atom_ext_mode_set, |
2496 | .mode_set = radeon_atom_ext_mode_set, |
2520 | .commit = radeon_atom_ext_commit, |
2497 | .commit = radeon_atom_ext_commit, |
2521 | .disable = radeon_atom_ext_disable, |
2498 | .disable = radeon_atom_ext_disable, |
2522 | /* no detect for TMDS/LVDS yet */ |
2499 | /* no detect for TMDS/LVDS yet */ |
2523 | }; |
2500 | }; |
2524 | 2501 | ||
2525 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
2502 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
2526 | .dpms = radeon_atom_encoder_dpms, |
2503 | .dpms = radeon_atom_encoder_dpms, |
2527 | .mode_fixup = radeon_atom_mode_fixup, |
2504 | .mode_fixup = radeon_atom_mode_fixup, |
2528 | .prepare = radeon_atom_encoder_prepare, |
2505 | .prepare = radeon_atom_encoder_prepare, |
2529 | .mode_set = radeon_atom_encoder_mode_set, |
2506 | .mode_set = radeon_atom_encoder_mode_set, |
2530 | .commit = radeon_atom_encoder_commit, |
2507 | .commit = radeon_atom_encoder_commit, |
2531 | .disable = radeon_atom_encoder_disable, |
2508 | .disable = radeon_atom_encoder_disable, |
2532 | .detect = radeon_atom_dig_detect, |
2509 | .detect = radeon_atom_dig_detect, |
2533 | }; |
2510 | }; |
2534 | 2511 | ||
2535 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { |
2512 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { |
2536 | .dpms = radeon_atom_encoder_dpms, |
2513 | .dpms = radeon_atom_encoder_dpms, |
2537 | .mode_fixup = radeon_atom_mode_fixup, |
2514 | .mode_fixup = radeon_atom_mode_fixup, |
2538 | .prepare = radeon_atom_encoder_prepare, |
2515 | .prepare = radeon_atom_encoder_prepare, |
2539 | .mode_set = radeon_atom_encoder_mode_set, |
2516 | .mode_set = radeon_atom_encoder_mode_set, |
2540 | .commit = radeon_atom_encoder_commit, |
2517 | .commit = radeon_atom_encoder_commit, |
2541 | .detect = radeon_atom_dac_detect, |
2518 | .detect = radeon_atom_dac_detect, |
2542 | }; |
2519 | }; |
2543 | 2520 | ||
2544 | void radeon_enc_destroy(struct drm_encoder *encoder) |
2521 | void radeon_enc_destroy(struct drm_encoder *encoder) |
2545 | { |
2522 | { |
2546 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2523 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2547 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
2524 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
2548 | radeon_atom_backlight_exit(radeon_encoder); |
2525 | radeon_atom_backlight_exit(radeon_encoder); |
2549 | kfree(radeon_encoder->enc_priv); |
2526 | kfree(radeon_encoder->enc_priv); |
2550 | drm_encoder_cleanup(encoder); |
2527 | drm_encoder_cleanup(encoder); |
2551 | kfree(radeon_encoder); |
2528 | kfree(radeon_encoder); |
2552 | } |
2529 | } |
2553 | 2530 | ||
2554 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { |
2531 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { |
2555 | .destroy = radeon_enc_destroy, |
2532 | .destroy = radeon_enc_destroy, |
2556 | }; |
2533 | }; |
2557 | 2534 | ||
2558 | static struct radeon_encoder_atom_dac * |
2535 | static struct radeon_encoder_atom_dac * |
2559 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) |
2536 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) |
2560 | { |
2537 | { |
2561 | struct drm_device *dev = radeon_encoder->base.dev; |
2538 | struct drm_device *dev = radeon_encoder->base.dev; |
2562 | struct radeon_device *rdev = dev->dev_private; |
2539 | struct radeon_device *rdev = dev->dev_private; |
2563 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
2540 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
2564 | 2541 | ||
2565 | if (!dac) |
2542 | if (!dac) |
2566 | return NULL; |
2543 | return NULL; |
2567 | 2544 | ||
2568 | dac->tv_std = radeon_atombios_get_tv_info(rdev); |
2545 | dac->tv_std = radeon_atombios_get_tv_info(rdev); |
2569 | return dac; |
2546 | return dac; |
2570 | } |
2547 | } |
2571 | 2548 | ||
2572 | static struct radeon_encoder_atom_dig * |
2549 | static struct radeon_encoder_atom_dig * |
2573 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
2550 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
2574 | { |
2551 | { |
2575 | int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
2552 | int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
2576 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
2553 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
2577 | 2554 | ||
2578 | if (!dig) |
2555 | if (!dig) |
2579 | return NULL; |
2556 | return NULL; |
2580 | 2557 | ||
2581 | /* coherent mode by default */ |
2558 | /* coherent mode by default */ |
2582 | dig->coherent_mode = true; |
2559 | dig->coherent_mode = true; |
2583 | dig->dig_encoder = -1; |
2560 | dig->dig_encoder = -1; |
2584 | 2561 | ||
2585 | if (encoder_enum == 2) |
2562 | if (encoder_enum == 2) |
2586 | dig->linkb = true; |
2563 | dig->linkb = true; |
2587 | else |
2564 | else |
2588 | dig->linkb = false; |
2565 | dig->linkb = false; |
2589 | 2566 | ||
2590 | return dig; |
2567 | return dig; |
2591 | } |
2568 | } |
2592 | 2569 | ||
2593 | void |
2570 | void |
2594 | radeon_add_atom_encoder(struct drm_device *dev, |
2571 | radeon_add_atom_encoder(struct drm_device *dev, |
2595 | uint32_t encoder_enum, |
2572 | uint32_t encoder_enum, |
2596 | uint32_t supported_device, |
2573 | uint32_t supported_device, |
2597 | u16 caps) |
2574 | u16 caps) |
2598 | { |
2575 | { |
2599 | struct radeon_device *rdev = dev->dev_private; |
2576 | struct radeon_device *rdev = dev->dev_private; |
2600 | struct drm_encoder *encoder; |
2577 | struct drm_encoder *encoder; |
2601 | struct radeon_encoder *radeon_encoder; |
2578 | struct radeon_encoder *radeon_encoder; |
2602 | 2579 | ||
2603 | /* see if we already added it */ |
2580 | /* see if we already added it */ |
2604 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
2581 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
2605 | radeon_encoder = to_radeon_encoder(encoder); |
2582 | radeon_encoder = to_radeon_encoder(encoder); |
2606 | if (radeon_encoder->encoder_enum == encoder_enum) { |
2583 | if (radeon_encoder->encoder_enum == encoder_enum) { |
2607 | radeon_encoder->devices |= supported_device; |
2584 | radeon_encoder->devices |= supported_device; |
2608 | return; |
2585 | return; |
2609 | } |
2586 | } |
2610 | 2587 | ||
2611 | } |
2588 | } |
2612 | 2589 | ||
2613 | /* add a new one */ |
2590 | /* add a new one */ |
2614 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
2591 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
2615 | if (!radeon_encoder) |
2592 | if (!radeon_encoder) |
2616 | return; |
2593 | return; |
2617 | 2594 | ||
2618 | encoder = &radeon_encoder->base; |
2595 | encoder = &radeon_encoder->base; |
2619 | switch (rdev->num_crtc) { |
2596 | switch (rdev->num_crtc) { |
2620 | case 1: |
2597 | case 1: |
2621 | encoder->possible_crtcs = 0x1; |
2598 | encoder->possible_crtcs = 0x1; |
2622 | break; |
2599 | break; |
2623 | case 2: |
2600 | case 2: |
2624 | default: |
2601 | default: |
2625 | encoder->possible_crtcs = 0x3; |
2602 | encoder->possible_crtcs = 0x3; |
2626 | break; |
2603 | break; |
2627 | case 4: |
2604 | case 4: |
2628 | encoder->possible_crtcs = 0xf; |
2605 | encoder->possible_crtcs = 0xf; |
2629 | break; |
2606 | break; |
2630 | case 6: |
2607 | case 6: |
2631 | encoder->possible_crtcs = 0x3f; |
2608 | encoder->possible_crtcs = 0x3f; |
2632 | break; |
2609 | break; |
2633 | } |
2610 | } |
2634 | 2611 | ||
2635 | radeon_encoder->enc_priv = NULL; |
2612 | radeon_encoder->enc_priv = NULL; |
2636 | 2613 | ||
2637 | radeon_encoder->encoder_enum = encoder_enum; |
2614 | radeon_encoder->encoder_enum = encoder_enum; |
2638 | radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
2615 | radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
2639 | radeon_encoder->devices = supported_device; |
2616 | radeon_encoder->devices = supported_device; |
2640 | radeon_encoder->rmx_type = RMX_OFF; |
2617 | radeon_encoder->rmx_type = RMX_OFF; |
2641 | radeon_encoder->underscan_type = UNDERSCAN_OFF; |
2618 | radeon_encoder->underscan_type = UNDERSCAN_OFF; |
2642 | radeon_encoder->is_ext_encoder = false; |
2619 | radeon_encoder->is_ext_encoder = false; |
2643 | radeon_encoder->caps = caps; |
2620 | radeon_encoder->caps = caps; |
2644 | 2621 | ||
2645 | switch (radeon_encoder->encoder_id) { |
2622 | switch (radeon_encoder->encoder_id) { |
2646 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
2623 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
2647 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
2624 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
2648 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
2625 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
2649 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
2626 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
2650 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2627 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2651 | radeon_encoder->rmx_type = RMX_FULL; |
2628 | radeon_encoder->rmx_type = RMX_FULL; |
2652 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2629 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2653 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2630 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2654 | } else { |
2631 | } else { |
2655 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2632 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2656 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2633 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2657 | } |
2634 | } |
2658 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
2635 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
2659 | break; |
2636 | break; |
2660 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
2637 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
2661 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
2638 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
2662 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
2639 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
2663 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
2640 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
2664 | break; |
2641 | break; |
2665 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
2642 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
2666 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
2643 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
2667 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
2644 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
2668 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
2645 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
2669 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
2646 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
2670 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
2647 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
2671 | break; |
2648 | break; |
2672 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
2649 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
2673 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
2650 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
2674 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2651 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2675 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2652 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
2676 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2653 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2677 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2654 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
2678 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2655 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
2679 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
2656 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
2680 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2657 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2681 | radeon_encoder->rmx_type = RMX_FULL; |
2658 | radeon_encoder->rmx_type = RMX_FULL; |
2682 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2659 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2683 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2660 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2684 | } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { |
2661 | } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { |
2685 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
2662 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
2686 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2663 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2687 | } else { |
2664 | } else { |
2688 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2665 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2689 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2666 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2690 | } |
2667 | } |
2691 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
2668 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
2692 | break; |
2669 | break; |
2693 | case ENCODER_OBJECT_ID_SI170B: |
2670 | case ENCODER_OBJECT_ID_SI170B: |
2694 | case ENCODER_OBJECT_ID_CH7303: |
2671 | case ENCODER_OBJECT_ID_CH7303: |
2695 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: |
2672 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: |
2696 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: |
2673 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: |
2697 | case ENCODER_OBJECT_ID_TITFP513: |
2674 | case ENCODER_OBJECT_ID_TITFP513: |
2698 | case ENCODER_OBJECT_ID_VT1623: |
2675 | case ENCODER_OBJECT_ID_VT1623: |
2699 | case ENCODER_OBJECT_ID_HDMI_SI1930: |
2676 | case ENCODER_OBJECT_ID_HDMI_SI1930: |
2700 | case ENCODER_OBJECT_ID_TRAVIS: |
2677 | case ENCODER_OBJECT_ID_TRAVIS: |
2701 | case ENCODER_OBJECT_ID_NUTMEG: |
2678 | case ENCODER_OBJECT_ID_NUTMEG: |
2702 | /* these are handled by the primary encoders */ |
2679 | /* these are handled by the primary encoders */ |
2703 | radeon_encoder->is_ext_encoder = true; |
2680 | radeon_encoder->is_ext_encoder = true; |
2704 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
2681 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
2705 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2682 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
2706 | else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) |
2683 | else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) |
2707 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
2684 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
2708 | else |
2685 | else |
2709 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2686 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
2710 | drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); |
2687 | drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); |
2711 | break; |
2688 | break; |
2712 | } |
2689 | } |
2713 | }><>><>><>><>>><>=>>>><> |
2690 | }><>><>><>><>>><>=>>>><> |