WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/atombios_dp.c

 	/* timeout */
 	if (args.v1.ucReplyStatus == 1) {
 		DRM_DEBUG_KMS("dp_aux_ch timeout\n");
 		r = -ETIMEDOUT;
 		goto done;
-			}
+	}
 	/* flags not zero */
 	if (args.v1.ucReplyStatus == 2) {
 		DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
 		r = -EIO;
 		goto done;
+	}
 	/* error */
 	if (args.v1.ucReplyStatus == 3) {
 		DRM_DEBUG_KMS("dp_aux_ch error\n");
 		r = -EIO;
 		goto done;
+	}
 #define BARE_ADDRESS_SIZE 3
 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
 static ssize_t
-radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
+radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
+{
 	struct radeon_i2c_chan *chan =
 		container_of(aux, struct radeon_i2c_chan, aux);
 	if (WARN_ON(msg->size > 16))
 		return -E2BIG;
 	tx_buf[0] = msg->address & 0xff;
+	tx_buf[1] = (msg->address >> 8) & 0xff;
-	tx_buf[1] = msg->address >> 8;
+	tx_buf[2] = (msg->request << 4) |
-	tx_buf[2] = msg->request << 4;
+		((msg->address >> 16) & 0xf);
 	tx_buf[3] = msg->size ? (msg->size - 1) : 0;
+	switch (msg->request & ~DP_AUX_I2C_MOT) {
+	case DP_AUX_NATIVE_WRITE:
+	case DP_AUX_I2C_WRITE:
+	case DP_AUX_I2C_WRITE_STATUS_UPDATE:
+		/* The atom implementation only supports writes with a max payload of
+		 * 12 bytes since it uses 4 bits for the total count (header + payload)
+		 * in the parameter space.  The atom interface supports 16 byte
+		 * payloads for reads. The hw itself supports up to 16 bytes of payload.
-	switch (msg->request & ~DP_AUX_I2C_MOT) {
+		 */
-	case DP_AUX_NATIVE_WRITE:
+		if (WARN_ON_ONCE(msg->size > 12))
-	case DP_AUX_I2C_WRITE:
+			return -E2BIG;
 		/* tx_size needs to be 4 even for bare address packets since the atom
 		 * table needs the info in tx_buf[3].
 					    tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
 		break;
 	default:
 		ret = -EINVAL;
 		break;
-			}
+	}
 	if (ret >= 0)
 		msg->reply = ack >> 4;
-			return ret;
+	return ret;
+}
+void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
+{
-void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
+	struct drm_device *dev = radeon_connector->base.dev;
 	struct radeon_device *rdev = dev->dev_private;
+	int ret;
+	radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
+	radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
+	if (ASIC_IS_DCE5(rdev)) {
+		if (radeon_auxch)
-	int ret;
+			radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native;
+		else
 			radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
-	radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
+	} else {
-	radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
+		radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
 /***** general DP utility functions *****/
 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_LEVEL_3
 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPH_LEVEL_3
-static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
+static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
 				int lane_count,
 				u8 train_set[4])
+{
 	return (link_rate * lane_num * 8) / bpp;
+}
 /***** radeon specific DP functions *****/
-static int radeon_dp_get_max_link_rate(struct drm_connector *connector,
+int radeon_dp_get_max_link_rate(struct drm_connector *connector,
-				       u8 dpcd[DP_DPCD_SIZE])
+				const u8 dpcd[DP_DPCD_SIZE])
+{
 	int max_link_rate;
 /* First get the min lane# when low rate is used according to pixel clock
  * (prefer low rate), second check max lane# supported by DP panel,
  * if the max lane# < low rate lane# then use max lane# instead.
  */
 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
-					u8 dpcd[DP_DPCD_SIZE],
+					const u8 dpcd[DP_DPCD_SIZE],
 					int pix_clock)
+{
 	int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 	int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
 	int max_lane_num = drm_dp_max_lane_count(dpcd);
 	return lane_num;
+}
 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
-				       u8 dpcd[DP_DPCD_SIZE],
+				       const u8 dpcd[DP_DPCD_SIZE],
 				       int pix_clock)
+{
 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
+{
 	struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 	u8 msg[DP_DPCD_SIZE];
+	int ret, i;
-	int ret;
+	for (i = 0; i < 7; i++) {
-	ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
+		ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
-			       DP_DPCD_SIZE);
+				       DP_DPCD_SIZE);
-	if (ret > 0) {
+		if (ret == DP_DPCD_SIZE) {
-		memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
+			memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
-		DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
+			DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
+				      dig_connector->dpcd);
 			      dig_connector->dpcd);
 			radeon_dp_probe_oui(radeon_connector);
 		radeon_dp_probe_oui(radeon_connector);
 			return true;
 		return true;
 	}
 	dig_connector->dpcd[0] = 0;
 	return false;
+}
 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 	if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 		/* DP bridge chips */
 		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
 				      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
-		if (tmp & 1)
+			if (tmp & 1)
-			panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
+				panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
-		else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
+			else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
-			 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
+				 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
-		panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
+				panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
-		else
+			else
-			panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
+				panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
+		}
 	} else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 		/* eDP */
 		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
 				      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
-		if (tmp & 1)
+			if (tmp & 1)
-			panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
+				panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
+		}
+	}
 		return;
 	dig_connector = radeon_connector->con_priv;
 	if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 	    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
-	dig_connector->dp_clock =
+		dig_connector->dp_clock =
 			radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
-	dig_connector->dp_lane_count =
+		dig_connector->dp_lane_count =
 			radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
+	}
+}
+{
 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 	struct radeon_connector_atom_dig *dig_connector;
 	int dp_clock;
+	if ((mode->clock > 340000) &&
+	    (!radeon_connector_is_dp12_capable(connector)))
+		return MODE_CLOCK_HIGH;
 	if (!radeon_connector->con_priv)
 		return MODE_CLOCK_HIGH;
 	dig_connector = radeon_connector->con_priv;
 	radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
 	/* possibly enable downspread on the sink */
 	if (dp_info->dpcd[3] & 0x1)
 		drm_dp_dpcd_writeb(dp_info->aux,
-				      DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
+				   DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 	else
 		drm_dp_dpcd_writeb(dp_info->aux,
-				      DP_DOWNSPREAD_CTRL, 0);
+				   DP_DOWNSPREAD_CTRL, 0);
 	if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
-	    (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
-		drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
+	if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
 		drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
 	/* set the lane count on the sink */
 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
 					  dp_info->dp_clock, dp_info->enc_id, 0);
 	/* disable the training pattern on the sink */
 	drm_dp_dpcd_writeb(dp_info->aux,
-			      DP_TRAINING_PATTERN_SET,
+			   DP_TRAINING_PATTERN_SET,
-			      DP_TRAINING_PATTERN_DISABLE);
+			   DP_TRAINING_PATTERN_DISABLE);
 	return 0;
+}
 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
+{
 	udelay(400);
 	/* disable the training pattern on the sink */
 	drm_dp_dpcd_writeb(dp_info->aux,
-			      DP_TRAINING_PATTERN_SET,
+			   DP_TRAINING_PATTERN_SET,
-			      DP_TRAINING_PATTERN_DISABLE);
+			   DP_TRAINING_PATTERN_DISABLE);
 	else
 		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
 	if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
 	    == 1) {
-	if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
+		if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
-		dp_info.tp3_supported = true;
+			dp_info.tp3_supported = true;
-	else
+		else
-		dp_info.tp3_supported = false;
+			dp_info.tp3_supported = false;
 	} else {
 		dp_info.tp3_supported = false;
+	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/atombios_dp.c – Rev 5271 → 6104