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Line 20... | Line 20... | ||
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: Dave Airlie |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
24 | * Alex Deucher |
- | 25 | * Jerome Glisse |
|
25 | */ |
26 | */ |
26 | #include "drmP.h" |
27 | #include |
27 | #include "radeon_drm.h" |
28 | #include |
28 | #include "radeon.h" |
29 | #include "radeon.h" |
Line 29... | Line 30... | ||
29 | 30 | ||
30 | #include "atom.h" |
31 | #include "atom.h" |
31 | #include "atom-bits.h" |
32 | #include "atom-bits.h" |
Line 32... | Line 33... | ||
32 | #include "drm_dp_helper.h" |
33 | #include |
33 | 34 | ||
34 | /* move these to drm_dp_helper.c/h */ |
35 | /* move these to drm_dp_helper.c/h */ |
35 | #define DP_LINK_CONFIGURATION_SIZE 9 |
36 | #define DP_LINK_CONFIGURATION_SIZE 9 |
Line 61... | Line 62... | ||
61 | unsigned char *base; |
62 | unsigned char *base; |
62 | int recv_bytes; |
63 | int recv_bytes; |
Line 63... | Line 64... | ||
63 | 64 | ||
Line 64... | Line 65... | ||
64 | memset(&args, 0, sizeof(args)); |
65 | memset(&args, 0, sizeof(args)); |
Line 65... | Line 66... | ||
65 | 66 | ||
Line 66... | Line 67... | ||
66 | base = (unsigned char *)rdev->mode_info.atom_context->scratch; |
67 | base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); |
67 | 68 | ||
68 | memcpy(base, send, send_bytes); |
69 | memcpy(base, send, send_bytes); |
69 | 70 | ||
70 | args.v1.lpAuxRequest = 0; |
71 | args.v1.lpAuxRequest = 0 + 4; |
71 | args.v1.lpDataOut = 16; |
72 | args.v1.lpDataOut = 16 + 4; |
72 | args.v1.ucDataOutLen = 0; |
73 | args.v1.ucDataOutLen = 0; |
Line 113... | Line 114... | ||
113 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
114 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
114 | int ret; |
115 | int ret; |
115 | u8 msg[20]; |
116 | u8 msg[20]; |
116 | int msg_bytes = send_bytes + 4; |
117 | int msg_bytes = send_bytes + 4; |
117 | u8 ack; |
118 | u8 ack; |
- | 119 | unsigned retry; |
|
Line 118... | Line 120... | ||
118 | 120 | ||
119 | if (send_bytes > 16) |
121 | if (send_bytes > 16) |
Line 120... | Line 122... | ||
120 | return -1; |
122 | return -1; |
121 | 123 | ||
122 | msg[0] = address; |
124 | msg[0] = address; |
123 | msg[1] = address >> 8; |
125 | msg[1] = address >> 8; |
124 | msg[2] = AUX_NATIVE_WRITE << 4; |
126 | msg[2] = AUX_NATIVE_WRITE << 4; |
Line 125... | Line 127... | ||
125 | msg[3] = (msg_bytes << 4) | (send_bytes - 1); |
127 | msg[3] = (msg_bytes << 4) | (send_bytes - 1); |
126 | memcpy(&msg[4], send, send_bytes); |
128 | memcpy(&msg[4], send, send_bytes); |
127 | 129 | ||
- | 130 | for (retry = 0; retry < 4; retry++) { |
|
- | 131 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
|
128 | while (1) { |
132 | msg, msg_bytes, NULL, 0, delay, &ack); |
129 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
133 | if (ret == -EBUSY) |
130 | msg, msg_bytes, NULL, 0, delay, &ack); |
134 | continue; |
131 | if (ret < 0) |
135 | else if (ret < 0) |
132 | return ret; |
136 | return ret; |
133 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
137 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
134 | break; |
138 | return send_bytes; |
135 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
139 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
136 | udelay(400); |
140 | udelay(400); |
Line 137... | Line 141... | ||
137 | else |
141 | else |
138 | return -EIO; |
142 | return -EIO; |
Line 139... | Line 143... | ||
139 | } |
143 | } |
140 | 144 | ||
141 | return send_bytes; |
145 | return -EIO; |
142 | } |
146 | } |
143 | 147 | ||
144 | static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, |
148 | static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, |
145 | u16 address, u8 *recv, int recv_bytes, u8 delay) |
149 | u16 address, u8 *recv, int recv_bytes, u8 delay) |
146 | { |
150 | { |
- | 151 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
|
Line 147... | Line 152... | ||
147 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
152 | u8 msg[4]; |
148 | u8 msg[4]; |
153 | int msg_bytes = 4; |
149 | int msg_bytes = 4; |
154 | u8 ack; |
150 | u8 ack; |
155 | int ret; |
Line 151... | Line 156... | ||
151 | int ret; |
156 | unsigned retry; |
152 | 157 | ||
153 | msg[0] = address; |
158 | msg[0] = address; |
154 | msg[1] = address >> 8; |
159 | msg[1] = address >> 8; |
155 | msg[2] = AUX_NATIVE_READ << 4; |
160 | msg[2] = AUX_NATIVE_READ << 4; |
156 | msg[3] = (msg_bytes << 4) | (recv_bytes - 1); |
161 | msg[3] = (msg_bytes << 4) | (recv_bytes - 1); |
157 | 162 | ||
158 | while (1) { |
163 | for (retry = 0; retry < 4; retry++) { |
159 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
164 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
160 | msg, msg_bytes, recv, recv_bytes, delay, &ack); |
165 | msg, msg_bytes, recv, recv_bytes, delay, &ack); |
161 | if (ret == 0) |
166 | if (ret == -EBUSY) |
- | 167 | continue; |
|
- | 168 | else if (ret < 0) |
|
162 | return -EPROTO; |
169 | return ret; |
163 | if (ret < 0) |
170 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
164 | return ret; |
171 | return ret; |
- | 172 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
|
- | 173 | udelay(400); |
|
165 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
174 | else if (ret == 0) |
Line 166... | Line 175... | ||
166 | return ret; |
175 | return -EPROTO; |
167 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
176 | else |
168 | udelay(400); |
177 | return -EIO; |
Line 230... | Line 239... | ||
230 | } |
239 | } |
Line 231... | Line 240... | ||
231 | 240 | ||
232 | for (retry = 0; retry < 4; retry++) { |
241 | for (retry = 0; retry < 4; retry++) { |
233 | ret = radeon_process_aux_ch(auxch, |
242 | ret = radeon_process_aux_ch(auxch, |
- | 243 | msg, msg_bytes, reply, reply_bytes, 0, &ack); |
|
- | 244 | if (ret == -EBUSY) |
|
234 | msg, msg_bytes, reply, reply_bytes, 0, &ack); |
245 | continue; |
235 | if (ret < 0) { |
246 | else if (ret < 0) { |
236 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
247 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
237 | return ret; |
248 | return ret; |
Line 238... | Line 249... | ||
238 | } |
249 | } |
Line 271... | Line 282... | ||
271 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); |
282 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); |
272 | return -EREMOTEIO; |
283 | return -EREMOTEIO; |
273 | } |
284 | } |
274 | } |
285 | } |
Line 275... | Line 286... | ||
275 | 286 | ||
276 | DRM_ERROR("aux i2c too many retries, giving up\n"); |
287 | DRM_DEBUG_KMS("aux i2c too many retries, giving up\n"); |
277 | return -EREMOTEIO; |
288 | return -EREMOTEIO; |
Line 278... | Line 289... | ||
278 | } |
289 | } |
Line 448... | Line 459... | ||
448 | */ |
459 | */ |
449 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, |
460 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, |
450 | u8 dpcd[DP_DPCD_SIZE], |
461 | u8 dpcd[DP_DPCD_SIZE], |
451 | int pix_clock) |
462 | int pix_clock) |
452 | { |
463 | { |
453 | int bpp = convert_bpc_to_bpp(connector->display_info.bpc); |
464 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
454 | int max_link_rate = dp_get_max_link_rate(dpcd); |
465 | int max_link_rate = dp_get_max_link_rate(dpcd); |
455 | int max_lane_num = dp_get_max_lane_number(dpcd); |
466 | int max_lane_num = dp_get_max_lane_number(dpcd); |
456 | int lane_num; |
467 | int lane_num; |
457 | int max_dp_pix_clock; |
468 | int max_dp_pix_clock; |
Line 467... | Line 478... | ||
467 | 478 | ||
468 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
479 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
469 | u8 dpcd[DP_DPCD_SIZE], |
480 | u8 dpcd[DP_DPCD_SIZE], |
470 | int pix_clock) |
481 | int pix_clock) |
471 | { |
482 | { |
472 | int bpp = convert_bpc_to_bpp(connector->display_info.bpc); |
483 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
Line 473... | Line 484... | ||
473 | int lane_num, max_pix_clock; |
484 | int lane_num, max_pix_clock; |
- | 485 | ||
474 | 486 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
|
Line 475... | Line 487... | ||
475 | if (radeon_connector_encoder_is_dp_bridge(connector)) |
487 | ENCODER_OBJECT_ID_NUTMEG) |
476 | return 270000; |
488 | return 270000; |
477 | 489 | ||
Line 517... | Line 529... | ||
517 | 529 | ||
518 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, |
530 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, |
519 | dig_connector->dp_i2c_bus->rec.i2c_id, 0); |
531 | dig_connector->dp_i2c_bus->rec.i2c_id, 0); |
Line -... | Line 532... | ||
- | 532 | } |
|
- | 533 | ||
- | 534 | static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) |
|
- | 535 | { |
|
- | 536 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
|
- | 537 | u8 buf[3]; |
|
- | 538 | ||
- | 539 | if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
|
- | 540 | return; |
|
- | 541 | ||
- | 542 | if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0)) |
|
- | 543 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
|
- | 544 | buf[0], buf[1], buf[2]); |
|
- | 545 | ||
- | 546 | if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0)) |
|
- | 547 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
|
- | 548 | buf[0], buf[1], buf[2]); |
|
520 | } |
549 | } |
521 | 550 | ||
522 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
551 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
523 | { |
552 | { |
524 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
553 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
Line 530... | Line 559... | ||
530 | memcpy(dig_connector->dpcd, msg, 8); |
559 | memcpy(dig_connector->dpcd, msg, 8); |
531 | DRM_DEBUG_KMS("DPCD: "); |
560 | DRM_DEBUG_KMS("DPCD: "); |
532 | for (i = 0; i < 8; i++) |
561 | for (i = 0; i < 8; i++) |
533 | DRM_DEBUG_KMS("%02x ", msg[i]); |
562 | DRM_DEBUG_KMS("%02x ", msg[i]); |
534 | DRM_DEBUG_KMS("\n"); |
563 | DRM_DEBUG_KMS("\n"); |
- | 564 | ||
- | 565 | radeon_dp_probe_oui(radeon_connector); |
|
- | 566 | ||
535 | return true; |
567 | return true; |
536 | } |
568 | } |
537 | dig_connector->dpcd[0] = 0; |
569 | dig_connector->dpcd[0] = 0; |
538 | return false; |
570 | return false; |
539 | } |
571 | } |
Line 540... | Line 572... | ||
540 | 572 | ||
541 | static void radeon_dp_set_panel_mode(struct drm_encoder *encoder, |
573 | int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
542 | struct drm_connector *connector) |
574 | struct drm_connector *connector) |
543 | { |
575 | { |
544 | struct drm_device *dev = encoder->dev; |
576 | struct drm_device *dev = encoder->dev; |
- | 577 | struct radeon_device *rdev = dev->dev_private; |
|
545 | struct radeon_device *rdev = dev->dev_private; |
578 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
- | 579 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
|
- | 580 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); |
|
Line 546... | Line 581... | ||
546 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
581 | u8 tmp; |
547 | 582 | ||
Line -... | Line 583... | ||
- | 583 | if (!ASIC_IS_DCE4(rdev)) |
|
- | 584 | return panel_mode; |
|
548 | if (!ASIC_IS_DCE4(rdev)) |
585 | |
- | 586 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
|
- | 587 | /* DP bridge chips */ |
|
- | 588 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); |
|
- | 589 | if (tmp & 1) |
|
549 | return; |
590 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
- | 591 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || |
|
- | 592 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) |
|
- | 593 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
|
- | 594 | else |
|
- | 595 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
|
- | 596 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
|
- | 597 | /* eDP */ |
|
- | 598 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); |
|
Line 550... | Line -... | ||
550 | - | ||
551 | if (radeon_connector_encoder_is_dp_bridge(connector)) |
- | |
552 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
599 | if (tmp & 1) |
553 | 600 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
|
Line 554... | Line 601... | ||
554 | atombios_dig_encoder_setup(encoder, |
601 | } |
555 | ATOM_ENCODER_CMD_SETUP_PANEL_MODE, |
602 | |
556 | panel_mode); |
603 | return panel_mode; |
557 | } |
604 | } |
558 | 605 | ||
Line 559... | Line 606... | ||
559 | void radeon_dp_set_link_config(struct drm_connector *connector, |
606 | void radeon_dp_set_link_config(struct drm_connector *connector, |
Line 601... | Line 648... | ||
601 | { |
648 | { |
602 | int ret; |
649 | int ret; |
603 | ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, |
650 | ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, |
604 | link_status, DP_LINK_STATUS_SIZE, 100); |
651 | link_status, DP_LINK_STATUS_SIZE, 100); |
605 | if (ret <= 0) { |
652 | if (ret <= 0) { |
606 | DRM_ERROR("displayport link status failed\n"); |
- | |
607 | return false; |
653 | return false; |
608 | } |
654 | } |
Line 609... | Line 655... | ||
609 | 655 | ||
- | 656 | DRM_DEBUG_KMS("link status %*ph\n", 6, link_status); |
|
- | 657 | return true; |
|
- | 658 | } |
|
- | 659 | ||
- | 660 | bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) |
|
- | 661 | { |
|
- | 662 | u8 link_status[DP_LINK_STATUS_SIZE]; |
|
- | 663 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
|
610 | DRM_DEBUG_KMS("link status %02x %02x %02x %02x %02x %02x\n", |
664 | |
- | 665 | if (!radeon_dp_get_link_status(radeon_connector, link_status)) |
|
611 | link_status[0], link_status[1], link_status[2], |
666 | return false; |
- | 667 | if (dp_channel_eq_ok(link_status, dig->dp_lane_count)) |
|
612 | link_status[3], link_status[4], link_status[5]); |
668 | return false; |
613 | return true; |
669 | return true; |
Line 614... | Line 670... | ||
614 | } |
670 | } |
615 | 671 | ||
Line 677... | Line 733... | ||
677 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp); |
733 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp); |
678 | } |
734 | } |
Line 679... | Line 735... | ||
679 | 735 | ||
680 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
736 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
- | 737 | { |
|
- | 738 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); |
|
681 | { |
739 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Line 682... | Line 740... | ||
682 | u8 tmp; |
740 | u8 tmp; |
683 | 741 | ||
684 | /* power up the sink */ |
742 | /* power up the sink */ |
Line 692... | Line 750... | ||
692 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); |
750 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); |
693 | else |
751 | else |
694 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
752 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
695 | DP_DOWNSPREAD_CTRL, 0); |
753 | DP_DOWNSPREAD_CTRL, 0); |
Line -... | Line 754... | ||
- | 754 | ||
- | 755 | if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && |
|
696 | 756 | (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { |
|
- | 757 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1); |
|
Line 697... | Line 758... | ||
697 | radeon_dp_set_panel_mode(dp_info->encoder, dp_info->connector); |
758 | } |
698 | 759 | ||
699 | /* set the lane count on the sink */ |
760 | /* set the lane count on the sink */ |
- | 761 | tmp = dp_info->dp_lane_count; |
|
700 | tmp = dp_info->dp_lane_count; |
762 | if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 && |
701 | if (dp_info->dpcd[0] >= 0x11) |
763 | dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP) |
Line 702... | Line 764... | ||
702 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
764 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
703 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); |
765 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); |
Line 762... | Line 824... | ||
762 | if (dp_info->rd_interval == 0) |
824 | if (dp_info->rd_interval == 0) |
763 | udelay(100); |
825 | udelay(100); |
764 | else |
826 | else |
765 | mdelay(dp_info->rd_interval * 4); |
827 | mdelay(dp_info->rd_interval * 4); |
Line 766... | Line 828... | ||
766 | 828 | ||
- | 829 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
|
767 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) |
830 | DRM_ERROR("displayport link status failed\n"); |
- | 831 | break; |
|
Line 768... | Line 832... | ||
768 | break; |
832 | } |
769 | 833 | ||
770 | if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
834 | if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
771 | clock_recovery = true; |
835 | clock_recovery = true; |
Line 825... | Line 889... | ||
825 | if (dp_info->rd_interval == 0) |
889 | if (dp_info->rd_interval == 0) |
826 | udelay(400); |
890 | udelay(400); |
827 | else |
891 | else |
828 | mdelay(dp_info->rd_interval * 4); |
892 | mdelay(dp_info->rd_interval * 4); |
Line 829... | Line 893... | ||
829 | 893 | ||
- | 894 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
|
830 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) |
895 | DRM_ERROR("displayport link status failed\n"); |
- | 896 | break; |
|
Line 831... | Line 897... | ||
831 | break; |
897 | } |
832 | 898 | ||
833 | if (dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
899 | if (dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
834 | channel_eq = true; |
900 | channel_eq = true; |