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Line 319... Line 319...
319 
 
 319 
 
320 
	for (lane = 0; lane < 4; lane++)
 320 
	for (lane = 0; lane < 4; lane++)
321 
		train_set[lane] = v | p;
 321 
		train_set[lane] = v | p;
Line -... Line 322...
- 
 
 322 
}
- 
 
 323 
 
- 
 
 324 
union aux_channel_transaction {
- 
 
 325 
	PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
Line 322... Line 326...
322 
}
 326 
	PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
323 
 
 327 
};
324 
 
 328 
 
325 
/* radeon aux chan functions */
 329 
/* radeon aux chan functions */
326 
bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
 330 
bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
327 
			   int num_bytes, u8 *read_byte,
 331 
			   int num_bytes, u8 *read_byte,
328 
			   u8 read_buf_len, u8 delay)
 332 
			   u8 read_buf_len, u8 delay)
329 
{
 333 
{
330 
	struct drm_device *dev = chan->dev;
 334 
	struct drm_device *dev = chan->dev;
331 
	struct radeon_device *rdev = dev->dev_private;
 335 
	struct radeon_device *rdev = dev->dev_private;
332 
	PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args;
 336 
	union aux_channel_transaction args;
Line 333... Line 337...
333 
	int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
 337 
	int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
Line 339... Line 343...
339 
	base = (unsigned char *)rdev->mode_info.atom_context->scratch;
 343 
	base = (unsigned char *)rdev->mode_info.atom_context->scratch;
Line 340... Line 344...
340 
 
 344 
 
341 
retry:
 345 
retry:
Line 342... Line 346...
342 
	memcpy(base, req_bytes, num_bytes);
 346 
	memcpy(base, req_bytes, num_bytes);
343 
 
 347 
 
344 
	args.lpAuxRequest = 0;
 348 
	args.v1.lpAuxRequest = 0;
345 
	args.lpDataOut = 16;
 349 
	args.v1.lpDataOut = 16;
346 
	args.ucDataOutLen = 0;
 350 
	args.v1.ucDataOutLen = 0;
- 
 
 351 
	args.v1.ucChannelID = chan->rec.i2c_id;
- 
 
 352 
	args.v1.ucDelay = delay / 10;
Line 347... Line 353...
347 
	args.ucChannelID = chan->rec.i2c_id;
 353 
	if (ASIC_IS_DCE4(rdev))
Line 348... Line 354...
348 
	args.ucDelay = delay / 10;
 354 
		args.v2.ucHPD_ID = chan->rec.hpd_id;
349 
 
 355 
 
350 
	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 356 
	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
351 
 
 357 
 
352 
	if (args.ucReplyStatus && !args.ucDataOutLen) {
 358 
	if (args.v1.ucReplyStatus && !args.v1.ucDataOutLen) {
353 
		if (args.ucReplyStatus == 0x20 && retry_count++ < 10)
 359 
		if (args.v1.ucReplyStatus == 0x20 && retry_count++ < 10)
354 
			goto retry;
 360 
			goto retry;
355 
		DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n",
 361 
		DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n",
Line 356... Line 362...
356 
			  req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
 362 
			  req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
357 
			  chan->rec.i2c_id, args.ucReplyStatus, retry_count);
 363 
			  chan->rec.i2c_id, args.v1.ucReplyStatus, retry_count);
358 
		return false;
 364 
		return false;
359 
	}
 365 
	}
360 
 
 366 
 
361 
	if (args.ucDataOutLen && read_byte && read_buf_len) {
 367 
	if (args.v1.ucDataOutLen && read_byte && read_buf_len) {
362 
		if (read_buf_len < args.ucDataOutLen) {
 368 
		if (read_buf_len < args.v1.ucDataOutLen) {
363 
			DRM_ERROR("Buffer to small for return answer %d %d\n",
 369 
			DRM_ERROR("Buffer to small for return answer %d %d\n",
364 
				  read_buf_len, args.ucDataOutLen);
 370 
				  read_buf_len, args.v1.ucDataOutLen);
365 
			return false;
 371 
			return false;
366 
		}
 372 
		}
367 
		{
 373 
		{
368 
			int len = min(read_buf_len, args.ucDataOutLen);
 374 
			int len = min(read_buf_len, args.v1.ucDataOutLen);
Line 624... Line 630...
624 
	dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
 630 
	dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
625 
	/* set link bw and lanes on the sink */
 631 
	/* set link bw and lanes on the sink */
626 
	dp_set_link_bw_lanes(radeon_connector, link_configuration);
 632 
	dp_set_link_bw_lanes(radeon_connector, link_configuration);
627 
	/* disable downspread on the sink */
 633 
	/* disable downspread on the sink */
628 
	dp_set_downspread(radeon_connector, 0);
 634 
	dp_set_downspread(radeon_connector, 0);
- 
 
 635 
	if (ASIC_IS_DCE4(rdev)) {
- 
 
 636 
		/* start training on the source */
- 
 
 637 
		atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_START);
- 
 
 638 
		/* set training pattern 1 on the source */
- 
 
 639 
		atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1);
- 
 
 640 
	} else {
629 
	/* start training on the source */
 641 
	/* start training on the source */
630 
	radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
 642 
	radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
631 
				  dig_connector->dp_clock, enc_id, 0);
 643 
				  dig_connector->dp_clock, enc_id, 0);
632 
	/* set training pattern 1 on the source */
 644 
	/* set training pattern 1 on the source */
633 
	radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 645 
	radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
634 
				  dig_connector->dp_clock, enc_id, 0);
 646 
				  dig_connector->dp_clock, enc_id, 0);
- 
 
 647 
	}
Line 635... Line 648...
635 
 
 648 
 
636 
	/* set initial vs/emph */
 649 
	/* set initial vs/emph */
637 
	memset(train_set, 0, 4);
 650 
	memset(train_set, 0, 4);
638 
	udelay(400);
 651 
	udelay(400);
Line 689... Line 702...
689 
 
 702 
 
690 
 
 703 
 
691 
	/* set training pattern 2 on the sink */
 704 
	/* set training pattern 2 on the sink */
- 
 
 705 
	dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2);
- 
 
 706 
	/* set training pattern 2 on the source */
- 
 
 707 
	if (ASIC_IS_DCE4(rdev))
692 
	dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2);
 708 
		atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2);
693 
	/* set training pattern 2 on the source */
 709 
	else
Line 694... Line 710...
694 
	radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 710 
	radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
695 
				  dig_connector->dp_clock, enc_id, 1);
 711 
				  dig_connector->dp_clock, enc_id, 1);
Line 727... Line 743...
727 
			  train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 743 
			  train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
728 
			  (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 744 
			  (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
729 
			  >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 745 
			  >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
Line 730... Line 746...
730 
 
 746 
 
- 
 
 747 
	/* disable the training pattern on the sink */
- 
 
 748 
	if (ASIC_IS_DCE4(rdev))
- 
 
 749 
		atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE);
731 
	/* disable the training pattern on the sink */
 750 
	else
- 
 
 751 
		radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
Line 732... Line 752...
732 
	dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
 752 
					  dig_connector->dp_clock, enc_id, 0);
733 
 
 753 
 
734 
	radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
 754 
	radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,