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1 | /* |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
13 | * all copies or substantial portions of the Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: Dave Airlie |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
24 | * Alex Deucher |
25 | */ |
25 | */ |
26 | #include |
26 | #include |
27 | #include |
27 | #include |
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include "radeon.h" |
31 | #include "radeon.h" |
32 | #include "atom.h" |
32 | #include "atom.h" |
33 | #include "atom-bits.h" |
33 | #include "atom-bits.h" |
34 | 34 | ||
35 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
35 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
36 | struct drm_display_mode *mode, |
36 | struct drm_display_mode *mode, |
37 | struct drm_display_mode *adjusted_mode) |
37 | struct drm_display_mode *adjusted_mode) |
38 | { |
38 | { |
39 | struct drm_device *dev = crtc->dev; |
39 | struct drm_device *dev = crtc->dev; |
40 | struct radeon_device *rdev = dev->dev_private; |
40 | struct radeon_device *rdev = dev->dev_private; |
41 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
41 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
42 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; |
42 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; |
43 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); |
43 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); |
44 | int a1, a2; |
44 | int a1, a2; |
45 | 45 | ||
46 | memset(&args, 0, sizeof(args)); |
46 | memset(&args, 0, sizeof(args)); |
47 | 47 | ||
48 | args.ucCRTC = radeon_crtc->crtc_id; |
48 | args.ucCRTC = radeon_crtc->crtc_id; |
49 | 49 | ||
50 | switch (radeon_crtc->rmx_type) { |
50 | switch (radeon_crtc->rmx_type) { |
51 | case RMX_CENTER: |
51 | case RMX_CENTER: |
52 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
52 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
53 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
53 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
54 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
54 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
55 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
55 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
56 | break; |
56 | break; |
57 | case RMX_ASPECT: |
57 | case RMX_ASPECT: |
58 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
58 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
59 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
59 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
60 | 60 | ||
61 | if (a1 > a2) { |
61 | if (a1 > a2) { |
62 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
62 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
63 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
63 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
64 | } else if (a2 > a1) { |
64 | } else if (a2 > a1) { |
65 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
65 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
66 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
66 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
67 | } |
67 | } |
68 | break; |
68 | break; |
69 | case RMX_FULL: |
69 | case RMX_FULL: |
70 | default: |
70 | default: |
71 | args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); |
71 | args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); |
72 | args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); |
72 | args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); |
73 | args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); |
73 | args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); |
74 | args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); |
74 | args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); |
75 | break; |
75 | break; |
76 | } |
76 | } |
77 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
77 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
78 | } |
78 | } |
79 | 79 | ||
80 | static void atombios_scaler_setup(struct drm_crtc *crtc) |
80 | static void atombios_scaler_setup(struct drm_crtc *crtc) |
81 | { |
81 | { |
82 | struct drm_device *dev = crtc->dev; |
82 | struct drm_device *dev = crtc->dev; |
83 | struct radeon_device *rdev = dev->dev_private; |
83 | struct radeon_device *rdev = dev->dev_private; |
84 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
84 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
85 | ENABLE_SCALER_PS_ALLOCATION args; |
85 | ENABLE_SCALER_PS_ALLOCATION args; |
86 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
86 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
87 | struct radeon_encoder *radeon_encoder = |
87 | struct radeon_encoder *radeon_encoder = |
88 | to_radeon_encoder(radeon_crtc->encoder); |
88 | to_radeon_encoder(radeon_crtc->encoder); |
89 | /* fixme - fill in enc_priv for atom dac */ |
89 | /* fixme - fill in enc_priv for atom dac */ |
90 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
90 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
91 | bool is_tv = false, is_cv = false; |
91 | bool is_tv = false, is_cv = false; |
92 | 92 | ||
93 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
93 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
94 | return; |
94 | return; |
95 | 95 | ||
96 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
96 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
97 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
97 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
98 | tv_std = tv_dac->tv_std; |
98 | tv_std = tv_dac->tv_std; |
99 | is_tv = true; |
99 | is_tv = true; |
100 | } |
100 | } |
101 | 101 | ||
102 | memset(&args, 0, sizeof(args)); |
102 | memset(&args, 0, sizeof(args)); |
103 | 103 | ||
104 | args.ucScaler = radeon_crtc->crtc_id; |
104 | args.ucScaler = radeon_crtc->crtc_id; |
105 | 105 | ||
106 | if (is_tv) { |
106 | if (is_tv) { |
107 | switch (tv_std) { |
107 | switch (tv_std) { |
108 | case TV_STD_NTSC: |
108 | case TV_STD_NTSC: |
109 | default: |
109 | default: |
110 | args.ucTVStandard = ATOM_TV_NTSC; |
110 | args.ucTVStandard = ATOM_TV_NTSC; |
111 | break; |
111 | break; |
112 | case TV_STD_PAL: |
112 | case TV_STD_PAL: |
113 | args.ucTVStandard = ATOM_TV_PAL; |
113 | args.ucTVStandard = ATOM_TV_PAL; |
114 | break; |
114 | break; |
115 | case TV_STD_PAL_M: |
115 | case TV_STD_PAL_M: |
116 | args.ucTVStandard = ATOM_TV_PALM; |
116 | args.ucTVStandard = ATOM_TV_PALM; |
117 | break; |
117 | break; |
118 | case TV_STD_PAL_60: |
118 | case TV_STD_PAL_60: |
119 | args.ucTVStandard = ATOM_TV_PAL60; |
119 | args.ucTVStandard = ATOM_TV_PAL60; |
120 | break; |
120 | break; |
121 | case TV_STD_NTSC_J: |
121 | case TV_STD_NTSC_J: |
122 | args.ucTVStandard = ATOM_TV_NTSCJ; |
122 | args.ucTVStandard = ATOM_TV_NTSCJ; |
123 | break; |
123 | break; |
124 | case TV_STD_SCART_PAL: |
124 | case TV_STD_SCART_PAL: |
125 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ |
125 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ |
126 | break; |
126 | break; |
127 | case TV_STD_SECAM: |
127 | case TV_STD_SECAM: |
128 | args.ucTVStandard = ATOM_TV_SECAM; |
128 | args.ucTVStandard = ATOM_TV_SECAM; |
129 | break; |
129 | break; |
130 | case TV_STD_PAL_CN: |
130 | case TV_STD_PAL_CN: |
131 | args.ucTVStandard = ATOM_TV_PALCN; |
131 | args.ucTVStandard = ATOM_TV_PALCN; |
132 | break; |
132 | break; |
133 | } |
133 | } |
134 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
134 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
135 | } else if (is_cv) { |
135 | } else if (is_cv) { |
136 | args.ucTVStandard = ATOM_TV_CV; |
136 | args.ucTVStandard = ATOM_TV_CV; |
137 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
137 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
138 | } else { |
138 | } else { |
139 | switch (radeon_crtc->rmx_type) { |
139 | switch (radeon_crtc->rmx_type) { |
140 | case RMX_FULL: |
140 | case RMX_FULL: |
141 | args.ucEnable = ATOM_SCALER_EXPANSION; |
141 | args.ucEnable = ATOM_SCALER_EXPANSION; |
142 | break; |
142 | break; |
143 | case RMX_CENTER: |
143 | case RMX_CENTER: |
144 | args.ucEnable = ATOM_SCALER_CENTER; |
144 | args.ucEnable = ATOM_SCALER_CENTER; |
145 | break; |
145 | break; |
146 | case RMX_ASPECT: |
146 | case RMX_ASPECT: |
147 | args.ucEnable = ATOM_SCALER_EXPANSION; |
147 | args.ucEnable = ATOM_SCALER_EXPANSION; |
148 | break; |
148 | break; |
149 | default: |
149 | default: |
150 | if (ASIC_IS_AVIVO(rdev)) |
150 | if (ASIC_IS_AVIVO(rdev)) |
151 | args.ucEnable = ATOM_SCALER_DISABLE; |
151 | args.ucEnable = ATOM_SCALER_DISABLE; |
152 | else |
152 | else |
153 | args.ucEnable = ATOM_SCALER_CENTER; |
153 | args.ucEnable = ATOM_SCALER_CENTER; |
154 | break; |
154 | break; |
155 | } |
155 | } |
156 | } |
156 | } |
157 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
157 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
158 | if ((is_tv || is_cv) |
158 | if ((is_tv || is_cv) |
159 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { |
159 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { |
160 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); |
160 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); |
161 | } |
161 | } |
162 | } |
162 | } |
163 | 163 | ||
164 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
164 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
165 | { |
165 | { |
166 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
166 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
167 | struct drm_device *dev = crtc->dev; |
167 | struct drm_device *dev = crtc->dev; |
168 | struct radeon_device *rdev = dev->dev_private; |
168 | struct radeon_device *rdev = dev->dev_private; |
169 | int index = |
169 | int index = |
170 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); |
170 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); |
171 | ENABLE_CRTC_PS_ALLOCATION args; |
171 | ENABLE_CRTC_PS_ALLOCATION args; |
172 | 172 | ||
173 | memset(&args, 0, sizeof(args)); |
173 | memset(&args, 0, sizeof(args)); |
174 | 174 | ||
175 | args.ucCRTC = radeon_crtc->crtc_id; |
175 | args.ucCRTC = radeon_crtc->crtc_id; |
176 | args.ucEnable = lock; |
176 | args.ucEnable = lock; |
177 | 177 | ||
178 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
178 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
179 | } |
179 | } |
180 | 180 | ||
181 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) |
181 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) |
182 | { |
182 | { |
183 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
183 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
184 | struct drm_device *dev = crtc->dev; |
184 | struct drm_device *dev = crtc->dev; |
185 | struct radeon_device *rdev = dev->dev_private; |
185 | struct radeon_device *rdev = dev->dev_private; |
186 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); |
186 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); |
187 | ENABLE_CRTC_PS_ALLOCATION args; |
187 | ENABLE_CRTC_PS_ALLOCATION args; |
188 | 188 | ||
189 | memset(&args, 0, sizeof(args)); |
189 | memset(&args, 0, sizeof(args)); |
190 | 190 | ||
191 | args.ucCRTC = radeon_crtc->crtc_id; |
191 | args.ucCRTC = radeon_crtc->crtc_id; |
192 | args.ucEnable = state; |
192 | args.ucEnable = state; |
193 | 193 | ||
194 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
194 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
195 | } |
195 | } |
196 | 196 | ||
197 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) |
197 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) |
198 | { |
198 | { |
199 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
199 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
200 | struct drm_device *dev = crtc->dev; |
200 | struct drm_device *dev = crtc->dev; |
201 | struct radeon_device *rdev = dev->dev_private; |
201 | struct radeon_device *rdev = dev->dev_private; |
202 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); |
202 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); |
203 | ENABLE_CRTC_PS_ALLOCATION args; |
203 | ENABLE_CRTC_PS_ALLOCATION args; |
204 | 204 | ||
205 | memset(&args, 0, sizeof(args)); |
205 | memset(&args, 0, sizeof(args)); |
206 | 206 | ||
207 | args.ucCRTC = radeon_crtc->crtc_id; |
207 | args.ucCRTC = radeon_crtc->crtc_id; |
208 | args.ucEnable = state; |
208 | args.ucEnable = state; |
209 | 209 | ||
210 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
210 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
211 | } |
211 | } |
212 | 212 | ||
213 | static const u32 vga_control_regs[6] = |
213 | static const u32 vga_control_regs[6] = |
214 | { |
214 | { |
215 | AVIVO_D1VGA_CONTROL, |
215 | AVIVO_D1VGA_CONTROL, |
216 | AVIVO_D2VGA_CONTROL, |
216 | AVIVO_D2VGA_CONTROL, |
217 | EVERGREEN_D3VGA_CONTROL, |
217 | EVERGREEN_D3VGA_CONTROL, |
218 | EVERGREEN_D4VGA_CONTROL, |
218 | EVERGREEN_D4VGA_CONTROL, |
219 | EVERGREEN_D5VGA_CONTROL, |
219 | EVERGREEN_D5VGA_CONTROL, |
220 | EVERGREEN_D6VGA_CONTROL, |
220 | EVERGREEN_D6VGA_CONTROL, |
221 | }; |
221 | }; |
222 | 222 | ||
223 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
223 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
224 | { |
224 | { |
225 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
225 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
226 | struct drm_device *dev = crtc->dev; |
226 | struct drm_device *dev = crtc->dev; |
227 | struct radeon_device *rdev = dev->dev_private; |
227 | struct radeon_device *rdev = dev->dev_private; |
228 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
228 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
229 | BLANK_CRTC_PS_ALLOCATION args; |
229 | BLANK_CRTC_PS_ALLOCATION args; |
230 | u32 vga_control = 0; |
230 | u32 vga_control = 0; |
231 | 231 | ||
232 | memset(&args, 0, sizeof(args)); |
232 | memset(&args, 0, sizeof(args)); |
233 | 233 | ||
234 | if (ASIC_IS_DCE8(rdev)) { |
234 | if (ASIC_IS_DCE8(rdev)) { |
235 | vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); |
235 | vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); |
236 | WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); |
236 | WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); |
237 | } |
237 | } |
238 | 238 | ||
239 | args.ucCRTC = radeon_crtc->crtc_id; |
239 | args.ucCRTC = radeon_crtc->crtc_id; |
240 | args.ucBlanking = state; |
240 | args.ucBlanking = state; |
241 | 241 | ||
242 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
242 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
243 | 243 | ||
244 | if (ASIC_IS_DCE8(rdev)) { |
244 | if (ASIC_IS_DCE8(rdev)) { |
245 | WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); |
245 | WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); |
246 | } |
246 | } |
247 | } |
247 | } |
248 | 248 | ||
249 | static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) |
249 | static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) |
250 | { |
250 | { |
251 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
251 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
252 | struct drm_device *dev = crtc->dev; |
252 | struct drm_device *dev = crtc->dev; |
253 | struct radeon_device *rdev = dev->dev_private; |
253 | struct radeon_device *rdev = dev->dev_private; |
254 | int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); |
254 | int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); |
255 | ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; |
255 | ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; |
256 | 256 | ||
257 | memset(&args, 0, sizeof(args)); |
257 | memset(&args, 0, sizeof(args)); |
258 | 258 | ||
259 | args.ucDispPipeId = radeon_crtc->crtc_id; |
259 | args.ucDispPipeId = radeon_crtc->crtc_id; |
260 | args.ucEnable = state; |
260 | args.ucEnable = state; |
261 | 261 | ||
262 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
262 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
263 | } |
263 | } |
264 | 264 | ||
265 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
265 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
266 | { |
266 | { |
267 | struct drm_device *dev = crtc->dev; |
267 | struct drm_device *dev = crtc->dev; |
268 | struct radeon_device *rdev = dev->dev_private; |
268 | struct radeon_device *rdev = dev->dev_private; |
269 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
269 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
270 | 270 | ||
271 | switch (mode) { |
271 | switch (mode) { |
272 | case DRM_MODE_DPMS_ON: |
272 | case DRM_MODE_DPMS_ON: |
273 | radeon_crtc->enabled = true; |
273 | radeon_crtc->enabled = true; |
274 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
274 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
275 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
275 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
276 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
276 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
277 | atombios_blank_crtc(crtc, ATOM_DISABLE); |
277 | atombios_blank_crtc(crtc, ATOM_DISABLE); |
- | 278 | if (dev->num_crtcs > radeon_crtc->crtc_id) |
|
278 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
279 | drm_vblank_on(dev, radeon_crtc->crtc_id); |
279 | radeon_crtc_load_lut(crtc); |
280 | radeon_crtc_load_lut(crtc); |
280 | break; |
281 | break; |
281 | case DRM_MODE_DPMS_STANDBY: |
282 | case DRM_MODE_DPMS_STANDBY: |
282 | case DRM_MODE_DPMS_SUSPEND: |
283 | case DRM_MODE_DPMS_SUSPEND: |
283 | case DRM_MODE_DPMS_OFF: |
284 | case DRM_MODE_DPMS_OFF: |
- | 285 | if (dev->num_crtcs > radeon_crtc->crtc_id) |
|
284 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
286 | drm_vblank_off(dev, radeon_crtc->crtc_id); |
285 | if (radeon_crtc->enabled) |
287 | if (radeon_crtc->enabled) |
286 | atombios_blank_crtc(crtc, ATOM_ENABLE); |
288 | atombios_blank_crtc(crtc, ATOM_ENABLE); |
287 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
289 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
288 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
290 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
289 | atombios_enable_crtc(crtc, ATOM_DISABLE); |
291 | atombios_enable_crtc(crtc, ATOM_DISABLE); |
290 | radeon_crtc->enabled = false; |
292 | radeon_crtc->enabled = false; |
291 | break; |
293 | break; |
292 | } |
294 | } |
293 | /* adjust pm to dpms */ |
295 | /* adjust pm to dpms */ |
294 | radeon_pm_compute_clocks(rdev); |
296 | radeon_pm_compute_clocks(rdev); |
295 | } |
297 | } |
296 | 298 | ||
297 | static void |
299 | static void |
298 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
300 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
299 | struct drm_display_mode *mode) |
301 | struct drm_display_mode *mode) |
300 | { |
302 | { |
301 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
303 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
302 | struct drm_device *dev = crtc->dev; |
304 | struct drm_device *dev = crtc->dev; |
303 | struct radeon_device *rdev = dev->dev_private; |
305 | struct radeon_device *rdev = dev->dev_private; |
304 | SET_CRTC_USING_DTD_TIMING_PARAMETERS args; |
306 | SET_CRTC_USING_DTD_TIMING_PARAMETERS args; |
305 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
307 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
306 | u16 misc = 0; |
308 | u16 misc = 0; |
307 | 309 | ||
308 | memset(&args, 0, sizeof(args)); |
310 | memset(&args, 0, sizeof(args)); |
309 | args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); |
311 | args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); |
310 | args.usH_Blanking_Time = |
312 | args.usH_Blanking_Time = |
311 | cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); |
313 | cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); |
312 | args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); |
314 | args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); |
313 | args.usV_Blanking_Time = |
315 | args.usV_Blanking_Time = |
314 | cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); |
316 | cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); |
315 | args.usH_SyncOffset = |
317 | args.usH_SyncOffset = |
316 | cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); |
318 | cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); |
317 | args.usH_SyncWidth = |
319 | args.usH_SyncWidth = |
318 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
320 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
319 | args.usV_SyncOffset = |
321 | args.usV_SyncOffset = |
320 | cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); |
322 | cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); |
321 | args.usV_SyncWidth = |
323 | args.usV_SyncWidth = |
322 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
324 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
323 | args.ucH_Border = radeon_crtc->h_border; |
325 | args.ucH_Border = radeon_crtc->h_border; |
324 | args.ucV_Border = radeon_crtc->v_border; |
326 | args.ucV_Border = radeon_crtc->v_border; |
325 | 327 | ||
326 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
328 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
327 | misc |= ATOM_VSYNC_POLARITY; |
329 | misc |= ATOM_VSYNC_POLARITY; |
328 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
330 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
329 | misc |= ATOM_HSYNC_POLARITY; |
331 | misc |= ATOM_HSYNC_POLARITY; |
330 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
332 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
331 | misc |= ATOM_COMPOSITESYNC; |
333 | misc |= ATOM_COMPOSITESYNC; |
332 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
334 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
333 | misc |= ATOM_INTERLACE; |
335 | misc |= ATOM_INTERLACE; |
334 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
336 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
335 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
337 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
336 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
338 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
337 | misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; |
339 | misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; |
338 | 340 | ||
339 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
341 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
340 | args.ucCRTC = radeon_crtc->crtc_id; |
342 | args.ucCRTC = radeon_crtc->crtc_id; |
341 | 343 | ||
342 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
344 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
343 | } |
345 | } |
344 | 346 | ||
345 | static void atombios_crtc_set_timing(struct drm_crtc *crtc, |
347 | static void atombios_crtc_set_timing(struct drm_crtc *crtc, |
346 | struct drm_display_mode *mode) |
348 | struct drm_display_mode *mode) |
347 | { |
349 | { |
348 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
350 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
349 | struct drm_device *dev = crtc->dev; |
351 | struct drm_device *dev = crtc->dev; |
350 | struct radeon_device *rdev = dev->dev_private; |
352 | struct radeon_device *rdev = dev->dev_private; |
351 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; |
353 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; |
352 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
354 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
353 | u16 misc = 0; |
355 | u16 misc = 0; |
354 | 356 | ||
355 | memset(&args, 0, sizeof(args)); |
357 | memset(&args, 0, sizeof(args)); |
356 | args.usH_Total = cpu_to_le16(mode->crtc_htotal); |
358 | args.usH_Total = cpu_to_le16(mode->crtc_htotal); |
357 | args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); |
359 | args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); |
358 | args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); |
360 | args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); |
359 | args.usH_SyncWidth = |
361 | args.usH_SyncWidth = |
360 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
362 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
361 | args.usV_Total = cpu_to_le16(mode->crtc_vtotal); |
363 | args.usV_Total = cpu_to_le16(mode->crtc_vtotal); |
362 | args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); |
364 | args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); |
363 | args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); |
365 | args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); |
364 | args.usV_SyncWidth = |
366 | args.usV_SyncWidth = |
365 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
367 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
366 | 368 | ||
367 | args.ucOverscanRight = radeon_crtc->h_border; |
369 | args.ucOverscanRight = radeon_crtc->h_border; |
368 | args.ucOverscanLeft = radeon_crtc->h_border; |
370 | args.ucOverscanLeft = radeon_crtc->h_border; |
369 | args.ucOverscanBottom = radeon_crtc->v_border; |
371 | args.ucOverscanBottom = radeon_crtc->v_border; |
370 | args.ucOverscanTop = radeon_crtc->v_border; |
372 | args.ucOverscanTop = radeon_crtc->v_border; |
371 | 373 | ||
372 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
374 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
373 | misc |= ATOM_VSYNC_POLARITY; |
375 | misc |= ATOM_VSYNC_POLARITY; |
374 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
376 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
375 | misc |= ATOM_HSYNC_POLARITY; |
377 | misc |= ATOM_HSYNC_POLARITY; |
376 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
378 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
377 | misc |= ATOM_COMPOSITESYNC; |
379 | misc |= ATOM_COMPOSITESYNC; |
378 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
380 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
379 | misc |= ATOM_INTERLACE; |
381 | misc |= ATOM_INTERLACE; |
380 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
382 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
381 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
383 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
382 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
384 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
383 | misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; |
385 | misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; |
384 | 386 | ||
385 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
387 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
386 | args.ucCRTC = radeon_crtc->crtc_id; |
388 | args.ucCRTC = radeon_crtc->crtc_id; |
387 | 389 | ||
388 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
390 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
389 | } |
391 | } |
390 | 392 | ||
391 | static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) |
393 | static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) |
392 | { |
394 | { |
393 | u32 ss_cntl; |
395 | u32 ss_cntl; |
394 | 396 | ||
395 | if (ASIC_IS_DCE4(rdev)) { |
397 | if (ASIC_IS_DCE4(rdev)) { |
396 | switch (pll_id) { |
398 | switch (pll_id) { |
397 | case ATOM_PPLL1: |
399 | case ATOM_PPLL1: |
398 | ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); |
400 | ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); |
399 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
401 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
400 | WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); |
402 | WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); |
401 | break; |
403 | break; |
402 | case ATOM_PPLL2: |
404 | case ATOM_PPLL2: |
403 | ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); |
405 | ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); |
404 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
406 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
405 | WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); |
407 | WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); |
406 | break; |
408 | break; |
407 | case ATOM_DCPLL: |
409 | case ATOM_DCPLL: |
408 | case ATOM_PPLL_INVALID: |
410 | case ATOM_PPLL_INVALID: |
409 | return; |
411 | return; |
410 | } |
412 | } |
411 | } else if (ASIC_IS_AVIVO(rdev)) { |
413 | } else if (ASIC_IS_AVIVO(rdev)) { |
412 | switch (pll_id) { |
414 | switch (pll_id) { |
413 | case ATOM_PPLL1: |
415 | case ATOM_PPLL1: |
414 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); |
416 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); |
415 | ss_cntl &= ~1; |
417 | ss_cntl &= ~1; |
416 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); |
418 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); |
417 | break; |
419 | break; |
418 | case ATOM_PPLL2: |
420 | case ATOM_PPLL2: |
419 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); |
421 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); |
420 | ss_cntl &= ~1; |
422 | ss_cntl &= ~1; |
421 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); |
423 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); |
422 | break; |
424 | break; |
423 | case ATOM_DCPLL: |
425 | case ATOM_DCPLL: |
424 | case ATOM_PPLL_INVALID: |
426 | case ATOM_PPLL_INVALID: |
425 | return; |
427 | return; |
426 | } |
428 | } |
427 | } |
429 | } |
428 | } |
430 | } |
429 | 431 | ||
430 | 432 | ||
431 | union atom_enable_ss { |
433 | union atom_enable_ss { |
432 | ENABLE_LVDS_SS_PARAMETERS lvds_ss; |
434 | ENABLE_LVDS_SS_PARAMETERS lvds_ss; |
433 | ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; |
435 | ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; |
434 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; |
436 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; |
435 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; |
437 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; |
436 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; |
438 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; |
437 | }; |
439 | }; |
438 | 440 | ||
439 | static void atombios_crtc_program_ss(struct radeon_device *rdev, |
441 | static void atombios_crtc_program_ss(struct radeon_device *rdev, |
440 | int enable, |
442 | int enable, |
441 | int pll_id, |
443 | int pll_id, |
442 | int crtc_id, |
444 | int crtc_id, |
443 | struct radeon_atom_ss *ss) |
445 | struct radeon_atom_ss *ss) |
444 | { |
446 | { |
445 | unsigned i; |
447 | unsigned i; |
446 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
448 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
447 | union atom_enable_ss args; |
449 | union atom_enable_ss args; |
448 | 450 | ||
449 | if (enable) { |
451 | if (enable) { |
450 | /* Don't mess with SS if percentage is 0 or external ss. |
452 | /* Don't mess with SS if percentage is 0 or external ss. |
451 | * SS is already disabled previously, and disabling it |
453 | * SS is already disabled previously, and disabling it |
452 | * again can cause display problems if the pll is already |
454 | * again can cause display problems if the pll is already |
453 | * programmed. |
455 | * programmed. |
454 | */ |
456 | */ |
455 | if (ss->percentage == 0) |
457 | if (ss->percentage == 0) |
456 | return; |
458 | return; |
457 | if (ss->type & ATOM_EXTERNAL_SS_MASK) |
459 | if (ss->type & ATOM_EXTERNAL_SS_MASK) |
458 | return; |
460 | return; |
459 | } else { |
461 | } else { |
460 | for (i = 0; i < rdev->num_crtc; i++) { |
462 | for (i = 0; i < rdev->num_crtc; i++) { |
461 | if (rdev->mode_info.crtcs[i] && |
463 | if (rdev->mode_info.crtcs[i] && |
462 | rdev->mode_info.crtcs[i]->enabled && |
464 | rdev->mode_info.crtcs[i]->enabled && |
463 | i != crtc_id && |
465 | i != crtc_id && |
464 | pll_id == rdev->mode_info.crtcs[i]->pll_id) { |
466 | pll_id == rdev->mode_info.crtcs[i]->pll_id) { |
465 | /* one other crtc is using this pll don't turn |
467 | /* one other crtc is using this pll don't turn |
466 | * off spread spectrum as it might turn off |
468 | * off spread spectrum as it might turn off |
467 | * display on active crtc |
469 | * display on active crtc |
468 | */ |
470 | */ |
469 | return; |
471 | return; |
470 | } |
472 | } |
471 | } |
473 | } |
472 | } |
474 | } |
473 | 475 | ||
474 | memset(&args, 0, sizeof(args)); |
476 | memset(&args, 0, sizeof(args)); |
475 | 477 | ||
476 | if (ASIC_IS_DCE5(rdev)) { |
478 | if (ASIC_IS_DCE5(rdev)) { |
477 | args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); |
479 | args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); |
478 | args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
480 | args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
479 | switch (pll_id) { |
481 | switch (pll_id) { |
480 | case ATOM_PPLL1: |
482 | case ATOM_PPLL1: |
481 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; |
483 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; |
482 | break; |
484 | break; |
483 | case ATOM_PPLL2: |
485 | case ATOM_PPLL2: |
484 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; |
486 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; |
485 | break; |
487 | break; |
486 | case ATOM_DCPLL: |
488 | case ATOM_DCPLL: |
487 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; |
489 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; |
488 | break; |
490 | break; |
489 | case ATOM_PPLL_INVALID: |
491 | case ATOM_PPLL_INVALID: |
490 | return; |
492 | return; |
491 | } |
493 | } |
492 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
494 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
493 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
495 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
494 | args.v3.ucEnable = enable; |
496 | args.v3.ucEnable = enable; |
495 | } else if (ASIC_IS_DCE4(rdev)) { |
497 | } else if (ASIC_IS_DCE4(rdev)) { |
496 | args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
498 | args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
497 | args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
499 | args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
498 | switch (pll_id) { |
500 | switch (pll_id) { |
499 | case ATOM_PPLL1: |
501 | case ATOM_PPLL1: |
500 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; |
502 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; |
501 | break; |
503 | break; |
502 | case ATOM_PPLL2: |
504 | case ATOM_PPLL2: |
503 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; |
505 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; |
504 | break; |
506 | break; |
505 | case ATOM_DCPLL: |
507 | case ATOM_DCPLL: |
506 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; |
508 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; |
507 | break; |
509 | break; |
508 | case ATOM_PPLL_INVALID: |
510 | case ATOM_PPLL_INVALID: |
509 | return; |
511 | return; |
510 | } |
512 | } |
511 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
513 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
512 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
514 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
513 | args.v2.ucEnable = enable; |
515 | args.v2.ucEnable = enable; |
514 | } else if (ASIC_IS_DCE3(rdev)) { |
516 | } else if (ASIC_IS_DCE3(rdev)) { |
515 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
517 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
516 | args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
518 | args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
517 | args.v1.ucSpreadSpectrumStep = ss->step; |
519 | args.v1.ucSpreadSpectrumStep = ss->step; |
518 | args.v1.ucSpreadSpectrumDelay = ss->delay; |
520 | args.v1.ucSpreadSpectrumDelay = ss->delay; |
519 | args.v1.ucSpreadSpectrumRange = ss->range; |
521 | args.v1.ucSpreadSpectrumRange = ss->range; |
520 | args.v1.ucPpll = pll_id; |
522 | args.v1.ucPpll = pll_id; |
521 | args.v1.ucEnable = enable; |
523 | args.v1.ucEnable = enable; |
522 | } else if (ASIC_IS_AVIVO(rdev)) { |
524 | } else if (ASIC_IS_AVIVO(rdev)) { |
523 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
525 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
524 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { |
526 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { |
525 | atombios_disable_ss(rdev, pll_id); |
527 | atombios_disable_ss(rdev, pll_id); |
526 | return; |
528 | return; |
527 | } |
529 | } |
528 | args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
530 | args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
529 | args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
531 | args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
530 | args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; |
532 | args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; |
531 | args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; |
533 | args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; |
532 | args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; |
534 | args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; |
533 | args.lvds_ss_2.ucEnable = enable; |
535 | args.lvds_ss_2.ucEnable = enable; |
534 | } else { |
536 | } else { |
535 | if (enable == ATOM_DISABLE) { |
537 | if (enable == ATOM_DISABLE) { |
536 | atombios_disable_ss(rdev, pll_id); |
538 | atombios_disable_ss(rdev, pll_id); |
537 | return; |
539 | return; |
538 | } |
540 | } |
539 | args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
541 | args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
540 | args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
542 | args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
541 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; |
543 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; |
542 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; |
544 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; |
543 | args.lvds_ss.ucEnable = enable; |
545 | args.lvds_ss.ucEnable = enable; |
544 | } |
546 | } |
545 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
547 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
546 | } |
548 | } |
547 | 549 | ||
548 | union adjust_pixel_clock { |
550 | union adjust_pixel_clock { |
549 | ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; |
551 | ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; |
550 | ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; |
552 | ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; |
551 | }; |
553 | }; |
552 | 554 | ||
553 | static u32 atombios_adjust_pll(struct drm_crtc *crtc, |
555 | static u32 atombios_adjust_pll(struct drm_crtc *crtc, |
554 | struct drm_display_mode *mode) |
556 | struct drm_display_mode *mode) |
555 | { |
557 | { |
556 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
558 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
557 | struct drm_device *dev = crtc->dev; |
559 | struct drm_device *dev = crtc->dev; |
558 | struct radeon_device *rdev = dev->dev_private; |
560 | struct radeon_device *rdev = dev->dev_private; |
559 | struct drm_encoder *encoder = radeon_crtc->encoder; |
561 | struct drm_encoder *encoder = radeon_crtc->encoder; |
560 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
562 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
561 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
563 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
562 | u32 adjusted_clock = mode->clock; |
564 | u32 adjusted_clock = mode->clock; |
563 | int encoder_mode = atombios_get_encoder_mode(encoder); |
565 | int encoder_mode = atombios_get_encoder_mode(encoder); |
564 | u32 dp_clock = mode->clock; |
566 | u32 dp_clock = mode->clock; |
565 | u32 clock = mode->clock; |
567 | u32 clock = mode->clock; |
566 | int bpc = radeon_crtc->bpc; |
568 | int bpc = radeon_crtc->bpc; |
567 | bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); |
569 | bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); |
568 | 570 | ||
569 | /* reset the pll flags */ |
571 | /* reset the pll flags */ |
570 | radeon_crtc->pll_flags = 0; |
572 | radeon_crtc->pll_flags = 0; |
571 | 573 | ||
572 | if (ASIC_IS_AVIVO(rdev)) { |
574 | if (ASIC_IS_AVIVO(rdev)) { |
573 | if ((rdev->family == CHIP_RS600) || |
575 | if ((rdev->family == CHIP_RS600) || |
574 | (rdev->family == CHIP_RS690) || |
576 | (rdev->family == CHIP_RS690) || |
575 | (rdev->family == CHIP_RS740)) |
577 | (rdev->family == CHIP_RS740)) |
576 | radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ |
578 | radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ |
577 | RADEON_PLL_PREFER_CLOSEST_LOWER); |
579 | RADEON_PLL_PREFER_CLOSEST_LOWER); |
578 | 580 | ||
579 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
581 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
580 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
582 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
581 | else |
583 | else |
582 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
584 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
583 | 585 | ||
584 | if (rdev->family < CHIP_RV770) |
586 | if (rdev->family < CHIP_RV770) |
585 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; |
587 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; |
586 | /* use frac fb div on APUs */ |
588 | /* use frac fb div on APUs */ |
587 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) |
589 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) |
588 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
590 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
589 | /* use frac fb div on RS780/RS880 */ |
591 | /* use frac fb div on RS780/RS880 */ |
590 | if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) |
592 | if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) |
591 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
593 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
592 | if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) |
594 | if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) |
593 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
595 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
594 | } else { |
596 | } else { |
595 | radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; |
597 | radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; |
596 | 598 | ||
597 | if (mode->clock > 200000) /* range limits??? */ |
599 | if (mode->clock > 200000) /* range limits??? */ |
598 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
600 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
599 | else |
601 | else |
600 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
602 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
601 | } |
603 | } |
602 | 604 | ||
603 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
605 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
604 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { |
606 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { |
605 | if (connector) { |
607 | if (connector) { |
606 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
608 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
607 | struct radeon_connector_atom_dig *dig_connector = |
609 | struct radeon_connector_atom_dig *dig_connector = |
608 | radeon_connector->con_priv; |
610 | radeon_connector->con_priv; |
609 | 611 | ||
610 | dp_clock = dig_connector->dp_clock; |
612 | dp_clock = dig_connector->dp_clock; |
611 | } |
613 | } |
612 | } |
614 | } |
613 | 615 | ||
614 | if (radeon_encoder->is_mst_encoder) { |
616 | if (radeon_encoder->is_mst_encoder) { |
615 | struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; |
617 | struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; |
616 | struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; |
618 | struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; |
617 | 619 | ||
618 | dp_clock = dig_connector->dp_clock; |
620 | dp_clock = dig_connector->dp_clock; |
619 | } |
621 | } |
620 | 622 | ||
621 | /* use recommended ref_div for ss */ |
623 | /* use recommended ref_div for ss */ |
622 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
624 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
623 | if (radeon_crtc->ss_enabled) { |
625 | if (radeon_crtc->ss_enabled) { |
624 | if (radeon_crtc->ss.refdiv) { |
626 | if (radeon_crtc->ss.refdiv) { |
625 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
627 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
626 | radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; |
628 | radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; |
627 | if (ASIC_IS_AVIVO(rdev)) |
629 | if (ASIC_IS_AVIVO(rdev)) |
628 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
630 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
629 | } |
631 | } |
630 | } |
632 | } |
631 | } |
633 | } |
632 | 634 | ||
633 | if (ASIC_IS_AVIVO(rdev)) { |
635 | if (ASIC_IS_AVIVO(rdev)) { |
634 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ |
636 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ |
635 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) |
637 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) |
636 | adjusted_clock = mode->clock * 2; |
638 | adjusted_clock = mode->clock * 2; |
637 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
639 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
638 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; |
640 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; |
639 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
641 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
640 | radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; |
642 | radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; |
641 | } else { |
643 | } else { |
642 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
644 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
643 | radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
645 | radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
644 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
646 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
645 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
647 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
646 | } |
648 | } |
647 | 649 | ||
648 | /* adjust pll for deep color modes */ |
650 | /* adjust pll for deep color modes */ |
649 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { |
651 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { |
650 | switch (bpc) { |
652 | switch (bpc) { |
651 | case 8: |
653 | case 8: |
652 | default: |
654 | default: |
653 | break; |
655 | break; |
654 | case 10: |
656 | case 10: |
655 | clock = (clock * 5) / 4; |
657 | clock = (clock * 5) / 4; |
656 | break; |
658 | break; |
657 | case 12: |
659 | case 12: |
658 | clock = (clock * 3) / 2; |
660 | clock = (clock * 3) / 2; |
659 | break; |
661 | break; |
660 | case 16: |
662 | case 16: |
661 | clock = clock * 2; |
663 | clock = clock * 2; |
662 | break; |
664 | break; |
663 | } |
665 | } |
664 | } |
666 | } |
665 | 667 | ||
666 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
668 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
667 | * accordingly based on the encoder/transmitter to work around |
669 | * accordingly based on the encoder/transmitter to work around |
668 | * special hw requirements. |
670 | * special hw requirements. |
669 | */ |
671 | */ |
670 | if (ASIC_IS_DCE3(rdev)) { |
672 | if (ASIC_IS_DCE3(rdev)) { |
671 | union adjust_pixel_clock args; |
673 | union adjust_pixel_clock args; |
672 | u8 frev, crev; |
674 | u8 frev, crev; |
673 | int index; |
675 | int index; |
674 | 676 | ||
675 | index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); |
677 | index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); |
676 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
678 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
677 | &crev)) |
679 | &crev)) |
678 | return adjusted_clock; |
680 | return adjusted_clock; |
679 | 681 | ||
680 | memset(&args, 0, sizeof(args)); |
682 | memset(&args, 0, sizeof(args)); |
681 | 683 | ||
682 | switch (frev) { |
684 | switch (frev) { |
683 | case 1: |
685 | case 1: |
684 | switch (crev) { |
686 | switch (crev) { |
685 | case 1: |
687 | case 1: |
686 | case 2: |
688 | case 2: |
687 | args.v1.usPixelClock = cpu_to_le16(clock / 10); |
689 | args.v1.usPixelClock = cpu_to_le16(clock / 10); |
688 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; |
690 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; |
689 | args.v1.ucEncodeMode = encoder_mode; |
691 | args.v1.ucEncodeMode = encoder_mode; |
690 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
692 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
691 | args.v1.ucConfig |= |
693 | args.v1.ucConfig |= |
692 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; |
694 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; |
693 | 695 | ||
694 | atom_execute_table(rdev->mode_info.atom_context, |
696 | atom_execute_table(rdev->mode_info.atom_context, |
695 | index, (uint32_t *)&args); |
697 | index, (uint32_t *)&args); |
696 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; |
698 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; |
697 | break; |
699 | break; |
698 | case 3: |
700 | case 3: |
699 | args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); |
701 | args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); |
700 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; |
702 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; |
701 | args.v3.sInput.ucEncodeMode = encoder_mode; |
703 | args.v3.sInput.ucEncodeMode = encoder_mode; |
702 | args.v3.sInput.ucDispPllConfig = 0; |
704 | args.v3.sInput.ucDispPllConfig = 0; |
703 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
705 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
704 | args.v3.sInput.ucDispPllConfig |= |
706 | args.v3.sInput.ucDispPllConfig |= |
705 | DISPPLL_CONFIG_SS_ENABLE; |
707 | DISPPLL_CONFIG_SS_ENABLE; |
706 | if (ENCODER_MODE_IS_DP(encoder_mode)) { |
708 | if (ENCODER_MODE_IS_DP(encoder_mode)) { |
707 | args.v3.sInput.ucDispPllConfig |= |
709 | args.v3.sInput.ucDispPllConfig |= |
708 | DISPPLL_CONFIG_COHERENT_MODE; |
710 | DISPPLL_CONFIG_COHERENT_MODE; |
709 | /* 16200 or 27000 */ |
711 | /* 16200 or 27000 */ |
710 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); |
712 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); |
711 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
713 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
712 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
714 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
713 | if (dig->coherent_mode) |
715 | if (dig->coherent_mode) |
714 | args.v3.sInput.ucDispPllConfig |= |
716 | args.v3.sInput.ucDispPllConfig |= |
715 | DISPPLL_CONFIG_COHERENT_MODE; |
717 | DISPPLL_CONFIG_COHERENT_MODE; |
716 | if (is_duallink) |
718 | if (is_duallink) |
717 | args.v3.sInput.ucDispPllConfig |= |
719 | args.v3.sInput.ucDispPllConfig |= |
718 | DISPPLL_CONFIG_DUAL_LINK; |
720 | DISPPLL_CONFIG_DUAL_LINK; |
719 | } |
721 | } |
720 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != |
722 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != |
721 | ENCODER_OBJECT_ID_NONE) |
723 | ENCODER_OBJECT_ID_NONE) |
722 | args.v3.sInput.ucExtTransmitterID = |
724 | args.v3.sInput.ucExtTransmitterID = |
723 | radeon_encoder_get_dp_bridge_encoder_id(encoder); |
725 | radeon_encoder_get_dp_bridge_encoder_id(encoder); |
724 | else |
726 | else |
725 | args.v3.sInput.ucExtTransmitterID = 0; |
727 | args.v3.sInput.ucExtTransmitterID = 0; |
726 | 728 | ||
727 | atom_execute_table(rdev->mode_info.atom_context, |
729 | atom_execute_table(rdev->mode_info.atom_context, |
728 | index, (uint32_t *)&args); |
730 | index, (uint32_t *)&args); |
729 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; |
731 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; |
730 | if (args.v3.sOutput.ucRefDiv) { |
732 | if (args.v3.sOutput.ucRefDiv) { |
731 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
733 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
732 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
734 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
733 | radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; |
735 | radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; |
734 | } |
736 | } |
735 | if (args.v3.sOutput.ucPostDiv) { |
737 | if (args.v3.sOutput.ucPostDiv) { |
736 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
738 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
737 | radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; |
739 | radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; |
738 | radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; |
740 | radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; |
739 | } |
741 | } |
740 | break; |
742 | break; |
741 | default: |
743 | default: |
742 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
744 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
743 | return adjusted_clock; |
745 | return adjusted_clock; |
744 | } |
746 | } |
745 | break; |
747 | break; |
746 | default: |
748 | default: |
747 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
749 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
748 | return adjusted_clock; |
750 | return adjusted_clock; |
749 | } |
751 | } |
750 | } |
752 | } |
751 | return adjusted_clock; |
753 | return adjusted_clock; |
752 | } |
754 | } |
753 | 755 | ||
754 | union set_pixel_clock { |
756 | union set_pixel_clock { |
755 | SET_PIXEL_CLOCK_PS_ALLOCATION base; |
757 | SET_PIXEL_CLOCK_PS_ALLOCATION base; |
756 | PIXEL_CLOCK_PARAMETERS v1; |
758 | PIXEL_CLOCK_PARAMETERS v1; |
757 | PIXEL_CLOCK_PARAMETERS_V2 v2; |
759 | PIXEL_CLOCK_PARAMETERS_V2 v2; |
758 | PIXEL_CLOCK_PARAMETERS_V3 v3; |
760 | PIXEL_CLOCK_PARAMETERS_V3 v3; |
759 | PIXEL_CLOCK_PARAMETERS_V5 v5; |
761 | PIXEL_CLOCK_PARAMETERS_V5 v5; |
760 | PIXEL_CLOCK_PARAMETERS_V6 v6; |
762 | PIXEL_CLOCK_PARAMETERS_V6 v6; |
761 | }; |
763 | }; |
762 | 764 | ||
763 | /* on DCE5, make sure the voltage is high enough to support the |
765 | /* on DCE5, make sure the voltage is high enough to support the |
764 | * required disp clk. |
766 | * required disp clk. |
765 | */ |
767 | */ |
766 | static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, |
768 | static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, |
767 | u32 dispclk) |
769 | u32 dispclk) |
768 | { |
770 | { |
769 | u8 frev, crev; |
771 | u8 frev, crev; |
770 | int index; |
772 | int index; |
771 | union set_pixel_clock args; |
773 | union set_pixel_clock args; |
772 | 774 | ||
773 | memset(&args, 0, sizeof(args)); |
775 | memset(&args, 0, sizeof(args)); |
774 | 776 | ||
775 | index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
777 | index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
776 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
778 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
777 | &crev)) |
779 | &crev)) |
778 | return; |
780 | return; |
779 | 781 | ||
780 | switch (frev) { |
782 | switch (frev) { |
781 | case 1: |
783 | case 1: |
782 | switch (crev) { |
784 | switch (crev) { |
783 | case 5: |
785 | case 5: |
784 | /* if the default dcpll clock is specified, |
786 | /* if the default dcpll clock is specified, |
785 | * SetPixelClock provides the dividers |
787 | * SetPixelClock provides the dividers |
786 | */ |
788 | */ |
787 | args.v5.ucCRTC = ATOM_CRTC_INVALID; |
789 | args.v5.ucCRTC = ATOM_CRTC_INVALID; |
788 | args.v5.usPixelClock = cpu_to_le16(dispclk); |
790 | args.v5.usPixelClock = cpu_to_le16(dispclk); |
789 | args.v5.ucPpll = ATOM_DCPLL; |
791 | args.v5.ucPpll = ATOM_DCPLL; |
790 | break; |
792 | break; |
791 | case 6: |
793 | case 6: |
792 | /* if the default dcpll clock is specified, |
794 | /* if the default dcpll clock is specified, |
793 | * SetPixelClock provides the dividers |
795 | * SetPixelClock provides the dividers |
794 | */ |
796 | */ |
795 | args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); |
797 | args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); |
796 | if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) |
798 | if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) |
797 | args.v6.ucPpll = ATOM_EXT_PLL1; |
799 | args.v6.ucPpll = ATOM_EXT_PLL1; |
798 | else if (ASIC_IS_DCE6(rdev)) |
800 | else if (ASIC_IS_DCE6(rdev)) |
799 | args.v6.ucPpll = ATOM_PPLL0; |
801 | args.v6.ucPpll = ATOM_PPLL0; |
800 | else |
802 | else |
801 | args.v6.ucPpll = ATOM_DCPLL; |
803 | args.v6.ucPpll = ATOM_DCPLL; |
802 | break; |
804 | break; |
803 | default: |
805 | default: |
804 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
806 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
805 | return; |
807 | return; |
806 | } |
808 | } |
807 | break; |
809 | break; |
808 | default: |
810 | default: |
809 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
811 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
810 | return; |
812 | return; |
811 | } |
813 | } |
812 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
814 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
813 | } |
815 | } |
814 | 816 | ||
815 | static void atombios_crtc_program_pll(struct drm_crtc *crtc, |
817 | static void atombios_crtc_program_pll(struct drm_crtc *crtc, |
816 | u32 crtc_id, |
818 | u32 crtc_id, |
817 | int pll_id, |
819 | int pll_id, |
818 | u32 encoder_mode, |
820 | u32 encoder_mode, |
819 | u32 encoder_id, |
821 | u32 encoder_id, |
820 | u32 clock, |
822 | u32 clock, |
821 | u32 ref_div, |
823 | u32 ref_div, |
822 | u32 fb_div, |
824 | u32 fb_div, |
823 | u32 frac_fb_div, |
825 | u32 frac_fb_div, |
824 | u32 post_div, |
826 | u32 post_div, |
825 | int bpc, |
827 | int bpc, |
826 | bool ss_enabled, |
828 | bool ss_enabled, |
827 | struct radeon_atom_ss *ss) |
829 | struct radeon_atom_ss *ss) |
828 | { |
830 | { |
829 | struct drm_device *dev = crtc->dev; |
831 | struct drm_device *dev = crtc->dev; |
830 | struct radeon_device *rdev = dev->dev_private; |
832 | struct radeon_device *rdev = dev->dev_private; |
831 | u8 frev, crev; |
833 | u8 frev, crev; |
832 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
834 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
833 | union set_pixel_clock args; |
835 | union set_pixel_clock args; |
834 | 836 | ||
835 | memset(&args, 0, sizeof(args)); |
837 | memset(&args, 0, sizeof(args)); |
836 | 838 | ||
837 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
839 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
838 | &crev)) |
840 | &crev)) |
839 | return; |
841 | return; |
840 | 842 | ||
841 | switch (frev) { |
843 | switch (frev) { |
842 | case 1: |
844 | case 1: |
843 | switch (crev) { |
845 | switch (crev) { |
844 | case 1: |
846 | case 1: |
845 | if (clock == ATOM_DISABLE) |
847 | if (clock == ATOM_DISABLE) |
846 | return; |
848 | return; |
847 | args.v1.usPixelClock = cpu_to_le16(clock / 10); |
849 | args.v1.usPixelClock = cpu_to_le16(clock / 10); |
848 | args.v1.usRefDiv = cpu_to_le16(ref_div); |
850 | args.v1.usRefDiv = cpu_to_le16(ref_div); |
849 | args.v1.usFbDiv = cpu_to_le16(fb_div); |
851 | args.v1.usFbDiv = cpu_to_le16(fb_div); |
850 | args.v1.ucFracFbDiv = frac_fb_div; |
852 | args.v1.ucFracFbDiv = frac_fb_div; |
851 | args.v1.ucPostDiv = post_div; |
853 | args.v1.ucPostDiv = post_div; |
852 | args.v1.ucPpll = pll_id; |
854 | args.v1.ucPpll = pll_id; |
853 | args.v1.ucCRTC = crtc_id; |
855 | args.v1.ucCRTC = crtc_id; |
854 | args.v1.ucRefDivSrc = 1; |
856 | args.v1.ucRefDivSrc = 1; |
855 | break; |
857 | break; |
856 | case 2: |
858 | case 2: |
857 | args.v2.usPixelClock = cpu_to_le16(clock / 10); |
859 | args.v2.usPixelClock = cpu_to_le16(clock / 10); |
858 | args.v2.usRefDiv = cpu_to_le16(ref_div); |
860 | args.v2.usRefDiv = cpu_to_le16(ref_div); |
859 | args.v2.usFbDiv = cpu_to_le16(fb_div); |
861 | args.v2.usFbDiv = cpu_to_le16(fb_div); |
860 | args.v2.ucFracFbDiv = frac_fb_div; |
862 | args.v2.ucFracFbDiv = frac_fb_div; |
861 | args.v2.ucPostDiv = post_div; |
863 | args.v2.ucPostDiv = post_div; |
862 | args.v2.ucPpll = pll_id; |
864 | args.v2.ucPpll = pll_id; |
863 | args.v2.ucCRTC = crtc_id; |
865 | args.v2.ucCRTC = crtc_id; |
864 | args.v2.ucRefDivSrc = 1; |
866 | args.v2.ucRefDivSrc = 1; |
865 | break; |
867 | break; |
866 | case 3: |
868 | case 3: |
867 | args.v3.usPixelClock = cpu_to_le16(clock / 10); |
869 | args.v3.usPixelClock = cpu_to_le16(clock / 10); |
868 | args.v3.usRefDiv = cpu_to_le16(ref_div); |
870 | args.v3.usRefDiv = cpu_to_le16(ref_div); |
869 | args.v3.usFbDiv = cpu_to_le16(fb_div); |
871 | args.v3.usFbDiv = cpu_to_le16(fb_div); |
870 | args.v3.ucFracFbDiv = frac_fb_div; |
872 | args.v3.ucFracFbDiv = frac_fb_div; |
871 | args.v3.ucPostDiv = post_div; |
873 | args.v3.ucPostDiv = post_div; |
872 | args.v3.ucPpll = pll_id; |
874 | args.v3.ucPpll = pll_id; |
873 | if (crtc_id == ATOM_CRTC2) |
875 | if (crtc_id == ATOM_CRTC2) |
874 | args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; |
876 | args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; |
875 | else |
877 | else |
876 | args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; |
878 | args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; |
877 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
879 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
878 | args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; |
880 | args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; |
879 | args.v3.ucTransmitterId = encoder_id; |
881 | args.v3.ucTransmitterId = encoder_id; |
880 | args.v3.ucEncoderMode = encoder_mode; |
882 | args.v3.ucEncoderMode = encoder_mode; |
881 | break; |
883 | break; |
882 | case 5: |
884 | case 5: |
883 | args.v5.ucCRTC = crtc_id; |
885 | args.v5.ucCRTC = crtc_id; |
884 | args.v5.usPixelClock = cpu_to_le16(clock / 10); |
886 | args.v5.usPixelClock = cpu_to_le16(clock / 10); |
885 | args.v5.ucRefDiv = ref_div; |
887 | args.v5.ucRefDiv = ref_div; |
886 | args.v5.usFbDiv = cpu_to_le16(fb_div); |
888 | args.v5.usFbDiv = cpu_to_le16(fb_div); |
887 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
889 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
888 | args.v5.ucPostDiv = post_div; |
890 | args.v5.ucPostDiv = post_div; |
889 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ |
891 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ |
890 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
892 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
891 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; |
893 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; |
892 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { |
894 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { |
893 | switch (bpc) { |
895 | switch (bpc) { |
894 | case 8: |
896 | case 8: |
895 | default: |
897 | default: |
896 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; |
898 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; |
897 | break; |
899 | break; |
898 | case 10: |
900 | case 10: |
899 | /* yes this is correct, the atom define is wrong */ |
901 | /* yes this is correct, the atom define is wrong */ |
900 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP; |
902 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP; |
901 | break; |
903 | break; |
902 | case 12: |
904 | case 12: |
903 | /* yes this is correct, the atom define is wrong */ |
905 | /* yes this is correct, the atom define is wrong */ |
904 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; |
906 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; |
905 | break; |
907 | break; |
906 | } |
908 | } |
907 | } |
909 | } |
908 | args.v5.ucTransmitterID = encoder_id; |
910 | args.v5.ucTransmitterID = encoder_id; |
909 | args.v5.ucEncoderMode = encoder_mode; |
911 | args.v5.ucEncoderMode = encoder_mode; |
910 | args.v5.ucPpll = pll_id; |
912 | args.v5.ucPpll = pll_id; |
911 | break; |
913 | break; |
912 | case 6: |
914 | case 6: |
913 | args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); |
915 | args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); |
914 | args.v6.ucRefDiv = ref_div; |
916 | args.v6.ucRefDiv = ref_div; |
915 | args.v6.usFbDiv = cpu_to_le16(fb_div); |
917 | args.v6.usFbDiv = cpu_to_le16(fb_div); |
916 | args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
918 | args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
917 | args.v6.ucPostDiv = post_div; |
919 | args.v6.ucPostDiv = post_div; |
918 | args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ |
920 | args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ |
919 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
921 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
920 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; |
922 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; |
921 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { |
923 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { |
922 | switch (bpc) { |
924 | switch (bpc) { |
923 | case 8: |
925 | case 8: |
924 | default: |
926 | default: |
925 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; |
927 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; |
926 | break; |
928 | break; |
927 | case 10: |
929 | case 10: |
928 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; |
930 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; |
929 | break; |
931 | break; |
930 | case 12: |
932 | case 12: |
931 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; |
933 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; |
932 | break; |
934 | break; |
933 | case 16: |
935 | case 16: |
934 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; |
936 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; |
935 | break; |
937 | break; |
936 | } |
938 | } |
937 | } |
939 | } |
938 | args.v6.ucTransmitterID = encoder_id; |
940 | args.v6.ucTransmitterID = encoder_id; |
939 | args.v6.ucEncoderMode = encoder_mode; |
941 | args.v6.ucEncoderMode = encoder_mode; |
940 | args.v6.ucPpll = pll_id; |
942 | args.v6.ucPpll = pll_id; |
941 | break; |
943 | break; |
942 | default: |
944 | default: |
943 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
945 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
944 | return; |
946 | return; |
945 | } |
947 | } |
946 | break; |
948 | break; |
947 | default: |
949 | default: |
948 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
950 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
949 | return; |
951 | return; |
950 | } |
952 | } |
951 | 953 | ||
952 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
954 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
953 | } |
955 | } |
954 | 956 | ||
955 | static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
957 | static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
956 | { |
958 | { |
957 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
959 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
958 | struct drm_device *dev = crtc->dev; |
960 | struct drm_device *dev = crtc->dev; |
959 | struct radeon_device *rdev = dev->dev_private; |
961 | struct radeon_device *rdev = dev->dev_private; |
960 | struct radeon_encoder *radeon_encoder = |
962 | struct radeon_encoder *radeon_encoder = |
961 | to_radeon_encoder(radeon_crtc->encoder); |
963 | to_radeon_encoder(radeon_crtc->encoder); |
962 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
964 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
963 | 965 | ||
964 | radeon_crtc->bpc = 8; |
966 | radeon_crtc->bpc = 8; |
965 | radeon_crtc->ss_enabled = false; |
967 | radeon_crtc->ss_enabled = false; |
966 | 968 | ||
967 | if (radeon_encoder->is_mst_encoder) { |
969 | if (radeon_encoder->is_mst_encoder) { |
968 | radeon_dp_mst_prepare_pll(crtc, mode); |
970 | radeon_dp_mst_prepare_pll(crtc, mode); |
969 | } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
971 | } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
970 | (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { |
972 | (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { |
971 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
973 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
972 | struct drm_connector *connector = |
974 | struct drm_connector *connector = |
973 | radeon_get_connector_for_encoder(radeon_crtc->encoder); |
975 | radeon_get_connector_for_encoder(radeon_crtc->encoder); |
974 | struct radeon_connector *radeon_connector = |
976 | struct radeon_connector *radeon_connector = |
975 | to_radeon_connector(connector); |
977 | to_radeon_connector(connector); |
976 | struct radeon_connector_atom_dig *dig_connector = |
978 | struct radeon_connector_atom_dig *dig_connector = |
977 | radeon_connector->con_priv; |
979 | radeon_connector->con_priv; |
978 | int dp_clock; |
980 | int dp_clock; |
979 | 981 | ||
980 | /* Assign mode clock for hdmi deep color max clock limit check */ |
982 | /* Assign mode clock for hdmi deep color max clock limit check */ |
981 | radeon_connector->pixelclock_for_modeset = mode->clock; |
983 | radeon_connector->pixelclock_for_modeset = mode->clock; |
982 | radeon_crtc->bpc = radeon_get_monitor_bpc(connector); |
984 | radeon_crtc->bpc = radeon_get_monitor_bpc(connector); |
983 | 985 | ||
984 | switch (encoder_mode) { |
986 | switch (encoder_mode) { |
985 | case ATOM_ENCODER_MODE_DP_MST: |
987 | case ATOM_ENCODER_MODE_DP_MST: |
986 | case ATOM_ENCODER_MODE_DP: |
988 | case ATOM_ENCODER_MODE_DP: |
987 | /* DP/eDP */ |
989 | /* DP/eDP */ |
988 | dp_clock = dig_connector->dp_clock / 10; |
990 | dp_clock = dig_connector->dp_clock / 10; |
989 | if (ASIC_IS_DCE4(rdev)) |
991 | if (ASIC_IS_DCE4(rdev)) |
990 | radeon_crtc->ss_enabled = |
992 | radeon_crtc->ss_enabled = |
991 | radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, |
993 | radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, |
992 | ASIC_INTERNAL_SS_ON_DP, |
994 | ASIC_INTERNAL_SS_ON_DP, |
993 | dp_clock); |
995 | dp_clock); |
994 | else { |
996 | else { |
995 | if (dp_clock == 16200) { |
997 | if (dp_clock == 16200) { |
996 | radeon_crtc->ss_enabled = |
998 | radeon_crtc->ss_enabled = |
997 | radeon_atombios_get_ppll_ss_info(rdev, |
999 | radeon_atombios_get_ppll_ss_info(rdev, |
998 | &radeon_crtc->ss, |
1000 | &radeon_crtc->ss, |
999 | ATOM_DP_SS_ID2); |
1001 | ATOM_DP_SS_ID2); |
1000 | if (!radeon_crtc->ss_enabled) |
1002 | if (!radeon_crtc->ss_enabled) |
1001 | radeon_crtc->ss_enabled = |
1003 | radeon_crtc->ss_enabled = |
1002 | radeon_atombios_get_ppll_ss_info(rdev, |
1004 | radeon_atombios_get_ppll_ss_info(rdev, |
1003 | &radeon_crtc->ss, |
1005 | &radeon_crtc->ss, |
1004 | ATOM_DP_SS_ID1); |
1006 | ATOM_DP_SS_ID1); |
1005 | } else { |
1007 | } else { |
1006 | radeon_crtc->ss_enabled = |
1008 | radeon_crtc->ss_enabled = |
1007 | radeon_atombios_get_ppll_ss_info(rdev, |
1009 | radeon_atombios_get_ppll_ss_info(rdev, |
1008 | &radeon_crtc->ss, |
1010 | &radeon_crtc->ss, |
1009 | ATOM_DP_SS_ID1); |
1011 | ATOM_DP_SS_ID1); |
1010 | } |
1012 | } |
1011 | /* disable spread spectrum on DCE3 DP */ |
1013 | /* disable spread spectrum on DCE3 DP */ |
1012 | radeon_crtc->ss_enabled = false; |
1014 | radeon_crtc->ss_enabled = false; |
1013 | } |
1015 | } |
1014 | break; |
1016 | break; |
1015 | case ATOM_ENCODER_MODE_LVDS: |
1017 | case ATOM_ENCODER_MODE_LVDS: |
1016 | if (ASIC_IS_DCE4(rdev)) |
1018 | if (ASIC_IS_DCE4(rdev)) |
1017 | radeon_crtc->ss_enabled = |
1019 | radeon_crtc->ss_enabled = |
1018 | radeon_atombios_get_asic_ss_info(rdev, |
1020 | radeon_atombios_get_asic_ss_info(rdev, |
1019 | &radeon_crtc->ss, |
1021 | &radeon_crtc->ss, |
1020 | dig->lcd_ss_id, |
1022 | dig->lcd_ss_id, |
1021 | mode->clock / 10); |
1023 | mode->clock / 10); |
1022 | else |
1024 | else |
1023 | radeon_crtc->ss_enabled = |
1025 | radeon_crtc->ss_enabled = |
1024 | radeon_atombios_get_ppll_ss_info(rdev, |
1026 | radeon_atombios_get_ppll_ss_info(rdev, |
1025 | &radeon_crtc->ss, |
1027 | &radeon_crtc->ss, |
1026 | dig->lcd_ss_id); |
1028 | dig->lcd_ss_id); |
1027 | break; |
1029 | break; |
1028 | case ATOM_ENCODER_MODE_DVI: |
1030 | case ATOM_ENCODER_MODE_DVI: |
1029 | if (ASIC_IS_DCE4(rdev)) |
1031 | if (ASIC_IS_DCE4(rdev)) |
1030 | radeon_crtc->ss_enabled = |
1032 | radeon_crtc->ss_enabled = |
1031 | radeon_atombios_get_asic_ss_info(rdev, |
1033 | radeon_atombios_get_asic_ss_info(rdev, |
1032 | &radeon_crtc->ss, |
1034 | &radeon_crtc->ss, |
1033 | ASIC_INTERNAL_SS_ON_TMDS, |
1035 | ASIC_INTERNAL_SS_ON_TMDS, |
1034 | mode->clock / 10); |
1036 | mode->clock / 10); |
1035 | break; |
1037 | break; |
1036 | case ATOM_ENCODER_MODE_HDMI: |
1038 | case ATOM_ENCODER_MODE_HDMI: |
1037 | if (ASIC_IS_DCE4(rdev)) |
1039 | if (ASIC_IS_DCE4(rdev)) |
1038 | radeon_crtc->ss_enabled = |
1040 | radeon_crtc->ss_enabled = |
1039 | radeon_atombios_get_asic_ss_info(rdev, |
1041 | radeon_atombios_get_asic_ss_info(rdev, |
1040 | &radeon_crtc->ss, |
1042 | &radeon_crtc->ss, |
1041 | ASIC_INTERNAL_SS_ON_HDMI, |
1043 | ASIC_INTERNAL_SS_ON_HDMI, |
1042 | mode->clock / 10); |
1044 | mode->clock / 10); |
1043 | break; |
1045 | break; |
1044 | default: |
1046 | default: |
1045 | break; |
1047 | break; |
1046 | } |
1048 | } |
1047 | } |
1049 | } |
1048 | 1050 | ||
1049 | /* adjust pixel clock as needed */ |
1051 | /* adjust pixel clock as needed */ |
1050 | radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); |
1052 | radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); |
1051 | 1053 | ||
1052 | return true; |
1054 | return true; |
1053 | } |
1055 | } |
1054 | 1056 | ||
1055 | static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
1057 | static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
1056 | { |
1058 | { |
1057 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1059 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1058 | struct drm_device *dev = crtc->dev; |
1060 | struct drm_device *dev = crtc->dev; |
1059 | struct radeon_device *rdev = dev->dev_private; |
1061 | struct radeon_device *rdev = dev->dev_private; |
1060 | struct radeon_encoder *radeon_encoder = |
1062 | struct radeon_encoder *radeon_encoder = |
1061 | to_radeon_encoder(radeon_crtc->encoder); |
1063 | to_radeon_encoder(radeon_crtc->encoder); |
1062 | u32 pll_clock = mode->clock; |
1064 | u32 pll_clock = mode->clock; |
1063 | u32 clock = mode->clock; |
1065 | u32 clock = mode->clock; |
1064 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
1066 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
1065 | struct radeon_pll *pll; |
1067 | struct radeon_pll *pll; |
1066 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
1068 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
1067 | 1069 | ||
1068 | /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */ |
1070 | /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */ |
1069 | if (ASIC_IS_DCE5(rdev) && |
1071 | if (ASIC_IS_DCE5(rdev) && |
1070 | (encoder_mode == ATOM_ENCODER_MODE_HDMI) && |
1072 | (encoder_mode == ATOM_ENCODER_MODE_HDMI) && |
1071 | (radeon_crtc->bpc > 8)) |
1073 | (radeon_crtc->bpc > 8)) |
1072 | clock = radeon_crtc->adjusted_clock; |
1074 | clock = radeon_crtc->adjusted_clock; |
1073 | 1075 | ||
1074 | switch (radeon_crtc->pll_id) { |
1076 | switch (radeon_crtc->pll_id) { |
1075 | case ATOM_PPLL1: |
1077 | case ATOM_PPLL1: |
1076 | pll = &rdev->clock.p1pll; |
1078 | pll = &rdev->clock.p1pll; |
1077 | break; |
1079 | break; |
1078 | case ATOM_PPLL2: |
1080 | case ATOM_PPLL2: |
1079 | pll = &rdev->clock.p2pll; |
1081 | pll = &rdev->clock.p2pll; |
1080 | break; |
1082 | break; |
1081 | case ATOM_DCPLL: |
1083 | case ATOM_DCPLL: |
1082 | case ATOM_PPLL_INVALID: |
1084 | case ATOM_PPLL_INVALID: |
1083 | default: |
1085 | default: |
1084 | pll = &rdev->clock.dcpll; |
1086 | pll = &rdev->clock.dcpll; |
1085 | break; |
1087 | break; |
1086 | } |
1088 | } |
1087 | 1089 | ||
1088 | /* update pll params */ |
1090 | /* update pll params */ |
1089 | pll->flags = radeon_crtc->pll_flags; |
1091 | pll->flags = radeon_crtc->pll_flags; |
1090 | pll->reference_div = radeon_crtc->pll_reference_div; |
1092 | pll->reference_div = radeon_crtc->pll_reference_div; |
1091 | pll->post_div = radeon_crtc->pll_post_div; |
1093 | pll->post_div = radeon_crtc->pll_post_div; |
1092 | 1094 | ||
1093 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1095 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1094 | /* TV seems to prefer the legacy algo on some boards */ |
1096 | /* TV seems to prefer the legacy algo on some boards */ |
1095 | radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1097 | radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1096 | &fb_div, &frac_fb_div, &ref_div, &post_div); |
1098 | &fb_div, &frac_fb_div, &ref_div, &post_div); |
1097 | else if (ASIC_IS_AVIVO(rdev)) |
1099 | else if (ASIC_IS_AVIVO(rdev)) |
1098 | radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1100 | radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1099 | &fb_div, &frac_fb_div, &ref_div, &post_div); |
1101 | &fb_div, &frac_fb_div, &ref_div, &post_div); |
1100 | else |
1102 | else |
1101 | radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1103 | radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1102 | &fb_div, &frac_fb_div, &ref_div, &post_div); |
1104 | &fb_div, &frac_fb_div, &ref_div, &post_div); |
1103 | 1105 | ||
1104 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, |
1106 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, |
1105 | radeon_crtc->crtc_id, &radeon_crtc->ss); |
1107 | radeon_crtc->crtc_id, &radeon_crtc->ss); |
1106 | 1108 | ||
1107 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
1109 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
1108 | encoder_mode, radeon_encoder->encoder_id, clock, |
1110 | encoder_mode, radeon_encoder->encoder_id, clock, |
1109 | ref_div, fb_div, frac_fb_div, post_div, |
1111 | ref_div, fb_div, frac_fb_div, post_div, |
1110 | radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); |
1112 | radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); |
1111 | 1113 | ||
1112 | if (radeon_crtc->ss_enabled) { |
1114 | if (radeon_crtc->ss_enabled) { |
1113 | /* calculate ss amount and step size */ |
1115 | /* calculate ss amount and step size */ |
1114 | if (ASIC_IS_DCE4(rdev)) { |
1116 | if (ASIC_IS_DCE4(rdev)) { |
1115 | u32 step_size; |
1117 | u32 step_size; |
1116 | u32 amount = (((fb_div * 10) + frac_fb_div) * |
1118 | u32 amount = (((fb_div * 10) + frac_fb_div) * |
1117 | (u32)radeon_crtc->ss.percentage) / |
1119 | (u32)radeon_crtc->ss.percentage) / |
1118 | (100 * (u32)radeon_crtc->ss.percentage_divider); |
1120 | (100 * (u32)radeon_crtc->ss.percentage_divider); |
1119 | radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; |
1121 | radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; |
1120 | radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & |
1122 | radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & |
1121 | ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; |
1123 | ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; |
1122 | if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) |
1124 | if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) |
1123 | step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / |
1125 | step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / |
1124 | (125 * 25 * pll->reference_freq / 100); |
1126 | (125 * 25 * pll->reference_freq / 100); |
1125 | else |
1127 | else |
1126 | step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / |
1128 | step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / |
1127 | (125 * 25 * pll->reference_freq / 100); |
1129 | (125 * 25 * pll->reference_freq / 100); |
1128 | radeon_crtc->ss.step = step_size; |
1130 | radeon_crtc->ss.step = step_size; |
1129 | } |
1131 | } |
1130 | 1132 | ||
1131 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, |
1133 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, |
1132 | radeon_crtc->crtc_id, &radeon_crtc->ss); |
1134 | radeon_crtc->crtc_id, &radeon_crtc->ss); |
1133 | } |
1135 | } |
1134 | } |
1136 | } |
1135 | 1137 | ||
1136 | static int dce4_crtc_do_set_base(struct drm_crtc *crtc, |
1138 | static int dce4_crtc_do_set_base(struct drm_crtc *crtc, |
1137 | struct drm_framebuffer *fb, |
1139 | struct drm_framebuffer *fb, |
1138 | int x, int y, int atomic) |
1140 | int x, int y, int atomic) |
1139 | { |
1141 | { |
1140 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1142 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1141 | struct drm_device *dev = crtc->dev; |
1143 | struct drm_device *dev = crtc->dev; |
1142 | struct radeon_device *rdev = dev->dev_private; |
1144 | struct radeon_device *rdev = dev->dev_private; |
1143 | struct radeon_framebuffer *radeon_fb; |
1145 | struct radeon_framebuffer *radeon_fb; |
1144 | struct drm_framebuffer *target_fb; |
1146 | struct drm_framebuffer *target_fb; |
1145 | struct drm_gem_object *obj; |
1147 | struct drm_gem_object *obj; |
1146 | struct radeon_bo *rbo; |
1148 | struct radeon_bo *rbo; |
1147 | uint64_t fb_location; |
1149 | uint64_t fb_location; |
1148 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
1150 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
1149 | unsigned bankw, bankh, mtaspect, tile_split; |
1151 | unsigned bankw, bankh, mtaspect, tile_split; |
1150 | u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); |
1152 | u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); |
1151 | u32 tmp, viewport_w, viewport_h; |
1153 | u32 tmp, viewport_w, viewport_h; |
1152 | int r; |
1154 | int r; |
1153 | bool bypass_lut = false; |
1155 | bool bypass_lut = false; |
1154 | 1156 | ||
1155 | /* no fb bound */ |
1157 | /* no fb bound */ |
1156 | if (!atomic && !crtc->primary->fb) { |
1158 | if (!atomic && !crtc->primary->fb) { |
1157 | DRM_DEBUG_KMS("No FB bound\n"); |
1159 | DRM_DEBUG_KMS("No FB bound\n"); |
1158 | return 0; |
1160 | return 0; |
1159 | } |
1161 | } |
1160 | 1162 | ||
1161 | if (atomic) { |
1163 | if (atomic) { |
1162 | radeon_fb = to_radeon_framebuffer(fb); |
1164 | radeon_fb = to_radeon_framebuffer(fb); |
1163 | target_fb = fb; |
1165 | target_fb = fb; |
1164 | } |
1166 | } |
1165 | else { |
1167 | else { |
1166 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
1168 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
1167 | target_fb = crtc->primary->fb; |
1169 | target_fb = crtc->primary->fb; |
1168 | } |
1170 | } |
1169 | 1171 | ||
1170 | /* If atomic, assume fb object is pinned & idle & fenced and |
1172 | /* If atomic, assume fb object is pinned & idle & fenced and |
1171 | * just update base pointers |
1173 | * just update base pointers |
1172 | */ |
1174 | */ |
1173 | obj = radeon_fb->obj; |
1175 | obj = radeon_fb->obj; |
1174 | rbo = gem_to_radeon_bo(obj); |
1176 | rbo = gem_to_radeon_bo(obj); |
1175 | r = radeon_bo_reserve(rbo, false); |
1177 | r = radeon_bo_reserve(rbo, false); |
1176 | if (unlikely(r != 0)) |
1178 | if (unlikely(r != 0)) |
1177 | return r; |
1179 | return r; |
1178 | 1180 | ||
1179 | if (atomic) |
1181 | if (atomic) |
1180 | fb_location = radeon_bo_gpu_offset(rbo); |
1182 | fb_location = radeon_bo_gpu_offset(rbo); |
1181 | else { |
1183 | else { |
1182 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
1184 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
1183 | if (unlikely(r != 0)) { |
1185 | if (unlikely(r != 0)) { |
1184 | radeon_bo_unreserve(rbo); |
1186 | radeon_bo_unreserve(rbo); |
1185 | return -EINVAL; |
1187 | return -EINVAL; |
1186 | } |
1188 | } |
1187 | } |
1189 | } |
1188 | 1190 | ||
1189 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1191 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1190 | radeon_bo_unreserve(rbo); |
1192 | radeon_bo_unreserve(rbo); |
1191 | 1193 | ||
1192 | switch (target_fb->pixel_format) { |
1194 | switch (target_fb->pixel_format) { |
1193 | case DRM_FORMAT_C8: |
1195 | case DRM_FORMAT_C8: |
1194 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | |
1196 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | |
1195 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); |
1197 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); |
1196 | break; |
1198 | break; |
1197 | case DRM_FORMAT_XRGB4444: |
1199 | case DRM_FORMAT_XRGB4444: |
1198 | case DRM_FORMAT_ARGB4444: |
1200 | case DRM_FORMAT_ARGB4444: |
1199 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1201 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1200 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); |
1202 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); |
1201 | #ifdef __BIG_ENDIAN |
1203 | #ifdef __BIG_ENDIAN |
1202 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
1204 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
1203 | #endif |
1205 | #endif |
1204 | break; |
1206 | break; |
1205 | case DRM_FORMAT_XRGB1555: |
1207 | case DRM_FORMAT_XRGB1555: |
1206 | case DRM_FORMAT_ARGB1555: |
1208 | case DRM_FORMAT_ARGB1555: |
1207 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1209 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1208 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); |
1210 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); |
1209 | #ifdef __BIG_ENDIAN |
1211 | #ifdef __BIG_ENDIAN |
1210 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
1212 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
1211 | #endif |
1213 | #endif |
1212 | break; |
1214 | break; |
1213 | case DRM_FORMAT_BGRX5551: |
1215 | case DRM_FORMAT_BGRX5551: |
1214 | case DRM_FORMAT_BGRA5551: |
1216 | case DRM_FORMAT_BGRA5551: |
1215 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1217 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1216 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); |
1218 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); |
1217 | #ifdef __BIG_ENDIAN |
1219 | #ifdef __BIG_ENDIAN |
1218 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
1220 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
1219 | #endif |
1221 | #endif |
1220 | break; |
1222 | break; |
1221 | case DRM_FORMAT_RGB565: |
1223 | case DRM_FORMAT_RGB565: |
1222 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1224 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1223 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); |
1225 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); |
1224 | #ifdef __BIG_ENDIAN |
1226 | #ifdef __BIG_ENDIAN |
1225 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
1227 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
1226 | #endif |
1228 | #endif |
1227 | break; |
1229 | break; |
1228 | case DRM_FORMAT_XRGB8888: |
1230 | case DRM_FORMAT_XRGB8888: |
1229 | case DRM_FORMAT_ARGB8888: |
1231 | case DRM_FORMAT_ARGB8888: |
1230 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
1232 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
1231 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); |
1233 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); |
1232 | #ifdef __BIG_ENDIAN |
1234 | #ifdef __BIG_ENDIAN |
1233 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
1235 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
1234 | #endif |
1236 | #endif |
1235 | break; |
1237 | break; |
1236 | case DRM_FORMAT_XRGB2101010: |
1238 | case DRM_FORMAT_XRGB2101010: |
1237 | case DRM_FORMAT_ARGB2101010: |
1239 | case DRM_FORMAT_ARGB2101010: |
1238 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
1240 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
1239 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); |
1241 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); |
1240 | #ifdef __BIG_ENDIAN |
1242 | #ifdef __BIG_ENDIAN |
1241 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
1243 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
1242 | #endif |
1244 | #endif |
1243 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ |
1245 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ |
1244 | bypass_lut = true; |
1246 | bypass_lut = true; |
1245 | break; |
1247 | break; |
1246 | case DRM_FORMAT_BGRX1010102: |
1248 | case DRM_FORMAT_BGRX1010102: |
1247 | case DRM_FORMAT_BGRA1010102: |
1249 | case DRM_FORMAT_BGRA1010102: |
1248 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
1250 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
1249 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); |
1251 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); |
1250 | #ifdef __BIG_ENDIAN |
1252 | #ifdef __BIG_ENDIAN |
1251 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
1253 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
1252 | #endif |
1254 | #endif |
1253 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ |
1255 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ |
1254 | bypass_lut = true; |
1256 | bypass_lut = true; |
1255 | break; |
1257 | break; |
1256 | default: |
1258 | default: |
1257 | DRM_ERROR("Unsupported screen format %s\n", |
1259 | DRM_ERROR("Unsupported screen format %s\n", |
1258 | drm_get_format_name(target_fb->pixel_format)); |
1260 | drm_get_format_name(target_fb->pixel_format)); |
1259 | return -EINVAL; |
1261 | return -EINVAL; |
1260 | } |
1262 | } |
1261 | 1263 | ||
1262 | if (tiling_flags & RADEON_TILING_MACRO) { |
1264 | if (tiling_flags & RADEON_TILING_MACRO) { |
1263 | evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); |
1265 | evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); |
1264 | 1266 | ||
1265 | /* Set NUM_BANKS. */ |
1267 | /* Set NUM_BANKS. */ |
1266 | if (rdev->family >= CHIP_TAHITI) { |
1268 | if (rdev->family >= CHIP_TAHITI) { |
1267 | unsigned index, num_banks; |
1269 | unsigned index, num_banks; |
1268 | 1270 | ||
1269 | if (rdev->family >= CHIP_BONAIRE) { |
1271 | if (rdev->family >= CHIP_BONAIRE) { |
1270 | unsigned tileb, tile_split_bytes; |
1272 | unsigned tileb, tile_split_bytes; |
1271 | 1273 | ||
1272 | /* Calculate the macrotile mode index. */ |
1274 | /* Calculate the macrotile mode index. */ |
1273 | tile_split_bytes = 64 << tile_split; |
1275 | tile_split_bytes = 64 << tile_split; |
1274 | tileb = 8 * 8 * target_fb->bits_per_pixel / 8; |
1276 | tileb = 8 * 8 * target_fb->bits_per_pixel / 8; |
1275 | tileb = min(tile_split_bytes, tileb); |
1277 | tileb = min(tile_split_bytes, tileb); |
1276 | 1278 | ||
1277 | for (index = 0; tileb > 64; index++) |
1279 | for (index = 0; tileb > 64; index++) |
1278 | tileb >>= 1; |
1280 | tileb >>= 1; |
1279 | 1281 | ||
1280 | if (index >= 16) { |
1282 | if (index >= 16) { |
1281 | DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", |
1283 | DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", |
1282 | target_fb->bits_per_pixel, tile_split); |
1284 | target_fb->bits_per_pixel, tile_split); |
1283 | return -EINVAL; |
1285 | return -EINVAL; |
1284 | } |
1286 | } |
1285 | 1287 | ||
1286 | num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; |
1288 | num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; |
1287 | } else { |
1289 | } else { |
1288 | switch (target_fb->bits_per_pixel) { |
1290 | switch (target_fb->bits_per_pixel) { |
1289 | case 8: |
1291 | case 8: |
1290 | index = 10; |
1292 | index = 10; |
1291 | break; |
1293 | break; |
1292 | case 16: |
1294 | case 16: |
1293 | index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP; |
1295 | index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP; |
1294 | break; |
1296 | break; |
1295 | default: |
1297 | default: |
1296 | case 32: |
1298 | case 32: |
1297 | index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP; |
1299 | index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP; |
1298 | break; |
1300 | break; |
1299 | } |
1301 | } |
1300 | 1302 | ||
1301 | num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; |
1303 | num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; |
1302 | } |
1304 | } |
1303 | 1305 | ||
1304 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); |
1306 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); |
1305 | } else { |
1307 | } else { |
1306 | /* NI and older. */ |
1308 | /* NI and older. */ |
1307 | if (rdev->family >= CHIP_CAYMAN) |
1309 | if (rdev->family >= CHIP_CAYMAN) |
1308 | tmp = rdev->config.cayman.tile_config; |
1310 | tmp = rdev->config.cayman.tile_config; |
1309 | else |
1311 | else |
1310 | tmp = rdev->config.evergreen.tile_config; |
1312 | tmp = rdev->config.evergreen.tile_config; |
1311 | 1313 | ||
1312 | switch ((tmp & 0xf0) >> 4) { |
1314 | switch ((tmp & 0xf0) >> 4) { |
1313 | case 0: /* 4 banks */ |
1315 | case 0: /* 4 banks */ |
1314 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); |
1316 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); |
1315 | break; |
1317 | break; |
1316 | case 1: /* 8 banks */ |
1318 | case 1: /* 8 banks */ |
1317 | default: |
1319 | default: |
1318 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); |
1320 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); |
1319 | break; |
1321 | break; |
1320 | case 2: /* 16 banks */ |
1322 | case 2: /* 16 banks */ |
1321 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); |
1323 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); |
1322 | break; |
1324 | break; |
1323 | } |
1325 | } |
1324 | } |
1326 | } |
1325 | 1327 | ||
1326 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); |
1328 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); |
1327 | fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); |
1329 | fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); |
1328 | fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); |
1330 | fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); |
1329 | fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); |
1331 | fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); |
1330 | fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); |
1332 | fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); |
1331 | if (rdev->family >= CHIP_BONAIRE) { |
1333 | if (rdev->family >= CHIP_BONAIRE) { |
1332 | /* XXX need to know more about the surface tiling mode */ |
1334 | /* XXX need to know more about the surface tiling mode */ |
1333 | fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING); |
1335 | fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING); |
1334 | } |
1336 | } |
1335 | } else if (tiling_flags & RADEON_TILING_MICRO) |
1337 | } else if (tiling_flags & RADEON_TILING_MICRO) |
1336 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); |
1338 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); |
1337 | 1339 | ||
1338 | if (rdev->family >= CHIP_BONAIRE) { |
1340 | if (rdev->family >= CHIP_BONAIRE) { |
1339 | /* Read the pipe config from the 2D TILED SCANOUT mode. |
1341 | /* Read the pipe config from the 2D TILED SCANOUT mode. |
1340 | * It should be the same for the other modes too, but not all |
1342 | * It should be the same for the other modes too, but not all |
1341 | * modes set the pipe config field. */ |
1343 | * modes set the pipe config field. */ |
1342 | u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; |
1344 | u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; |
1343 | 1345 | ||
1344 | fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); |
1346 | fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); |
1345 | } else if ((rdev->family == CHIP_TAHITI) || |
1347 | } else if ((rdev->family == CHIP_TAHITI) || |
1346 | (rdev->family == CHIP_PITCAIRN)) |
1348 | (rdev->family == CHIP_PITCAIRN)) |
1347 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); |
1349 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); |
1348 | else if ((rdev->family == CHIP_VERDE) || |
1350 | else if ((rdev->family == CHIP_VERDE) || |
1349 | (rdev->family == CHIP_OLAND) || |
1351 | (rdev->family == CHIP_OLAND) || |
1350 | (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ |
1352 | (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ |
1351 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); |
1353 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); |
1352 | 1354 | ||
1353 | switch (radeon_crtc->crtc_id) { |
1355 | switch (radeon_crtc->crtc_id) { |
1354 | case 0: |
1356 | case 0: |
1355 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
1357 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
1356 | break; |
1358 | break; |
1357 | case 1: |
1359 | case 1: |
1358 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
1360 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
1359 | break; |
1361 | break; |
1360 | case 2: |
1362 | case 2: |
1361 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); |
1363 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); |
1362 | break; |
1364 | break; |
1363 | case 3: |
1365 | case 3: |
1364 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); |
1366 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); |
1365 | break; |
1367 | break; |
1366 | case 4: |
1368 | case 4: |
1367 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); |
1369 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); |
1368 | break; |
1370 | break; |
1369 | case 5: |
1371 | case 5: |
1370 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); |
1372 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); |
1371 | break; |
1373 | break; |
1372 | default: |
1374 | default: |
1373 | break; |
1375 | break; |
1374 | } |
1376 | } |
1375 | 1377 | ||
1376 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
1378 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
1377 | upper_32_bits(fb_location)); |
1379 | upper_32_bits(fb_location)); |
1378 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
1380 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
1379 | upper_32_bits(fb_location)); |
1381 | upper_32_bits(fb_location)); |
1380 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1382 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1381 | (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
1383 | (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
1382 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1384 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1383 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
1385 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
1384 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
1386 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
1385 | WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
1387 | WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
1386 | 1388 | ||
1387 | /* |
1389 | /* |
1388 | * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT |
1390 | * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT |
1389 | * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to |
1391 | * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to |
1390 | * retain the full precision throughout the pipeline. |
1392 | * retain the full precision throughout the pipeline. |
1391 | */ |
1393 | */ |
1392 | WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, |
1394 | WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, |
1393 | (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), |
1395 | (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), |
1394 | ~EVERGREEN_LUT_10BIT_BYPASS_EN); |
1396 | ~EVERGREEN_LUT_10BIT_BYPASS_EN); |
1395 | 1397 | ||
1396 | if (bypass_lut) |
1398 | if (bypass_lut) |
1397 | DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); |
1399 | DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); |
1398 | 1400 | ||
1399 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
1401 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
1400 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
1402 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
1401 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); |
1403 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); |
1402 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
1404 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
1403 | WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1405 | WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1404 | WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); |
1406 | WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); |
1405 | 1407 | ||
1406 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
1408 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
1407 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1409 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1408 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
1410 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
1409 | 1411 | ||
1410 | if (rdev->family >= CHIP_BONAIRE) |
1412 | if (rdev->family >= CHIP_BONAIRE) |
1411 | WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
1413 | WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
1412 | target_fb->height); |
1414 | target_fb->height); |
1413 | else |
1415 | else |
1414 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
1416 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
1415 | target_fb->height); |
1417 | target_fb->height); |
1416 | x &= ~3; |
1418 | x &= ~3; |
1417 | y &= ~1; |
1419 | y &= ~1; |
1418 | WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, |
1420 | WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, |
1419 | (x << 16) | y); |
1421 | (x << 16) | y); |
1420 | viewport_w = crtc->mode.hdisplay; |
1422 | viewport_w = crtc->mode.hdisplay; |
1421 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
1423 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
1422 | if ((rdev->family >= CHIP_BONAIRE) && |
1424 | if ((rdev->family >= CHIP_BONAIRE) && |
1423 | (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)) |
1425 | (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)) |
1424 | viewport_h *= 2; |
1426 | viewport_h *= 2; |
1425 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
1427 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
1426 | (viewport_w << 16) | viewport_h); |
1428 | (viewport_w << 16) | viewport_h); |
1427 | 1429 | ||
1428 | /* pageflip setup */ |
1430 | /* pageflip setup */ |
1429 | /* make sure flip is at vb rather than hb */ |
1431 | /* make sure flip is at vb rather than hb */ |
1430 | tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
1432 | tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
1431 | tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
1433 | tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
1432 | WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
1434 | WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
1433 | 1435 | ||
1434 | /* set pageflip to happen only at start of vblank interval (front porch) */ |
1436 | /* set pageflip to happen only at start of vblank interval (front porch) */ |
1435 | WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); |
1437 | WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); |
1436 | 1438 | ||
1437 | if (!atomic && fb && fb != crtc->primary->fb) { |
1439 | if (!atomic && fb && fb != crtc->primary->fb) { |
1438 | radeon_fb = to_radeon_framebuffer(fb); |
1440 | radeon_fb = to_radeon_framebuffer(fb); |
1439 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
1441 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
1440 | r = radeon_bo_reserve(rbo, false); |
1442 | r = radeon_bo_reserve(rbo, false); |
1441 | if (unlikely(r != 0)) |
1443 | if (unlikely(r != 0)) |
1442 | return r; |
1444 | return r; |
1443 | radeon_bo_unpin(rbo); |
1445 | radeon_bo_unpin(rbo); |
1444 | radeon_bo_unreserve(rbo); |
1446 | radeon_bo_unreserve(rbo); |
1445 | } |
1447 | } |
1446 | 1448 | ||
1447 | /* Bytes per pixel may have changed */ |
1449 | /* Bytes per pixel may have changed */ |
1448 | radeon_bandwidth_update(rdev); |
1450 | radeon_bandwidth_update(rdev); |
1449 | 1451 | ||
1450 | return 0; |
1452 | return 0; |
1451 | } |
1453 | } |
1452 | 1454 | ||
1453 | static int avivo_crtc_do_set_base(struct drm_crtc *crtc, |
1455 | static int avivo_crtc_do_set_base(struct drm_crtc *crtc, |
1454 | struct drm_framebuffer *fb, |
1456 | struct drm_framebuffer *fb, |
1455 | int x, int y, int atomic) |
1457 | int x, int y, int atomic) |
1456 | { |
1458 | { |
1457 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1459 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1458 | struct drm_device *dev = crtc->dev; |
1460 | struct drm_device *dev = crtc->dev; |
1459 | struct radeon_device *rdev = dev->dev_private; |
1461 | struct radeon_device *rdev = dev->dev_private; |
1460 | struct radeon_framebuffer *radeon_fb; |
1462 | struct radeon_framebuffer *radeon_fb; |
1461 | struct drm_gem_object *obj; |
1463 | struct drm_gem_object *obj; |
1462 | struct radeon_bo *rbo; |
1464 | struct radeon_bo *rbo; |
1463 | struct drm_framebuffer *target_fb; |
1465 | struct drm_framebuffer *target_fb; |
1464 | uint64_t fb_location; |
1466 | uint64_t fb_location; |
1465 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
1467 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
1466 | u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; |
1468 | u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; |
1467 | u32 tmp, viewport_w, viewport_h; |
1469 | u32 tmp, viewport_w, viewport_h; |
1468 | int r; |
1470 | int r; |
1469 | bool bypass_lut = false; |
1471 | bool bypass_lut = false; |
1470 | 1472 | ||
1471 | /* no fb bound */ |
1473 | /* no fb bound */ |
1472 | if (!atomic && !crtc->primary->fb) { |
1474 | if (!atomic && !crtc->primary->fb) { |
1473 | DRM_DEBUG_KMS("No FB bound\n"); |
1475 | DRM_DEBUG_KMS("No FB bound\n"); |
1474 | return 0; |
1476 | return 0; |
1475 | } |
1477 | } |
1476 | 1478 | ||
1477 | if (atomic) { |
1479 | if (atomic) { |
1478 | radeon_fb = to_radeon_framebuffer(fb); |
1480 | radeon_fb = to_radeon_framebuffer(fb); |
1479 | target_fb = fb; |
1481 | target_fb = fb; |
1480 | } |
1482 | } |
1481 | else { |
1483 | else { |
1482 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
1484 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
1483 | target_fb = crtc->primary->fb; |
1485 | target_fb = crtc->primary->fb; |
1484 | } |
1486 | } |
1485 | 1487 | ||
1486 | obj = radeon_fb->obj; |
1488 | obj = radeon_fb->obj; |
1487 | rbo = gem_to_radeon_bo(obj); |
1489 | rbo = gem_to_radeon_bo(obj); |
1488 | r = radeon_bo_reserve(rbo, false); |
1490 | r = radeon_bo_reserve(rbo, false); |
1489 | if (unlikely(r != 0)) |
1491 | if (unlikely(r != 0)) |
1490 | return r; |
1492 | return r; |
1491 | 1493 | ||
1492 | /* If atomic, assume fb object is pinned & idle & fenced and |
1494 | /* If atomic, assume fb object is pinned & idle & fenced and |
1493 | * just update base pointers |
1495 | * just update base pointers |
1494 | */ |
1496 | */ |
1495 | if (atomic) |
1497 | if (atomic) |
1496 | fb_location = radeon_bo_gpu_offset(rbo); |
1498 | fb_location = radeon_bo_gpu_offset(rbo); |
1497 | else { |
1499 | else { |
1498 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
1500 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
1499 | if (unlikely(r != 0)) { |
1501 | if (unlikely(r != 0)) { |
1500 | radeon_bo_unreserve(rbo); |
1502 | radeon_bo_unreserve(rbo); |
1501 | return -EINVAL; |
1503 | return -EINVAL; |
1502 | } |
1504 | } |
1503 | } |
1505 | } |
1504 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1506 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1505 | radeon_bo_unreserve(rbo); |
1507 | radeon_bo_unreserve(rbo); |
1506 | 1508 | ||
1507 | switch (target_fb->pixel_format) { |
1509 | switch (target_fb->pixel_format) { |
1508 | case DRM_FORMAT_C8: |
1510 | case DRM_FORMAT_C8: |
1509 | fb_format = |
1511 | fb_format = |
1510 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
1512 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
1511 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
1513 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
1512 | break; |
1514 | break; |
1513 | case DRM_FORMAT_XRGB4444: |
1515 | case DRM_FORMAT_XRGB4444: |
1514 | case DRM_FORMAT_ARGB4444: |
1516 | case DRM_FORMAT_ARGB4444: |
1515 | fb_format = |
1517 | fb_format = |
1516 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
1518 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
1517 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444; |
1519 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444; |
1518 | #ifdef __BIG_ENDIAN |
1520 | #ifdef __BIG_ENDIAN |
1519 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
1521 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
1520 | #endif |
1522 | #endif |
1521 | break; |
1523 | break; |
1522 | case DRM_FORMAT_XRGB1555: |
1524 | case DRM_FORMAT_XRGB1555: |
1523 | fb_format = |
1525 | fb_format = |
1524 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
1526 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
1525 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
1527 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
1526 | #ifdef __BIG_ENDIAN |
1528 | #ifdef __BIG_ENDIAN |
1527 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
1529 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
1528 | #endif |
1530 | #endif |
1529 | break; |
1531 | break; |
1530 | case DRM_FORMAT_RGB565: |
1532 | case DRM_FORMAT_RGB565: |
1531 | fb_format = |
1533 | fb_format = |
1532 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
1534 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
1533 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
1535 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
1534 | #ifdef __BIG_ENDIAN |
1536 | #ifdef __BIG_ENDIAN |
1535 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
1537 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
1536 | #endif |
1538 | #endif |
1537 | break; |
1539 | break; |
1538 | case DRM_FORMAT_XRGB8888: |
1540 | case DRM_FORMAT_XRGB8888: |
1539 | case DRM_FORMAT_ARGB8888: |
1541 | case DRM_FORMAT_ARGB8888: |
1540 | fb_format = |
1542 | fb_format = |
1541 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
1543 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
1542 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
1544 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
1543 | #ifdef __BIG_ENDIAN |
1545 | #ifdef __BIG_ENDIAN |
1544 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; |
1546 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; |
1545 | #endif |
1547 | #endif |
1546 | break; |
1548 | break; |
1547 | case DRM_FORMAT_XRGB2101010: |
1549 | case DRM_FORMAT_XRGB2101010: |
1548 | case DRM_FORMAT_ARGB2101010: |
1550 | case DRM_FORMAT_ARGB2101010: |
1549 | fb_format = |
1551 | fb_format = |
1550 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
1552 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
1551 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010; |
1553 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010; |
1552 | #ifdef __BIG_ENDIAN |
1554 | #ifdef __BIG_ENDIAN |
1553 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; |
1555 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; |
1554 | #endif |
1556 | #endif |
1555 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ |
1557 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ |
1556 | bypass_lut = true; |
1558 | bypass_lut = true; |
1557 | break; |
1559 | break; |
1558 | default: |
1560 | default: |
1559 | DRM_ERROR("Unsupported screen format %s\n", |
1561 | DRM_ERROR("Unsupported screen format %s\n", |
1560 | drm_get_format_name(target_fb->pixel_format)); |
1562 | drm_get_format_name(target_fb->pixel_format)); |
1561 | return -EINVAL; |
1563 | return -EINVAL; |
1562 | } |
1564 | } |
1563 | 1565 | ||
1564 | if (rdev->family >= CHIP_R600) { |
1566 | if (rdev->family >= CHIP_R600) { |
1565 | if (tiling_flags & RADEON_TILING_MACRO) |
1567 | if (tiling_flags & RADEON_TILING_MACRO) |
1566 | fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; |
1568 | fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; |
1567 | else if (tiling_flags & RADEON_TILING_MICRO) |
1569 | else if (tiling_flags & RADEON_TILING_MICRO) |
1568 | fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; |
1570 | fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; |
1569 | } else { |
1571 | } else { |
1570 | if (tiling_flags & RADEON_TILING_MACRO) |
1572 | if (tiling_flags & RADEON_TILING_MACRO) |
1571 | fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; |
1573 | fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; |
1572 | 1574 | ||
1573 | if (tiling_flags & RADEON_TILING_MICRO) |
1575 | if (tiling_flags & RADEON_TILING_MICRO) |
1574 | fb_format |= AVIVO_D1GRPH_TILED; |
1576 | fb_format |= AVIVO_D1GRPH_TILED; |
1575 | } |
1577 | } |
1576 | 1578 | ||
1577 | if (radeon_crtc->crtc_id == 0) |
1579 | if (radeon_crtc->crtc_id == 0) |
1578 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
1580 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
1579 | else |
1581 | else |
1580 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
1582 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
1581 | 1583 | ||
1582 | if (rdev->family >= CHIP_RV770) { |
1584 | if (rdev->family >= CHIP_RV770) { |
1583 | if (radeon_crtc->crtc_id) { |
1585 | if (radeon_crtc->crtc_id) { |
1584 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1586 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1585 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1587 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1586 | } else { |
1588 | } else { |
1587 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1589 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1588 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1590 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1589 | } |
1591 | } |
1590 | } |
1592 | } |
1591 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1593 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1592 | (u32) fb_location); |
1594 | (u32) fb_location); |
1593 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + |
1595 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + |
1594 | radeon_crtc->crtc_offset, (u32) fb_location); |
1596 | radeon_crtc->crtc_offset, (u32) fb_location); |
1595 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
1597 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
1596 | if (rdev->family >= CHIP_R600) |
1598 | if (rdev->family >= CHIP_R600) |
1597 | WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
1599 | WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
1598 | 1600 | ||
1599 | /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */ |
1601 | /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */ |
1600 | WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, |
1602 | WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, |
1601 | (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN); |
1603 | (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN); |
1602 | 1604 | ||
1603 | if (bypass_lut) |
1605 | if (bypass_lut) |
1604 | DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); |
1606 | DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); |
1605 | 1607 | ||
1606 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
1608 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
1607 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
1609 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
1608 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
1610 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
1609 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
1611 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
1610 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1612 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1611 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); |
1613 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); |
1612 | 1614 | ||
1613 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
1615 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
1614 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1616 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1615 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
1617 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
1616 | 1618 | ||
1617 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
1619 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
1618 | target_fb->height); |
1620 | target_fb->height); |
1619 | x &= ~3; |
1621 | x &= ~3; |
1620 | y &= ~1; |
1622 | y &= ~1; |
1621 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, |
1623 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, |
1622 | (x << 16) | y); |
1624 | (x << 16) | y); |
1623 | viewport_w = crtc->mode.hdisplay; |
1625 | viewport_w = crtc->mode.hdisplay; |
1624 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
1626 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
1625 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
1627 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
1626 | (viewport_w << 16) | viewport_h); |
1628 | (viewport_w << 16) | viewport_h); |
1627 | 1629 | ||
1628 | /* pageflip setup */ |
1630 | /* pageflip setup */ |
1629 | /* make sure flip is at vb rather than hb */ |
1631 | /* make sure flip is at vb rather than hb */ |
1630 | tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
1632 | tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
1631 | tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
1633 | tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
1632 | WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
1634 | WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
1633 | 1635 | ||
1634 | /* set pageflip to happen only at start of vblank interval (front porch) */ |
1636 | /* set pageflip to happen only at start of vblank interval (front porch) */ |
1635 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); |
1637 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); |
1636 | 1638 | ||
1637 | if (!atomic && fb && fb != crtc->primary->fb) { |
1639 | if (!atomic && fb && fb != crtc->primary->fb) { |
1638 | radeon_fb = to_radeon_framebuffer(fb); |
1640 | radeon_fb = to_radeon_framebuffer(fb); |
1639 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
1641 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
1640 | r = radeon_bo_reserve(rbo, false); |
1642 | r = radeon_bo_reserve(rbo, false); |
1641 | if (unlikely(r != 0)) |
1643 | if (unlikely(r != 0)) |
1642 | return r; |
1644 | return r; |
1643 | radeon_bo_unpin(rbo); |
1645 | radeon_bo_unpin(rbo); |
1644 | radeon_bo_unreserve(rbo); |
1646 | radeon_bo_unreserve(rbo); |
1645 | } |
1647 | } |
1646 | 1648 | ||
1647 | /* Bytes per pixel may have changed */ |
1649 | /* Bytes per pixel may have changed */ |
1648 | radeon_bandwidth_update(rdev); |
1650 | radeon_bandwidth_update(rdev); |
1649 | 1651 | ||
1650 | return 0; |
1652 | return 0; |
1651 | } |
1653 | } |
1652 | 1654 | ||
1653 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
1655 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
1654 | struct drm_framebuffer *old_fb) |
1656 | struct drm_framebuffer *old_fb) |
1655 | { |
1657 | { |
1656 | struct drm_device *dev = crtc->dev; |
1658 | struct drm_device *dev = crtc->dev; |
1657 | struct radeon_device *rdev = dev->dev_private; |
1659 | struct radeon_device *rdev = dev->dev_private; |
1658 | 1660 | ||
1659 | if (ASIC_IS_DCE4(rdev)) |
1661 | if (ASIC_IS_DCE4(rdev)) |
1660 | return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1662 | return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1661 | else if (ASIC_IS_AVIVO(rdev)) |
1663 | else if (ASIC_IS_AVIVO(rdev)) |
1662 | return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1664 | return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1663 | else |
1665 | else |
1664 | return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1666 | return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1665 | } |
1667 | } |
1666 | 1668 | ||
1667 | int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
1669 | int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
1668 | struct drm_framebuffer *fb, |
1670 | struct drm_framebuffer *fb, |
1669 | int x, int y, enum mode_set_atomic state) |
1671 | int x, int y, enum mode_set_atomic state) |
1670 | { |
1672 | { |
1671 | struct drm_device *dev = crtc->dev; |
1673 | struct drm_device *dev = crtc->dev; |
1672 | struct radeon_device *rdev = dev->dev_private; |
1674 | struct radeon_device *rdev = dev->dev_private; |
1673 | 1675 | ||
1674 | if (ASIC_IS_DCE4(rdev)) |
1676 | if (ASIC_IS_DCE4(rdev)) |
1675 | return dce4_crtc_do_set_base(crtc, fb, x, y, 1); |
1677 | return dce4_crtc_do_set_base(crtc, fb, x, y, 1); |
1676 | else if (ASIC_IS_AVIVO(rdev)) |
1678 | else if (ASIC_IS_AVIVO(rdev)) |
1677 | return avivo_crtc_do_set_base(crtc, fb, x, y, 1); |
1679 | return avivo_crtc_do_set_base(crtc, fb, x, y, 1); |
1678 | else |
1680 | else |
1679 | return radeon_crtc_do_set_base(crtc, fb, x, y, 1); |
1681 | return radeon_crtc_do_set_base(crtc, fb, x, y, 1); |
1680 | } |
1682 | } |
1681 | 1683 | ||
1682 | /* properly set additional regs when using atombios */ |
1684 | /* properly set additional regs when using atombios */ |
1683 | static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) |
1685 | static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) |
1684 | { |
1686 | { |
1685 | struct drm_device *dev = crtc->dev; |
1687 | struct drm_device *dev = crtc->dev; |
1686 | struct radeon_device *rdev = dev->dev_private; |
1688 | struct radeon_device *rdev = dev->dev_private; |
1687 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1689 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1688 | u32 disp_merge_cntl; |
1690 | u32 disp_merge_cntl; |
1689 | 1691 | ||
1690 | switch (radeon_crtc->crtc_id) { |
1692 | switch (radeon_crtc->crtc_id) { |
1691 | case 0: |
1693 | case 0: |
1692 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
1694 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
1693 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
1695 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
1694 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
1696 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
1695 | break; |
1697 | break; |
1696 | case 1: |
1698 | case 1: |
1697 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
1699 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
1698 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
1700 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
1699 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); |
1701 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); |
1700 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); |
1702 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); |
1701 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
1703 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
1702 | break; |
1704 | break; |
1703 | } |
1705 | } |
1704 | } |
1706 | } |
1705 | 1707 | ||
1706 | /** |
1708 | /** |
1707 | * radeon_get_pll_use_mask - look up a mask of which pplls are in use |
1709 | * radeon_get_pll_use_mask - look up a mask of which pplls are in use |
1708 | * |
1710 | * |
1709 | * @crtc: drm crtc |
1711 | * @crtc: drm crtc |
1710 | * |
1712 | * |
1711 | * Returns the mask of which PPLLs (Pixel PLLs) are in use. |
1713 | * Returns the mask of which PPLLs (Pixel PLLs) are in use. |
1712 | */ |
1714 | */ |
1713 | static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) |
1715 | static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) |
1714 | { |
1716 | { |
1715 | struct drm_device *dev = crtc->dev; |
1717 | struct drm_device *dev = crtc->dev; |
1716 | struct drm_crtc *test_crtc; |
1718 | struct drm_crtc *test_crtc; |
1717 | struct radeon_crtc *test_radeon_crtc; |
1719 | struct radeon_crtc *test_radeon_crtc; |
1718 | u32 pll_in_use = 0; |
1720 | u32 pll_in_use = 0; |
1719 | 1721 | ||
1720 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
1722 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
1721 | if (crtc == test_crtc) |
1723 | if (crtc == test_crtc) |
1722 | continue; |
1724 | continue; |
1723 | 1725 | ||
1724 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1726 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1725 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1727 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1726 | pll_in_use |= (1 << test_radeon_crtc->pll_id); |
1728 | pll_in_use |= (1 << test_radeon_crtc->pll_id); |
1727 | } |
1729 | } |
1728 | return pll_in_use; |
1730 | return pll_in_use; |
1729 | } |
1731 | } |
1730 | 1732 | ||
1731 | /** |
1733 | /** |
1732 | * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP |
1734 | * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP |
1733 | * |
1735 | * |
1734 | * @crtc: drm crtc |
1736 | * @crtc: drm crtc |
1735 | * |
1737 | * |
1736 | * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is |
1738 | * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is |
1737 | * also in DP mode. For DP, a single PPLL can be used for all DP |
1739 | * also in DP mode. For DP, a single PPLL can be used for all DP |
1738 | * crtcs/encoders. |
1740 | * crtcs/encoders. |
1739 | */ |
1741 | */ |
1740 | static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) |
1742 | static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) |
1741 | { |
1743 | { |
1742 | struct drm_device *dev = crtc->dev; |
1744 | struct drm_device *dev = crtc->dev; |
1743 | struct radeon_device *rdev = dev->dev_private; |
1745 | struct radeon_device *rdev = dev->dev_private; |
1744 | struct drm_crtc *test_crtc; |
1746 | struct drm_crtc *test_crtc; |
1745 | struct radeon_crtc *test_radeon_crtc; |
1747 | struct radeon_crtc *test_radeon_crtc; |
1746 | 1748 | ||
1747 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
1749 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
1748 | if (crtc == test_crtc) |
1750 | if (crtc == test_crtc) |
1749 | continue; |
1751 | continue; |
1750 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1752 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1751 | if (test_radeon_crtc->encoder && |
1753 | if (test_radeon_crtc->encoder && |
1752 | ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
1754 | ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
1753 | /* PPLL2 is exclusive to UNIPHYA on DCE61 */ |
1755 | /* PPLL2 is exclusive to UNIPHYA on DCE61 */ |
1754 | if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && |
1756 | if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && |
1755 | test_radeon_crtc->pll_id == ATOM_PPLL2) |
1757 | test_radeon_crtc->pll_id == ATOM_PPLL2) |
1756 | continue; |
1758 | continue; |
1757 | /* for DP use the same PLL for all */ |
1759 | /* for DP use the same PLL for all */ |
1758 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1760 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1759 | return test_radeon_crtc->pll_id; |
1761 | return test_radeon_crtc->pll_id; |
1760 | } |
1762 | } |
1761 | } |
1763 | } |
1762 | return ATOM_PPLL_INVALID; |
1764 | return ATOM_PPLL_INVALID; |
1763 | } |
1765 | } |
1764 | 1766 | ||
1765 | /** |
1767 | /** |
1766 | * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc |
1768 | * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc |
1767 | * |
1769 | * |
1768 | * @crtc: drm crtc |
1770 | * @crtc: drm crtc |
1769 | * @encoder: drm encoder |
1771 | * @encoder: drm encoder |
1770 | * |
1772 | * |
1771 | * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can |
1773 | * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can |
1772 | * be shared (i.e., same clock). |
1774 | * be shared (i.e., same clock). |
1773 | */ |
1775 | */ |
1774 | static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) |
1776 | static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) |
1775 | { |
1777 | { |
1776 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1778 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1777 | struct drm_device *dev = crtc->dev; |
1779 | struct drm_device *dev = crtc->dev; |
1778 | struct radeon_device *rdev = dev->dev_private; |
1780 | struct radeon_device *rdev = dev->dev_private; |
1779 | struct drm_crtc *test_crtc; |
1781 | struct drm_crtc *test_crtc; |
1780 | struct radeon_crtc *test_radeon_crtc; |
1782 | struct radeon_crtc *test_radeon_crtc; |
1781 | u32 adjusted_clock, test_adjusted_clock; |
1783 | u32 adjusted_clock, test_adjusted_clock; |
1782 | 1784 | ||
1783 | adjusted_clock = radeon_crtc->adjusted_clock; |
1785 | adjusted_clock = radeon_crtc->adjusted_clock; |
1784 | 1786 | ||
1785 | if (adjusted_clock == 0) |
1787 | if (adjusted_clock == 0) |
1786 | return ATOM_PPLL_INVALID; |
1788 | return ATOM_PPLL_INVALID; |
1787 | 1789 | ||
1788 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
1790 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
1789 | if (crtc == test_crtc) |
1791 | if (crtc == test_crtc) |
1790 | continue; |
1792 | continue; |
1791 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1793 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1792 | if (test_radeon_crtc->encoder && |
1794 | if (test_radeon_crtc->encoder && |
1793 | !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
1795 | !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
1794 | /* PPLL2 is exclusive to UNIPHYA on DCE61 */ |
1796 | /* PPLL2 is exclusive to UNIPHYA on DCE61 */ |
1795 | if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && |
1797 | if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && |
1796 | test_radeon_crtc->pll_id == ATOM_PPLL2) |
1798 | test_radeon_crtc->pll_id == ATOM_PPLL2) |
1797 | continue; |
1799 | continue; |
1798 | /* check if we are already driving this connector with another crtc */ |
1800 | /* check if we are already driving this connector with another crtc */ |
1799 | if (test_radeon_crtc->connector == radeon_crtc->connector) { |
1801 | if (test_radeon_crtc->connector == radeon_crtc->connector) { |
1800 | /* if we are, return that pll */ |
1802 | /* if we are, return that pll */ |
1801 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1803 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1802 | return test_radeon_crtc->pll_id; |
1804 | return test_radeon_crtc->pll_id; |
1803 | } |
1805 | } |
1804 | /* for non-DP check the clock */ |
1806 | /* for non-DP check the clock */ |
1805 | test_adjusted_clock = test_radeon_crtc->adjusted_clock; |
1807 | test_adjusted_clock = test_radeon_crtc->adjusted_clock; |
1806 | if ((crtc->mode.clock == test_crtc->mode.clock) && |
1808 | if ((crtc->mode.clock == test_crtc->mode.clock) && |
1807 | (adjusted_clock == test_adjusted_clock) && |
1809 | (adjusted_clock == test_adjusted_clock) && |
1808 | (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && |
1810 | (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && |
1809 | (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) |
1811 | (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) |
1810 | return test_radeon_crtc->pll_id; |
1812 | return test_radeon_crtc->pll_id; |
1811 | } |
1813 | } |
1812 | } |
1814 | } |
1813 | return ATOM_PPLL_INVALID; |
1815 | return ATOM_PPLL_INVALID; |
1814 | } |
1816 | } |
1815 | 1817 | ||
1816 | /** |
1818 | /** |
1817 | * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. |
1819 | * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. |
1818 | * |
1820 | * |
1819 | * @crtc: drm crtc |
1821 | * @crtc: drm crtc |
1820 | * |
1822 | * |
1821 | * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors |
1823 | * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors |
1822 | * a single PPLL can be used for all DP crtcs/encoders. For non-DP |
1824 | * a single PPLL can be used for all DP crtcs/encoders. For non-DP |
1823 | * monitors a dedicated PPLL must be used. If a particular board has |
1825 | * monitors a dedicated PPLL must be used. If a particular board has |
1824 | * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming |
1826 | * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming |
1825 | * as there is no need to program the PLL itself. If we are not able to |
1827 | * as there is no need to program the PLL itself. If we are not able to |
1826 | * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to |
1828 | * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to |
1827 | * avoid messing up an existing monitor. |
1829 | * avoid messing up an existing monitor. |
1828 | * |
1830 | * |
1829 | * Asic specific PLL information |
1831 | * Asic specific PLL information |
1830 | * |
1832 | * |
1831 | * DCE 8.x |
1833 | * DCE 8.x |
1832 | * KB/KV |
1834 | * KB/KV |
1833 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) |
1835 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) |
1834 | * CI |
1836 | * CI |
1835 | * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
1837 | * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
1836 | * |
1838 | * |
1837 | * DCE 6.1 |
1839 | * DCE 6.1 |
1838 | * - PPLL2 is only available to UNIPHYA (both DP and non-DP) |
1840 | * - PPLL2 is only available to UNIPHYA (both DP and non-DP) |
1839 | * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) |
1841 | * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) |
1840 | * |
1842 | * |
1841 | * DCE 6.0 |
1843 | * DCE 6.0 |
1842 | * - PPLL0 is available to all UNIPHY (DP only) |
1844 | * - PPLL0 is available to all UNIPHY (DP only) |
1843 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
1845 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
1844 | * |
1846 | * |
1845 | * DCE 5.0 |
1847 | * DCE 5.0 |
1846 | * - DCPLL is available to all UNIPHY (DP only) |
1848 | * - DCPLL is available to all UNIPHY (DP only) |
1847 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
1849 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
1848 | * |
1850 | * |
1849 | * DCE 3.0/4.0/4.1 |
1851 | * DCE 3.0/4.0/4.1 |
1850 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
1852 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
1851 | * |
1853 | * |
1852 | */ |
1854 | */ |
1853 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) |
1855 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) |
1854 | { |
1856 | { |
1855 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1857 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1856 | struct drm_device *dev = crtc->dev; |
1858 | struct drm_device *dev = crtc->dev; |
1857 | struct radeon_device *rdev = dev->dev_private; |
1859 | struct radeon_device *rdev = dev->dev_private; |
1858 | struct radeon_encoder *radeon_encoder = |
1860 | struct radeon_encoder *radeon_encoder = |
1859 | to_radeon_encoder(radeon_crtc->encoder); |
1861 | to_radeon_encoder(radeon_crtc->encoder); |
1860 | u32 pll_in_use; |
1862 | u32 pll_in_use; |
1861 | int pll; |
1863 | int pll; |
1862 | 1864 | ||
1863 | if (ASIC_IS_DCE8(rdev)) { |
1865 | if (ASIC_IS_DCE8(rdev)) { |
1864 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1866 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1865 | if (rdev->clock.dp_extclk) |
1867 | if (rdev->clock.dp_extclk) |
1866 | /* skip PPLL programming if using ext clock */ |
1868 | /* skip PPLL programming if using ext clock */ |
1867 | return ATOM_PPLL_INVALID; |
1869 | return ATOM_PPLL_INVALID; |
1868 | else { |
1870 | else { |
1869 | /* use the same PPLL for all DP monitors */ |
1871 | /* use the same PPLL for all DP monitors */ |
1870 | pll = radeon_get_shared_dp_ppll(crtc); |
1872 | pll = radeon_get_shared_dp_ppll(crtc); |
1871 | if (pll != ATOM_PPLL_INVALID) |
1873 | if (pll != ATOM_PPLL_INVALID) |
1872 | return pll; |
1874 | return pll; |
1873 | } |
1875 | } |
1874 | } else { |
1876 | } else { |
1875 | /* use the same PPLL for all monitors with the same clock */ |
1877 | /* use the same PPLL for all monitors with the same clock */ |
1876 | pll = radeon_get_shared_nondp_ppll(crtc); |
1878 | pll = radeon_get_shared_nondp_ppll(crtc); |
1877 | if (pll != ATOM_PPLL_INVALID) |
1879 | if (pll != ATOM_PPLL_INVALID) |
1878 | return pll; |
1880 | return pll; |
1879 | } |
1881 | } |
1880 | /* otherwise, pick one of the plls */ |
1882 | /* otherwise, pick one of the plls */ |
1881 | if ((rdev->family == CHIP_KABINI) || |
1883 | if ((rdev->family == CHIP_KABINI) || |
1882 | (rdev->family == CHIP_MULLINS)) { |
1884 | (rdev->family == CHIP_MULLINS)) { |
1883 | /* KB/ML has PPLL1 and PPLL2 */ |
1885 | /* KB/ML has PPLL1 and PPLL2 */ |
1884 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1886 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1885 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1887 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1886 | return ATOM_PPLL2; |
1888 | return ATOM_PPLL2; |
1887 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1889 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1888 | return ATOM_PPLL1; |
1890 | return ATOM_PPLL1; |
1889 | DRM_ERROR("unable to allocate a PPLL\n"); |
1891 | DRM_ERROR("unable to allocate a PPLL\n"); |
1890 | return ATOM_PPLL_INVALID; |
1892 | return ATOM_PPLL_INVALID; |
1891 | } else { |
1893 | } else { |
1892 | /* CI/KV has PPLL0, PPLL1, and PPLL2 */ |
1894 | /* CI/KV has PPLL0, PPLL1, and PPLL2 */ |
1893 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1895 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1894 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1896 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1895 | return ATOM_PPLL2; |
1897 | return ATOM_PPLL2; |
1896 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1898 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1897 | return ATOM_PPLL1; |
1899 | return ATOM_PPLL1; |
1898 | if (!(pll_in_use & (1 << ATOM_PPLL0))) |
1900 | if (!(pll_in_use & (1 << ATOM_PPLL0))) |
1899 | return ATOM_PPLL0; |
1901 | return ATOM_PPLL0; |
1900 | DRM_ERROR("unable to allocate a PPLL\n"); |
1902 | DRM_ERROR("unable to allocate a PPLL\n"); |
1901 | return ATOM_PPLL_INVALID; |
1903 | return ATOM_PPLL_INVALID; |
1902 | } |
1904 | } |
1903 | } else if (ASIC_IS_DCE61(rdev)) { |
1905 | } else if (ASIC_IS_DCE61(rdev)) { |
1904 | struct radeon_encoder_atom_dig *dig = |
1906 | struct radeon_encoder_atom_dig *dig = |
1905 | radeon_encoder->enc_priv; |
1907 | radeon_encoder->enc_priv; |
1906 | 1908 | ||
1907 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && |
1909 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && |
1908 | (dig->linkb == false)) |
1910 | (dig->linkb == false)) |
1909 | /* UNIPHY A uses PPLL2 */ |
1911 | /* UNIPHY A uses PPLL2 */ |
1910 | return ATOM_PPLL2; |
1912 | return ATOM_PPLL2; |
1911 | else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1913 | else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1912 | /* UNIPHY B/C/D/E/F */ |
1914 | /* UNIPHY B/C/D/E/F */ |
1913 | if (rdev->clock.dp_extclk) |
1915 | if (rdev->clock.dp_extclk) |
1914 | /* skip PPLL programming if using ext clock */ |
1916 | /* skip PPLL programming if using ext clock */ |
1915 | return ATOM_PPLL_INVALID; |
1917 | return ATOM_PPLL_INVALID; |
1916 | else { |
1918 | else { |
1917 | /* use the same PPLL for all DP monitors */ |
1919 | /* use the same PPLL for all DP monitors */ |
1918 | pll = radeon_get_shared_dp_ppll(crtc); |
1920 | pll = radeon_get_shared_dp_ppll(crtc); |
1919 | if (pll != ATOM_PPLL_INVALID) |
1921 | if (pll != ATOM_PPLL_INVALID) |
1920 | return pll; |
1922 | return pll; |
1921 | } |
1923 | } |
1922 | } else { |
1924 | } else { |
1923 | /* use the same PPLL for all monitors with the same clock */ |
1925 | /* use the same PPLL for all monitors with the same clock */ |
1924 | pll = radeon_get_shared_nondp_ppll(crtc); |
1926 | pll = radeon_get_shared_nondp_ppll(crtc); |
1925 | if (pll != ATOM_PPLL_INVALID) |
1927 | if (pll != ATOM_PPLL_INVALID) |
1926 | return pll; |
1928 | return pll; |
1927 | } |
1929 | } |
1928 | /* UNIPHY B/C/D/E/F */ |
1930 | /* UNIPHY B/C/D/E/F */ |
1929 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1931 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1930 | if (!(pll_in_use & (1 << ATOM_PPLL0))) |
1932 | if (!(pll_in_use & (1 << ATOM_PPLL0))) |
1931 | return ATOM_PPLL0; |
1933 | return ATOM_PPLL0; |
1932 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1934 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1933 | return ATOM_PPLL1; |
1935 | return ATOM_PPLL1; |
1934 | DRM_ERROR("unable to allocate a PPLL\n"); |
1936 | DRM_ERROR("unable to allocate a PPLL\n"); |
1935 | return ATOM_PPLL_INVALID; |
1937 | return ATOM_PPLL_INVALID; |
1936 | } else if (ASIC_IS_DCE41(rdev)) { |
1938 | } else if (ASIC_IS_DCE41(rdev)) { |
1937 | /* Don't share PLLs on DCE4.1 chips */ |
1939 | /* Don't share PLLs on DCE4.1 chips */ |
1938 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1940 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1939 | if (rdev->clock.dp_extclk) |
1941 | if (rdev->clock.dp_extclk) |
1940 | /* skip PPLL programming if using ext clock */ |
1942 | /* skip PPLL programming if using ext clock */ |
1941 | return ATOM_PPLL_INVALID; |
1943 | return ATOM_PPLL_INVALID; |
1942 | } |
1944 | } |
1943 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1945 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1944 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1946 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1945 | return ATOM_PPLL1; |
1947 | return ATOM_PPLL1; |
1946 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1948 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1947 | return ATOM_PPLL2; |
1949 | return ATOM_PPLL2; |
1948 | DRM_ERROR("unable to allocate a PPLL\n"); |
1950 | DRM_ERROR("unable to allocate a PPLL\n"); |
1949 | return ATOM_PPLL_INVALID; |
1951 | return ATOM_PPLL_INVALID; |
1950 | } else if (ASIC_IS_DCE4(rdev)) { |
1952 | } else if (ASIC_IS_DCE4(rdev)) { |
1951 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
1953 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
1952 | * depending on the asic: |
1954 | * depending on the asic: |
1953 | * DCE4: PPLL or ext clock |
1955 | * DCE4: PPLL or ext clock |
1954 | * DCE5: PPLL, DCPLL, or ext clock |
1956 | * DCE5: PPLL, DCPLL, or ext clock |
1955 | * DCE6: PPLL, PPLL0, or ext clock |
1957 | * DCE6: PPLL, PPLL0, or ext clock |
1956 | * |
1958 | * |
1957 | * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip |
1959 | * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip |
1958 | * PPLL/DCPLL programming and only program the DP DTO for the |
1960 | * PPLL/DCPLL programming and only program the DP DTO for the |
1959 | * crtc virtual pixel clock. |
1961 | * crtc virtual pixel clock. |
1960 | */ |
1962 | */ |
1961 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1963 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1962 | if (rdev->clock.dp_extclk) |
1964 | if (rdev->clock.dp_extclk) |
1963 | /* skip PPLL programming if using ext clock */ |
1965 | /* skip PPLL programming if using ext clock */ |
1964 | return ATOM_PPLL_INVALID; |
1966 | return ATOM_PPLL_INVALID; |
1965 | else if (ASIC_IS_DCE6(rdev)) |
1967 | else if (ASIC_IS_DCE6(rdev)) |
1966 | /* use PPLL0 for all DP */ |
1968 | /* use PPLL0 for all DP */ |
1967 | return ATOM_PPLL0; |
1969 | return ATOM_PPLL0; |
1968 | else if (ASIC_IS_DCE5(rdev)) |
1970 | else if (ASIC_IS_DCE5(rdev)) |
1969 | /* use DCPLL for all DP */ |
1971 | /* use DCPLL for all DP */ |
1970 | return ATOM_DCPLL; |
1972 | return ATOM_DCPLL; |
1971 | else { |
1973 | else { |
1972 | /* use the same PPLL for all DP monitors */ |
1974 | /* use the same PPLL for all DP monitors */ |
1973 | pll = radeon_get_shared_dp_ppll(crtc); |
1975 | pll = radeon_get_shared_dp_ppll(crtc); |
1974 | if (pll != ATOM_PPLL_INVALID) |
1976 | if (pll != ATOM_PPLL_INVALID) |
1975 | return pll; |
1977 | return pll; |
1976 | } |
1978 | } |
1977 | } else { |
1979 | } else { |
1978 | /* use the same PPLL for all monitors with the same clock */ |
1980 | /* use the same PPLL for all monitors with the same clock */ |
1979 | pll = radeon_get_shared_nondp_ppll(crtc); |
1981 | pll = radeon_get_shared_nondp_ppll(crtc); |
1980 | if (pll != ATOM_PPLL_INVALID) |
1982 | if (pll != ATOM_PPLL_INVALID) |
1981 | return pll; |
1983 | return pll; |
1982 | } |
1984 | } |
1983 | /* all other cases */ |
1985 | /* all other cases */ |
1984 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1986 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1985 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1987 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1986 | return ATOM_PPLL1; |
1988 | return ATOM_PPLL1; |
1987 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1989 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1988 | return ATOM_PPLL2; |
1990 | return ATOM_PPLL2; |
1989 | DRM_ERROR("unable to allocate a PPLL\n"); |
1991 | DRM_ERROR("unable to allocate a PPLL\n"); |
1990 | return ATOM_PPLL_INVALID; |
1992 | return ATOM_PPLL_INVALID; |
1991 | } else { |
1993 | } else { |
1992 | /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ |
1994 | /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ |
1993 | /* some atombios (observed in some DCE2/DCE3) code have a bug, |
1995 | /* some atombios (observed in some DCE2/DCE3) code have a bug, |
1994 | * the matching btw pll and crtc is done through |
1996 | * the matching btw pll and crtc is done through |
1995 | * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the |
1997 | * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the |
1996 | * pll (1 or 2) to select which register to write. ie if using |
1998 | * pll (1 or 2) to select which register to write. ie if using |
1997 | * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 |
1999 | * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 |
1998 | * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to |
2000 | * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to |
1999 | * choose which value to write. Which is reverse order from |
2001 | * choose which value to write. Which is reverse order from |
2000 | * register logic. So only case that works is when pllid is |
2002 | * register logic. So only case that works is when pllid is |
2001 | * same as crtcid or when both pll and crtc are enabled and |
2003 | * same as crtcid or when both pll and crtc are enabled and |
2002 | * both use same clock. |
2004 | * both use same clock. |
2003 | * |
2005 | * |
2004 | * So just return crtc id as if crtc and pll were hard linked |
2006 | * So just return crtc id as if crtc and pll were hard linked |
2005 | * together even if they aren't |
2007 | * together even if they aren't |
2006 | */ |
2008 | */ |
2007 | return radeon_crtc->crtc_id; |
2009 | return radeon_crtc->crtc_id; |
2008 | } |
2010 | } |
2009 | } |
2011 | } |
2010 | 2012 | ||
2011 | void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) |
2013 | void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) |
2012 | { |
2014 | { |
2013 | /* always set DCPLL */ |
2015 | /* always set DCPLL */ |
2014 | if (ASIC_IS_DCE6(rdev)) |
2016 | if (ASIC_IS_DCE6(rdev)) |
2015 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); |
2017 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); |
2016 | else if (ASIC_IS_DCE4(rdev)) { |
2018 | else if (ASIC_IS_DCE4(rdev)) { |
2017 | struct radeon_atom_ss ss; |
2019 | struct radeon_atom_ss ss; |
2018 | bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, |
2020 | bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, |
2019 | ASIC_INTERNAL_SS_ON_DCPLL, |
2021 | ASIC_INTERNAL_SS_ON_DCPLL, |
2020 | rdev->clock.default_dispclk); |
2022 | rdev->clock.default_dispclk); |
2021 | if (ss_enabled) |
2023 | if (ss_enabled) |
2022 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); |
2024 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); |
2023 | /* XXX: DCE5, make sure voltage, dispclk is high enough */ |
2025 | /* XXX: DCE5, make sure voltage, dispclk is high enough */ |
2024 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); |
2026 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); |
2025 | if (ss_enabled) |
2027 | if (ss_enabled) |
2026 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); |
2028 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); |
2027 | } |
2029 | } |
2028 | 2030 | ||
2029 | } |
2031 | } |
2030 | 2032 | ||
2031 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
2033 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
2032 | struct drm_display_mode *mode, |
2034 | struct drm_display_mode *mode, |
2033 | struct drm_display_mode *adjusted_mode, |
2035 | struct drm_display_mode *adjusted_mode, |
2034 | int x, int y, struct drm_framebuffer *old_fb) |
2036 | int x, int y, struct drm_framebuffer *old_fb) |
2035 | { |
2037 | { |
2036 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
2038 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
2037 | struct drm_device *dev = crtc->dev; |
2039 | struct drm_device *dev = crtc->dev; |
2038 | struct radeon_device *rdev = dev->dev_private; |
2040 | struct radeon_device *rdev = dev->dev_private; |
2039 | struct radeon_encoder *radeon_encoder = |
2041 | struct radeon_encoder *radeon_encoder = |
2040 | to_radeon_encoder(radeon_crtc->encoder); |
2042 | to_radeon_encoder(radeon_crtc->encoder); |
2041 | bool is_tvcv = false; |
2043 | bool is_tvcv = false; |
2042 | 2044 | ||
2043 | if (radeon_encoder->active_device & |
2045 | if (radeon_encoder->active_device & |
2044 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
2046 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
2045 | is_tvcv = true; |
2047 | is_tvcv = true; |
2046 | 2048 | ||
2047 | if (!radeon_crtc->adjusted_clock) |
2049 | if (!radeon_crtc->adjusted_clock) |
2048 | return -EINVAL; |
2050 | return -EINVAL; |
2049 | 2051 | ||
2050 | atombios_crtc_set_pll(crtc, adjusted_mode); |
2052 | atombios_crtc_set_pll(crtc, adjusted_mode); |
2051 | 2053 | ||
2052 | if (ASIC_IS_DCE4(rdev)) |
2054 | if (ASIC_IS_DCE4(rdev)) |
2053 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
2055 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
2054 | else if (ASIC_IS_AVIVO(rdev)) { |
2056 | else if (ASIC_IS_AVIVO(rdev)) { |
2055 | if (is_tvcv) |
2057 | if (is_tvcv) |
2056 | atombios_crtc_set_timing(crtc, adjusted_mode); |
2058 | atombios_crtc_set_timing(crtc, adjusted_mode); |
2057 | else |
2059 | else |
2058 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
2060 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
2059 | } else { |
2061 | } else { |
2060 | atombios_crtc_set_timing(crtc, adjusted_mode); |
2062 | atombios_crtc_set_timing(crtc, adjusted_mode); |
2061 | if (radeon_crtc->crtc_id == 0) |
2063 | if (radeon_crtc->crtc_id == 0) |
2062 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
2064 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
2063 | radeon_legacy_atom_fixup(crtc); |
2065 | radeon_legacy_atom_fixup(crtc); |
2064 | } |
2066 | } |
2065 | atombios_crtc_set_base(crtc, x, y, old_fb); |
2067 | atombios_crtc_set_base(crtc, x, y, old_fb); |
2066 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
2068 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
2067 | atombios_scaler_setup(crtc); |
2069 | atombios_scaler_setup(crtc); |
2068 | // radeon_cursor_reset(crtc); |
2070 | // radeon_cursor_reset(crtc); |
2069 | /* update the hw version fpr dpm */ |
2071 | /* update the hw version fpr dpm */ |
2070 | radeon_crtc->hw_mode = *adjusted_mode; |
2072 | radeon_crtc->hw_mode = *adjusted_mode; |
2071 | 2073 | ||
2072 | return 0; |
2074 | return 0; |
2073 | } |
2075 | } |
2074 | 2076 | ||
2075 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
2077 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
2076 | const struct drm_display_mode *mode, |
2078 | const struct drm_display_mode *mode, |
2077 | struct drm_display_mode *adjusted_mode) |
2079 | struct drm_display_mode *adjusted_mode) |
2078 | { |
2080 | { |
2079 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
2081 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
2080 | struct drm_device *dev = crtc->dev; |
2082 | struct drm_device *dev = crtc->dev; |
2081 | struct drm_encoder *encoder; |
2083 | struct drm_encoder *encoder; |
2082 | 2084 | ||
2083 | /* assign the encoder to the radeon crtc to avoid repeated lookups later */ |
2085 | /* assign the encoder to the radeon crtc to avoid repeated lookups later */ |
2084 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
2086 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
2085 | if (encoder->crtc == crtc) { |
2087 | if (encoder->crtc == crtc) { |
2086 | radeon_crtc->encoder = encoder; |
2088 | radeon_crtc->encoder = encoder; |
2087 | radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); |
2089 | radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); |
2088 | break; |
2090 | break; |
2089 | } |
2091 | } |
2090 | } |
2092 | } |
2091 | if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { |
2093 | if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { |
2092 | radeon_crtc->encoder = NULL; |
2094 | radeon_crtc->encoder = NULL; |
2093 | radeon_crtc->connector = NULL; |
2095 | radeon_crtc->connector = NULL; |
2094 | return false; |
2096 | return false; |
2095 | } |
2097 | } |
2096 | if (radeon_crtc->encoder) { |
2098 | if (radeon_crtc->encoder) { |
2097 | struct radeon_encoder *radeon_encoder = |
2099 | struct radeon_encoder *radeon_encoder = |
2098 | to_radeon_encoder(radeon_crtc->encoder); |
2100 | to_radeon_encoder(radeon_crtc->encoder); |
2099 | 2101 | ||
2100 | radeon_crtc->output_csc = radeon_encoder->output_csc; |
2102 | radeon_crtc->output_csc = radeon_encoder->output_csc; |
2101 | } |
2103 | } |
2102 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
2104 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
2103 | return false; |
2105 | return false; |
2104 | if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) |
2106 | if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) |
2105 | return false; |
2107 | return false; |
2106 | /* pick pll */ |
2108 | /* pick pll */ |
2107 | radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); |
2109 | radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); |
2108 | /* if we can't get a PPLL for a non-DP encoder, fail */ |
2110 | /* if we can't get a PPLL for a non-DP encoder, fail */ |
2109 | if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && |
2111 | if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && |
2110 | !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) |
2112 | !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) |
2111 | return false; |
2113 | return false; |
2112 | 2114 | ||
2113 | return true; |
2115 | return true; |
2114 | } |
2116 | } |
2115 | 2117 | ||
2116 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
2118 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
2117 | { |
2119 | { |
2118 | struct drm_device *dev = crtc->dev; |
2120 | struct drm_device *dev = crtc->dev; |
2119 | struct radeon_device *rdev = dev->dev_private; |
2121 | struct radeon_device *rdev = dev->dev_private; |
2120 | 2122 | ||
2121 | /* disable crtc pair power gating before programming */ |
2123 | /* disable crtc pair power gating before programming */ |
2122 | if (ASIC_IS_DCE6(rdev)) |
2124 | if (ASIC_IS_DCE6(rdev)) |
2123 | atombios_powergate_crtc(crtc, ATOM_DISABLE); |
2125 | atombios_powergate_crtc(crtc, ATOM_DISABLE); |
2124 | 2126 | ||
2125 | atombios_lock_crtc(crtc, ATOM_ENABLE); |
2127 | atombios_lock_crtc(crtc, ATOM_ENABLE); |
2126 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
2128 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
2127 | } |
2129 | } |
2128 | 2130 | ||
2129 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
2131 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
2130 | { |
2132 | { |
2131 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
2133 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
2132 | atombios_lock_crtc(crtc, ATOM_DISABLE); |
2134 | atombios_lock_crtc(crtc, ATOM_DISABLE); |
2133 | } |
2135 | } |
2134 | 2136 | ||
2135 | static void atombios_crtc_disable(struct drm_crtc *crtc) |
2137 | static void atombios_crtc_disable(struct drm_crtc *crtc) |
2136 | { |
2138 | { |
2137 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
2139 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
2138 | struct drm_device *dev = crtc->dev; |
2140 | struct drm_device *dev = crtc->dev; |
2139 | struct radeon_device *rdev = dev->dev_private; |
2141 | struct radeon_device *rdev = dev->dev_private; |
2140 | struct radeon_atom_ss ss; |
2142 | struct radeon_atom_ss ss; |
2141 | int i; |
2143 | int i; |
2142 | 2144 | ||
2143 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
2145 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
2144 | if (crtc->primary->fb) { |
2146 | if (crtc->primary->fb) { |
2145 | int r; |
2147 | int r; |
2146 | struct radeon_framebuffer *radeon_fb; |
2148 | struct radeon_framebuffer *radeon_fb; |
2147 | struct radeon_bo *rbo; |
2149 | struct radeon_bo *rbo; |
2148 | 2150 | ||
2149 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
2151 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
2150 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
2152 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
2151 | r = radeon_bo_reserve(rbo, false); |
2153 | r = radeon_bo_reserve(rbo, false); |
2152 | if (unlikely(r)) |
2154 | if (unlikely(r)) |
2153 | DRM_ERROR("failed to reserve rbo before unpin\n"); |
2155 | DRM_ERROR("failed to reserve rbo before unpin\n"); |
2154 | else { |
2156 | else { |
2155 | radeon_bo_unpin(rbo); |
2157 | radeon_bo_unpin(rbo); |
2156 | radeon_bo_unreserve(rbo); |
2158 | radeon_bo_unreserve(rbo); |
2157 | } |
2159 | } |
2158 | } |
2160 | } |
2159 | /* disable the GRPH */ |
2161 | /* disable the GRPH */ |
2160 | if (ASIC_IS_DCE4(rdev)) |
2162 | if (ASIC_IS_DCE4(rdev)) |
2161 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); |
2163 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); |
2162 | else if (ASIC_IS_AVIVO(rdev)) |
2164 | else if (ASIC_IS_AVIVO(rdev)) |
2163 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); |
2165 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); |
2164 | 2166 | ||
2165 | if (ASIC_IS_DCE6(rdev)) |
2167 | if (ASIC_IS_DCE6(rdev)) |
2166 | atombios_powergate_crtc(crtc, ATOM_ENABLE); |
2168 | atombios_powergate_crtc(crtc, ATOM_ENABLE); |
2167 | 2169 | ||
2168 | for (i = 0; i < rdev->num_crtc; i++) { |
2170 | for (i = 0; i < rdev->num_crtc; i++) { |
2169 | if (rdev->mode_info.crtcs[i] && |
2171 | if (rdev->mode_info.crtcs[i] && |
2170 | rdev->mode_info.crtcs[i]->enabled && |
2172 | rdev->mode_info.crtcs[i]->enabled && |
2171 | i != radeon_crtc->crtc_id && |
2173 | i != radeon_crtc->crtc_id && |
2172 | radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { |
2174 | radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { |
2173 | /* one other crtc is using this pll don't turn |
2175 | /* one other crtc is using this pll don't turn |
2174 | * off the pll |
2176 | * off the pll |
2175 | */ |
2177 | */ |
2176 | goto done; |
2178 | goto done; |
2177 | } |
2179 | } |
2178 | } |
2180 | } |
2179 | 2181 | ||
2180 | switch (radeon_crtc->pll_id) { |
2182 | switch (radeon_crtc->pll_id) { |
2181 | case ATOM_PPLL1: |
2183 | case ATOM_PPLL1: |
2182 | case ATOM_PPLL2: |
2184 | case ATOM_PPLL2: |
2183 | /* disable the ppll */ |
2185 | /* disable the ppll */ |
2184 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
2186 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
2185 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
2187 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
2186 | break; |
2188 | break; |
2187 | case ATOM_PPLL0: |
2189 | case ATOM_PPLL0: |
2188 | /* disable the ppll */ |
2190 | /* disable the ppll */ |
2189 | if ((rdev->family == CHIP_ARUBA) || |
2191 | if ((rdev->family == CHIP_ARUBA) || |
2190 | (rdev->family == CHIP_KAVERI) || |
2192 | (rdev->family == CHIP_KAVERI) || |
2191 | (rdev->family == CHIP_BONAIRE) || |
2193 | (rdev->family == CHIP_BONAIRE) || |
2192 | (rdev->family == CHIP_HAWAII)) |
2194 | (rdev->family == CHIP_HAWAII)) |
2193 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
2195 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
2194 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
2196 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
2195 | break; |
2197 | break; |
2196 | default: |
2198 | default: |
2197 | break; |
2199 | break; |
2198 | } |
2200 | } |
2199 | done: |
2201 | done: |
2200 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
2202 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
2201 | radeon_crtc->adjusted_clock = 0; |
2203 | radeon_crtc->adjusted_clock = 0; |
2202 | radeon_crtc->encoder = NULL; |
2204 | radeon_crtc->encoder = NULL; |
2203 | radeon_crtc->connector = NULL; |
2205 | radeon_crtc->connector = NULL; |
2204 | } |
2206 | } |
2205 | 2207 | ||
2206 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
2208 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
2207 | .dpms = atombios_crtc_dpms, |
2209 | .dpms = atombios_crtc_dpms, |
2208 | .mode_fixup = atombios_crtc_mode_fixup, |
2210 | .mode_fixup = atombios_crtc_mode_fixup, |
2209 | .mode_set = atombios_crtc_mode_set, |
2211 | .mode_set = atombios_crtc_mode_set, |
2210 | .mode_set_base = atombios_crtc_set_base, |
2212 | .mode_set_base = atombios_crtc_set_base, |
2211 | .mode_set_base_atomic = atombios_crtc_set_base_atomic, |
2213 | .mode_set_base_atomic = atombios_crtc_set_base_atomic, |
2212 | .prepare = atombios_crtc_prepare, |
2214 | .prepare = atombios_crtc_prepare, |
2213 | .commit = atombios_crtc_commit, |
2215 | .commit = atombios_crtc_commit, |
2214 | .load_lut = radeon_crtc_load_lut, |
2216 | .load_lut = radeon_crtc_load_lut, |
2215 | .disable = atombios_crtc_disable, |
2217 | .disable = atombios_crtc_disable, |
2216 | }; |
2218 | }; |
2217 | 2219 | ||
2218 | void radeon_atombios_init_crtc(struct drm_device *dev, |
2220 | void radeon_atombios_init_crtc(struct drm_device *dev, |
2219 | struct radeon_crtc *radeon_crtc) |
2221 | struct radeon_crtc *radeon_crtc) |
2220 | { |
2222 | { |
2221 | struct radeon_device *rdev = dev->dev_private; |
2223 | struct radeon_device *rdev = dev->dev_private; |
2222 | 2224 | ||
2223 | if (ASIC_IS_DCE4(rdev)) { |
2225 | if (ASIC_IS_DCE4(rdev)) { |
2224 | switch (radeon_crtc->crtc_id) { |
2226 | switch (radeon_crtc->crtc_id) { |
2225 | case 0: |
2227 | case 0: |
2226 | default: |
2228 | default: |
2227 | radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; |
2229 | radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; |
2228 | break; |
2230 | break; |
2229 | case 1: |
2231 | case 1: |
2230 | radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; |
2232 | radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; |
2231 | break; |
2233 | break; |
2232 | case 2: |
2234 | case 2: |
2233 | radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; |
2235 | radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; |
2234 | break; |
2236 | break; |
2235 | case 3: |
2237 | case 3: |
2236 | radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; |
2238 | radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; |
2237 | break; |
2239 | break; |
2238 | case 4: |
2240 | case 4: |
2239 | radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; |
2241 | radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; |
2240 | break; |
2242 | break; |
2241 | case 5: |
2243 | case 5: |
2242 | radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; |
2244 | radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; |
2243 | break; |
2245 | break; |
2244 | } |
2246 | } |
2245 | } else { |
2247 | } else { |
2246 | if (radeon_crtc->crtc_id == 1) |
2248 | if (radeon_crtc->crtc_id == 1) |
2247 | radeon_crtc->crtc_offset = |
2249 | radeon_crtc->crtc_offset = |
2248 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
2250 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
2249 | else |
2251 | else |
2250 | radeon_crtc->crtc_offset = 0; |
2252 | radeon_crtc->crtc_offset = 0; |
2251 | } |
2253 | } |
2252 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
2254 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
2253 | radeon_crtc->adjusted_clock = 0; |
2255 | radeon_crtc->adjusted_clock = 0; |
2254 | radeon_crtc->encoder = NULL; |
2256 | radeon_crtc->encoder = NULL; |
2255 | radeon_crtc->connector = NULL; |
2257 | radeon_crtc->connector = NULL; |
2256 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
2258 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
2257 | }>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>>=> |
2259 | }>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>>=> |