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| Rev 2997 | Rev 3031 | ||
|---|---|---|---|
| Line 1694... | Line 1694... | ||
| 1694 | return ATOM_PPLL1; |
1694 | return ATOM_PPLL1; |
| 1695 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1695 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
| 1696 | return ATOM_PPLL2; |
1696 | return ATOM_PPLL2; |
| 1697 | DRM_ERROR("unable to allocate a PPLL\n"); |
1697 | DRM_ERROR("unable to allocate a PPLL\n"); |
| 1698 | return ATOM_PPLL_INVALID; |
1698 | return ATOM_PPLL_INVALID; |
| 1699 | } else { |
- | |
| 1700 | if (ASIC_IS_AVIVO(rdev)) { |
1699 | } else if (ASIC_IS_AVIVO(rdev)) { |
| 1701 | /* in DP mode, the DP ref clock can come from either PPLL |
1700 | /* in DP mode, the DP ref clock can come from either PPLL |
| 1702 | * depending on the asic: |
1701 | * depending on the asic: |
| 1703 | * DCE3: PPLL1 or PPLL2 |
1702 | * DCE3: PPLL1 or PPLL2 |
| 1704 | */ |
1703 | */ |
| 1705 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1704 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
| Line 1713... | Line 1712... | ||
| 1713 | if (pll != ATOM_PPLL_INVALID) |
1712 | if (pll != ATOM_PPLL_INVALID) |
| 1714 | return pll; |
1713 | return pll; |
| 1715 | } |
1714 | } |
| 1716 | /* all other cases */ |
1715 | /* all other cases */ |
| 1717 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1716 | pll_in_use = radeon_get_pll_use_mask(crtc); |
| - | 1717 | /* the order shouldn't matter here, but we probably |
|
| - | 1718 | * need this until we have atomic modeset |
|
| - | 1719 | */ |
|
| - | 1720 | if (rdev->flags & RADEON_IS_IGP) { |
|
| 1718 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1721 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
| 1719 | return ATOM_PPLL1; |
1722 | return ATOM_PPLL1; |
| 1720 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1723 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
| 1721 | return ATOM_PPLL2; |
1724 | return ATOM_PPLL2; |
| - | 1725 | } else { |
|
| - | 1726 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
|
| - | 1727 | return ATOM_PPLL2; |
|
| - | 1728 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
|
| - | 1729 | return ATOM_PPLL1; |
|
| - | 1730 | } |
|
| 1722 | DRM_ERROR("unable to allocate a PPLL\n"); |
1731 | DRM_ERROR("unable to allocate a PPLL\n"); |
| 1723 | return ATOM_PPLL_INVALID; |
1732 | return ATOM_PPLL_INVALID; |
| 1724 | } else { |
1733 | } else { |
| 1725 | /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ |
1734 | /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ |
| 1726 | return radeon_crtc->crtc_id; |
1735 | return radeon_crtc->crtc_id; |
| 1727 | } |
1736 | } |
| 1728 | } |
1737 | } |
| 1729 | } |
- | |
| Line 1730... | Line 1738... | ||
| 1730 | 1738 | ||
| 1731 | void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) |
1739 | void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) |
| 1732 | { |
1740 | { |
| 1733 | /* always set DCPLL */ |
1741 | /* always set DCPLL */ |