WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/atombios_crtc.c

 #include "radeon_fixed.h"
 #include "radeon.h"
 #include "atom.h"
 #include "atom-bits.h"
-/* evil but including atombios.h is much worse */
-bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
-				SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
 				int32_t *pixel_clock);
 static void atombios_overscan_setup(struct drm_crtc *crtc,
 				    struct drm_display_mode *mode,
 				    struct drm_display_mode *adjusted_mode)
+{
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	switch (mode) {
+	case DRM_MODE_DPMS_ON:
-	case DRM_MODE_DPMS_ON:
+		atombios_enable_crtc(crtc, 1);
 		if (ASIC_IS_DCE3(rdev))
-			atombios_enable_crtc_memreq(crtc, 1);
-		atombios_enable_crtc(crtc, 1);
+			atombios_enable_crtc_memreq(crtc, 1);
 		atombios_blank_crtc(crtc, 0);
 		break;
 	case DRM_MODE_DPMS_STANDBY:
 	case DRM_MODE_DPMS_SUSPEND:
 	case DRM_MODE_DPMS_OFF:
-		atombios_blank_crtc(crtc, 1);
-		atombios_enable_crtc(crtc, 0);
+		atombios_blank_crtc(crtc, 1);
 		if (ASIC_IS_DCE3(rdev))
+			atombios_enable_crtc_memreq(crtc, 0);
-			atombios_enable_crtc_memreq(crtc, 0);
+		atombios_enable_crtc(crtc, 0);
 		break;
+	}
 	if (mode != DRM_MODE_DPMS_OFF) {
-		radeon_crtc_load_lut(crtc);
+         radeon_crtc_load_lut(crtc);
+	}
+}
 static void
+atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
-atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
+			     struct drm_display_mode *mode)
 			     SET_CRTC_USING_DTD_TIMING_PARAMETERS * crtc_param)
-{
+	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
+	struct radeon_device *rdev = dev->dev_private;
+	SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
-	struct radeon_device *rdev = dev->dev_private;
+	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
-	SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param;
+	u16 misc = 0;
-	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
+	memset(&args, 0, sizeof(args));
-	conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size);
+	args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
-	conv_param.usH_Blanking_Time =
+	args.usH_Blanking_Time =
+		cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
-	    cpu_to_le16(crtc_param->usH_Blanking_Time);
+	args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
+	args.usV_Blanking_Time =
-	conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size);
+	    cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
+	args.usH_SyncOffset =
-	conv_param.usV_Blanking_Time =
+		cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
+	args.usH_SyncWidth =
-	    cpu_to_le16(crtc_param->usV_Blanking_Time);
+		cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
+	args.usV_SyncOffset =
-	conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset);
+		cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
+	args.usV_SyncWidth =
+		cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
+	/*args.ucH_Border = mode->hborder;*/
+	/*args.ucV_Border = mode->vborder;*/
+	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+		misc |= ATOM_VSYNC_POLARITY;
+	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
+		misc |= ATOM_HSYNC_POLARITY;
+	if (mode->flags & DRM_MODE_FLAG_CSYNC)
+		misc |= ATOM_COMPOSITESYNC;
+	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
-	conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
+		misc |= ATOM_INTERLACE;
-	conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset);
+	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
-	conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
+		misc |= ATOM_DOUBLE_CLOCK_MODE;
-	conv_param.susModeMiscInfo.usAccess =
-	    cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
+	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
-	conv_param.ucCRTC = crtc_param->ucCRTC;
+	args.ucCRTC = radeon_crtc->crtc_id;
-	printk("executing set crtc dtd timing\n");
-	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
+	printk("executing set crtc dtd timing\n");
+	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+}
-void atombios_crtc_set_timing(struct drm_crtc *crtc,
+static void atombios_crtc_set_timing(struct drm_crtc *crtc,
-			      SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *
+				     struct drm_display_mode *mode)
+{
+	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+	struct drm_device *dev = crtc->dev;
+	struct radeon_device *rdev = dev->dev_private;
+	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
+	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
+	u16 misc = 0;
+	memset(&args, 0, sizeof(args));
+	args.usH_Total = cpu_to_le16(mode->crtc_htotal);
+	args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
+	args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
+	args.usH_SyncWidth =
+		cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
+	args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
+	args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
+	args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
+	args.usV_SyncWidth =
+		cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
+	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+		misc |= ATOM_VSYNC_POLARITY;
+	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
+		misc |= ATOM_HSYNC_POLARITY;
-			      crtc_param)
-{
-	struct drm_device *dev = crtc->dev;
-	struct radeon_device *rdev = dev->dev_private;
-	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param;
-	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
-	conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total);
-	conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp);
+	if (mode->flags & DRM_MODE_FLAG_CSYNC)
-	conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart);
-	conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
+		misc |= ATOM_COMPOSITESYNC;
-	conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total);
-	conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp);
-	conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart);
-	conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
-	conv_param.susModeMiscInfo.usAccess =
-	    cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
+	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
-	conv_param.ucCRTC = crtc_param->ucCRTC;
+		misc |= ATOM_INTERLACE;
+	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
+		misc |= ATOM_DOUBLE_CLOCK_MODE;
+	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
+	args.ucCRTC = radeon_crtc->crtc_id;
+	printk("executing set crtc timing\n");
+	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+}
+static void atombios_set_ss(struct drm_crtc *crtc, int enable)
+{
+	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+	struct drm_device *dev = crtc->dev;
+	struct radeon_device *rdev = dev->dev_private;
+	struct drm_encoder *encoder = NULL;
+	struct radeon_encoder *radeon_encoder = NULL;
+	struct radeon_encoder_atom_dig *dig = NULL;
+	int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
+	ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION args;
+	ENABLE_LVDS_SS_PARAMETERS legacy_args;
+	uint16_t percentage = 0;
+	uint8_t type = 0, step = 0, delay = 0, range = 0;
+	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+		if (encoder->crtc == crtc) {
+			radeon_encoder = to_radeon_encoder(encoder);
+			/* only enable spread spectrum on LVDS */
+			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+				dig = radeon_encoder->enc_priv;
+				if (dig && dig->ss) {
+					percentage = dig->ss->percentage;
+					type = dig->ss->type;
+					step = dig->ss->step;
+					delay = dig->ss->delay;
+					range = dig->ss->range;
+				} else if (enable)
+					return;
+			} else if (enable)
+				return;
+			break;
+		}
+	}
+	if (!radeon_encoder)
+		return;
+	if (ASIC_IS_AVIVO(rdev)) {
+		memset(&args, 0, sizeof(args));
+		args.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
+		args.ucSpreadSpectrumType = type;
+		args.ucSpreadSpectrumStep = step;
+		args.ucSpreadSpectrumDelay = delay;
+		args.ucSpreadSpectrumRange = range;
+		args.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+		args.ucEnable = enable;
+		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+	} else {
-	conv_param.ucOverscanRight = crtc_param->ucOverscanRight;
+		memset(&legacy_args, 0, sizeof(legacy_args));
-	conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft;
+		legacy_args.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
-	conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom;
+		legacy_args.ucSpreadSpectrumType = type;
-	conv_param.ucOverscanTop = crtc_param->ucOverscanTop;
+		legacy_args.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
-	conv_param.ucReserved = crtc_param->ucReserved;
+		legacy_args.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
 		legacy_args.ucEnable = enable;
-	printk("executing set crtc timing\n");
+		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&legacy_args);
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
+}
 void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
+{
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
+	struct drm_encoder *encoder = NULL;
-	struct drm_encoder *encoder = NULL;
+	struct radeon_encoder *radeon_encoder = NULL;
-	struct radeon_encoder *radeon_encoder = NULL;
+	uint8_t frev, crev;
-	uint8_t frev, crev;
+	int index;
-	int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+	SET_PIXEL_CLOCK_PS_ALLOCATION args;
-	SET_PIXEL_CLOCK_PS_ALLOCATION args;
+	PIXEL_CLOCK_PARAMETERS *spc1_ptr;
-	PIXEL_CLOCK_PARAMETERS *spc1_ptr;
-	PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
-	PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
+	PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
-	uint32_t sclock = mode->clock;
+	PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
-	uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
+	uint32_t pll_clock = mode->clock;
-	struct radeon_pll *pll;
+	uint32_t adjusted_clock;
-	int pll_flags = 0;
+	uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 	struct radeon_pll *pll;
-	memset(&args, 0, sizeof(args));
+	int pll_flags = 0;
-	if (ASIC_IS_AVIVO(rdev)) {
+	memset(&args, 0, sizeof(args));
-		uint32_t ss_cntl;
-		if ((rdev->family == CHIP_RS600) ||
-		    (rdev->family == CHIP_RS690) ||
-		    (rdev->family == CHIP_RS740))
-			pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
-				      RADEON_PLL_PREFER_CLOSEST_LOWER);
-		if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)	/* range limits??? */
 			pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
-		else
+	if (ASIC_IS_AVIVO(rdev)) {
-			pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
+		if ((rdev->family == CHIP_RS600) ||
 		    (rdev->family == CHIP_RS690) ||
 			radeon_encoder = to_radeon_encoder(encoder);
 			break;
+		}
+	}
+	/* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
+	 * accordingly based on the encoder/transmitter to work around
+	 * special hw requirements.
+	 */
+	if (ASIC_IS_DCE3(rdev)) {
+		ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_args;
+		if (!encoder)
+			return;
+		memset(&adjust_pll_args, 0, sizeof(adjust_pll_args));
+		adjust_pll_args.usPixelClock = cpu_to_le16(mode->clock / 10);
+		adjust_pll_args.ucTransmitterID = radeon_encoder->encoder_id;
+		adjust_pll_args.ucEncodeMode = atombios_get_encoder_mode(encoder);
+		index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
+		atom_execute_table(rdev->mode_info.atom_context,
+				   index, (uint32_t *)&adjust_pll_args);
+		adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10;
+	} else {
+		/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
+		if (ASIC_IS_AVIVO(rdev) &&
+		    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
+			adjusted_clock = mode->clock * 2;
+		else
+			adjusted_clock = mode->clock;
+	}
 	if (radeon_crtc->crtc_id == 0)
 		pll = &rdev->clock.p1pll;
 	else
 		pll = &rdev->clock.p2pll;
+	radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
-	radeon_compute_pll(pll, mode->clock, &sclock, &fb_div, &frac_fb_div,
+			   &ref_div, &post_div, pll_flags);
 			   &ref_div, &post_div, pll_flags);
 	index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 			      &crev);
 	switch (frev) {
 	case 1:
 		switch (crev) {
 		case 1:
 			spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput;
-			spc1_ptr->usPixelClock = cpu_to_le16(sclock);
+			spc1_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
 			spc1_ptr->usRefDiv = cpu_to_le16(ref_div);
 			spc1_ptr->ucRefDivSrc = 1;
 			break;
 		case 2:
 			spc2_ptr =
 			    (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput;
-			spc2_ptr->usPixelClock = cpu_to_le16(sclock);
+			spc2_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
 			spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
 			spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
 			spc2_ptr->ucFracFbDiv = frac_fb_div;
 			spc2_ptr->ucPostDiv = post_div;
 			spc2_ptr->ucPpll =
 		case 3:
 			if (!encoder)
 				return;
 			spc3_ptr =
 			    (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput;
-			spc3_ptr->usPixelClock = cpu_to_le16(sclock);
+			spc3_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
 			spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
 			spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
 			spc3_ptr->ucFracFbDiv = frac_fb_div;
 			spc3_ptr->ucPostDiv = post_div;
 			spc3_ptr->ucPpll =
 	if (radeon_crtc->crtc_id == 0)
 		WREG32(AVIVO_D1VGA_CONTROL, 0);
 	else
+		WREG32(AVIVO_D2VGA_CONTROL, 0);
+	if (rdev->family >= CHIP_RV770) {
+		if (radeon_crtc->crtc_id) {
+			WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
+			WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
+		} else {
+			WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
+			WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
+		}
 		WREG32(AVIVO_D2VGA_CONTROL, 0);
 	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 	       (u32) fb_location);
 	WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
 	       radeon_crtc->crtc_offset, (u32) fb_location);
 //   if (old_fb && old_fb != crtc->fb) {
 //       radeon_fb = to_radeon_framebuffer(old_fb);
 //       radeon_gem_object_unpin(radeon_fb->obj);
 //   }
+	/* Bytes per pixel may have changed */
+	radeon_bandwidth_update(rdev);
     LEAVE();
 			   int x, int y, struct drm_framebuffer *old_fb)
+{
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
-	struct drm_encoder *encoder;
-	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
-	int need_tv_timings = 0;
-	bool ret;
-	/* TODO color tiling */
-	memset(&crtc_timing, 0, sizeof(crtc_timing));
-	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
-		/* find tv std */
-		if (encoder->crtc == crtc) {
-			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
-				struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
-				if (tv_dac) {
-					if (tv_dac->tv_std == TV_STD_NTSC ||
-					    tv_dac->tv_std == TV_STD_NTSC_J ||
-					    tv_dac->tv_std == TV_STD_PAL_M)
-						need_tv_timings = 1;
-					else
-						need_tv_timings = 2;
-					break;
-				}
-			}
-		}
-	}
-	crtc_timing.ucCRTC = radeon_crtc->crtc_id;
-	if (need_tv_timings) {
-		ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1,
-						 &crtc_timing, &adjusted_mode->clock);
-		if (ret == false)
-			need_tv_timings = 0;
-	}
-	if (!need_tv_timings) {
-	crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
-	crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
-	crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
-	crtc_timing.usH_SyncWidth =
-	    adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
-	crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
-	crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
-	crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
-	crtc_timing.usV_SyncWidth =
-	    adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
-	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
-		crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
-	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
-		crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
-	if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
-		crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
-	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
-		crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
-	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
-		crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
+	/* TODO color tiling */
+	atombios_set_ss(crtc, 0);
+	atombios_crtc_set_pll(crtc, adjusted_mode);
-	atombios_crtc_set_pll(crtc, adjusted_mode);
+	atombios_set_ss(crtc, 1);
-	atombios_crtc_set_timing(crtc, &crtc_timing);
+	atombios_crtc_set_timing(crtc, adjusted_mode);
 	if (ASIC_IS_AVIVO(rdev))
-		atombios_crtc_set_base(crtc, x, y, old_fb);
-	else {
-		if (radeon_crtc->crtc_id == 0) {
-			SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing;
-			memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing));
-			/* setup FP shadow regs on R4xx */
-			crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id;
-			crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay;
-			crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay;
-			crtc_dtd_timing.usH_Blanking_Time =
-			    adjusted_mode->crtc_hblank_end -
-			    adjusted_mode->crtc_hdisplay;
-			crtc_dtd_timing.usV_Blanking_Time =
-			    adjusted_mode->crtc_vblank_end -
-			    adjusted_mode->crtc_vdisplay;
-			crtc_dtd_timing.usH_SyncOffset =
-			    adjusted_mode->crtc_hsync_start -
-			    adjusted_mode->crtc_hdisplay;
-			crtc_dtd_timing.usV_SyncOffset =
-			    adjusted_mode->crtc_vsync_start -
-			    adjusted_mode->crtc_vdisplay;
-			crtc_dtd_timing.usH_SyncWidth =
-			    adjusted_mode->crtc_hsync_end -
-			    adjusted_mode->crtc_hsync_start;
-			crtc_dtd_timing.usV_SyncWidth =
-			    adjusted_mode->crtc_vsync_end -
-			    adjusted_mode->crtc_vsync_start;
-			/* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */
-			/* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */
-			if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
-				crtc_dtd_timing.susModeMiscInfo.usAccess |=
-				    ATOM_VSYNC_POLARITY;
-			if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
-				crtc_dtd_timing.susModeMiscInfo.usAccess |=
-				    ATOM_HSYNC_POLARITY;
-			if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
-				crtc_dtd_timing.susModeMiscInfo.usAccess |=
-				    ATOM_COMPOSITESYNC;
-			if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
-				crtc_dtd_timing.susModeMiscInfo.usAccess |=
-				    ATOM_INTERLACE;
-			if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
-				crtc_dtd_timing.susModeMiscInfo.usAccess |=
+		atombios_crtc_set_base(crtc, x, y, old_fb);
-				    ATOM_DOUBLE_CLOCK_MODE;
 	else {
-			atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing);
+		if (radeon_crtc->crtc_id == 0)
 			atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
 		radeon_crtc_set_base(crtc, x, y, old_fb);
 		radeon_legacy_atom_set_surface(crtc);
-	}
 	atombios_overscan_setup(crtc, mode, adjusted_mode);
-	atombios_scaler_setup(crtc);
+	atombios_overscan_setup(crtc, mode, adjusted_mode);
-	radeon_bandwidth_update(rdev);
+	atombios_scaler_setup(crtc);
 	return 0;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/atombios_crtc.c – Rev 1246 → 1268