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1 | /* |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
13 | * all copies or substantial portions of the Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: Dave Airlie |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
24 | * Alex Deucher |
25 | */ |
25 | */ |
26 | #include |
26 | #include |
27 | #include |
27 | #include |
28 | #include |
28 | #include |
29 | #include "radeon_fixed.h" |
29 | #include "radeon_fixed.h" |
30 | #include "radeon.h" |
30 | #include "radeon.h" |
31 | #include "atom.h" |
31 | #include "atom.h" |
32 | #include "atom-bits.h" |
32 | #include "atom-bits.h" |
33 | 33 | ||
34 | /* evil but including atombios.h is much worse */ |
34 | /* evil but including atombios.h is much worse */ |
35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
36 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, |
36 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, |
37 | int32_t *pixel_clock); |
37 | int32_t *pixel_clock); |
38 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
38 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
39 | struct drm_display_mode *mode, |
39 | struct drm_display_mode *mode, |
40 | struct drm_display_mode *adjusted_mode) |
40 | struct drm_display_mode *adjusted_mode) |
41 | { |
41 | { |
42 | struct drm_device *dev = crtc->dev; |
42 | struct drm_device *dev = crtc->dev; |
43 | struct radeon_device *rdev = dev->dev_private; |
43 | struct radeon_device *rdev = dev->dev_private; |
44 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
44 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
45 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; |
45 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; |
46 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); |
46 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); |
47 | int a1, a2; |
47 | int a1, a2; |
48 | 48 | ||
49 | memset(&args, 0, sizeof(args)); |
49 | memset(&args, 0, sizeof(args)); |
50 | 50 | ||
51 | args.usOverscanRight = 0; |
51 | args.usOverscanRight = 0; |
52 | args.usOverscanLeft = 0; |
52 | args.usOverscanLeft = 0; |
53 | args.usOverscanBottom = 0; |
53 | args.usOverscanBottom = 0; |
54 | args.usOverscanTop = 0; |
54 | args.usOverscanTop = 0; |
55 | args.ucCRTC = radeon_crtc->crtc_id; |
55 | args.ucCRTC = radeon_crtc->crtc_id; |
56 | 56 | ||
57 | switch (radeon_crtc->rmx_type) { |
57 | switch (radeon_crtc->rmx_type) { |
58 | case RMX_CENTER: |
58 | case RMX_CENTER: |
59 | args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
59 | args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
60 | args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
60 | args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
61 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
61 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
62 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
62 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
63 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
63 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
64 | break; |
64 | break; |
65 | case RMX_ASPECT: |
65 | case RMX_ASPECT: |
66 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
66 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
67 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
67 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
68 | 68 | ||
69 | if (a1 > a2) { |
69 | if (a1 > a2) { |
70 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
70 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
71 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
71 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
72 | } else if (a2 > a1) { |
72 | } else if (a2 > a1) { |
73 | args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
73 | args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
74 | args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
74 | args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
75 | } |
75 | } |
76 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
76 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
77 | break; |
77 | break; |
78 | case RMX_FULL: |
78 | case RMX_FULL: |
79 | default: |
79 | default: |
80 | args.usOverscanRight = 0; |
80 | args.usOverscanRight = 0; |
81 | args.usOverscanLeft = 0; |
81 | args.usOverscanLeft = 0; |
82 | args.usOverscanBottom = 0; |
82 | args.usOverscanBottom = 0; |
83 | args.usOverscanTop = 0; |
83 | args.usOverscanTop = 0; |
84 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
84 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
85 | break; |
85 | break; |
86 | } |
86 | } |
87 | } |
87 | } |
88 | 88 | ||
89 | static void atombios_scaler_setup(struct drm_crtc *crtc) |
89 | static void atombios_scaler_setup(struct drm_crtc *crtc) |
90 | { |
90 | { |
91 | struct drm_device *dev = crtc->dev; |
91 | struct drm_device *dev = crtc->dev; |
92 | struct radeon_device *rdev = dev->dev_private; |
92 | struct radeon_device *rdev = dev->dev_private; |
93 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
93 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
94 | ENABLE_SCALER_PS_ALLOCATION args; |
94 | ENABLE_SCALER_PS_ALLOCATION args; |
95 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
95 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
96 | 96 | ||
97 | /* fixme - fill in enc_priv for atom dac */ |
97 | /* fixme - fill in enc_priv for atom dac */ |
98 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
98 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
99 | bool is_tv = false, is_cv = false; |
99 | bool is_tv = false, is_cv = false; |
100 | struct drm_encoder *encoder; |
100 | struct drm_encoder *encoder; |
101 | 101 | ||
102 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
102 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
103 | return; |
103 | return; |
104 | 104 | ||
105 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
105 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
106 | /* find tv std */ |
106 | /* find tv std */ |
107 | if (encoder->crtc == crtc) { |
107 | if (encoder->crtc == crtc) { |
108 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
108 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
109 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
109 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
110 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
110 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
111 | tv_std = tv_dac->tv_std; |
111 | tv_std = tv_dac->tv_std; |
112 | is_tv = true; |
112 | is_tv = true; |
113 | } |
113 | } |
114 | } |
114 | } |
115 | } |
115 | } |
116 | 116 | ||
117 | memset(&args, 0, sizeof(args)); |
117 | memset(&args, 0, sizeof(args)); |
118 | 118 | ||
119 | args.ucScaler = radeon_crtc->crtc_id; |
119 | args.ucScaler = radeon_crtc->crtc_id; |
120 | 120 | ||
121 | if (is_tv) { |
121 | if (is_tv) { |
122 | switch (tv_std) { |
122 | switch (tv_std) { |
123 | case TV_STD_NTSC: |
123 | case TV_STD_NTSC: |
124 | default: |
124 | default: |
125 | args.ucTVStandard = ATOM_TV_NTSC; |
125 | args.ucTVStandard = ATOM_TV_NTSC; |
126 | break; |
126 | break; |
127 | case TV_STD_PAL: |
127 | case TV_STD_PAL: |
128 | args.ucTVStandard = ATOM_TV_PAL; |
128 | args.ucTVStandard = ATOM_TV_PAL; |
129 | break; |
129 | break; |
130 | case TV_STD_PAL_M: |
130 | case TV_STD_PAL_M: |
131 | args.ucTVStandard = ATOM_TV_PALM; |
131 | args.ucTVStandard = ATOM_TV_PALM; |
132 | break; |
132 | break; |
133 | case TV_STD_PAL_60: |
133 | case TV_STD_PAL_60: |
134 | args.ucTVStandard = ATOM_TV_PAL60; |
134 | args.ucTVStandard = ATOM_TV_PAL60; |
135 | break; |
135 | break; |
136 | case TV_STD_NTSC_J: |
136 | case TV_STD_NTSC_J: |
137 | args.ucTVStandard = ATOM_TV_NTSCJ; |
137 | args.ucTVStandard = ATOM_TV_NTSCJ; |
138 | break; |
138 | break; |
139 | case TV_STD_SCART_PAL: |
139 | case TV_STD_SCART_PAL: |
140 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ |
140 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ |
141 | break; |
141 | break; |
142 | case TV_STD_SECAM: |
142 | case TV_STD_SECAM: |
143 | args.ucTVStandard = ATOM_TV_SECAM; |
143 | args.ucTVStandard = ATOM_TV_SECAM; |
144 | break; |
144 | break; |
145 | case TV_STD_PAL_CN: |
145 | case TV_STD_PAL_CN: |
146 | args.ucTVStandard = ATOM_TV_PALCN; |
146 | args.ucTVStandard = ATOM_TV_PALCN; |
147 | break; |
147 | break; |
148 | } |
148 | } |
149 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
149 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
150 | } else if (is_cv) { |
150 | } else if (is_cv) { |
151 | args.ucTVStandard = ATOM_TV_CV; |
151 | args.ucTVStandard = ATOM_TV_CV; |
152 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
152 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
153 | } else { |
153 | } else { |
154 | switch (radeon_crtc->rmx_type) { |
154 | switch (radeon_crtc->rmx_type) { |
155 | case RMX_FULL: |
155 | case RMX_FULL: |
156 | args.ucEnable = ATOM_SCALER_EXPANSION; |
156 | args.ucEnable = ATOM_SCALER_EXPANSION; |
157 | break; |
157 | break; |
158 | case RMX_CENTER: |
158 | case RMX_CENTER: |
159 | args.ucEnable = ATOM_SCALER_CENTER; |
159 | args.ucEnable = ATOM_SCALER_CENTER; |
160 | break; |
160 | break; |
161 | case RMX_ASPECT: |
161 | case RMX_ASPECT: |
162 | args.ucEnable = ATOM_SCALER_EXPANSION; |
162 | args.ucEnable = ATOM_SCALER_EXPANSION; |
163 | break; |
163 | break; |
164 | default: |
164 | default: |
165 | if (ASIC_IS_AVIVO(rdev)) |
165 | if (ASIC_IS_AVIVO(rdev)) |
166 | args.ucEnable = ATOM_SCALER_DISABLE; |
166 | args.ucEnable = ATOM_SCALER_DISABLE; |
167 | else |
167 | else |
168 | args.ucEnable = ATOM_SCALER_CENTER; |
168 | args.ucEnable = ATOM_SCALER_CENTER; |
169 | break; |
169 | break; |
170 | } |
170 | } |
171 | } |
171 | } |
172 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
172 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
173 | if ((is_tv || is_cv) |
173 | if ((is_tv || is_cv) |
174 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { |
174 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { |
175 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); |
175 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); |
176 | } |
176 | } |
177 | } |
177 | } |
178 | 178 | ||
179 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
179 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
180 | { |
180 | { |
181 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
181 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
182 | struct drm_device *dev = crtc->dev; |
182 | struct drm_device *dev = crtc->dev; |
183 | struct radeon_device *rdev = dev->dev_private; |
183 | struct radeon_device *rdev = dev->dev_private; |
184 | int index = |
184 | int index = |
185 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); |
185 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); |
186 | ENABLE_CRTC_PS_ALLOCATION args; |
186 | ENABLE_CRTC_PS_ALLOCATION args; |
187 | 187 | ||
188 | memset(&args, 0, sizeof(args)); |
188 | memset(&args, 0, sizeof(args)); |
189 | 189 | ||
190 | args.ucCRTC = radeon_crtc->crtc_id; |
190 | args.ucCRTC = radeon_crtc->crtc_id; |
191 | args.ucEnable = lock; |
191 | args.ucEnable = lock; |
192 | 192 | ||
193 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
193 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
194 | } |
194 | } |
195 | 195 | ||
196 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) |
196 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) |
197 | { |
197 | { |
198 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
198 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
199 | struct drm_device *dev = crtc->dev; |
199 | struct drm_device *dev = crtc->dev; |
200 | struct radeon_device *rdev = dev->dev_private; |
200 | struct radeon_device *rdev = dev->dev_private; |
201 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); |
201 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); |
202 | ENABLE_CRTC_PS_ALLOCATION args; |
202 | ENABLE_CRTC_PS_ALLOCATION args; |
203 | 203 | ||
204 | memset(&args, 0, sizeof(args)); |
204 | memset(&args, 0, sizeof(args)); |
205 | 205 | ||
206 | args.ucCRTC = radeon_crtc->crtc_id; |
206 | args.ucCRTC = radeon_crtc->crtc_id; |
207 | args.ucEnable = state; |
207 | args.ucEnable = state; |
208 | 208 | ||
209 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
209 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
210 | } |
210 | } |
211 | 211 | ||
212 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) |
212 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) |
213 | { |
213 | { |
214 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
214 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
215 | struct drm_device *dev = crtc->dev; |
215 | struct drm_device *dev = crtc->dev; |
216 | struct radeon_device *rdev = dev->dev_private; |
216 | struct radeon_device *rdev = dev->dev_private; |
217 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); |
217 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); |
218 | ENABLE_CRTC_PS_ALLOCATION args; |
218 | ENABLE_CRTC_PS_ALLOCATION args; |
219 | 219 | ||
220 | memset(&args, 0, sizeof(args)); |
220 | memset(&args, 0, sizeof(args)); |
221 | 221 | ||
222 | args.ucCRTC = radeon_crtc->crtc_id; |
222 | args.ucCRTC = radeon_crtc->crtc_id; |
223 | args.ucEnable = state; |
223 | args.ucEnable = state; |
224 | 224 | ||
225 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
225 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
226 | } |
226 | } |
227 | 227 | ||
228 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
228 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
229 | { |
229 | { |
230 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
230 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
231 | struct drm_device *dev = crtc->dev; |
231 | struct drm_device *dev = crtc->dev; |
232 | struct radeon_device *rdev = dev->dev_private; |
232 | struct radeon_device *rdev = dev->dev_private; |
233 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
233 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
234 | BLANK_CRTC_PS_ALLOCATION args; |
234 | BLANK_CRTC_PS_ALLOCATION args; |
235 | 235 | ||
236 | memset(&args, 0, sizeof(args)); |
236 | memset(&args, 0, sizeof(args)); |
237 | 237 | ||
238 | args.ucCRTC = radeon_crtc->crtc_id; |
238 | args.ucCRTC = radeon_crtc->crtc_id; |
239 | args.ucBlanking = state; |
239 | args.ucBlanking = state; |
240 | 240 | ||
241 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
241 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
242 | } |
242 | } |
243 | 243 | ||
244 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
244 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
245 | { |
245 | { |
246 | struct drm_device *dev = crtc->dev; |
246 | struct drm_device *dev = crtc->dev; |
247 | struct radeon_device *rdev = dev->dev_private; |
247 | struct radeon_device *rdev = dev->dev_private; |
248 | 248 | ||
249 | switch (mode) { |
249 | switch (mode) { |
250 | case DRM_MODE_DPMS_ON: |
250 | case DRM_MODE_DPMS_ON: |
251 | if (ASIC_IS_DCE3(rdev)) |
251 | if (ASIC_IS_DCE3(rdev)) |
252 | atombios_enable_crtc_memreq(crtc, 1); |
252 | atombios_enable_crtc_memreq(crtc, 1); |
253 | atombios_enable_crtc(crtc, 1); |
253 | atombios_enable_crtc(crtc, 1); |
254 | atombios_blank_crtc(crtc, 0); |
254 | atombios_blank_crtc(crtc, 0); |
255 | break; |
255 | break; |
256 | case DRM_MODE_DPMS_STANDBY: |
256 | case DRM_MODE_DPMS_STANDBY: |
257 | case DRM_MODE_DPMS_SUSPEND: |
257 | case DRM_MODE_DPMS_SUSPEND: |
258 | case DRM_MODE_DPMS_OFF: |
258 | case DRM_MODE_DPMS_OFF: |
259 | atombios_blank_crtc(crtc, 1); |
259 | atombios_blank_crtc(crtc, 1); |
260 | atombios_enable_crtc(crtc, 0); |
260 | atombios_enable_crtc(crtc, 0); |
261 | if (ASIC_IS_DCE3(rdev)) |
261 | if (ASIC_IS_DCE3(rdev)) |
262 | atombios_enable_crtc_memreq(crtc, 0); |
262 | atombios_enable_crtc_memreq(crtc, 0); |
263 | break; |
263 | break; |
264 | } |
264 | } |
265 | 265 | ||
266 | if (mode != DRM_MODE_DPMS_OFF) { |
266 | if (mode != DRM_MODE_DPMS_OFF) { |
267 | radeon_crtc_load_lut(crtc); |
267 | radeon_crtc_load_lut(crtc); |
268 | } |
268 | } |
269 | } |
269 | } |
270 | 270 | ||
271 | static void |
271 | static void |
272 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
272 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
273 | SET_CRTC_USING_DTD_TIMING_PARAMETERS * crtc_param) |
273 | SET_CRTC_USING_DTD_TIMING_PARAMETERS * crtc_param) |
274 | { |
274 | { |
275 | struct drm_device *dev = crtc->dev; |
275 | struct drm_device *dev = crtc->dev; |
276 | struct radeon_device *rdev = dev->dev_private; |
276 | struct radeon_device *rdev = dev->dev_private; |
277 | SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param; |
277 | SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param; |
278 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
278 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
279 | 279 | ||
280 | conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size); |
280 | conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size); |
281 | conv_param.usH_Blanking_Time = |
281 | conv_param.usH_Blanking_Time = |
282 | cpu_to_le16(crtc_param->usH_Blanking_Time); |
282 | cpu_to_le16(crtc_param->usH_Blanking_Time); |
283 | conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size); |
283 | conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size); |
284 | conv_param.usV_Blanking_Time = |
284 | conv_param.usV_Blanking_Time = |
285 | cpu_to_le16(crtc_param->usV_Blanking_Time); |
285 | cpu_to_le16(crtc_param->usV_Blanking_Time); |
286 | conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset); |
286 | conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset); |
287 | conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); |
287 | conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); |
288 | conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset); |
288 | conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset); |
289 | conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); |
289 | conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); |
290 | conv_param.susModeMiscInfo.usAccess = |
290 | conv_param.susModeMiscInfo.usAccess = |
291 | cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); |
291 | cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); |
292 | conv_param.ucCRTC = crtc_param->ucCRTC; |
292 | conv_param.ucCRTC = crtc_param->ucCRTC; |
293 | 293 | ||
294 | printk("executing set crtc dtd timing\n"); |
294 | printk("executing set crtc dtd timing\n"); |
295 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param); |
295 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param); |
296 | } |
296 | } |
297 | 297 | ||
298 | void atombios_crtc_set_timing(struct drm_crtc *crtc, |
298 | void atombios_crtc_set_timing(struct drm_crtc *crtc, |
299 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION * |
299 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION * |
300 | crtc_param) |
300 | crtc_param) |
301 | { |
301 | { |
302 | struct drm_device *dev = crtc->dev; |
302 | struct drm_device *dev = crtc->dev; |
303 | struct radeon_device *rdev = dev->dev_private; |
303 | struct radeon_device *rdev = dev->dev_private; |
304 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param; |
304 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param; |
305 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
305 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
306 | 306 | ||
307 | conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total); |
307 | conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total); |
308 | conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp); |
308 | conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp); |
309 | conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart); |
309 | conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart); |
310 | conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); |
310 | conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); |
311 | conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total); |
311 | conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total); |
312 | conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp); |
312 | conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp); |
313 | conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart); |
313 | conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart); |
314 | conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); |
314 | conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); |
315 | conv_param.susModeMiscInfo.usAccess = |
315 | conv_param.susModeMiscInfo.usAccess = |
316 | cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); |
316 | cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); |
317 | conv_param.ucCRTC = crtc_param->ucCRTC; |
317 | conv_param.ucCRTC = crtc_param->ucCRTC; |
318 | conv_param.ucOverscanRight = crtc_param->ucOverscanRight; |
318 | conv_param.ucOverscanRight = crtc_param->ucOverscanRight; |
319 | conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft; |
319 | conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft; |
320 | conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom; |
320 | conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom; |
321 | conv_param.ucOverscanTop = crtc_param->ucOverscanTop; |
321 | conv_param.ucOverscanTop = crtc_param->ucOverscanTop; |
322 | conv_param.ucReserved = crtc_param->ucReserved; |
322 | conv_param.ucReserved = crtc_param->ucReserved; |
323 | 323 | ||
324 | printk("executing set crtc timing\n"); |
324 | printk("executing set crtc timing\n"); |
325 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param); |
325 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param); |
326 | } |
326 | } |
327 | 327 | ||
328 | void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
328 | void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
329 | { |
329 | { |
330 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
330 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
331 | struct drm_device *dev = crtc->dev; |
331 | struct drm_device *dev = crtc->dev; |
332 | struct radeon_device *rdev = dev->dev_private; |
332 | struct radeon_device *rdev = dev->dev_private; |
333 | struct drm_encoder *encoder = NULL; |
333 | struct drm_encoder *encoder = NULL; |
334 | struct radeon_encoder *radeon_encoder = NULL; |
334 | struct radeon_encoder *radeon_encoder = NULL; |
335 | uint8_t frev, crev; |
335 | uint8_t frev, crev; |
336 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
336 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
337 | SET_PIXEL_CLOCK_PS_ALLOCATION args; |
337 | SET_PIXEL_CLOCK_PS_ALLOCATION args; |
338 | PIXEL_CLOCK_PARAMETERS *spc1_ptr; |
338 | PIXEL_CLOCK_PARAMETERS *spc1_ptr; |
339 | PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr; |
339 | PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr; |
340 | PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr; |
340 | PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr; |
341 | uint32_t sclock = mode->clock; |
341 | uint32_t sclock = mode->clock; |
342 | uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
342 | uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
343 | struct radeon_pll *pll; |
343 | struct radeon_pll *pll; |
344 | int pll_flags = 0; |
344 | int pll_flags = 0; |
345 | 345 | ||
346 | memset(&args, 0, sizeof(args)); |
346 | memset(&args, 0, sizeof(args)); |
347 | 347 | ||
348 | if (ASIC_IS_AVIVO(rdev)) { |
348 | if (ASIC_IS_AVIVO(rdev)) { |
349 | uint32_t ss_cntl; |
349 | uint32_t ss_cntl; |
350 | 350 | ||
351 | if ((rdev->family == CHIP_RS600) || |
351 | if ((rdev->family == CHIP_RS600) || |
352 | (rdev->family == CHIP_RS690) || |
352 | (rdev->family == CHIP_RS690) || |
353 | (rdev->family == CHIP_RS740)) |
353 | (rdev->family == CHIP_RS740)) |
354 | pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV | |
354 | pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV | |
355 | RADEON_PLL_PREFER_CLOSEST_LOWER); |
355 | RADEON_PLL_PREFER_CLOSEST_LOWER); |
356 | 356 | ||
357 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
357 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
358 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
358 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
359 | else |
359 | else |
360 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
360 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
361 | 361 | ||
362 | /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */ |
362 | /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */ |
363 | if (radeon_crtc->crtc_id == 0) { |
363 | if (radeon_crtc->crtc_id == 0) { |
364 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); |
364 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); |
365 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1); |
365 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1); |
366 | } else { |
366 | } else { |
367 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); |
367 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); |
368 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1); |
368 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1); |
369 | } |
369 | } |
370 | } else { |
370 | } else { |
371 | pll_flags |= RADEON_PLL_LEGACY; |
371 | pll_flags |= RADEON_PLL_LEGACY; |
372 | 372 | ||
373 | if (mode->clock > 200000) /* range limits??? */ |
373 | if (mode->clock > 200000) /* range limits??? */ |
374 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
374 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
375 | else |
375 | else |
376 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
376 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
377 | 377 | ||
378 | } |
378 | } |
379 | 379 | ||
380 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
380 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
381 | if (encoder->crtc == crtc) { |
381 | if (encoder->crtc == crtc) { |
382 | if (!ASIC_IS_AVIVO(rdev)) { |
382 | if (!ASIC_IS_AVIVO(rdev)) { |
383 | if (encoder->encoder_type != |
383 | if (encoder->encoder_type != |
384 | DRM_MODE_ENCODER_DAC) |
384 | DRM_MODE_ENCODER_DAC) |
385 | pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
385 | pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
386 | if (!ASIC_IS_AVIVO(rdev) |
386 | if (!ASIC_IS_AVIVO(rdev) |
387 | && (encoder->encoder_type == |
387 | && (encoder->encoder_type == |
388 | DRM_MODE_ENCODER_LVDS)) |
388 | DRM_MODE_ENCODER_LVDS)) |
389 | pll_flags |= RADEON_PLL_USE_REF_DIV; |
389 | pll_flags |= RADEON_PLL_USE_REF_DIV; |
390 | } |
390 | } |
391 | radeon_encoder = to_radeon_encoder(encoder); |
391 | radeon_encoder = to_radeon_encoder(encoder); |
392 | break; |
392 | break; |
393 | } |
393 | } |
394 | } |
394 | } |
395 | 395 | ||
396 | if (radeon_crtc->crtc_id == 0) |
396 | if (radeon_crtc->crtc_id == 0) |
397 | pll = &rdev->clock.p1pll; |
397 | pll = &rdev->clock.p1pll; |
398 | else |
398 | else |
399 | pll = &rdev->clock.p2pll; |
399 | pll = &rdev->clock.p2pll; |
400 | 400 | ||
401 | radeon_compute_pll(pll, mode->clock, &sclock, &fb_div, &frac_fb_div, |
401 | radeon_compute_pll(pll, mode->clock, &sclock, &fb_div, &frac_fb_div, |
402 | &ref_div, &post_div, pll_flags); |
402 | &ref_div, &post_div, pll_flags); |
403 | 403 | ||
404 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
404 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
405 | &crev); |
405 | &crev); |
406 | 406 | ||
407 | switch (frev) { |
407 | switch (frev) { |
408 | case 1: |
408 | case 1: |
409 | switch (crev) { |
409 | switch (crev) { |
410 | case 1: |
410 | case 1: |
411 | spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput; |
411 | spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput; |
412 | spc1_ptr->usPixelClock = cpu_to_le16(sclock); |
412 | spc1_ptr->usPixelClock = cpu_to_le16(sclock); |
413 | spc1_ptr->usRefDiv = cpu_to_le16(ref_div); |
413 | spc1_ptr->usRefDiv = cpu_to_le16(ref_div); |
414 | spc1_ptr->usFbDiv = cpu_to_le16(fb_div); |
414 | spc1_ptr->usFbDiv = cpu_to_le16(fb_div); |
415 | spc1_ptr->ucFracFbDiv = frac_fb_div; |
415 | spc1_ptr->ucFracFbDiv = frac_fb_div; |
416 | spc1_ptr->ucPostDiv = post_div; |
416 | spc1_ptr->ucPostDiv = post_div; |
417 | spc1_ptr->ucPpll = |
417 | spc1_ptr->ucPpll = |
418 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
418 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
419 | spc1_ptr->ucCRTC = radeon_crtc->crtc_id; |
419 | spc1_ptr->ucCRTC = radeon_crtc->crtc_id; |
420 | spc1_ptr->ucRefDivSrc = 1; |
420 | spc1_ptr->ucRefDivSrc = 1; |
421 | break; |
421 | break; |
422 | case 2: |
422 | case 2: |
423 | spc2_ptr = |
423 | spc2_ptr = |
424 | (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput; |
424 | (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput; |
425 | spc2_ptr->usPixelClock = cpu_to_le16(sclock); |
425 | spc2_ptr->usPixelClock = cpu_to_le16(sclock); |
426 | spc2_ptr->usRefDiv = cpu_to_le16(ref_div); |
426 | spc2_ptr->usRefDiv = cpu_to_le16(ref_div); |
427 | spc2_ptr->usFbDiv = cpu_to_le16(fb_div); |
427 | spc2_ptr->usFbDiv = cpu_to_le16(fb_div); |
428 | spc2_ptr->ucFracFbDiv = frac_fb_div; |
428 | spc2_ptr->ucFracFbDiv = frac_fb_div; |
429 | spc2_ptr->ucPostDiv = post_div; |
429 | spc2_ptr->ucPostDiv = post_div; |
430 | spc2_ptr->ucPpll = |
430 | spc2_ptr->ucPpll = |
431 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
431 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
432 | spc2_ptr->ucCRTC = radeon_crtc->crtc_id; |
432 | spc2_ptr->ucCRTC = radeon_crtc->crtc_id; |
433 | spc2_ptr->ucRefDivSrc = 1; |
433 | spc2_ptr->ucRefDivSrc = 1; |
434 | break; |
434 | break; |
435 | case 3: |
435 | case 3: |
436 | if (!encoder) |
436 | if (!encoder) |
437 | return; |
437 | return; |
438 | spc3_ptr = |
438 | spc3_ptr = |
439 | (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput; |
439 | (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput; |
440 | spc3_ptr->usPixelClock = cpu_to_le16(sclock); |
440 | spc3_ptr->usPixelClock = cpu_to_le16(sclock); |
441 | spc3_ptr->usRefDiv = cpu_to_le16(ref_div); |
441 | spc3_ptr->usRefDiv = cpu_to_le16(ref_div); |
442 | spc3_ptr->usFbDiv = cpu_to_le16(fb_div); |
442 | spc3_ptr->usFbDiv = cpu_to_le16(fb_div); |
443 | spc3_ptr->ucFracFbDiv = frac_fb_div; |
443 | spc3_ptr->ucFracFbDiv = frac_fb_div; |
444 | spc3_ptr->ucPostDiv = post_div; |
444 | spc3_ptr->ucPostDiv = post_div; |
445 | spc3_ptr->ucPpll = |
445 | spc3_ptr->ucPpll = |
446 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
446 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
447 | spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2); |
447 | spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2); |
448 | spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id; |
448 | spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id; |
449 | spc3_ptr->ucEncoderMode = |
449 | spc3_ptr->ucEncoderMode = |
450 | atombios_get_encoder_mode(encoder); |
450 | atombios_get_encoder_mode(encoder); |
451 | break; |
451 | break; |
452 | default: |
452 | default: |
453 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
453 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
454 | return; |
454 | return; |
455 | } |
455 | } |
456 | break; |
456 | break; |
457 | default: |
457 | default: |
458 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
458 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
459 | return; |
459 | return; |
460 | } |
460 | } |
461 | 461 | ||
462 | printk("executing set pll\n"); |
462 | printk("executing set pll\n"); |
463 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
463 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
464 | } |
464 | } |
465 | 465 | ||
466 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
466 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
467 | struct drm_framebuffer *old_fb) |
467 | struct drm_framebuffer *old_fb) |
468 | { |
468 | { |
469 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
469 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
470 | struct drm_device *dev = crtc->dev; |
470 | struct drm_device *dev = crtc->dev; |
471 | struct radeon_device *rdev = dev->dev_private; |
471 | struct radeon_device *rdev = dev->dev_private; |
472 | struct radeon_framebuffer *radeon_fb; |
472 | struct radeon_framebuffer *radeon_fb; |
473 | struct drm_gem_object *obj; |
473 | struct drm_gem_object *obj; |
474 | struct drm_radeon_gem_object *obj_priv; |
474 | struct drm_radeon_gem_object *obj_priv; |
475 | uint64_t fb_location; |
475 | uint64_t fb_location; |
476 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
476 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
477 | 477 | ||
478 | if (!crtc->fb) |
478 | if (!crtc->fb) |
479 | return -EINVAL; |
479 | return -EINVAL; |
480 | 480 | ||
481 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
481 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
482 | 482 | ||
483 | obj = radeon_fb->obj; |
483 | obj = radeon_fb->obj; |
484 | obj_priv = obj->driver_private; |
484 | obj_priv = obj->driver_private; |
485 | 485 | ||
486 | // if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) { |
486 | // if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) { |
487 | // return -EINVAL; |
487 | // return -EINVAL; |
488 | // } |
488 | // } |
489 | 489 | ||
490 | fb_location = 0; //rdev->mc.vram_location; |
490 | fb_location = 0; //rdev->mc.vram_location; |
491 | 491 | ||
492 | 492 | ||
493 | switch (crtc->fb->bits_per_pixel) { |
493 | switch (crtc->fb->bits_per_pixel) { |
494 | case 8: |
494 | case 8: |
495 | fb_format = |
495 | fb_format = |
496 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
496 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
497 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
497 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
498 | break; |
498 | break; |
499 | case 15: |
499 | case 15: |
500 | fb_format = |
500 | fb_format = |
501 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
501 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
502 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
502 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
503 | break; |
503 | break; |
504 | case 16: |
504 | case 16: |
505 | fb_format = |
505 | fb_format = |
506 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
506 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
507 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
507 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
508 | break; |
508 | break; |
509 | case 24: |
509 | case 24: |
510 | case 32: |
510 | case 32: |
511 | fb_format = |
511 | fb_format = |
512 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
512 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
513 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
513 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
514 | break; |
514 | break; |
515 | default: |
515 | default: |
516 | DRM_ERROR("Unsupported screen depth %d\n", |
516 | DRM_ERROR("Unsupported screen depth %d\n", |
517 | crtc->fb->bits_per_pixel); |
517 | crtc->fb->bits_per_pixel); |
518 | return -EINVAL; |
518 | return -EINVAL; |
519 | } |
519 | } |
520 | 520 | ||
521 | // radeon_object_get_tiling_flags(obj->driver_private, |
521 | // radeon_object_get_tiling_flags(obj->driver_private, |
522 | // &tiling_flags, NULL); |
522 | // &tiling_flags, NULL); |
523 | // if (tiling_flags & RADEON_TILING_MACRO) |
523 | // if (tiling_flags & RADEON_TILING_MACRO) |
524 | // fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; |
524 | // fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; |
525 | 525 | ||
526 | // if (tiling_flags & RADEON_TILING_MICRO) |
526 | // if (tiling_flags & RADEON_TILING_MICRO) |
527 | // fb_format |= AVIVO_D1GRPH_TILED; |
527 | // fb_format |= AVIVO_D1GRPH_TILED; |
528 | 528 | ||
529 | if (radeon_crtc->crtc_id == 0) |
529 | if (radeon_crtc->crtc_id == 0) |
530 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
530 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
531 | else |
531 | else |
532 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
532 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
533 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
533 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
534 | (u32) fb_location); |
534 | (u32) fb_location); |
535 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + |
535 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + |
536 | radeon_crtc->crtc_offset, (u32) fb_location); |
536 | radeon_crtc->crtc_offset, (u32) fb_location); |
537 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
537 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
538 | 538 | ||
539 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
539 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
540 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
540 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
541 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
541 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
542 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
542 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
543 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); |
543 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); |
544 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); |
544 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); |
545 | 545 | ||
546 | fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
546 | fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
547 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
547 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
548 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
548 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
549 | 549 | ||
550 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
550 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
551 | crtc->mode.vdisplay); |
551 | crtc->mode.vdisplay); |
552 | x &= ~3; |
552 | x &= ~3; |
553 | y &= ~1; |
553 | y &= ~1; |
554 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, |
554 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, |
555 | (x << 16) | y); |
555 | (x << 16) | y); |
556 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
556 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
557 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
557 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
558 | 558 | ||
559 | if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) |
559 | if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) |
560 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
560 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
561 | AVIVO_D1MODE_INTERLEAVE_EN); |
561 | AVIVO_D1MODE_INTERLEAVE_EN); |
562 | else |
562 | else |
563 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
563 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
564 | 564 | ||
565 | if (old_fb && old_fb != crtc->fb) { |
565 | if (old_fb && old_fb != crtc->fb) { |
566 | // radeon_fb = to_radeon_framebuffer(old_fb); |
566 | // radeon_fb = to_radeon_framebuffer(old_fb); |
567 | // radeon_gem_object_unpin(radeon_fb->obj); |
567 | // radeon_gem_object_unpin(radeon_fb->obj); |
568 | } |
568 | } |
569 | return 0; |
569 | return 0; |
570 | } |
570 | } |
571 | 571 | ||
572 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
572 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
573 | struct drm_display_mode *mode, |
573 | struct drm_display_mode *mode, |
574 | struct drm_display_mode *adjusted_mode, |
574 | struct drm_display_mode *adjusted_mode, |
575 | int x, int y, struct drm_framebuffer *old_fb) |
575 | int x, int y, struct drm_framebuffer *old_fb) |
576 | { |
576 | { |
577 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
577 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
578 | struct drm_device *dev = crtc->dev; |
578 | struct drm_device *dev = crtc->dev; |
579 | struct radeon_device *rdev = dev->dev_private; |
579 | struct radeon_device *rdev = dev->dev_private; |
580 | struct drm_encoder *encoder; |
580 | struct drm_encoder *encoder; |
581 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; |
581 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; |
582 | int need_tv_timings = 0; |
582 | int need_tv_timings = 0; |
583 | bool ret; |
583 | bool ret; |
584 | 584 | ||
585 | /* TODO color tiling */ |
585 | /* TODO color tiling */ |
586 | memset(&crtc_timing, 0, sizeof(crtc_timing)); |
586 | memset(&crtc_timing, 0, sizeof(crtc_timing)); |
587 | 587 | ||
588 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
588 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
589 | /* find tv std */ |
589 | /* find tv std */ |
590 | if (encoder->crtc == crtc) { |
590 | if (encoder->crtc == crtc) { |
591 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
591 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
592 | 592 | ||
593 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
593 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
594 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
594 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
595 | if (tv_dac) { |
595 | if (tv_dac) { |
596 | if (tv_dac->tv_std == TV_STD_NTSC || |
596 | if (tv_dac->tv_std == TV_STD_NTSC || |
597 | tv_dac->tv_std == TV_STD_NTSC_J || |
597 | tv_dac->tv_std == TV_STD_NTSC_J || |
598 | tv_dac->tv_std == TV_STD_PAL_M) |
598 | tv_dac->tv_std == TV_STD_PAL_M) |
599 | need_tv_timings = 1; |
599 | need_tv_timings = 1; |
600 | else |
600 | else |
601 | need_tv_timings = 2; |
601 | need_tv_timings = 2; |
602 | break; |
602 | break; |
603 | } |
603 | } |
604 | } |
604 | } |
605 | } |
605 | } |
606 | } |
606 | } |
607 | 607 | ||
608 | crtc_timing.ucCRTC = radeon_crtc->crtc_id; |
608 | crtc_timing.ucCRTC = radeon_crtc->crtc_id; |
609 | if (need_tv_timings) { |
609 | if (need_tv_timings) { |
610 | ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1, |
610 | ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1, |
611 | &crtc_timing, &adjusted_mode->clock); |
611 | &crtc_timing, &adjusted_mode->clock); |
612 | if (ret == false) |
612 | if (ret == false) |
613 | need_tv_timings = 0; |
613 | need_tv_timings = 0; |
614 | } |
614 | } |
615 | 615 | ||
616 | if (!need_tv_timings) { |
616 | if (!need_tv_timings) { |
617 | crtc_timing.usH_Total = adjusted_mode->crtc_htotal; |
617 | crtc_timing.usH_Total = adjusted_mode->crtc_htotal; |
618 | crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay; |
618 | crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay; |
619 | crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start; |
619 | crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start; |
620 | crtc_timing.usH_SyncWidth = |
620 | crtc_timing.usH_SyncWidth = |
621 | adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; |
621 | adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; |
622 | 622 | ||
623 | crtc_timing.usV_Total = adjusted_mode->crtc_vtotal; |
623 | crtc_timing.usV_Total = adjusted_mode->crtc_vtotal; |
624 | crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay; |
624 | crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay; |
625 | crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start; |
625 | crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start; |
626 | crtc_timing.usV_SyncWidth = |
626 | crtc_timing.usV_SyncWidth = |
627 | adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; |
627 | adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; |
628 | 628 | ||
629 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
629 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
630 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; |
630 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; |
631 | 631 | ||
632 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
632 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
633 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; |
633 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; |
634 | 634 | ||
635 | if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) |
635 | if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) |
636 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC; |
636 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC; |
637 | 637 | ||
638 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
638 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
639 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE; |
639 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE; |
640 | 640 | ||
641 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
641 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
642 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; |
642 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; |
643 | } |
643 | } |
644 | 644 | ||
645 | atombios_crtc_set_pll(crtc, adjusted_mode); |
645 | atombios_crtc_set_pll(crtc, adjusted_mode); |
646 | atombios_crtc_set_timing(crtc, &crtc_timing); |
646 | atombios_crtc_set_timing(crtc, &crtc_timing); |
647 | 647 | ||
648 | if (ASIC_IS_AVIVO(rdev)) |
648 | if (ASIC_IS_AVIVO(rdev)) |
649 | atombios_crtc_set_base(crtc, x, y, old_fb); |
649 | atombios_crtc_set_base(crtc, x, y, old_fb); |
650 | else { |
650 | else { |
651 | if (radeon_crtc->crtc_id == 0) { |
651 | if (radeon_crtc->crtc_id == 0) { |
652 | SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing; |
652 | SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing; |
653 | memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing)); |
653 | memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing)); |
654 | 654 | ||
655 | /* setup FP shadow regs on R4xx */ |
655 | /* setup FP shadow regs on R4xx */ |
656 | crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id; |
656 | crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id; |
657 | crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay; |
657 | crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay; |
658 | crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay; |
658 | crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay; |
659 | crtc_dtd_timing.usH_Blanking_Time = |
659 | crtc_dtd_timing.usH_Blanking_Time = |
660 | adjusted_mode->crtc_hblank_end - |
660 | adjusted_mode->crtc_hblank_end - |
661 | adjusted_mode->crtc_hdisplay; |
661 | adjusted_mode->crtc_hdisplay; |
662 | crtc_dtd_timing.usV_Blanking_Time = |
662 | crtc_dtd_timing.usV_Blanking_Time = |
663 | adjusted_mode->crtc_vblank_end - |
663 | adjusted_mode->crtc_vblank_end - |
664 | adjusted_mode->crtc_vdisplay; |
664 | adjusted_mode->crtc_vdisplay; |
665 | crtc_dtd_timing.usH_SyncOffset = |
665 | crtc_dtd_timing.usH_SyncOffset = |
666 | adjusted_mode->crtc_hsync_start - |
666 | adjusted_mode->crtc_hsync_start - |
667 | adjusted_mode->crtc_hdisplay; |
667 | adjusted_mode->crtc_hdisplay; |
668 | crtc_dtd_timing.usV_SyncOffset = |
668 | crtc_dtd_timing.usV_SyncOffset = |
669 | adjusted_mode->crtc_vsync_start - |
669 | adjusted_mode->crtc_vsync_start - |
670 | adjusted_mode->crtc_vdisplay; |
670 | adjusted_mode->crtc_vdisplay; |
671 | crtc_dtd_timing.usH_SyncWidth = |
671 | crtc_dtd_timing.usH_SyncWidth = |
672 | adjusted_mode->crtc_hsync_end - |
672 | adjusted_mode->crtc_hsync_end - |
673 | adjusted_mode->crtc_hsync_start; |
673 | adjusted_mode->crtc_hsync_start; |
674 | crtc_dtd_timing.usV_SyncWidth = |
674 | crtc_dtd_timing.usV_SyncWidth = |
675 | adjusted_mode->crtc_vsync_end - |
675 | adjusted_mode->crtc_vsync_end - |
676 | adjusted_mode->crtc_vsync_start; |
676 | adjusted_mode->crtc_vsync_start; |
677 | /* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */ |
677 | /* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */ |
678 | /* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */ |
678 | /* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */ |
679 | 679 | ||
680 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
680 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
681 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
681 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
682 | ATOM_VSYNC_POLARITY; |
682 | ATOM_VSYNC_POLARITY; |
683 | 683 | ||
684 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
684 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
685 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
685 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
686 | ATOM_HSYNC_POLARITY; |
686 | ATOM_HSYNC_POLARITY; |
687 | 687 | ||
688 | if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) |
688 | if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) |
689 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
689 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
690 | ATOM_COMPOSITESYNC; |
690 | ATOM_COMPOSITESYNC; |
691 | 691 | ||
692 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
692 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
693 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
693 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
694 | ATOM_INTERLACE; |
694 | ATOM_INTERLACE; |
695 | 695 | ||
696 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
696 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
697 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
697 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
698 | ATOM_DOUBLE_CLOCK_MODE; |
698 | ATOM_DOUBLE_CLOCK_MODE; |
699 | 699 | ||
700 | atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing); |
700 | atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing); |
701 | } |
701 | } |
702 | radeon_crtc_set_base(crtc, x, y, old_fb); |
702 | radeon_crtc_set_base(crtc, x, y, old_fb); |
703 | radeon_legacy_atom_set_surface(crtc); |
703 | radeon_legacy_atom_set_surface(crtc); |
704 | } |
704 | } |
705 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
705 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
706 | atombios_scaler_setup(crtc); |
706 | atombios_scaler_setup(crtc); |
707 | radeon_bandwidth_update(rdev); |
707 | radeon_bandwidth_update(rdev); |
708 | return 0; |
708 | return 0; |
709 | } |
709 | } |
710 | 710 | ||
711 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
711 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
712 | struct drm_display_mode *mode, |
712 | struct drm_display_mode *mode, |
713 | struct drm_display_mode *adjusted_mode) |
713 | struct drm_display_mode *adjusted_mode) |
714 | { |
714 | { |
715 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
715 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
716 | return false; |
716 | return false; |
717 | return true; |
717 | return true; |
718 | } |
718 | } |
719 | 719 | ||
720 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
720 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
721 | { |
721 | { |
722 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
722 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
723 | atombios_lock_crtc(crtc, 1); |
723 | atombios_lock_crtc(crtc, 1); |
724 | } |
724 | } |
725 | 725 | ||
726 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
726 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
727 | { |
727 | { |
728 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
728 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
729 | atombios_lock_crtc(crtc, 0); |
729 | atombios_lock_crtc(crtc, 0); |
730 | } |
730 | } |
731 | 731 | ||
732 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
732 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
733 | .dpms = atombios_crtc_dpms, |
733 | .dpms = atombios_crtc_dpms, |
734 | .mode_fixup = atombios_crtc_mode_fixup, |
734 | .mode_fixup = atombios_crtc_mode_fixup, |
735 | .mode_set = atombios_crtc_mode_set, |
735 | .mode_set = atombios_crtc_mode_set, |
736 | .mode_set_base = atombios_crtc_set_base, |
736 | .mode_set_base = atombios_crtc_set_base, |
737 | .prepare = atombios_crtc_prepare, |
737 | .prepare = atombios_crtc_prepare, |
738 | .commit = atombios_crtc_commit, |
738 | .commit = atombios_crtc_commit, |
- | 739 | .load_lut = radeon_crtc_load_lut, |
|
739 | }; |
740 | }; |
740 | 741 | ||
741 | void radeon_atombios_init_crtc(struct drm_device *dev, |
742 | void radeon_atombios_init_crtc(struct drm_device *dev, |
742 | struct radeon_crtc *radeon_crtc) |
743 | struct radeon_crtc *radeon_crtc) |
743 | { |
744 | { |
744 | if (radeon_crtc->crtc_id == 1) |
745 | if (radeon_crtc->crtc_id == 1) |
745 | radeon_crtc->crtc_offset = |
746 | radeon_crtc->crtc_offset = |
746 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
747 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
747 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
748 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
748 | }><>><>><>=> |
749 | }><>><>><>=> |