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1 | /* |
1 | /* |
2 | * Copyright 2006-2007 Advanced Micro Devices, Inc. |
2 | * Copyright 2006-2007 Advanced Micro Devices, Inc. |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
12 | * all copies or substantial portions of the Software. |
13 | * |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | */ |
21 | */ |
22 | 22 | ||
23 | 23 | ||
24 | /****************************************************************************/ |
24 | /****************************************************************************/ |
25 | /*Portion I: Definitions shared between VBIOS and Driver */ |
25 | /*Portion I: Definitions shared between VBIOS and Driver */ |
26 | /****************************************************************************/ |
26 | /****************************************************************************/ |
27 | 27 | ||
28 | 28 | ||
29 | #ifndef _ATOMBIOS_H |
29 | #ifndef _ATOMBIOS_H |
30 | #define _ATOMBIOS_H |
30 | #define _ATOMBIOS_H |
31 | 31 | ||
32 | #define ATOM_VERSION_MAJOR 0x00020000 |
32 | #define ATOM_VERSION_MAJOR 0x00020000 |
33 | #define ATOM_VERSION_MINOR 0x00000002 |
33 | #define ATOM_VERSION_MINOR 0x00000002 |
34 | 34 | ||
35 | #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) |
35 | #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) |
36 | 36 | ||
37 | /* Endianness should be specified before inclusion, |
37 | /* Endianness should be specified before inclusion, |
38 | * default to little endian |
38 | * default to little endian |
39 | */ |
39 | */ |
40 | #ifndef ATOM_BIG_ENDIAN |
40 | #ifndef ATOM_BIG_ENDIAN |
41 | #error Endian not specified |
41 | #error Endian not specified |
42 | #endif |
42 | #endif |
43 | 43 | ||
44 | #ifdef _H2INC |
44 | #ifdef _H2INC |
45 | #ifndef ULONG |
45 | #ifndef ULONG |
46 | typedef unsigned long ULONG; |
46 | typedef unsigned long ULONG; |
47 | #endif |
47 | #endif |
48 | 48 | ||
49 | #ifndef UCHAR |
49 | #ifndef UCHAR |
50 | typedef unsigned char UCHAR; |
50 | typedef unsigned char UCHAR; |
51 | #endif |
51 | #endif |
52 | 52 | ||
53 | #ifndef USHORT |
53 | #ifndef USHORT |
54 | typedef unsigned short USHORT; |
54 | typedef unsigned short USHORT; |
55 | #endif |
55 | #endif |
56 | #endif |
56 | #endif |
57 | 57 | ||
58 | #define ATOM_DAC_A 0 |
58 | #define ATOM_DAC_A 0 |
59 | #define ATOM_DAC_B 1 |
59 | #define ATOM_DAC_B 1 |
60 | #define ATOM_EXT_DAC 2 |
60 | #define ATOM_EXT_DAC 2 |
61 | 61 | ||
62 | #define ATOM_CRTC1 0 |
62 | #define ATOM_CRTC1 0 |
63 | #define ATOM_CRTC2 1 |
63 | #define ATOM_CRTC2 1 |
64 | #define ATOM_CRTC3 2 |
64 | #define ATOM_CRTC3 2 |
65 | #define ATOM_CRTC4 3 |
65 | #define ATOM_CRTC4 3 |
66 | #define ATOM_CRTC5 4 |
66 | #define ATOM_CRTC5 4 |
67 | #define ATOM_CRTC6 5 |
67 | #define ATOM_CRTC6 5 |
68 | #define ATOM_CRTC_INVALID 0xFF |
68 | #define ATOM_CRTC_INVALID 0xFF |
69 | 69 | ||
70 | #define ATOM_DIGA 0 |
70 | #define ATOM_DIGA 0 |
71 | #define ATOM_DIGB 1 |
71 | #define ATOM_DIGB 1 |
72 | 72 | ||
73 | #define ATOM_PPLL1 0 |
73 | #define ATOM_PPLL1 0 |
74 | #define ATOM_PPLL2 1 |
74 | #define ATOM_PPLL2 1 |
75 | #define ATOM_DCPLL 2 |
75 | #define ATOM_DCPLL 2 |
76 | #define ATOM_PPLL0 2 |
76 | #define ATOM_PPLL0 2 |
77 | #define ATOM_EXT_PLL1 8 |
77 | #define ATOM_EXT_PLL1 8 |
78 | #define ATOM_EXT_PLL2 9 |
78 | #define ATOM_EXT_PLL2 9 |
79 | #define ATOM_EXT_CLOCK 10 |
79 | #define ATOM_EXT_CLOCK 10 |
80 | #define ATOM_PPLL_INVALID 0xFF |
80 | #define ATOM_PPLL_INVALID 0xFF |
81 | 81 | ||
82 | #define ENCODER_REFCLK_SRC_P1PLL 0 |
82 | #define ENCODER_REFCLK_SRC_P1PLL 0 |
83 | #define ENCODER_REFCLK_SRC_P2PLL 1 |
83 | #define ENCODER_REFCLK_SRC_P2PLL 1 |
84 | #define ENCODER_REFCLK_SRC_DCPLL 2 |
84 | #define ENCODER_REFCLK_SRC_DCPLL 2 |
85 | #define ENCODER_REFCLK_SRC_EXTCLK 3 |
85 | #define ENCODER_REFCLK_SRC_EXTCLK 3 |
86 | #define ENCODER_REFCLK_SRC_INVALID 0xFF |
86 | #define ENCODER_REFCLK_SRC_INVALID 0xFF |
87 | 87 | ||
88 | #define ATOM_SCALER1 0 |
88 | #define ATOM_SCALER1 0 |
89 | #define ATOM_SCALER2 1 |
89 | #define ATOM_SCALER2 1 |
90 | 90 | ||
91 | #define ATOM_SCALER_DISABLE 0 |
91 | #define ATOM_SCALER_DISABLE 0 |
92 | #define ATOM_SCALER_CENTER 1 |
92 | #define ATOM_SCALER_CENTER 1 |
93 | #define ATOM_SCALER_EXPANSION 2 |
93 | #define ATOM_SCALER_EXPANSION 2 |
94 | #define ATOM_SCALER_MULTI_EX 3 |
94 | #define ATOM_SCALER_MULTI_EX 3 |
95 | 95 | ||
96 | #define ATOM_DISABLE 0 |
96 | #define ATOM_DISABLE 0 |
97 | #define ATOM_ENABLE 1 |
97 | #define ATOM_ENABLE 1 |
98 | #define ATOM_LCD_BLOFF (ATOM_DISABLE+2) |
98 | #define ATOM_LCD_BLOFF (ATOM_DISABLE+2) |
99 | #define ATOM_LCD_BLON (ATOM_ENABLE+2) |
99 | #define ATOM_LCD_BLON (ATOM_ENABLE+2) |
100 | #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) |
100 | #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) |
101 | #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) |
101 | #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) |
102 | #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) |
102 | #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) |
103 | #define ATOM_ENCODER_INIT (ATOM_DISABLE+7) |
103 | #define ATOM_ENCODER_INIT (ATOM_DISABLE+7) |
- | 104 | #define ATOM_INIT (ATOM_DISABLE+7) |
|
104 | #define ATOM_GET_STATUS (ATOM_DISABLE+8) |
105 | #define ATOM_GET_STATUS (ATOM_DISABLE+8) |
105 | 106 | ||
106 | #define ATOM_BLANKING 1 |
107 | #define ATOM_BLANKING 1 |
107 | #define ATOM_BLANKING_OFF 0 |
108 | #define ATOM_BLANKING_OFF 0 |
108 | 109 | ||
109 | #define ATOM_CURSOR1 0 |
110 | #define ATOM_CURSOR1 0 |
110 | #define ATOM_CURSOR2 1 |
111 | #define ATOM_CURSOR2 1 |
111 | 112 | ||
112 | #define ATOM_ICON1 0 |
113 | #define ATOM_ICON1 0 |
113 | #define ATOM_ICON2 1 |
114 | #define ATOM_ICON2 1 |
114 | 115 | ||
115 | #define ATOM_CRT1 0 |
116 | #define ATOM_CRT1 0 |
116 | #define ATOM_CRT2 1 |
117 | #define ATOM_CRT2 1 |
117 | 118 | ||
118 | #define ATOM_TV_NTSC 1 |
119 | #define ATOM_TV_NTSC 1 |
119 | #define ATOM_TV_NTSCJ 2 |
120 | #define ATOM_TV_NTSCJ 2 |
120 | #define ATOM_TV_PAL 3 |
121 | #define ATOM_TV_PAL 3 |
121 | #define ATOM_TV_PALM 4 |
122 | #define ATOM_TV_PALM 4 |
122 | #define ATOM_TV_PALCN 5 |
123 | #define ATOM_TV_PALCN 5 |
123 | #define ATOM_TV_PALN 6 |
124 | #define ATOM_TV_PALN 6 |
124 | #define ATOM_TV_PAL60 7 |
125 | #define ATOM_TV_PAL60 7 |
125 | #define ATOM_TV_SECAM 8 |
126 | #define ATOM_TV_SECAM 8 |
126 | #define ATOM_TV_CV 16 |
127 | #define ATOM_TV_CV 16 |
127 | 128 | ||
128 | #define ATOM_DAC1_PS2 1 |
129 | #define ATOM_DAC1_PS2 1 |
129 | #define ATOM_DAC1_CV 2 |
130 | #define ATOM_DAC1_CV 2 |
130 | #define ATOM_DAC1_NTSC 3 |
131 | #define ATOM_DAC1_NTSC 3 |
131 | #define ATOM_DAC1_PAL 4 |
132 | #define ATOM_DAC1_PAL 4 |
132 | 133 | ||
133 | #define ATOM_DAC2_PS2 ATOM_DAC1_PS2 |
134 | #define ATOM_DAC2_PS2 ATOM_DAC1_PS2 |
134 | #define ATOM_DAC2_CV ATOM_DAC1_CV |
135 | #define ATOM_DAC2_CV ATOM_DAC1_CV |
135 | #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC |
136 | #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC |
136 | #define ATOM_DAC2_PAL ATOM_DAC1_PAL |
137 | #define ATOM_DAC2_PAL ATOM_DAC1_PAL |
137 | 138 | ||
138 | #define ATOM_PM_ON 0 |
139 | #define ATOM_PM_ON 0 |
139 | #define ATOM_PM_STANDBY 1 |
140 | #define ATOM_PM_STANDBY 1 |
140 | #define ATOM_PM_SUSPEND 2 |
141 | #define ATOM_PM_SUSPEND 2 |
141 | #define ATOM_PM_OFF 3 |
142 | #define ATOM_PM_OFF 3 |
142 | 143 | ||
143 | /* Bit0:{=0:single, =1:dual}, |
144 | /* Bit0:{=0:single, =1:dual}, |
144 | Bit1 {=0:666RGB, =1:888RGB}, |
145 | Bit1 {=0:666RGB, =1:888RGB}, |
145 | Bit2:3:{Grey level} |
146 | Bit2:3:{Grey level} |
146 | Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ |
147 | Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ |
147 | 148 | ||
148 | #define ATOM_PANEL_MISC_DUAL 0x00000001 |
149 | #define ATOM_PANEL_MISC_DUAL 0x00000001 |
149 | #define ATOM_PANEL_MISC_888RGB 0x00000002 |
150 | #define ATOM_PANEL_MISC_888RGB 0x00000002 |
150 | #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C |
151 | #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C |
151 | #define ATOM_PANEL_MISC_FPDI 0x00000010 |
152 | #define ATOM_PANEL_MISC_FPDI 0x00000010 |
152 | #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 |
153 | #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 |
153 | #define ATOM_PANEL_MISC_SPATIAL 0x00000020 |
154 | #define ATOM_PANEL_MISC_SPATIAL 0x00000020 |
154 | #define ATOM_PANEL_MISC_TEMPORAL 0x00000040 |
155 | #define ATOM_PANEL_MISC_TEMPORAL 0x00000040 |
155 | #define ATOM_PANEL_MISC_API_ENABLED 0x00000080 |
156 | #define ATOM_PANEL_MISC_API_ENABLED 0x00000080 |
156 | 157 | ||
157 | 158 | ||
158 | #define MEMTYPE_DDR1 "DDR1" |
159 | #define MEMTYPE_DDR1 "DDR1" |
159 | #define MEMTYPE_DDR2 "DDR2" |
160 | #define MEMTYPE_DDR2 "DDR2" |
160 | #define MEMTYPE_DDR3 "DDR3" |
161 | #define MEMTYPE_DDR3 "DDR3" |
161 | #define MEMTYPE_DDR4 "DDR4" |
162 | #define MEMTYPE_DDR4 "DDR4" |
162 | 163 | ||
163 | #define ASIC_BUS_TYPE_PCI "PCI" |
164 | #define ASIC_BUS_TYPE_PCI "PCI" |
164 | #define ASIC_BUS_TYPE_AGP "AGP" |
165 | #define ASIC_BUS_TYPE_AGP "AGP" |
165 | #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" |
166 | #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" |
166 | 167 | ||
167 | /* Maximum size of that FireGL flag string */ |
168 | /* Maximum size of that FireGL flag string */ |
168 | 169 | ||
169 | #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support |
170 | #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support |
170 | #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) |
171 | #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) |
171 | 172 | ||
172 | #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop |
173 | #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop |
173 | #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING |
174 | #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING |
174 | 175 | ||
175 | #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support |
176 | #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support |
176 | #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) |
177 | #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) |
177 | 178 | ||
178 | #define HW_ASSISTED_I2C_STATUS_FAILURE 2 |
179 | #define HW_ASSISTED_I2C_STATUS_FAILURE 2 |
179 | #define HW_ASSISTED_I2C_STATUS_SUCCESS 1 |
180 | #define HW_ASSISTED_I2C_STATUS_SUCCESS 1 |
180 | 181 | ||
181 | #pragma pack(1) /* BIOS data must use byte aligment */ |
182 | #pragma pack(1) /* BIOS data must use byte aligment */ |
182 | 183 | ||
183 | /* Define offset to location of ROM header. */ |
184 | /* Define offset to location of ROM header. */ |
184 | 185 | ||
185 | #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L |
186 | #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L |
186 | #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L |
187 | #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L |
187 | 188 | ||
188 | #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 |
189 | #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 |
189 | #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ |
190 | #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ |
190 | #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f |
191 | #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f |
191 | #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e |
192 | #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e |
192 | 193 | ||
193 | /* Common header for all ROM Data tables. |
194 | /* Common header for all ROM Data tables. |
194 | Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. |
195 | Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. |
195 | And the pointer actually points to this header. */ |
196 | And the pointer actually points to this header. */ |
196 | 197 | ||
197 | typedef struct _ATOM_COMMON_TABLE_HEADER |
198 | typedef struct _ATOM_COMMON_TABLE_HEADER |
198 | { |
199 | { |
199 | USHORT usStructureSize; |
200 | USHORT usStructureSize; |
200 | UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ |
201 | UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ |
201 | UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ |
202 | UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ |
202 | /*Image can't be updated, while Driver needs to carry the new table! */ |
203 | /*Image can't be updated, while Driver needs to carry the new table! */ |
203 | }ATOM_COMMON_TABLE_HEADER; |
204 | }ATOM_COMMON_TABLE_HEADER; |
204 | 205 | ||
205 | /****************************************************************************/ |
206 | /****************************************************************************/ |
206 | // Structure stores the ROM header. |
207 | // Structure stores the ROM header. |
207 | /****************************************************************************/ |
208 | /****************************************************************************/ |
208 | typedef struct _ATOM_ROM_HEADER |
209 | typedef struct _ATOM_ROM_HEADER |
209 | { |
210 | { |
210 | ATOM_COMMON_TABLE_HEADER sHeader; |
211 | ATOM_COMMON_TABLE_HEADER sHeader; |
211 | UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, |
212 | UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, |
212 | atombios should init it as "ATOM", don't change the position */ |
213 | atombios should init it as "ATOM", don't change the position */ |
213 | USHORT usBiosRuntimeSegmentAddress; |
214 | USHORT usBiosRuntimeSegmentAddress; |
214 | USHORT usProtectedModeInfoOffset; |
215 | USHORT usProtectedModeInfoOffset; |
215 | USHORT usConfigFilenameOffset; |
216 | USHORT usConfigFilenameOffset; |
216 | USHORT usCRC_BlockOffset; |
217 | USHORT usCRC_BlockOffset; |
217 | USHORT usBIOS_BootupMessageOffset; |
218 | USHORT usBIOS_BootupMessageOffset; |
218 | USHORT usInt10Offset; |
219 | USHORT usInt10Offset; |
219 | USHORT usPciBusDevInitCode; |
220 | USHORT usPciBusDevInitCode; |
220 | USHORT usIoBaseAddress; |
221 | USHORT usIoBaseAddress; |
221 | USHORT usSubsystemVendorID; |
222 | USHORT usSubsystemVendorID; |
222 | USHORT usSubsystemID; |
223 | USHORT usSubsystemID; |
223 | USHORT usPCI_InfoOffset; |
224 | USHORT usPCI_InfoOffset; |
224 | USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ |
225 | USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ |
225 | USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ |
226 | USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ |
226 | UCHAR ucExtendedFunctionCode; |
227 | UCHAR ucExtendedFunctionCode; |
227 | UCHAR ucReserved; |
228 | UCHAR ucReserved; |
228 | }ATOM_ROM_HEADER; |
229 | }ATOM_ROM_HEADER; |
229 | 230 | ||
230 | /*==============================Command Table Portion==================================== */ |
231 | /*==============================Command Table Portion==================================== */ |
231 | 232 | ||
232 | #ifdef UEFI_BUILD |
233 | #ifdef UEFI_BUILD |
233 | #define UTEMP USHORT |
234 | #define UTEMP USHORT |
234 | #define USHORT void* |
235 | #define USHORT void* |
235 | #endif |
236 | #endif |
236 | 237 | ||
237 | /****************************************************************************/ |
238 | /****************************************************************************/ |
238 | // Structures used in Command.mtb |
239 | // Structures used in Command.mtb |
239 | /****************************************************************************/ |
240 | /****************************************************************************/ |
240 | typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ |
241 | typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ |
241 | USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 |
242 | USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 |
242 | USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON |
243 | USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON |
243 | USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init |
244 | USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init |
244 | USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios |
245 | USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios |
245 | USHORT DIGxEncoderControl; //Only used by Bios |
246 | USHORT DIGxEncoderControl; //Only used by Bios |
246 | USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init |
247 | USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init |
247 | USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 |
248 | USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 |
248 | USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed |
249 | USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed |
249 | USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 |
250 | USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 |
250 | USHORT GPIOPinControl; //Atomic Table, only used by Bios |
251 | USHORT GPIOPinControl; //Atomic Table, only used by Bios |
251 | USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 |
252 | USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 |
252 | USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 |
253 | USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 |
253 | USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 |
254 | USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 |
254 | USHORT DynamicClockGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init |
255 | USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init |
255 | USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock |
256 | USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock |
256 | USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock |
257 | USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock |
257 | USHORT MemoryPLLInit; |
258 | USHORT MemoryPLLInit; //Atomic Table, used only by Bios |
258 | USHORT AdjustDisplayPll; //only used by Bios |
259 | USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. |
259 | USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock |
260 | USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock |
260 | USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios |
261 | USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios |
261 | USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios |
262 | USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios |
262 | USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 |
263 | USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 |
263 | USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 |
264 | USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 |
264 | USHORT LCD1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
265 | USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 |
265 | USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
266 | USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
266 | USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
267 | USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
267 | USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
268 | USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
268 | USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead |
269 | USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead |
269 | USHORT GetConditionalGoldenSetting; //only used by Bios |
270 | USHORT GetConditionalGoldenSetting; //Only used by Bios |
270 | USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 |
271 | USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 |
271 | USHORT TMDSAEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 |
272 | USHORT PatchMCSetting; //only used by BIOS |
272 | USHORT LVDSEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 |
273 | USHORT MC_SEQ_Control; //only used by BIOS |
273 | USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead |
274 | USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead |
274 | USHORT EnableScaler; //Atomic Table, used only by Bios |
275 | USHORT EnableScaler; //Atomic Table, used only by Bios |
275 | USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 |
276 | USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 |
276 | USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 |
277 | USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 |
277 | USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 |
278 | USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 |
278 | USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 |
279 | USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 |
279 | USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios |
280 | USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios |
280 | USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 |
281 | USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 |
281 | USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 |
282 | USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 |
282 | USHORT SetCRTC_Replication; //Atomic Table, used only by Bios |
283 | USHORT SetCRTC_Replication; //Atomic Table, used only by Bios |
283 | USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 |
284 | USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 |
284 | USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios |
285 | USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios |
285 | USHORT UpdateCRTC_DoubleBufferRegisters; |
286 | USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios |
286 | USHORT LUT_AutoFill; //Atomic Table, only used by Bios |
287 | USHORT LUT_AutoFill; //Atomic Table, only used by Bios |
287 | USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios |
288 | USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios |
288 | USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 |
289 | USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 |
289 | USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 |
290 | USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 |
290 | USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 |
291 | USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 |
291 | USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 |
292 | USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 |
292 | USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
293 | USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
293 | USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios |
294 | USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios |
294 | USHORT MemoryCleanUp; //Atomic Table, only used by Bios |
295 | USHORT MemoryCleanUp; //Atomic Table, only used by Bios |
295 | USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios |
296 | USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios |
296 | USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components |
297 | USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components |
297 | USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components |
298 | USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components |
298 | USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init |
299 | USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init |
299 | USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 |
300 | USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 |
300 | USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock |
301 | USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock |
301 | USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock |
302 | USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock |
302 | USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock |
303 | USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock |
303 | USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios |
304 | USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios |
304 | USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock |
305 | USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock |
305 | USHORT MemoryTraining; //Atomic Table, used only by Bios |
306 | USHORT MemoryTraining; //Atomic Table, used only by Bios |
306 | USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 |
307 | USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 |
307 | USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
308 | USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
308 | USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 |
309 | USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 |
309 | USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
310 | USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
310 | USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
311 | USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 |
311 | USHORT SetupHWAssistedI2CStatus; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" |
312 | USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" |
312 | USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init |
313 | USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init |
313 | USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock |
314 | USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock |
314 | USHORT EnableYUV; //Atomic Table, indirectly used by various SW components,called from EnableVGARender |
315 | USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender |
315 | USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 |
316 | USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 |
316 | USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 |
317 | USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 |
317 | USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 |
318 | USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 |
318 | USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 |
319 | USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 |
319 | USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios |
320 | USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios |
320 | USHORT DPEncoderService; //Function Table,only used by Bios |
321 | USHORT DPEncoderService; //Function Table,only used by Bios |
- | 322 | USHORT GetVoltageInfo; //Function Table,only used by Bios since SI |
|
321 | }ATOM_MASTER_LIST_OF_COMMAND_TABLES; |
323 | }ATOM_MASTER_LIST_OF_COMMAND_TABLES; |
322 | 324 | ||
323 | // For backward compatible |
325 | // For backward compatible |
324 | #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction |
326 | #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction |
- | 327 | #define DPTranslatorControl DIG2EncoderControl |
|
325 | #define UNIPHYTransmitterControl DIG1TransmitterControl |
328 | #define UNIPHYTransmitterControl DIG1TransmitterControl |
326 | #define LVTMATransmitterControl DIG2TransmitterControl |
329 | #define LVTMATransmitterControl DIG2TransmitterControl |
327 | #define SetCRTC_DPM_State GetConditionalGoldenSetting |
330 | #define SetCRTC_DPM_State GetConditionalGoldenSetting |
328 | #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange |
331 | #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange |
329 | #define HPDInterruptService ReadHWAssistedI2CStatus |
332 | #define HPDInterruptService ReadHWAssistedI2CStatus |
330 | #define EnableVGA_Access GetSCLKOverMCLKRatio |
333 | #define EnableVGA_Access GetSCLKOverMCLKRatio |
- | 334 | #define EnableYUV GetDispObjectInfo |
|
- | 335 | #define DynamicClockGating EnableDispPowerGating |
|
- | 336 | #define SetupHWAssistedI2CStatus ComputeMemoryClockParam |
|
- | 337 | ||
- | 338 | #define TMDSAEncoderControl PatchMCSetting |
|
331 | #define GetDispObjectInfo EnableYUV |
339 | #define LVDSEncoderControl MC_SEQ_Control |
- | 340 | #define LCD1OutputControl HW_Misc_Operation |
|
- | 341 | ||
332 | 342 | ||
333 | typedef struct _ATOM_MASTER_COMMAND_TABLE |
343 | typedef struct _ATOM_MASTER_COMMAND_TABLE |
334 | { |
344 | { |
335 | ATOM_COMMON_TABLE_HEADER sHeader; |
345 | ATOM_COMMON_TABLE_HEADER sHeader; |
336 | ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; |
346 | ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; |
337 | }ATOM_MASTER_COMMAND_TABLE; |
347 | }ATOM_MASTER_COMMAND_TABLE; |
338 | 348 | ||
339 | /****************************************************************************/ |
349 | /****************************************************************************/ |
340 | // Structures used in every command table |
350 | // Structures used in every command table |
341 | /****************************************************************************/ |
351 | /****************************************************************************/ |
342 | typedef struct _ATOM_TABLE_ATTRIBUTE |
352 | typedef struct _ATOM_TABLE_ATTRIBUTE |
343 | { |
353 | { |
344 | #if ATOM_BIG_ENDIAN |
354 | #if ATOM_BIG_ENDIAN |
345 | USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag |
355 | USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag |
346 | USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), |
356 | USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), |
347 | USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), |
357 | USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), |
348 | #else |
358 | #else |
349 | USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), |
359 | USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), |
350 | USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), |
360 | USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), |
351 | USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag |
361 | USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag |
352 | #endif |
362 | #endif |
353 | }ATOM_TABLE_ATTRIBUTE; |
363 | }ATOM_TABLE_ATTRIBUTE; |
354 | 364 | ||
355 | typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS |
365 | typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS |
356 | { |
366 | { |
357 | ATOM_TABLE_ATTRIBUTE sbfAccess; |
367 | ATOM_TABLE_ATTRIBUTE sbfAccess; |
358 | USHORT susAccess; |
368 | USHORT susAccess; |
359 | }ATOM_TABLE_ATTRIBUTE_ACCESS; |
369 | }ATOM_TABLE_ATTRIBUTE_ACCESS; |
360 | 370 | ||
361 | /****************************************************************************/ |
371 | /****************************************************************************/ |
362 | // Common header for all command tables. |
372 | // Common header for all command tables. |
363 | // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. |
373 | // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. |
364 | // And the pointer actually points to this header. |
374 | // And the pointer actually points to this header. |
365 | /****************************************************************************/ |
375 | /****************************************************************************/ |
366 | typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER |
376 | typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER |
367 | { |
377 | { |
368 | ATOM_COMMON_TABLE_HEADER CommonHeader; |
378 | ATOM_COMMON_TABLE_HEADER CommonHeader; |
369 | ATOM_TABLE_ATTRIBUTE TableAttribute; |
379 | ATOM_TABLE_ATTRIBUTE TableAttribute; |
370 | }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; |
380 | }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; |
371 | 381 | ||
372 | /****************************************************************************/ |
382 | /****************************************************************************/ |
373 | // Structures used by ComputeMemoryEnginePLLTable |
383 | // Structures used by ComputeMemoryEnginePLLTable |
374 | /****************************************************************************/ |
384 | /****************************************************************************/ |
375 | #define COMPUTE_MEMORY_PLL_PARAM 1 |
385 | #define COMPUTE_MEMORY_PLL_PARAM 1 |
376 | #define COMPUTE_ENGINE_PLL_PARAM 2 |
386 | #define COMPUTE_ENGINE_PLL_PARAM 2 |
377 | #define ADJUST_MC_SETTING_PARAM 3 |
387 | #define ADJUST_MC_SETTING_PARAM 3 |
378 | 388 | ||
379 | /****************************************************************************/ |
389 | /****************************************************************************/ |
380 | // Structures used by AdjustMemoryControllerTable |
390 | // Structures used by AdjustMemoryControllerTable |
381 | /****************************************************************************/ |
391 | /****************************************************************************/ |
382 | typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ |
392 | typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ |
383 | { |
393 | { |
384 | #if ATOM_BIG_ENDIAN |
394 | #if ATOM_BIG_ENDIAN |
385 | ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block |
395 | ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block |
386 | ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] |
396 | ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] |
387 | ULONG ulClockFreq:24; |
397 | ULONG ulClockFreq:24; |
388 | #else |
398 | #else |
389 | ULONG ulClockFreq:24; |
399 | ULONG ulClockFreq:24; |
390 | ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] |
400 | ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] |
391 | ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block |
401 | ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block |
392 | #endif |
402 | #endif |
393 | }ATOM_ADJUST_MEMORY_CLOCK_FREQ; |
403 | }ATOM_ADJUST_MEMORY_CLOCK_FREQ; |
394 | #define POINTER_RETURN_FLAG 0x80 |
404 | #define POINTER_RETURN_FLAG 0x80 |
395 | 405 | ||
396 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS |
406 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS |
397 | { |
407 | { |
398 | ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div |
408 | ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div |
399 | UCHAR ucAction; //0:reserved //1:Memory //2:Engine |
409 | UCHAR ucAction; //0:reserved //1:Memory //2:Engine |
400 | UCHAR ucReserved; //may expand to return larger Fbdiv later |
410 | UCHAR ucReserved; //may expand to return larger Fbdiv later |
401 | UCHAR ucFbDiv; //return value |
411 | UCHAR ucFbDiv; //return value |
402 | UCHAR ucPostDiv; //return value |
412 | UCHAR ucPostDiv; //return value |
403 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; |
413 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; |
404 | 414 | ||
405 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 |
415 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 |
406 | { |
416 | { |
407 | ULONG ulClock; //When return, [23:0] return real clock |
417 | ULONG ulClock; //When return, [23:0] return real clock |
408 | UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register |
418 | UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register |
409 | USHORT usFbDiv; //return Feedback value to be written to register |
419 | USHORT usFbDiv; //return Feedback value to be written to register |
410 | UCHAR ucPostDiv; //return post div to be written to register |
420 | UCHAR ucPostDiv; //return post div to be written to register |
411 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; |
421 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; |
412 | #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS |
422 | #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS |
413 | 423 | ||
414 | 424 | ||
415 | #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value |
425 | #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value |
416 | #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) |
426 | #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) |
417 | #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition |
427 | #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition |
418 | #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change |
428 | #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change |
419 | #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup |
429 | #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup |
420 | #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL |
430 | #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL |
421 | #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK |
431 | #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK |
422 | 432 | ||
423 | #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) |
433 | #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) |
424 | #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition |
434 | #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition |
425 | #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change |
435 | #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change |
426 | #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup |
436 | #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup |
427 | #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL |
437 | #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL |
428 | 438 | ||
429 | typedef struct _ATOM_COMPUTE_CLOCK_FREQ |
439 | typedef struct _ATOM_COMPUTE_CLOCK_FREQ |
430 | { |
440 | { |
431 | #if ATOM_BIG_ENDIAN |
441 | #if ATOM_BIG_ENDIAN |
432 | ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM |
442 | ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM |
433 | ULONG ulClockFreq:24; // in unit of 10kHz |
443 | ULONG ulClockFreq:24; // in unit of 10kHz |
434 | #else |
444 | #else |
435 | ULONG ulClockFreq:24; // in unit of 10kHz |
445 | ULONG ulClockFreq:24; // in unit of 10kHz |
436 | ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM |
446 | ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM |
437 | #endif |
447 | #endif |
438 | }ATOM_COMPUTE_CLOCK_FREQ; |
448 | }ATOM_COMPUTE_CLOCK_FREQ; |
439 | 449 | ||
440 | typedef struct _ATOM_S_MPLL_FB_DIVIDER |
450 | typedef struct _ATOM_S_MPLL_FB_DIVIDER |
441 | { |
451 | { |
442 | USHORT usFbDivFrac; |
452 | USHORT usFbDivFrac; |
443 | USHORT usFbDiv; |
453 | USHORT usFbDiv; |
444 | }ATOM_S_MPLL_FB_DIVIDER; |
454 | }ATOM_S_MPLL_FB_DIVIDER; |
445 | 455 | ||
446 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 |
456 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 |
447 | { |
457 | { |
448 | union |
458 | union |
449 | { |
459 | { |
450 | ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter |
460 | ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter |
451 | ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter |
461 | ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter |
452 | }; |
462 | }; |
453 | UCHAR ucRefDiv; //Output Parameter |
463 | UCHAR ucRefDiv; //Output Parameter |
454 | UCHAR ucPostDiv; //Output Parameter |
464 | UCHAR ucPostDiv; //Output Parameter |
455 | UCHAR ucCntlFlag; //Output Parameter |
465 | UCHAR ucCntlFlag; //Output Parameter |
456 | UCHAR ucReserved; |
466 | UCHAR ucReserved; |
457 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; |
467 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; |
458 | 468 | ||
459 | // ucCntlFlag |
469 | // ucCntlFlag |
460 | #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 |
470 | #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 |
461 | #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 |
471 | #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 |
462 | #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 |
472 | #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 |
463 | #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 |
473 | #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 |
464 | 474 | ||
465 | 475 | ||
466 | // V4 are only used for APU which PLL outside GPU |
476 | // V4 are only used for APU which PLL outside GPU |
467 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 |
477 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 |
468 | { |
478 | { |
469 | #if ATOM_BIG_ENDIAN |
479 | #if ATOM_BIG_ENDIAN |
470 | ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly |
480 | ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly |
471 | ULONG ulClock:24; //Input= target clock, output = actual clock |
481 | ULONG ulClock:24; //Input= target clock, output = actual clock |
472 | #else |
482 | #else |
473 | ULONG ulClock:24; //Input= target clock, output = actual clock |
483 | ULONG ulClock:24; //Input= target clock, output = actual clock |
474 | ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly |
484 | ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly |
475 | #endif |
485 | #endif |
476 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; |
486 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; |
477 | 487 | ||
478 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 |
488 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 |
479 | { |
489 | { |
480 | union |
490 | union |
481 | { |
491 | { |
482 | ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter |
492 | ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter |
483 | ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter |
493 | ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter |
484 | }; |
494 | }; |
485 | UCHAR ucRefDiv; //Output Parameter |
495 | UCHAR ucRefDiv; //Output Parameter |
486 | UCHAR ucPostDiv; //Output Parameter |
496 | UCHAR ucPostDiv; //Output Parameter |
487 | union |
497 | union |
488 | { |
498 | { |
489 | UCHAR ucCntlFlag; //Output Flags |
499 | UCHAR ucCntlFlag; //Output Flags |
490 | UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode |
500 | UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode |
491 | }; |
501 | }; |
492 | UCHAR ucReserved; |
502 | UCHAR ucReserved; |
493 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; |
503 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; |
494 | 504 | ||
495 | // ucInputFlag |
505 | // ucInputFlag |
496 | #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode |
506 | #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode |
- | 507 | ||
- | 508 | // use for ComputeMemoryClockParamTable |
|
- | 509 | typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 |
|
- | 510 | { |
|
- | 511 | union |
|
- | 512 | { |
|
- | 513 | ULONG ulClock; |
|
- | 514 | ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) |
|
- | 515 | }; |
|
- | 516 | UCHAR ucDllSpeed; //Output |
|
- | 517 | UCHAR ucPostDiv; //Output |
|
- | 518 | union{ |
|
- | 519 | UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode |
|
- | 520 | UCHAR ucPllCntlFlag; //Output: |
|
- | 521 | }; |
|
- | 522 | UCHAR ucBWCntl; |
|
- | 523 | }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; |
|
- | 524 | ||
- | 525 | // definition of ucInputFlag |
|
- | 526 | #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 |
|
- | 527 | // definition of ucPllCntlFlag |
|
- | 528 | #define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 |
|
- | 529 | #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 |
|
- | 530 | #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 |
|
- | 531 | #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 |
|
- | 532 | ||
- | 533 | //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL |
|
- | 534 | #define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 |
|
497 | 535 | ||
498 | typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER |
536 | typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER |
499 | { |
537 | { |
500 | ATOM_COMPUTE_CLOCK_FREQ ulClock; |
538 | ATOM_COMPUTE_CLOCK_FREQ ulClock; |
501 | ULONG ulReserved[2]; |
539 | ULONG ulReserved[2]; |
502 | }DYNAMICE_MEMORY_SETTINGS_PARAMETER; |
540 | }DYNAMICE_MEMORY_SETTINGS_PARAMETER; |
503 | 541 | ||
504 | typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER |
542 | typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER |
505 | { |
543 | { |
506 | ATOM_COMPUTE_CLOCK_FREQ ulClock; |
544 | ATOM_COMPUTE_CLOCK_FREQ ulClock; |
507 | ULONG ulMemoryClock; |
545 | ULONG ulMemoryClock; |
508 | ULONG ulReserved; |
546 | ULONG ulReserved; |
509 | }DYNAMICE_ENGINE_SETTINGS_PARAMETER; |
547 | }DYNAMICE_ENGINE_SETTINGS_PARAMETER; |
510 | 548 | ||
511 | /****************************************************************************/ |
549 | /****************************************************************************/ |
512 | // Structures used by SetEngineClockTable |
550 | // Structures used by SetEngineClockTable |
513 | /****************************************************************************/ |
551 | /****************************************************************************/ |
514 | typedef struct _SET_ENGINE_CLOCK_PARAMETERS |
552 | typedef struct _SET_ENGINE_CLOCK_PARAMETERS |
515 | { |
553 | { |
516 | ULONG ulTargetEngineClock; //In 10Khz unit |
554 | ULONG ulTargetEngineClock; //In 10Khz unit |
517 | }SET_ENGINE_CLOCK_PARAMETERS; |
555 | }SET_ENGINE_CLOCK_PARAMETERS; |
518 | 556 | ||
519 | typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION |
557 | typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION |
520 | { |
558 | { |
521 | ULONG ulTargetEngineClock; //In 10Khz unit |
559 | ULONG ulTargetEngineClock; //In 10Khz unit |
522 | COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; |
560 | COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; |
523 | }SET_ENGINE_CLOCK_PS_ALLOCATION; |
561 | }SET_ENGINE_CLOCK_PS_ALLOCATION; |
524 | 562 | ||
525 | /****************************************************************************/ |
563 | /****************************************************************************/ |
526 | // Structures used by SetMemoryClockTable |
564 | // Structures used by SetMemoryClockTable |
527 | /****************************************************************************/ |
565 | /****************************************************************************/ |
528 | typedef struct _SET_MEMORY_CLOCK_PARAMETERS |
566 | typedef struct _SET_MEMORY_CLOCK_PARAMETERS |
529 | { |
567 | { |
530 | ULONG ulTargetMemoryClock; //In 10Khz unit |
568 | ULONG ulTargetMemoryClock; //In 10Khz unit |
531 | }SET_MEMORY_CLOCK_PARAMETERS; |
569 | }SET_MEMORY_CLOCK_PARAMETERS; |
532 | 570 | ||
533 | typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION |
571 | typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION |
534 | { |
572 | { |
535 | ULONG ulTargetMemoryClock; //In 10Khz unit |
573 | ULONG ulTargetMemoryClock; //In 10Khz unit |
536 | COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; |
574 | COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; |
537 | }SET_MEMORY_CLOCK_PS_ALLOCATION; |
575 | }SET_MEMORY_CLOCK_PS_ALLOCATION; |
538 | 576 | ||
539 | /****************************************************************************/ |
577 | /****************************************************************************/ |
540 | // Structures used by ASIC_Init.ctb |
578 | // Structures used by ASIC_Init.ctb |
541 | /****************************************************************************/ |
579 | /****************************************************************************/ |
542 | typedef struct _ASIC_INIT_PARAMETERS |
580 | typedef struct _ASIC_INIT_PARAMETERS |
543 | { |
581 | { |
544 | ULONG ulDefaultEngineClock; //In 10Khz unit |
582 | ULONG ulDefaultEngineClock; //In 10Khz unit |
545 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
583 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
546 | }ASIC_INIT_PARAMETERS; |
584 | }ASIC_INIT_PARAMETERS; |
547 | 585 | ||
548 | typedef struct _ASIC_INIT_PS_ALLOCATION |
586 | typedef struct _ASIC_INIT_PS_ALLOCATION |
549 | { |
587 | { |
550 | ASIC_INIT_PARAMETERS sASICInitClocks; |
588 | ASIC_INIT_PARAMETERS sASICInitClocks; |
551 | SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure |
589 | SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure |
552 | }ASIC_INIT_PS_ALLOCATION; |
590 | }ASIC_INIT_PS_ALLOCATION; |
553 | 591 | ||
554 | /****************************************************************************/ |
592 | /****************************************************************************/ |
555 | // Structure used by DynamicClockGatingTable.ctb |
593 | // Structure used by DynamicClockGatingTable.ctb |
556 | /****************************************************************************/ |
594 | /****************************************************************************/ |
557 | typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS |
595 | typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS |
558 | { |
596 | { |
559 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
597 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
560 | UCHAR ucPadding[3]; |
598 | UCHAR ucPadding[3]; |
561 | }DYNAMIC_CLOCK_GATING_PARAMETERS; |
599 | }DYNAMIC_CLOCK_GATING_PARAMETERS; |
562 | #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS |
600 | #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS |
563 | 601 | ||
564 | /****************************************************************************/ |
602 | /****************************************************************************/ |
- | 603 | // Structure used by EnableDispPowerGatingTable.ctb |
|
- | 604 | /****************************************************************************/ |
|
- | 605 | typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 |
|
- | 606 | { |
|
- | 607 | UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... |
|
- | 608 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
|
- | 609 | UCHAR ucPadding[2]; |
|
- | 610 | }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; |
|
- | 611 | ||
- | 612 | /****************************************************************************/ |
|
565 | // Structure used by EnableASIC_StaticPwrMgtTable.ctb |
613 | // Structure used by EnableASIC_StaticPwrMgtTable.ctb |
566 | /****************************************************************************/ |
614 | /****************************************************************************/ |
567 | typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS |
615 | typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS |
568 | { |
616 | { |
569 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
617 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
570 | UCHAR ucPadding[3]; |
618 | UCHAR ucPadding[3]; |
571 | }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; |
619 | }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; |
572 | #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS |
620 | #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS |
573 | 621 | ||
574 | /****************************************************************************/ |
622 | /****************************************************************************/ |
575 | // Structures used by DAC_LoadDetectionTable.ctb |
623 | // Structures used by DAC_LoadDetectionTable.ctb |
576 | /****************************************************************************/ |
624 | /****************************************************************************/ |
577 | typedef struct _DAC_LOAD_DETECTION_PARAMETERS |
625 | typedef struct _DAC_LOAD_DETECTION_PARAMETERS |
578 | { |
626 | { |
579 | USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} |
627 | USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} |
580 | UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} |
628 | UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} |
581 | UCHAR ucMisc; //Valid only when table revision =1.3 and above |
629 | UCHAR ucMisc; //Valid only when table revision =1.3 and above |
582 | }DAC_LOAD_DETECTION_PARAMETERS; |
630 | }DAC_LOAD_DETECTION_PARAMETERS; |
583 | 631 | ||
584 | // DAC_LOAD_DETECTION_PARAMETERS.ucMisc |
632 | // DAC_LOAD_DETECTION_PARAMETERS.ucMisc |
585 | #define DAC_LOAD_MISC_YPrPb 0x01 |
633 | #define DAC_LOAD_MISC_YPrPb 0x01 |
586 | 634 | ||
587 | typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION |
635 | typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION |
588 | { |
636 | { |
589 | DAC_LOAD_DETECTION_PARAMETERS sDacload; |
637 | DAC_LOAD_DETECTION_PARAMETERS sDacload; |
590 | ULONG Reserved[2];// Don't set this one, allocation for EXT DAC |
638 | ULONG Reserved[2];// Don't set this one, allocation for EXT DAC |
591 | }DAC_LOAD_DETECTION_PS_ALLOCATION; |
639 | }DAC_LOAD_DETECTION_PS_ALLOCATION; |
592 | 640 | ||
593 | /****************************************************************************/ |
641 | /****************************************************************************/ |
594 | // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb |
642 | // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb |
595 | /****************************************************************************/ |
643 | /****************************************************************************/ |
596 | typedef struct _DAC_ENCODER_CONTROL_PARAMETERS |
644 | typedef struct _DAC_ENCODER_CONTROL_PARAMETERS |
597 | { |
645 | { |
598 | USHORT usPixelClock; // in 10KHz; for bios convenient |
646 | USHORT usPixelClock; // in 10KHz; for bios convenient |
599 | UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) |
647 | UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) |
600 | UCHAR ucAction; // 0: turn off encoder |
648 | UCHAR ucAction; // 0: turn off encoder |
601 | // 1: setup and turn on encoder |
649 | // 1: setup and turn on encoder |
602 | // 7: ATOM_ENCODER_INIT Initialize DAC |
650 | // 7: ATOM_ENCODER_INIT Initialize DAC |
603 | }DAC_ENCODER_CONTROL_PARAMETERS; |
651 | }DAC_ENCODER_CONTROL_PARAMETERS; |
604 | 652 | ||
605 | #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS |
653 | #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS |
606 | 654 | ||
607 | /****************************************************************************/ |
655 | /****************************************************************************/ |
608 | // Structures used by DIG1EncoderControlTable |
656 | // Structures used by DIG1EncoderControlTable |
609 | // DIG2EncoderControlTable |
657 | // DIG2EncoderControlTable |
610 | // ExternalEncoderControlTable |
658 | // ExternalEncoderControlTable |
611 | /****************************************************************************/ |
659 | /****************************************************************************/ |
612 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS |
660 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS |
613 | { |
661 | { |
614 | USHORT usPixelClock; // in 10KHz; for bios convenient |
662 | USHORT usPixelClock; // in 10KHz; for bios convenient |
615 | UCHAR ucConfig; |
663 | UCHAR ucConfig; |
616 | // [2] Link Select: |
664 | // [2] Link Select: |
617 | // =0: PHY linkA if bfLane<3 |
665 | // =0: PHY linkA if bfLane<3 |
618 | // =1: PHY linkB if bfLanes<3 |
666 | // =1: PHY linkB if bfLanes<3 |
619 | // =0: PHY linkA+B if bfLanes=3 |
667 | // =0: PHY linkA+B if bfLanes=3 |
620 | // [3] Transmitter Sel |
668 | // [3] Transmitter Sel |
621 | // =0: UNIPHY or PCIEPHY |
669 | // =0: UNIPHY or PCIEPHY |
622 | // =1: LVTMA |
670 | // =1: LVTMA |
623 | UCHAR ucAction; // =0: turn off encoder |
671 | UCHAR ucAction; // =0: turn off encoder |
624 | // =1: turn on encoder |
672 | // =1: turn on encoder |
625 | UCHAR ucEncoderMode; |
673 | UCHAR ucEncoderMode; |
626 | // =0: DP encoder |
674 | // =0: DP encoder |
627 | // =1: LVDS encoder |
675 | // =1: LVDS encoder |
628 | // =2: DVI encoder |
676 | // =2: DVI encoder |
629 | // =3: HDMI encoder |
677 | // =3: HDMI encoder |
630 | // =4: SDVO encoder |
678 | // =4: SDVO encoder |
631 | UCHAR ucLaneNum; // how many lanes to enable |
679 | UCHAR ucLaneNum; // how many lanes to enable |
632 | UCHAR ucReserved[2]; |
680 | UCHAR ucReserved[2]; |
633 | }DIG_ENCODER_CONTROL_PARAMETERS; |
681 | }DIG_ENCODER_CONTROL_PARAMETERS; |
634 | #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS |
682 | #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS |
635 | #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS |
683 | #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS |
636 | 684 | ||
637 | //ucConfig |
685 | //ucConfig |
638 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 |
686 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 |
639 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 |
687 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 |
640 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 |
688 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 |
641 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 |
689 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 |
642 | #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 |
690 | #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 |
643 | #define ATOM_ENCODER_CONFIG_LINKA 0x00 |
691 | #define ATOM_ENCODER_CONFIG_LINKA 0x00 |
644 | #define ATOM_ENCODER_CONFIG_LINKB 0x04 |
692 | #define ATOM_ENCODER_CONFIG_LINKB 0x04 |
645 | #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA |
693 | #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA |
646 | #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB |
694 | #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB |
647 | #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 |
695 | #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 |
648 | #define ATOM_ENCODER_CONFIG_UNIPHY 0x00 |
696 | #define ATOM_ENCODER_CONFIG_UNIPHY 0x00 |
649 | #define ATOM_ENCODER_CONFIG_LVTMA 0x08 |
697 | #define ATOM_ENCODER_CONFIG_LVTMA 0x08 |
650 | #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 |
698 | #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 |
651 | #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 |
699 | #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 |
652 | #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 |
700 | #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 |
653 | // ucAction |
701 | // ucAction |
654 | // ATOM_ENABLE: Enable Encoder |
702 | // ATOM_ENABLE: Enable Encoder |
655 | // ATOM_DISABLE: Disable Encoder |
703 | // ATOM_DISABLE: Disable Encoder |
656 | 704 | ||
657 | //ucEncoderMode |
705 | //ucEncoderMode |
658 | #define ATOM_ENCODER_MODE_DP 0 |
706 | #define ATOM_ENCODER_MODE_DP 0 |
659 | #define ATOM_ENCODER_MODE_LVDS 1 |
707 | #define ATOM_ENCODER_MODE_LVDS 1 |
660 | #define ATOM_ENCODER_MODE_DVI 2 |
708 | #define ATOM_ENCODER_MODE_DVI 2 |
661 | #define ATOM_ENCODER_MODE_HDMI 3 |
709 | #define ATOM_ENCODER_MODE_HDMI 3 |
662 | #define ATOM_ENCODER_MODE_SDVO 4 |
710 | #define ATOM_ENCODER_MODE_SDVO 4 |
663 | #define ATOM_ENCODER_MODE_DP_AUDIO 5 |
711 | #define ATOM_ENCODER_MODE_DP_AUDIO 5 |
664 | #define ATOM_ENCODER_MODE_TV 13 |
712 | #define ATOM_ENCODER_MODE_TV 13 |
665 | #define ATOM_ENCODER_MODE_CV 14 |
713 | #define ATOM_ENCODER_MODE_CV 14 |
666 | #define ATOM_ENCODER_MODE_CRT 15 |
714 | #define ATOM_ENCODER_MODE_CRT 15 |
667 | #define ATOM_ENCODER_MODE_DVO 16 |
715 | #define ATOM_ENCODER_MODE_DVO 16 |
668 | #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 |
716 | #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 |
669 | #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 |
717 | #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 |
670 | 718 | ||
671 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 |
719 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 |
672 | { |
720 | { |
673 | #if ATOM_BIG_ENDIAN |
721 | #if ATOM_BIG_ENDIAN |
674 | UCHAR ucReserved1:2; |
722 | UCHAR ucReserved1:2; |
675 | UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF |
723 | UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF |
676 | UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F |
724 | UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F |
677 | UCHAR ucReserved:1; |
725 | UCHAR ucReserved:1; |
678 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
726 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
679 | #else |
727 | #else |
680 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
728 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
681 | UCHAR ucReserved:1; |
729 | UCHAR ucReserved:1; |
682 | UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F |
730 | UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F |
683 | UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF |
731 | UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF |
684 | UCHAR ucReserved1:2; |
732 | UCHAR ucReserved1:2; |
685 | #endif |
733 | #endif |
686 | }ATOM_DIG_ENCODER_CONFIG_V2; |
734 | }ATOM_DIG_ENCODER_CONFIG_V2; |
687 | 735 | ||
688 | 736 | ||
689 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 |
737 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 |
690 | { |
738 | { |
691 | USHORT usPixelClock; // in 10KHz; for bios convenient |
739 | USHORT usPixelClock; // in 10KHz; for bios convenient |
692 | ATOM_DIG_ENCODER_CONFIG_V2 acConfig; |
740 | ATOM_DIG_ENCODER_CONFIG_V2 acConfig; |
693 | UCHAR ucAction; |
741 | UCHAR ucAction; |
694 | UCHAR ucEncoderMode; |
742 | UCHAR ucEncoderMode; |
695 | // =0: DP encoder |
743 | // =0: DP encoder |
696 | // =1: LVDS encoder |
744 | // =1: LVDS encoder |
697 | // =2: DVI encoder |
745 | // =2: DVI encoder |
698 | // =3: HDMI encoder |
746 | // =3: HDMI encoder |
699 | // =4: SDVO encoder |
747 | // =4: SDVO encoder |
700 | UCHAR ucLaneNum; // how many lanes to enable |
748 | UCHAR ucLaneNum; // how many lanes to enable |
701 | UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS |
749 | UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS |
702 | UCHAR ucReserved; |
750 | UCHAR ucReserved; |
703 | }DIG_ENCODER_CONTROL_PARAMETERS_V2; |
751 | }DIG_ENCODER_CONTROL_PARAMETERS_V2; |
704 | 752 | ||
705 | //ucConfig |
753 | //ucConfig |
706 | #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 |
754 | #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 |
707 | #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 |
755 | #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 |
708 | #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 |
756 | #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 |
709 | #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 |
757 | #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 |
710 | #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 |
758 | #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 |
711 | #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 |
759 | #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 |
712 | #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 |
760 | #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 |
713 | #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 |
761 | #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 |
714 | #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 |
762 | #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 |
715 | #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 |
763 | #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 |
716 | 764 | ||
717 | // ucAction: |
765 | // ucAction: |
718 | // ATOM_DISABLE |
766 | // ATOM_DISABLE |
719 | // ATOM_ENABLE |
767 | // ATOM_ENABLE |
720 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 |
768 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 |
721 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 |
769 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 |
722 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a |
770 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a |
723 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 |
771 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 |
724 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b |
772 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b |
725 | #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c |
773 | #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c |
726 | #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d |
774 | #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d |
727 | #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e |
775 | #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e |
728 | #define ATOM_ENCODER_CMD_SETUP 0x0f |
776 | #define ATOM_ENCODER_CMD_SETUP 0x0f |
729 | #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 |
777 | #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 |
730 | 778 | ||
731 | // ucStatus |
779 | // ucStatus |
732 | #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 |
780 | #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 |
733 | #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 |
781 | #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 |
734 | 782 | ||
735 | //ucTableFormatRevision=1 |
783 | //ucTableFormatRevision=1 |
736 | //ucTableContentRevision=3 |
784 | //ucTableContentRevision=3 |
737 | // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver |
785 | // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver |
738 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 |
786 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 |
739 | { |
787 | { |
740 | #if ATOM_BIG_ENDIAN |
788 | #if ATOM_BIG_ENDIAN |
741 | UCHAR ucReserved1:1; |
789 | UCHAR ucReserved1:1; |
742 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) |
790 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) |
743 | UCHAR ucReserved:3; |
791 | UCHAR ucReserved:3; |
744 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
792 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
745 | #else |
793 | #else |
746 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
794 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
747 | UCHAR ucReserved:3; |
795 | UCHAR ucReserved:3; |
748 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) |
796 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) |
749 | UCHAR ucReserved1:1; |
797 | UCHAR ucReserved1:1; |
750 | #endif |
798 | #endif |
751 | }ATOM_DIG_ENCODER_CONFIG_V3; |
799 | }ATOM_DIG_ENCODER_CONFIG_V3; |
752 | 800 | ||
753 | #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 |
801 | #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 |
754 | #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 |
802 | #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 |
755 | #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 |
803 | #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 |
756 | #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 |
804 | #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 |
757 | #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 |
805 | #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 |
758 | #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 |
806 | #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 |
759 | #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 |
807 | #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 |
760 | #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 |
808 | #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 |
761 | #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 |
809 | #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 |
762 | #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 |
810 | #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 |
763 | 811 | ||
764 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 |
812 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 |
765 | { |
813 | { |
766 | USHORT usPixelClock; // in 10KHz; for bios convenient |
814 | USHORT usPixelClock; // in 10KHz; for bios convenient |
767 | ATOM_DIG_ENCODER_CONFIG_V3 acConfig; |
815 | ATOM_DIG_ENCODER_CONFIG_V3 acConfig; |
768 | UCHAR ucAction; |
816 | UCHAR ucAction; |
769 | union { |
817 | union { |
770 | UCHAR ucEncoderMode; |
818 | UCHAR ucEncoderMode; |
771 | // =0: DP encoder |
819 | // =0: DP encoder |
772 | // =1: LVDS encoder |
820 | // =1: LVDS encoder |
773 | // =2: DVI encoder |
821 | // =2: DVI encoder |
774 | // =3: HDMI encoder |
822 | // =3: HDMI encoder |
775 | // =4: SDVO encoder |
823 | // =4: SDVO encoder |
776 | // =5: DP audio |
824 | // =5: DP audio |
777 | UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE |
825 | UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE |
778 | // =0: external DP |
826 | // =0: external DP |
779 | // =1: internal DP2 |
827 | // =1: internal DP2 |
780 | // =0x11: internal DP1 for NutMeg/Travis DP translator |
828 | // =0x11: internal DP1 for NutMeg/Travis DP translator |
781 | }; |
829 | }; |
782 | UCHAR ucLaneNum; // how many lanes to enable |
830 | UCHAR ucLaneNum; // how many lanes to enable |
783 | UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP |
831 | UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP |
784 | UCHAR ucReserved; |
832 | UCHAR ucReserved; |
785 | }DIG_ENCODER_CONTROL_PARAMETERS_V3; |
833 | }DIG_ENCODER_CONTROL_PARAMETERS_V3; |
786 | 834 | ||
787 | //ucTableFormatRevision=1 |
835 | //ucTableFormatRevision=1 |
788 | //ucTableContentRevision=4 |
836 | //ucTableContentRevision=4 |
789 | // start from NI |
837 | // start from NI |
790 | // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver |
838 | // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver |
791 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 |
839 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 |
792 | { |
840 | { |
793 | #if ATOM_BIG_ENDIAN |
841 | #if ATOM_BIG_ENDIAN |
794 | UCHAR ucReserved1:1; |
842 | UCHAR ucReserved1:1; |
795 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) |
843 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) |
796 | UCHAR ucReserved:2; |
844 | UCHAR ucReserved:2; |
797 | UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version |
845 | UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version |
798 | #else |
846 | #else |
799 | UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version |
847 | UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version |
800 | UCHAR ucReserved:2; |
848 | UCHAR ucReserved:2; |
801 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) |
849 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) |
802 | UCHAR ucReserved1:1; |
850 | UCHAR ucReserved1:1; |
803 | #endif |
851 | #endif |
804 | }ATOM_DIG_ENCODER_CONFIG_V4; |
852 | }ATOM_DIG_ENCODER_CONFIG_V4; |
805 | 853 | ||
806 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 |
854 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 |
807 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 |
855 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 |
808 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 |
856 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 |
809 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 |
857 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 |
- | 858 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 |
|
810 | #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 |
859 | #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 |
811 | #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 |
860 | #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 |
812 | #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 |
861 | #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 |
813 | #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 |
862 | #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 |
814 | #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 |
863 | #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 |
815 | #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 |
864 | #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 |
816 | #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 |
865 | #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 |
- | 866 | #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 |
|
817 | 867 | ||
818 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 |
868 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 |
819 | { |
869 | { |
820 | USHORT usPixelClock; // in 10KHz; for bios convenient |
870 | USHORT usPixelClock; // in 10KHz; for bios convenient |
821 | union{ |
871 | union{ |
822 | ATOM_DIG_ENCODER_CONFIG_V4 acConfig; |
872 | ATOM_DIG_ENCODER_CONFIG_V4 acConfig; |
823 | UCHAR ucConfig; |
873 | UCHAR ucConfig; |
824 | }; |
874 | }; |
825 | UCHAR ucAction; |
875 | UCHAR ucAction; |
826 | union { |
876 | union { |
827 | UCHAR ucEncoderMode; |
877 | UCHAR ucEncoderMode; |
828 | // =0: DP encoder |
878 | // =0: DP encoder |
829 | // =1: LVDS encoder |
879 | // =1: LVDS encoder |
830 | // =2: DVI encoder |
880 | // =2: DVI encoder |
831 | // =3: HDMI encoder |
881 | // =3: HDMI encoder |
832 | // =4: SDVO encoder |
882 | // =4: SDVO encoder |
833 | // =5: DP audio |
883 | // =5: DP audio |
834 | UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE |
884 | UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE |
835 | // =0: external DP |
885 | // =0: external DP |
836 | // =1: internal DP2 |
886 | // =1: internal DP2 |
837 | // =0x11: internal DP1 for NutMeg/Travis DP translator |
887 | // =0x11: internal DP1 for NutMeg/Travis DP translator |
838 | }; |
888 | }; |
839 | UCHAR ucLaneNum; // how many lanes to enable |
889 | UCHAR ucLaneNum; // how many lanes to enable |
840 | UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP |
890 | UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP |
841 | UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version |
891 | UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version |
842 | }DIG_ENCODER_CONTROL_PARAMETERS_V4; |
892 | }DIG_ENCODER_CONTROL_PARAMETERS_V4; |
843 | 893 | ||
844 | // define ucBitPerColor: |
894 | // define ucBitPerColor: |
845 | #define PANEL_BPC_UNDEFINE 0x00 |
895 | #define PANEL_BPC_UNDEFINE 0x00 |
846 | #define PANEL_6BIT_PER_COLOR 0x01 |
896 | #define PANEL_6BIT_PER_COLOR 0x01 |
847 | #define PANEL_8BIT_PER_COLOR 0x02 |
897 | #define PANEL_8BIT_PER_COLOR 0x02 |
848 | #define PANEL_10BIT_PER_COLOR 0x03 |
898 | #define PANEL_10BIT_PER_COLOR 0x03 |
849 | #define PANEL_12BIT_PER_COLOR 0x04 |
899 | #define PANEL_12BIT_PER_COLOR 0x04 |
850 | #define PANEL_16BIT_PER_COLOR 0x05 |
900 | #define PANEL_16BIT_PER_COLOR 0x05 |
851 | 901 | ||
852 | //define ucPanelMode |
902 | //define ucPanelMode |
853 | #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 |
903 | #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 |
854 | #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 |
904 | #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 |
855 | #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 |
905 | #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 |
856 | 906 | ||
857 | /****************************************************************************/ |
907 | /****************************************************************************/ |
858 | // Structures used by UNIPHYTransmitterControlTable |
908 | // Structures used by UNIPHYTransmitterControlTable |
859 | // LVTMATransmitterControlTable |
909 | // LVTMATransmitterControlTable |
860 | // DVOOutputControlTable |
910 | // DVOOutputControlTable |
861 | /****************************************************************************/ |
911 | /****************************************************************************/ |
862 | typedef struct _ATOM_DP_VS_MODE |
912 | typedef struct _ATOM_DP_VS_MODE |
863 | { |
913 | { |
864 | UCHAR ucLaneSel; |
914 | UCHAR ucLaneSel; |
865 | UCHAR ucLaneSet; |
915 | UCHAR ucLaneSet; |
866 | }ATOM_DP_VS_MODE; |
916 | }ATOM_DP_VS_MODE; |
867 | 917 | ||
868 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS |
918 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS |
869 | { |
919 | { |
870 | union |
920 | union |
871 | { |
921 | { |
872 | USHORT usPixelClock; // in 10KHz; for bios convenient |
922 | USHORT usPixelClock; // in 10KHz; for bios convenient |
873 | USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h |
923 | USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h |
874 | ATOM_DP_VS_MODE asMode; // DP Voltage swing mode |
924 | ATOM_DP_VS_MODE asMode; // DP Voltage swing mode |
875 | }; |
925 | }; |
876 | UCHAR ucConfig; |
926 | UCHAR ucConfig; |
877 | // [0]=0: 4 lane Link, |
927 | // [0]=0: 4 lane Link, |
878 | // =1: 8 lane Link ( Dual Links TMDS ) |
928 | // =1: 8 lane Link ( Dual Links TMDS ) |
879 | // [1]=0: InCoherent mode |
929 | // [1]=0: InCoherent mode |
880 | // =1: Coherent Mode |
930 | // =1: Coherent Mode |
881 | // [2] Link Select: |
931 | // [2] Link Select: |
882 | // =0: PHY linkA if bfLane<3 |
932 | // =0: PHY linkA if bfLane<3 |
883 | // =1: PHY linkB if bfLanes<3 |
933 | // =1: PHY linkB if bfLanes<3 |
884 | // =0: PHY linkA+B if bfLanes=3 |
934 | // =0: PHY linkA+B if bfLanes=3 |
885 | // [5:4]PCIE lane Sel |
935 | // [5:4]PCIE lane Sel |
886 | // =0: lane 0~3 or 0~7 |
936 | // =0: lane 0~3 or 0~7 |
887 | // =1: lane 4~7 |
937 | // =1: lane 4~7 |
888 | // =2: lane 8~11 or 8~15 |
938 | // =2: lane 8~11 or 8~15 |
889 | // =3: lane 12~15 |
939 | // =3: lane 12~15 |
890 | UCHAR ucAction; // =0: turn off encoder |
940 | UCHAR ucAction; // =0: turn off encoder |
891 | // =1: turn on encoder |
941 | // =1: turn on encoder |
892 | UCHAR ucReserved[4]; |
942 | UCHAR ucReserved[4]; |
893 | }DIG_TRANSMITTER_CONTROL_PARAMETERS; |
943 | }DIG_TRANSMITTER_CONTROL_PARAMETERS; |
894 | 944 | ||
895 | #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS |
945 | #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS |
896 | 946 | ||
897 | //ucInitInfo |
947 | //ucInitInfo |
898 | #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff |
948 | #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff |
899 | 949 | ||
900 | //ucConfig |
950 | //ucConfig |
901 | #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 |
951 | #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 |
902 | #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 |
952 | #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 |
903 | #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 |
953 | #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 |
904 | #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 |
954 | #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 |
905 | #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 |
955 | #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 |
906 | #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 |
956 | #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 |
907 | #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 |
957 | #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 |
908 | 958 | ||
909 | #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE |
959 | #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE |
910 | #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE |
960 | #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE |
911 | #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE |
961 | #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE |
912 | 962 | ||
913 | #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 |
963 | #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 |
914 | #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 |
964 | #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 |
915 | #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 |
965 | #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 |
916 | #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 |
966 | #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 |
917 | #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 |
967 | #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 |
918 | #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 |
968 | #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 |
919 | #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 |
969 | #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 |
920 | #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 |
970 | #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 |
921 | #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 |
971 | #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 |
922 | #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 |
972 | #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 |
923 | #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 |
973 | #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 |
924 | 974 | ||
925 | //ucAction |
975 | //ucAction |
926 | #define ATOM_TRANSMITTER_ACTION_DISABLE 0 |
976 | #define ATOM_TRANSMITTER_ACTION_DISABLE 0 |
927 | #define ATOM_TRANSMITTER_ACTION_ENABLE 1 |
977 | #define ATOM_TRANSMITTER_ACTION_ENABLE 1 |
928 | #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 |
978 | #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 |
929 | #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 |
979 | #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 |
930 | #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 |
980 | #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 |
931 | #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 |
981 | #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 |
932 | #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 |
982 | #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 |
933 | #define ATOM_TRANSMITTER_ACTION_INIT 7 |
983 | #define ATOM_TRANSMITTER_ACTION_INIT 7 |
934 | #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 |
984 | #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 |
935 | #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 |
985 | #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 |
936 | #define ATOM_TRANSMITTER_ACTION_SETUP 10 |
986 | #define ATOM_TRANSMITTER_ACTION_SETUP 10 |
937 | #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 |
987 | #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 |
938 | #define ATOM_TRANSMITTER_ACTION_POWER_ON 12 |
988 | #define ATOM_TRANSMITTER_ACTION_POWER_ON 12 |
939 | #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 |
989 | #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 |
940 | 990 | ||
941 | // Following are used for DigTransmitterControlTable ver1.2 |
991 | // Following are used for DigTransmitterControlTable ver1.2 |
942 | typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 |
992 | typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 |
943 | { |
993 | { |
944 | #if ATOM_BIG_ENDIAN |
994 | #if ATOM_BIG_ENDIAN |
945 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
995 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
946 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
996 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
947 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
997 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
948 | UCHAR ucReserved:1; |
998 | UCHAR ucReserved:1; |
949 | UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector |
999 | UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector |
950 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) |
1000 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) |
951 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
1001 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
952 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
1002 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
953 | 1003 | ||
954 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
1004 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
955 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
1005 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
956 | #else |
1006 | #else |
957 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
1007 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
958 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
1008 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
959 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
1009 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
960 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
1010 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
961 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) |
1011 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) |
962 | UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector |
1012 | UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector |
963 | UCHAR ucReserved:1; |
1013 | UCHAR ucReserved:1; |
964 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
1014 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
965 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
1015 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
966 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
1016 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
967 | #endif |
1017 | #endif |
968 | }ATOM_DIG_TRANSMITTER_CONFIG_V2; |
1018 | }ATOM_DIG_TRANSMITTER_CONFIG_V2; |
969 | 1019 | ||
970 | //ucConfig |
1020 | //ucConfig |
971 | //Bit0 |
1021 | //Bit0 |
972 | #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 |
1022 | #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 |
973 | 1023 | ||
974 | //Bit1 |
1024 | //Bit1 |
975 | #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 |
1025 | #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 |
976 | 1026 | ||
977 | //Bit2 |
1027 | //Bit2 |
978 | #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 |
1028 | #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 |
979 | #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 |
1029 | #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 |
980 | #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 |
1030 | #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 |
981 | 1031 | ||
982 | // Bit3 |
1032 | // Bit3 |
983 | #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 |
1033 | #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 |
984 | #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP |
1034 | #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP |
985 | #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP |
1035 | #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP |
986 | 1036 | ||
987 | // Bit4 |
1037 | // Bit4 |
988 | #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 |
1038 | #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 |
989 | 1039 | ||
990 | // Bit7:6 |
1040 | // Bit7:6 |
991 | #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 |
1041 | #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 |
992 | #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB |
1042 | #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB |
993 | #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD |
1043 | #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD |
994 | #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF |
1044 | #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF |
995 | 1045 | ||
996 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 |
1046 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 |
997 | { |
1047 | { |
998 | union |
1048 | union |
999 | { |
1049 | { |
1000 | USHORT usPixelClock; // in 10KHz; for bios convenient |
1050 | USHORT usPixelClock; // in 10KHz; for bios convenient |
1001 | USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h |
1051 | USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h |
1002 | ATOM_DP_VS_MODE asMode; // DP Voltage swing mode |
1052 | ATOM_DP_VS_MODE asMode; // DP Voltage swing mode |
1003 | }; |
1053 | }; |
1004 | ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; |
1054 | ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; |
1005 | UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX |
1055 | UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX |
1006 | UCHAR ucReserved[4]; |
1056 | UCHAR ucReserved[4]; |
1007 | }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; |
1057 | }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; |
1008 | 1058 | ||
1009 | typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 |
1059 | typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 |
1010 | { |
1060 | { |
1011 | #if ATOM_BIG_ENDIAN |
1061 | #if ATOM_BIG_ENDIAN |
1012 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
1062 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
1013 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
1063 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
1014 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
1064 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
1015 | UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 |
1065 | UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 |
1016 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F |
1066 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F |
1017 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
1067 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
1018 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
1068 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
1019 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
1069 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
1020 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
1070 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
1021 | #else |
1071 | #else |
1022 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
1072 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
1023 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
1073 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
1024 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
1074 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
1025 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
1075 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
1026 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F |
1076 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F |
1027 | UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 |
1077 | UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 |
1028 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
1078 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
1029 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
1079 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
1030 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
1080 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
1031 | #endif |
1081 | #endif |
1032 | }ATOM_DIG_TRANSMITTER_CONFIG_V3; |
1082 | }ATOM_DIG_TRANSMITTER_CONFIG_V3; |
1033 | 1083 | ||
1034 | 1084 | ||
1035 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 |
1085 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 |
1036 | { |
1086 | { |
1037 | union |
1087 | union |
1038 | { |
1088 | { |
1039 | USHORT usPixelClock; // in 10KHz; for bios convenient |
1089 | USHORT usPixelClock; // in 10KHz; for bios convenient |
1040 | USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h |
1090 | USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h |
1041 | ATOM_DP_VS_MODE asMode; // DP Voltage swing mode |
1091 | ATOM_DP_VS_MODE asMode; // DP Voltage swing mode |
1042 | }; |
1092 | }; |
1043 | ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; |
1093 | ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; |
1044 | UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX |
1094 | UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX |
1045 | UCHAR ucLaneNum; |
1095 | UCHAR ucLaneNum; |
1046 | UCHAR ucReserved[3]; |
1096 | UCHAR ucReserved[3]; |
1047 | }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; |
1097 | }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; |
1048 | 1098 | ||
1049 | //ucConfig |
1099 | //ucConfig |
1050 | //Bit0 |
1100 | //Bit0 |
1051 | #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 |
1101 | #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 |
1052 | 1102 | ||
1053 | //Bit1 |
1103 | //Bit1 |
1054 | #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 |
1104 | #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 |
1055 | 1105 | ||
1056 | //Bit2 |
1106 | //Bit2 |
1057 | #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 |
1107 | #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 |
1058 | #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 |
1108 | #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 |
1059 | #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 |
1109 | #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 |
1060 | 1110 | ||
1061 | // Bit3 |
1111 | // Bit3 |
1062 | #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 |
1112 | #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 |
1063 | #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 |
1113 | #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 |
1064 | #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 |
1114 | #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 |
1065 | 1115 | ||
1066 | // Bit5:4 |
1116 | // Bit5:4 |
1067 | #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 |
1117 | #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 |
1068 | #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 |
1118 | #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 |
1069 | #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 |
1119 | #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 |
1070 | #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 |
1120 | #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 |
1071 | 1121 | ||
1072 | // Bit7:6 |
1122 | // Bit7:6 |
1073 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 |
1123 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 |
1074 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB |
1124 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB |
1075 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD |
1125 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD |
1076 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF |
1126 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF |
1077 | 1127 | ||
1078 | 1128 | ||
1079 | /****************************************************************************/ |
1129 | /****************************************************************************/ |
1080 | // Structures used by UNIPHYTransmitterControlTable V1.4 |
1130 | // Structures used by UNIPHYTransmitterControlTable V1.4 |
1081 | // ASIC Families: NI |
1131 | // ASIC Families: NI |
1082 | // ucTableFormatRevision=1 |
1132 | // ucTableFormatRevision=1 |
1083 | // ucTableContentRevision=4 |
1133 | // ucTableContentRevision=4 |
1084 | /****************************************************************************/ |
1134 | /****************************************************************************/ |
1085 | typedef struct _ATOM_DP_VS_MODE_V4 |
1135 | typedef struct _ATOM_DP_VS_MODE_V4 |
1086 | { |
1136 | { |
1087 | UCHAR ucLaneSel; |
1137 | UCHAR ucLaneSel; |
1088 | union |
1138 | union |
1089 | { |
1139 | { |
1090 | UCHAR ucLaneSet; |
1140 | UCHAR ucLaneSet; |
1091 | struct { |
1141 | struct { |
1092 | #if ATOM_BIG_ENDIAN |
1142 | #if ATOM_BIG_ENDIAN |
1093 | UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 |
1143 | UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 |
1094 | UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level |
1144 | UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level |
1095 | UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level |
1145 | UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level |
1096 | #else |
1146 | #else |
1097 | UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level |
1147 | UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level |
1098 | UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level |
1148 | UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level |
1099 | UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 |
1149 | UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 |
1100 | #endif |
1150 | #endif |
1101 | }; |
1151 | }; |
1102 | }; |
1152 | }; |
1103 | }ATOM_DP_VS_MODE_V4; |
1153 | }ATOM_DP_VS_MODE_V4; |
1104 | 1154 | ||
1105 | typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 |
1155 | typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 |
1106 | { |
1156 | { |
1107 | #if ATOM_BIG_ENDIAN |
1157 | #if ATOM_BIG_ENDIAN |
1108 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
1158 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
1109 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
1159 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
1110 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
1160 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
1111 | UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New |
1161 | UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New |
1112 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F |
1162 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F |
1113 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
1163 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
1114 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
1164 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
1115 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
1165 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
1116 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
1166 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
1117 | #else |
1167 | #else |
1118 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
1168 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector |
1119 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
1169 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) |
1120 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
1170 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E |
1121 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
1171 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F |
1122 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F |
1172 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F |
1123 | UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New |
1173 | UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New |
1124 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
1174 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) |
1125 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
1175 | // =1 Dig Transmitter 2 ( Uniphy CD ) |
1126 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
1176 | // =2 Dig Transmitter 3 ( Uniphy EF ) |
1127 | #endif |
1177 | #endif |
1128 | }ATOM_DIG_TRANSMITTER_CONFIG_V4; |
1178 | }ATOM_DIG_TRANSMITTER_CONFIG_V4; |
1129 | 1179 | ||
1130 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 |
1180 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 |
1131 | { |
1181 | { |
1132 | union |
1182 | union |
1133 | { |
1183 | { |
1134 | USHORT usPixelClock; // in 10KHz; for bios convenient |
1184 | USHORT usPixelClock; // in 10KHz; for bios convenient |
1135 | USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h |
1185 | USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h |
1136 | ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version |
1186 | ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version |
1137 | }; |
1187 | }; |
1138 | union |
1188 | union |
1139 | { |
1189 | { |
1140 | ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; |
1190 | ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; |
1141 | UCHAR ucConfig; |
1191 | UCHAR ucConfig; |
1142 | }; |
1192 | }; |
1143 | UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX |
1193 | UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX |
1144 | UCHAR ucLaneNum; |
1194 | UCHAR ucLaneNum; |
1145 | UCHAR ucReserved[3]; |
1195 | UCHAR ucReserved[3]; |
1146 | }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; |
1196 | }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; |
1147 | 1197 | ||
1148 | //ucConfig |
1198 | //ucConfig |
1149 | //Bit0 |
1199 | //Bit0 |
1150 | #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 |
1200 | #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 |
1151 | //Bit1 |
1201 | //Bit1 |
1152 | #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 |
1202 | #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 |
1153 | //Bit2 |
1203 | //Bit2 |
1154 | #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 |
1204 | #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 |
1155 | #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 |
1205 | #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 |
1156 | #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 |
1206 | #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 |
1157 | // Bit3 |
1207 | // Bit3 |
1158 | #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 |
1208 | #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 |
1159 | #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 |
1209 | #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 |
1160 | #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 |
1210 | #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 |
1161 | // Bit5:4 |
1211 | // Bit5:4 |
1162 | #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 |
1212 | #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 |
1163 | #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 |
1213 | #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 |
1164 | #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 |
1214 | #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 |
1165 | #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 |
1215 | #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 |
1166 | #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 |
1216 | #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 |
1167 | // Bit7:6 |
1217 | // Bit7:6 |
1168 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 |
1218 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 |
1169 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB |
1219 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB |
1170 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD |
1220 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD |
1171 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF |
1221 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF |
1172 | 1222 | ||
- | 1223 | ||
- | 1224 | typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 |
|
- | 1225 | { |
|
- | 1226 | #if ATOM_BIG_ENDIAN |
|
- | 1227 | UCHAR ucReservd1:1; |
|
- | 1228 | UCHAR ucHPDSel:3; |
|
- | 1229 | UCHAR ucPhyClkSrcId:2; |
|
- | 1230 | UCHAR ucCoherentMode:1; |
|
- | 1231 | UCHAR ucReserved:1; |
|
- | 1232 | #else |
|
- | 1233 | UCHAR ucReserved:1; |
|
- | 1234 | UCHAR ucCoherentMode:1; |
|
- | 1235 | UCHAR ucPhyClkSrcId:2; |
|
- | 1236 | UCHAR ucHPDSel:3; |
|
- | 1237 | UCHAR ucReservd1:1; |
|
- | 1238 | #endif |
|
- | 1239 | }ATOM_DIG_TRANSMITTER_CONFIG_V5; |
|
- | 1240 | ||
- | 1241 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 |
|
- | 1242 | { |
|
- | 1243 | USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio |
|
- | 1244 | UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF |
|
- | 1245 | UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx |
|
- | 1246 | UCHAR ucLaneNum; // indicate lane number 1-8 |
|
- | 1247 | UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h |
|
- | 1248 | UCHAR ucDigMode; // indicate DIG mode |
|
- | 1249 | union{ |
|
- | 1250 | ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; |
|
- | 1251 | UCHAR ucConfig; |
|
- | 1252 | }; |
|
- | 1253 | UCHAR ucDigEncoderSel; // indicate DIG front end encoder |
|
- | 1254 | UCHAR ucDPLaneSet; |
|
- | 1255 | UCHAR ucReserved; |
|
- | 1256 | UCHAR ucReserved1; |
|
- | 1257 | }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; |
|
- | 1258 | ||
- | 1259 | //ucPhyId |
|
- | 1260 | #define ATOM_PHY_ID_UNIPHYA 0 |
|
- | 1261 | #define ATOM_PHY_ID_UNIPHYB 1 |
|
- | 1262 | #define ATOM_PHY_ID_UNIPHYC 2 |
|
- | 1263 | #define ATOM_PHY_ID_UNIPHYD 3 |
|
- | 1264 | #define ATOM_PHY_ID_UNIPHYE 4 |
|
- | 1265 | #define ATOM_PHY_ID_UNIPHYF 5 |
|
- | 1266 | #define ATOM_PHY_ID_UNIPHYG 6 |
|
- | 1267 | ||
- | 1268 | // ucDigEncoderSel |
|
- | 1269 | #define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 |
|
- | 1270 | #define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 |
|
- | 1271 | #define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 |
|
- | 1272 | #define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 |
|
- | 1273 | #define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 |
|
- | 1274 | #define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 |
|
- | 1275 | #define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 |
|
- | 1276 | ||
- | 1277 | // ucDigMode |
|
- | 1278 | #define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 |
|
- | 1279 | #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 |
|
- | 1280 | #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 |
|
- | 1281 | #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 |
|
- | 1282 | #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 |
|
- | 1283 | #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 |
|
- | 1284 | ||
- | 1285 | // ucDPLaneSet |
|
- | 1286 | #define DP_LANE_SET__0DB_0_4V 0x00 |
|
- | 1287 | #define DP_LANE_SET__0DB_0_6V 0x01 |
|
- | 1288 | #define DP_LANE_SET__0DB_0_8V 0x02 |
|
- | 1289 | #define DP_LANE_SET__0DB_1_2V 0x03 |
|
- | 1290 | #define DP_LANE_SET__3_5DB_0_4V 0x08 |
|
- | 1291 | #define DP_LANE_SET__3_5DB_0_6V 0x09 |
|
- | 1292 | #define DP_LANE_SET__3_5DB_0_8V 0x0a |
|
- | 1293 | #define DP_LANE_SET__6DB_0_4V 0x10 |
|
- | 1294 | #define DP_LANE_SET__6DB_0_6V 0x11 |
|
- | 1295 | #define DP_LANE_SET__9_5DB_0_4V 0x18 |
|
- | 1296 | ||
- | 1297 | // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; |
|
- | 1298 | // Bit1 |
|
- | 1299 | #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 |
|
- | 1300 | ||
- | 1301 | // Bit3:2 |
|
- | 1302 | #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c |
|
- | 1303 | #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 |
|
- | 1304 | ||
- | 1305 | #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 |
|
- | 1306 | #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 |
|
- | 1307 | #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 |
|
- | 1308 | #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c |
|
- | 1309 | // Bit6:4 |
|
- | 1310 | #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 |
|
- | 1311 | #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 |
|
- | 1312 | ||
- | 1313 | #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 |
|
- | 1314 | #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 |
|
- | 1315 | #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 |
|
- | 1316 | #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 |
|
- | 1317 | #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 |
|
- | 1318 | #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 |
|
- | 1319 | #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 |
|
- | 1320 | ||
- | 1321 | #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 |
|
- | 1322 | ||
1173 | 1323 | ||
1174 | /****************************************************************************/ |
1324 | /****************************************************************************/ |
1175 | // Structures used by ExternalEncoderControlTable V1.3 |
1325 | // Structures used by ExternalEncoderControlTable V1.3 |
1176 | // ASIC Families: Evergreen, Llano, NI |
1326 | // ASIC Families: Evergreen, Llano, NI |
1177 | // ucTableFormatRevision=1 |
1327 | // ucTableFormatRevision=1 |
1178 | // ucTableContentRevision=3 |
1328 | // ucTableContentRevision=3 |
1179 | /****************************************************************************/ |
1329 | /****************************************************************************/ |
1180 | 1330 | ||
1181 | typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 |
1331 | typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 |
1182 | { |
1332 | { |
1183 | union{ |
1333 | union{ |
1184 | USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT |
1334 | USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT |
1185 | USHORT usConnectorId; // connector id, valid when ucAction = INIT |
1335 | USHORT usConnectorId; // connector id, valid when ucAction = INIT |
1186 | }; |
1336 | }; |
1187 | UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT |
1337 | UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT |
1188 | UCHAR ucAction; // |
1338 | UCHAR ucAction; // |
1189 | UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT |
1339 | UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT |
1190 | UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT |
1340 | UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT |
1191 | UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP |
1341 | UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP |
1192 | UCHAR ucReserved; |
1342 | UCHAR ucReserved; |
1193 | }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; |
1343 | }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; |
1194 | 1344 | ||
1195 | // ucAction |
1345 | // ucAction |
1196 | #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 |
1346 | #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 |
1197 | #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 |
1347 | #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 |
1198 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 |
1348 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 |
1199 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f |
1349 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f |
1200 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 |
1350 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 |
1201 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 |
1351 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 |
1202 | #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 |
1352 | #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 |
1203 | #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 |
1353 | #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 |
1204 | 1354 | ||
1205 | // ucConfig |
1355 | // ucConfig |
1206 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 |
1356 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 |
1207 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 |
1357 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 |
1208 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 |
1358 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 |
1209 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 |
1359 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 |
1210 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70 |
1360 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70 |
1211 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 |
1361 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 |
1212 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 |
1362 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 |
1213 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 |
1363 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 |
1214 | 1364 | ||
1215 | typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 |
1365 | typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 |
1216 | { |
1366 | { |
1217 | EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; |
1367 | EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; |
1218 | ULONG ulReserved[2]; |
1368 | ULONG ulReserved[2]; |
1219 | }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; |
1369 | }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; |
1220 | 1370 | ||
1221 | 1371 | ||
1222 | /****************************************************************************/ |
1372 | /****************************************************************************/ |
1223 | // Structures used by DAC1OuputControlTable |
1373 | // Structures used by DAC1OuputControlTable |
1224 | // DAC2OuputControlTable |
1374 | // DAC2OuputControlTable |
1225 | // LVTMAOutputControlTable (Before DEC30) |
1375 | // LVTMAOutputControlTable (Before DEC30) |
1226 | // TMDSAOutputControlTable (Before DEC30) |
1376 | // TMDSAOutputControlTable (Before DEC30) |
1227 | /****************************************************************************/ |
1377 | /****************************************************************************/ |
1228 | typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1378 | typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1229 | { |
1379 | { |
1230 | UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE |
1380 | UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE |
1231 | // When the display is LCD, in addition to above: |
1381 | // When the display is LCD, in addition to above: |
1232 | // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| |
1382 | // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| |
1233 | // ATOM_LCD_SELFTEST_STOP |
1383 | // ATOM_LCD_SELFTEST_STOP |
1234 | 1384 | ||
1235 | UCHAR aucPadding[3]; // padding to DWORD aligned |
1385 | UCHAR aucPadding[3]; // padding to DWORD aligned |
1236 | }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; |
1386 | }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; |
1237 | 1387 | ||
1238 | #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1388 | #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1239 | 1389 | ||
1240 | 1390 | ||
1241 | #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1391 | #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1242 | #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1392 | #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1243 | 1393 | ||
1244 | #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1394 | #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1245 | #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1395 | #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1246 | 1396 | ||
1247 | #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1397 | #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1248 | #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1398 | #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1249 | 1399 | ||
1250 | #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1400 | #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1251 | #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1401 | #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1252 | 1402 | ||
1253 | #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1403 | #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1254 | #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1404 | #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1255 | 1405 | ||
1256 | #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1406 | #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1257 | #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1407 | #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1258 | 1408 | ||
1259 | #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1409 | #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1260 | #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1410 | #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
1261 | 1411 | ||
1262 | #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1412 | #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
1263 | #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION |
1413 | #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION |
1264 | #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS |
1414 | #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS |
1265 | 1415 | ||
1266 | /****************************************************************************/ |
1416 | /****************************************************************************/ |
1267 | // Structures used by BlankCRTCTable |
1417 | // Structures used by BlankCRTCTable |
1268 | /****************************************************************************/ |
1418 | /****************************************************************************/ |
1269 | typedef struct _BLANK_CRTC_PARAMETERS |
1419 | typedef struct _BLANK_CRTC_PARAMETERS |
1270 | { |
1420 | { |
1271 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
1421 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
1272 | UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF |
1422 | UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF |
1273 | USHORT usBlackColorRCr; |
1423 | USHORT usBlackColorRCr; |
1274 | USHORT usBlackColorGY; |
1424 | USHORT usBlackColorGY; |
1275 | USHORT usBlackColorBCb; |
1425 | USHORT usBlackColorBCb; |
1276 | }BLANK_CRTC_PARAMETERS; |
1426 | }BLANK_CRTC_PARAMETERS; |
1277 | #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS |
1427 | #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS |
1278 | 1428 | ||
1279 | /****************************************************************************/ |
1429 | /****************************************************************************/ |
1280 | // Structures used by EnableCRTCTable |
1430 | // Structures used by EnableCRTCTable |
1281 | // EnableCRTCMemReqTable |
1431 | // EnableCRTCMemReqTable |
1282 | // UpdateCRTC_DoubleBufferRegistersTable |
1432 | // UpdateCRTC_DoubleBufferRegistersTable |
1283 | /****************************************************************************/ |
1433 | /****************************************************************************/ |
1284 | typedef struct _ENABLE_CRTC_PARAMETERS |
1434 | typedef struct _ENABLE_CRTC_PARAMETERS |
1285 | { |
1435 | { |
1286 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
1436 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
1287 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
1437 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
1288 | UCHAR ucPadding[2]; |
1438 | UCHAR ucPadding[2]; |
1289 | }ENABLE_CRTC_PARAMETERS; |
1439 | }ENABLE_CRTC_PARAMETERS; |
1290 | #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS |
1440 | #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS |
1291 | 1441 | ||
1292 | /****************************************************************************/ |
1442 | /****************************************************************************/ |
1293 | // Structures used by SetCRTC_OverScanTable |
1443 | // Structures used by SetCRTC_OverScanTable |
1294 | /****************************************************************************/ |
1444 | /****************************************************************************/ |
1295 | typedef struct _SET_CRTC_OVERSCAN_PARAMETERS |
1445 | typedef struct _SET_CRTC_OVERSCAN_PARAMETERS |
1296 | { |
1446 | { |
1297 | USHORT usOverscanRight; // right |
1447 | USHORT usOverscanRight; // right |
1298 | USHORT usOverscanLeft; // left |
1448 | USHORT usOverscanLeft; // left |
1299 | USHORT usOverscanBottom; // bottom |
1449 | USHORT usOverscanBottom; // bottom |
1300 | USHORT usOverscanTop; // top |
1450 | USHORT usOverscanTop; // top |
1301 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
1451 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
1302 | UCHAR ucPadding[3]; |
1452 | UCHAR ucPadding[3]; |
1303 | }SET_CRTC_OVERSCAN_PARAMETERS; |
1453 | }SET_CRTC_OVERSCAN_PARAMETERS; |
1304 | #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS |
1454 | #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS |
1305 | 1455 | ||
1306 | /****************************************************************************/ |
1456 | /****************************************************************************/ |
1307 | // Structures used by SetCRTC_ReplicationTable |
1457 | // Structures used by SetCRTC_ReplicationTable |
1308 | /****************************************************************************/ |
1458 | /****************************************************************************/ |
1309 | typedef struct _SET_CRTC_REPLICATION_PARAMETERS |
1459 | typedef struct _SET_CRTC_REPLICATION_PARAMETERS |
1310 | { |
1460 | { |
1311 | UCHAR ucH_Replication; // horizontal replication |
1461 | UCHAR ucH_Replication; // horizontal replication |
1312 | UCHAR ucV_Replication; // vertical replication |
1462 | UCHAR ucV_Replication; // vertical replication |
1313 | UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
1463 | UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
1314 | UCHAR ucPadding; |
1464 | UCHAR ucPadding; |
1315 | }SET_CRTC_REPLICATION_PARAMETERS; |
1465 | }SET_CRTC_REPLICATION_PARAMETERS; |
1316 | #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS |
1466 | #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS |
1317 | 1467 | ||
1318 | /****************************************************************************/ |
1468 | /****************************************************************************/ |
1319 | // Structures used by SelectCRTC_SourceTable |
1469 | // Structures used by SelectCRTC_SourceTable |
1320 | /****************************************************************************/ |
1470 | /****************************************************************************/ |
1321 | typedef struct _SELECT_CRTC_SOURCE_PARAMETERS |
1471 | typedef struct _SELECT_CRTC_SOURCE_PARAMETERS |
1322 | { |
1472 | { |
1323 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
1473 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
1324 | UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... |
1474 | UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... |
1325 | UCHAR ucPadding[2]; |
1475 | UCHAR ucPadding[2]; |
1326 | }SELECT_CRTC_SOURCE_PARAMETERS; |
1476 | }SELECT_CRTC_SOURCE_PARAMETERS; |
1327 | #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS |
1477 | #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS |
1328 | 1478 | ||
1329 | typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 |
1479 | typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 |
1330 | { |
1480 | { |
1331 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
1481 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
1332 | UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO |
1482 | UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO |
1333 | UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO |
1483 | UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO |
1334 | UCHAR ucPadding; |
1484 | UCHAR ucPadding; |
1335 | }SELECT_CRTC_SOURCE_PARAMETERS_V2; |
1485 | }SELECT_CRTC_SOURCE_PARAMETERS_V2; |
1336 | 1486 | ||
1337 | //ucEncoderID |
1487 | //ucEncoderID |
1338 | //#define ASIC_INT_DAC1_ENCODER_ID 0x00 |
1488 | //#define ASIC_INT_DAC1_ENCODER_ID 0x00 |
1339 | //#define ASIC_INT_TV_ENCODER_ID 0x02 |
1489 | //#define ASIC_INT_TV_ENCODER_ID 0x02 |
1340 | //#define ASIC_INT_DIG1_ENCODER_ID 0x03 |
1490 | //#define ASIC_INT_DIG1_ENCODER_ID 0x03 |
1341 | //#define ASIC_INT_DAC2_ENCODER_ID 0x04 |
1491 | //#define ASIC_INT_DAC2_ENCODER_ID 0x04 |
1342 | //#define ASIC_EXT_TV_ENCODER_ID 0x06 |
1492 | //#define ASIC_EXT_TV_ENCODER_ID 0x06 |
1343 | //#define ASIC_INT_DVO_ENCODER_ID 0x07 |
1493 | //#define ASIC_INT_DVO_ENCODER_ID 0x07 |
1344 | //#define ASIC_INT_DIG2_ENCODER_ID 0x09 |
1494 | //#define ASIC_INT_DIG2_ENCODER_ID 0x09 |
1345 | //#define ASIC_EXT_DIG_ENCODER_ID 0x05 |
1495 | //#define ASIC_EXT_DIG_ENCODER_ID 0x05 |
1346 | 1496 | ||
1347 | //ucEncodeMode |
1497 | //ucEncodeMode |
1348 | //#define ATOM_ENCODER_MODE_DP 0 |
1498 | //#define ATOM_ENCODER_MODE_DP 0 |
1349 | //#define ATOM_ENCODER_MODE_LVDS 1 |
1499 | //#define ATOM_ENCODER_MODE_LVDS 1 |
1350 | //#define ATOM_ENCODER_MODE_DVI 2 |
1500 | //#define ATOM_ENCODER_MODE_DVI 2 |
1351 | //#define ATOM_ENCODER_MODE_HDMI 3 |
1501 | //#define ATOM_ENCODER_MODE_HDMI 3 |
1352 | //#define ATOM_ENCODER_MODE_SDVO 4 |
1502 | //#define ATOM_ENCODER_MODE_SDVO 4 |
1353 | //#define ATOM_ENCODER_MODE_TV 13 |
1503 | //#define ATOM_ENCODER_MODE_TV 13 |
1354 | //#define ATOM_ENCODER_MODE_CV 14 |
1504 | //#define ATOM_ENCODER_MODE_CV 14 |
1355 | //#define ATOM_ENCODER_MODE_CRT 15 |
1505 | //#define ATOM_ENCODER_MODE_CRT 15 |
1356 | 1506 | ||
1357 | /****************************************************************************/ |
1507 | /****************************************************************************/ |
1358 | // Structures used by SetPixelClockTable |
1508 | // Structures used by SetPixelClockTable |
1359 | // GetPixelClockTable |
1509 | // GetPixelClockTable |
1360 | /****************************************************************************/ |
1510 | /****************************************************************************/ |
1361 | //Major revision=1., Minor revision=1 |
1511 | //Major revision=1., Minor revision=1 |
1362 | typedef struct _PIXEL_CLOCK_PARAMETERS |
1512 | typedef struct _PIXEL_CLOCK_PARAMETERS |
1363 | { |
1513 | { |
1364 | USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) |
1514 | USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) |
1365 | // 0 means disable PPLL |
1515 | // 0 means disable PPLL |
1366 | USHORT usRefDiv; // Reference divider |
1516 | USHORT usRefDiv; // Reference divider |
1367 | USHORT usFbDiv; // feedback divider |
1517 | USHORT usFbDiv; // feedback divider |
1368 | UCHAR ucPostDiv; // post divider |
1518 | UCHAR ucPostDiv; // post divider |
1369 | UCHAR ucFracFbDiv; // fractional feedback divider |
1519 | UCHAR ucFracFbDiv; // fractional feedback divider |
1370 | UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 |
1520 | UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 |
1371 | UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER |
1521 | UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER |
1372 | UCHAR ucCRTC; // Which CRTC uses this Ppll |
1522 | UCHAR ucCRTC; // Which CRTC uses this Ppll |
1373 | UCHAR ucPadding; |
1523 | UCHAR ucPadding; |
1374 | }PIXEL_CLOCK_PARAMETERS; |
1524 | }PIXEL_CLOCK_PARAMETERS; |
1375 | 1525 | ||
1376 | //Major revision=1., Minor revision=2, add ucMiscIfno |
1526 | //Major revision=1., Minor revision=2, add ucMiscIfno |
1377 | //ucMiscInfo: |
1527 | //ucMiscInfo: |
1378 | #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 |
1528 | #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 |
1379 | #define MISC_DEVICE_INDEX_MASK 0xF0 |
1529 | #define MISC_DEVICE_INDEX_MASK 0xF0 |
1380 | #define MISC_DEVICE_INDEX_SHIFT 4 |
1530 | #define MISC_DEVICE_INDEX_SHIFT 4 |
1381 | 1531 | ||
1382 | typedef struct _PIXEL_CLOCK_PARAMETERS_V2 |
1532 | typedef struct _PIXEL_CLOCK_PARAMETERS_V2 |
1383 | { |
1533 | { |
1384 | USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) |
1534 | USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) |
1385 | // 0 means disable PPLL |
1535 | // 0 means disable PPLL |
1386 | USHORT usRefDiv; // Reference divider |
1536 | USHORT usRefDiv; // Reference divider |
1387 | USHORT usFbDiv; // feedback divider |
1537 | USHORT usFbDiv; // feedback divider |
1388 | UCHAR ucPostDiv; // post divider |
1538 | UCHAR ucPostDiv; // post divider |
1389 | UCHAR ucFracFbDiv; // fractional feedback divider |
1539 | UCHAR ucFracFbDiv; // fractional feedback divider |
1390 | UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 |
1540 | UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 |
1391 | UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER |
1541 | UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER |
1392 | UCHAR ucCRTC; // Which CRTC uses this Ppll |
1542 | UCHAR ucCRTC; // Which CRTC uses this Ppll |
1393 | UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog |
1543 | UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog |
1394 | }PIXEL_CLOCK_PARAMETERS_V2; |
1544 | }PIXEL_CLOCK_PARAMETERS_V2; |
1395 | 1545 | ||
1396 | //Major revision=1., Minor revision=3, structure/definition change |
1546 | //Major revision=1., Minor revision=3, structure/definition change |
1397 | //ucEncoderMode: |
1547 | //ucEncoderMode: |
1398 | //ATOM_ENCODER_MODE_DP |
1548 | //ATOM_ENCODER_MODE_DP |
1399 | //ATOM_ENOCDER_MODE_LVDS |
1549 | //ATOM_ENOCDER_MODE_LVDS |
1400 | //ATOM_ENOCDER_MODE_DVI |
1550 | //ATOM_ENOCDER_MODE_DVI |
1401 | //ATOM_ENOCDER_MODE_HDMI |
1551 | //ATOM_ENOCDER_MODE_HDMI |
1402 | //ATOM_ENOCDER_MODE_SDVO |
1552 | //ATOM_ENOCDER_MODE_SDVO |
1403 | //ATOM_ENCODER_MODE_TV 13 |
1553 | //ATOM_ENCODER_MODE_TV 13 |
1404 | //ATOM_ENCODER_MODE_CV 14 |
1554 | //ATOM_ENCODER_MODE_CV 14 |
1405 | //ATOM_ENCODER_MODE_CRT 15 |
1555 | //ATOM_ENCODER_MODE_CRT 15 |
1406 | 1556 | ||
1407 | //ucDVOConfig |
1557 | //ucDVOConfig |
1408 | //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 |
1558 | //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 |
1409 | //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 |
1559 | //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 |
1410 | //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 |
1560 | //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 |
1411 | //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c |
1561 | //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c |
1412 | //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 |
1562 | //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 |
1413 | //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 |
1563 | //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 |
1414 | //#define DVO_ENCODER_CONFIG_24BIT 0x08 |
1564 | //#define DVO_ENCODER_CONFIG_24BIT 0x08 |
1415 | 1565 | ||
1416 | //ucMiscInfo: also changed, see below |
1566 | //ucMiscInfo: also changed, see below |
1417 | #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 |
1567 | #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 |
1418 | #define PIXEL_CLOCK_MISC_VGA_MODE 0x02 |
1568 | #define PIXEL_CLOCK_MISC_VGA_MODE 0x02 |
1419 | #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 |
1569 | #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 |
1420 | #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 |
1570 | #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 |
1421 | #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 |
1571 | #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 |
1422 | #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 |
1572 | #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 |
1423 | #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 |
1573 | #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 |
1424 | // V1.4 for RoadRunner |
1574 | // V1.4 for RoadRunner |
1425 | #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 |
1575 | #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 |
1426 | #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 |
1576 | #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 |
1427 | 1577 | ||
1428 | 1578 | ||
1429 | typedef struct _PIXEL_CLOCK_PARAMETERS_V3 |
1579 | typedef struct _PIXEL_CLOCK_PARAMETERS_V3 |
1430 | { |
1580 | { |
1431 | USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) |
1581 | USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) |
1432 | // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. |
1582 | // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. |
1433 | USHORT usRefDiv; // Reference divider |
1583 | USHORT usRefDiv; // Reference divider |
1434 | USHORT usFbDiv; // feedback divider |
1584 | USHORT usFbDiv; // feedback divider |
1435 | UCHAR ucPostDiv; // post divider |
1585 | UCHAR ucPostDiv; // post divider |
1436 | UCHAR ucFracFbDiv; // fractional feedback divider |
1586 | UCHAR ucFracFbDiv; // fractional feedback divider |
1437 | UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 |
1587 | UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 |
1438 | UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h |
1588 | UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h |
1439 | union |
1589 | union |
1440 | { |
1590 | { |
1441 | UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ |
1591 | UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ |
1442 | UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit |
1592 | UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit |
1443 | }; |
1593 | }; |
1444 | UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel |
1594 | UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel |
1445 | // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source |
1595 | // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source |
1446 | // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider |
1596 | // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider |
1447 | }PIXEL_CLOCK_PARAMETERS_V3; |
1597 | }PIXEL_CLOCK_PARAMETERS_V3; |
1448 | 1598 | ||
1449 | #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 |
1599 | #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 |
1450 | #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST |
1600 | #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST |
1451 | 1601 | ||
1452 | typedef struct _PIXEL_CLOCK_PARAMETERS_V5 |
1602 | typedef struct _PIXEL_CLOCK_PARAMETERS_V5 |
1453 | { |
1603 | { |
1454 | UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to |
1604 | UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to |
1455 | // drive the pixel clock. not used for DCPLL case. |
1605 | // drive the pixel clock. not used for DCPLL case. |
1456 | union{ |
1606 | union{ |
1457 | UCHAR ucReserved; |
1607 | UCHAR ucReserved; |
1458 | UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. |
1608 | UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. |
1459 | }; |
1609 | }; |
1460 | USHORT usPixelClock; // target the pixel clock to drive the CRTC timing |
1610 | USHORT usPixelClock; // target the pixel clock to drive the CRTC timing |
1461 | // 0 means disable PPLL/DCPLL. |
1611 | // 0 means disable PPLL/DCPLL. |
1462 | USHORT usFbDiv; // feedback divider integer part. |
1612 | USHORT usFbDiv; // feedback divider integer part. |
1463 | UCHAR ucPostDiv; // post divider. |
1613 | UCHAR ucPostDiv; // post divider. |
1464 | UCHAR ucRefDiv; // Reference divider |
1614 | UCHAR ucRefDiv; // Reference divider |
1465 | UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL |
1615 | UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL |
1466 | UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, |
1616 | UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, |
1467 | // indicate which graphic encoder will be used. |
1617 | // indicate which graphic encoder will be used. |
1468 | UCHAR ucEncoderMode; // Encoder mode: |
1618 | UCHAR ucEncoderMode; // Encoder mode: |
1469 | UCHAR ucMiscInfo; // bit[0]= Force program PPLL |
1619 | UCHAR ucMiscInfo; // bit[0]= Force program PPLL |
1470 | // bit[1]= when VGA timing is used. |
1620 | // bit[1]= when VGA timing is used. |
1471 | // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp |
1621 | // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp |
1472 | // bit[4]= RefClock source for PPLL. |
1622 | // bit[4]= RefClock source for PPLL. |
1473 | // =0: XTLAIN( default mode ) |
1623 | // =0: XTLAIN( default mode ) |
1474 | // =1: other external clock source, which is pre-defined |
1624 | // =1: other external clock source, which is pre-defined |
1475 | // by VBIOS depend on the feature required. |
1625 | // by VBIOS depend on the feature required. |
1476 | // bit[7:5]: reserved. |
1626 | // bit[7:5]: reserved. |
1477 | ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) |
1627 | ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) |
1478 | 1628 | ||
1479 | }PIXEL_CLOCK_PARAMETERS_V5; |
1629 | }PIXEL_CLOCK_PARAMETERS_V5; |
1480 | 1630 | ||
1481 | #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 |
1631 | #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 |
1482 | #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 |
1632 | #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 |
1483 | #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c |
1633 | #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c |
1484 | #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 |
1634 | #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 |
1485 | #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 |
1635 | #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 |
1486 | #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 |
1636 | #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 |
1487 | #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 |
1637 | #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 |
1488 | 1638 | ||
1489 | typedef struct _CRTC_PIXEL_CLOCK_FREQ |
1639 | typedef struct _CRTC_PIXEL_CLOCK_FREQ |
1490 | { |
1640 | { |
1491 | #if ATOM_BIG_ENDIAN |
1641 | #if ATOM_BIG_ENDIAN |
1492 | ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to |
1642 | ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to |
1493 | // drive the pixel clock. not used for DCPLL case. |
1643 | // drive the pixel clock. not used for DCPLL case. |
1494 | ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. |
1644 | ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. |
1495 | // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. |
1645 | // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. |
1496 | #else |
1646 | #else |
1497 | ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. |
1647 | ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. |
1498 | // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. |
1648 | // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. |
1499 | ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to |
1649 | ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to |
1500 | // drive the pixel clock. not used for DCPLL case. |
1650 | // drive the pixel clock. not used for DCPLL case. |
1501 | #endif |
1651 | #endif |
1502 | }CRTC_PIXEL_CLOCK_FREQ; |
1652 | }CRTC_PIXEL_CLOCK_FREQ; |
1503 | 1653 | ||
1504 | typedef struct _PIXEL_CLOCK_PARAMETERS_V6 |
1654 | typedef struct _PIXEL_CLOCK_PARAMETERS_V6 |
1505 | { |
1655 | { |
1506 | union{ |
1656 | union{ |
1507 | CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency |
1657 | CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency |
1508 | ULONG ulDispEngClkFreq; // dispclk frequency |
1658 | ULONG ulDispEngClkFreq; // dispclk frequency |
1509 | }; |
1659 | }; |
1510 | USHORT usFbDiv; // feedback divider integer part. |
1660 | USHORT usFbDiv; // feedback divider integer part. |
1511 | UCHAR ucPostDiv; // post divider. |
1661 | UCHAR ucPostDiv; // post divider. |
1512 | UCHAR ucRefDiv; // Reference divider |
1662 | UCHAR ucRefDiv; // Reference divider |
1513 | UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL |
1663 | UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL |
1514 | UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, |
1664 | UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, |
1515 | // indicate which graphic encoder will be used. |
1665 | // indicate which graphic encoder will be used. |
1516 | UCHAR ucEncoderMode; // Encoder mode: |
1666 | UCHAR ucEncoderMode; // Encoder mode: |
1517 | UCHAR ucMiscInfo; // bit[0]= Force program PPLL |
1667 | UCHAR ucMiscInfo; // bit[0]= Force program PPLL |
1518 | // bit[1]= when VGA timing is used. |
1668 | // bit[1]= when VGA timing is used. |
1519 | // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp |
1669 | // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp |
1520 | // bit[4]= RefClock source for PPLL. |
1670 | // bit[4]= RefClock source for PPLL. |
1521 | // =0: XTLAIN( default mode ) |
1671 | // =0: XTLAIN( default mode ) |
1522 | // =1: other external clock source, which is pre-defined |
1672 | // =1: other external clock source, which is pre-defined |
1523 | // by VBIOS depend on the feature required. |
1673 | // by VBIOS depend on the feature required. |
1524 | // bit[7:5]: reserved. |
1674 | // bit[7:5]: reserved. |
1525 | ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) |
1675 | ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) |
1526 | 1676 | ||
1527 | }PIXEL_CLOCK_PARAMETERS_V6; |
1677 | }PIXEL_CLOCK_PARAMETERS_V6; |
1528 | 1678 | ||
1529 | #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 |
1679 | #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 |
1530 | #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 |
1680 | #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 |
1531 | #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c |
1681 | #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c |
1532 | #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 |
1682 | #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 |
1533 | #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 |
1683 | #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 |
1534 | #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 |
1684 | #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 |
1535 | #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c |
1685 | #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c |
1536 | #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 |
1686 | #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 |
1537 | 1687 | ||
1538 | typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 |
1688 | typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 |
1539 | { |
1689 | { |
1540 | PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; |
1690 | PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; |
1541 | }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; |
1691 | }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; |
1542 | 1692 | ||
1543 | typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 |
1693 | typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 |
1544 | { |
1694 | { |
1545 | UCHAR ucStatus; |
1695 | UCHAR ucStatus; |
1546 | UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock |
1696 | UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock |
1547 | UCHAR ucReserved[2]; |
1697 | UCHAR ucReserved[2]; |
1548 | }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; |
1698 | }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; |
1549 | 1699 | ||
1550 | typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 |
1700 | typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 |
1551 | { |
1701 | { |
1552 | PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; |
1702 | PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; |
1553 | }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; |
1703 | }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; |
1554 | 1704 | ||
1555 | /****************************************************************************/ |
1705 | /****************************************************************************/ |
1556 | // Structures used by AdjustDisplayPllTable |
1706 | // Structures used by AdjustDisplayPllTable |
1557 | /****************************************************************************/ |
1707 | /****************************************************************************/ |
1558 | typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS |
1708 | typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS |
1559 | { |
1709 | { |
1560 | USHORT usPixelClock; |
1710 | USHORT usPixelClock; |
1561 | UCHAR ucTransmitterID; |
1711 | UCHAR ucTransmitterID; |
1562 | UCHAR ucEncodeMode; |
1712 | UCHAR ucEncodeMode; |
1563 | union |
1713 | union |
1564 | { |
1714 | { |
1565 | UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit |
1715 | UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit |
1566 | UCHAR ucConfig; //if none DVO, not defined yet |
1716 | UCHAR ucConfig; //if none DVO, not defined yet |
1567 | }; |
1717 | }; |
1568 | UCHAR ucReserved[3]; |
1718 | UCHAR ucReserved[3]; |
1569 | }ADJUST_DISPLAY_PLL_PARAMETERS; |
1719 | }ADJUST_DISPLAY_PLL_PARAMETERS; |
1570 | 1720 | ||
1571 | #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 |
1721 | #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 |
1572 | #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS |
1722 | #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS |
1573 | 1723 | ||
1574 | typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 |
1724 | typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 |
1575 | { |
1725 | { |
1576 | USHORT usPixelClock; // target pixel clock |
1726 | USHORT usPixelClock; // target pixel clock |
1577 | UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h |
1727 | UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h |
1578 | UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI |
1728 | UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI |
1579 | UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX |
1729 | UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX |
1580 | UCHAR ucExtTransmitterID; // external encoder id. |
1730 | UCHAR ucExtTransmitterID; // external encoder id. |
1581 | UCHAR ucReserved[2]; |
1731 | UCHAR ucReserved[2]; |
1582 | }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; |
1732 | }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; |
1583 | 1733 | ||
1584 | // usDispPllConfig v1.2 for RoadRunner |
1734 | // usDispPllConfig v1.2 for RoadRunner |
1585 | #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO |
1735 | #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO |
1586 | #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO |
1736 | #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO |
1587 | #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO |
1737 | #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO |
1588 | #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO |
1738 | #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO |
1589 | #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO |
1739 | #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO |
1590 | #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO |
1740 | #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO |
1591 | #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO |
1741 | #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO |
1592 | #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS |
1742 | #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS |
1593 | #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI |
1743 | #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI |
1594 | #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS |
1744 | #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS |
1595 | 1745 | ||
1596 | 1746 | ||
1597 | typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 |
1747 | typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 |
1598 | { |
1748 | { |
1599 | ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc |
1749 | ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc |
1600 | UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) |
1750 | UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) |
1601 | UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider |
1751 | UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider |
1602 | UCHAR ucReserved[2]; |
1752 | UCHAR ucReserved[2]; |
1603 | }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; |
1753 | }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; |
1604 | 1754 | ||
1605 | typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 |
1755 | typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 |
1606 | { |
1756 | { |
1607 | union |
1757 | union |
1608 | { |
1758 | { |
1609 | ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; |
1759 | ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; |
1610 | ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; |
1760 | ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; |
1611 | }; |
1761 | }; |
1612 | } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; |
1762 | } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; |
1613 | 1763 | ||
1614 | /****************************************************************************/ |
1764 | /****************************************************************************/ |
1615 | // Structures used by EnableYUVTable |
1765 | // Structures used by EnableYUVTable |
1616 | /****************************************************************************/ |
1766 | /****************************************************************************/ |
1617 | typedef struct _ENABLE_YUV_PARAMETERS |
1767 | typedef struct _ENABLE_YUV_PARAMETERS |
1618 | { |
1768 | { |
1619 | UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) |
1769 | UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) |
1620 | UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format |
1770 | UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format |
1621 | UCHAR ucPadding[2]; |
1771 | UCHAR ucPadding[2]; |
1622 | }ENABLE_YUV_PARAMETERS; |
1772 | }ENABLE_YUV_PARAMETERS; |
1623 | #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS |
1773 | #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS |
1624 | 1774 | ||
1625 | /****************************************************************************/ |
1775 | /****************************************************************************/ |
1626 | // Structures used by GetMemoryClockTable |
1776 | // Structures used by GetMemoryClockTable |
1627 | /****************************************************************************/ |
1777 | /****************************************************************************/ |
1628 | typedef struct _GET_MEMORY_CLOCK_PARAMETERS |
1778 | typedef struct _GET_MEMORY_CLOCK_PARAMETERS |
1629 | { |
1779 | { |
1630 | ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit |
1780 | ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit |
1631 | } GET_MEMORY_CLOCK_PARAMETERS; |
1781 | } GET_MEMORY_CLOCK_PARAMETERS; |
1632 | #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS |
1782 | #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS |
1633 | 1783 | ||
1634 | /****************************************************************************/ |
1784 | /****************************************************************************/ |
1635 | // Structures used by GetEngineClockTable |
1785 | // Structures used by GetEngineClockTable |
1636 | /****************************************************************************/ |
1786 | /****************************************************************************/ |
1637 | typedef struct _GET_ENGINE_CLOCK_PARAMETERS |
1787 | typedef struct _GET_ENGINE_CLOCK_PARAMETERS |
1638 | { |
1788 | { |
1639 | ULONG ulReturnEngineClock; // current engine speed in 10KHz unit |
1789 | ULONG ulReturnEngineClock; // current engine speed in 10KHz unit |
1640 | } GET_ENGINE_CLOCK_PARAMETERS; |
1790 | } GET_ENGINE_CLOCK_PARAMETERS; |
1641 | #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS |
1791 | #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS |
1642 | 1792 | ||
1643 | /****************************************************************************/ |
1793 | /****************************************************************************/ |
1644 | // Following Structures and constant may be obsolete |
1794 | // Following Structures and constant may be obsolete |
1645 | /****************************************************************************/ |
1795 | /****************************************************************************/ |
1646 | //Maxium 8 bytes,the data read in will be placed in the parameter space. |
1796 | //Maxium 8 bytes,the data read in will be placed in the parameter space. |
1647 | //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed |
1797 | //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed |
1648 | typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS |
1798 | typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS |
1649 | { |
1799 | { |
1650 | USHORT usPrescale; //Ratio between Engine clock and I2C clock |
1800 | USHORT usPrescale; //Ratio between Engine clock and I2C clock |
1651 | USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID |
1801 | USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID |
1652 | USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status |
1802 | USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status |
1653 | //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte |
1803 | //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte |
1654 | UCHAR ucSlaveAddr; //Read from which slave |
1804 | UCHAR ucSlaveAddr; //Read from which slave |
1655 | UCHAR ucLineNumber; //Read from which HW assisted line |
1805 | UCHAR ucLineNumber; //Read from which HW assisted line |
1656 | }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; |
1806 | }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; |
1657 | #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS |
1807 | #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS |
1658 | 1808 | ||
1659 | 1809 | ||
1660 | #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 |
1810 | #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 |
1661 | #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 |
1811 | #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 |
1662 | #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 |
1812 | #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 |
1663 | #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 |
1813 | #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 |
1664 | #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 |
1814 | #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 |
1665 | 1815 | ||
1666 | typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
1816 | typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
1667 | { |
1817 | { |
1668 | USHORT usPrescale; //Ratio between Engine clock and I2C clock |
1818 | USHORT usPrescale; //Ratio between Engine clock and I2C clock |
1669 | USHORT usByteOffset; //Write to which byte |
1819 | USHORT usByteOffset; //Write to which byte |
1670 | //Upper portion of usByteOffset is Format of data |
1820 | //Upper portion of usByteOffset is Format of data |
1671 | //1bytePS+offsetPS |
1821 | //1bytePS+offsetPS |
1672 | //2bytesPS+offsetPS |
1822 | //2bytesPS+offsetPS |
1673 | //blockID+offsetPS |
1823 | //blockID+offsetPS |
1674 | //blockID+offsetID |
1824 | //blockID+offsetID |
1675 | //blockID+counterID+offsetID |
1825 | //blockID+counterID+offsetID |
1676 | UCHAR ucData; //PS data1 |
1826 | UCHAR ucData; //PS data1 |
1677 | UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 |
1827 | UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 |
1678 | UCHAR ucSlaveAddr; //Write to which slave |
1828 | UCHAR ucSlaveAddr; //Write to which slave |
1679 | UCHAR ucLineNumber; //Write from which HW assisted line |
1829 | UCHAR ucLineNumber; //Write from which HW assisted line |
1680 | }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; |
1830 | }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; |
1681 | 1831 | ||
1682 | #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
1832 | #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
1683 | 1833 | ||
1684 | typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS |
1834 | typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS |
1685 | { |
1835 | { |
1686 | USHORT usPrescale; //Ratio between Engine clock and I2C clock |
1836 | USHORT usPrescale; //Ratio between Engine clock and I2C clock |
1687 | UCHAR ucSlaveAddr; //Write to which slave |
1837 | UCHAR ucSlaveAddr; //Write to which slave |
1688 | UCHAR ucLineNumber; //Write from which HW assisted line |
1838 | UCHAR ucLineNumber; //Write from which HW assisted line |
1689 | }SET_UP_HW_I2C_DATA_PARAMETERS; |
1839 | }SET_UP_HW_I2C_DATA_PARAMETERS; |
1690 | 1840 | ||
1691 | 1841 | ||
1692 | /**************************************************************************/ |
1842 | /**************************************************************************/ |
1693 | #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
1843 | #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
1694 | 1844 | ||
1695 | 1845 | ||
1696 | /****************************************************************************/ |
1846 | /****************************************************************************/ |
1697 | // Structures used by PowerConnectorDetectionTable |
1847 | // Structures used by PowerConnectorDetectionTable |
1698 | /****************************************************************************/ |
1848 | /****************************************************************************/ |
1699 | typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS |
1849 | typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS |
1700 | { |
1850 | { |
1701 | UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected |
1851 | UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected |
1702 | UCHAR ucPwrBehaviorId; |
1852 | UCHAR ucPwrBehaviorId; |
1703 | USHORT usPwrBudget; //how much power currently boot to in unit of watt |
1853 | USHORT usPwrBudget; //how much power currently boot to in unit of watt |
1704 | }POWER_CONNECTOR_DETECTION_PARAMETERS; |
1854 | }POWER_CONNECTOR_DETECTION_PARAMETERS; |
1705 | 1855 | ||
1706 | typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION |
1856 | typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION |
1707 | { |
1857 | { |
1708 | UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected |
1858 | UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected |
1709 | UCHAR ucReserved; |
1859 | UCHAR ucReserved; |
1710 | USHORT usPwrBudget; //how much power currently boot to in unit of watt |
1860 | USHORT usPwrBudget; //how much power currently boot to in unit of watt |
1711 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; |
1861 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; |
1712 | }POWER_CONNECTOR_DETECTION_PS_ALLOCATION; |
1862 | }POWER_CONNECTOR_DETECTION_PS_ALLOCATION; |
1713 | 1863 | ||
1714 | /****************************LVDS SS Command Table Definitions**********************/ |
1864 | /****************************LVDS SS Command Table Definitions**********************/ |
1715 | 1865 | ||
1716 | /****************************************************************************/ |
1866 | /****************************************************************************/ |
1717 | // Structures used by EnableSpreadSpectrumOnPPLLTable |
1867 | // Structures used by EnableSpreadSpectrumOnPPLLTable |
1718 | /****************************************************************************/ |
1868 | /****************************************************************************/ |
1719 | typedef struct _ENABLE_LVDS_SS_PARAMETERS |
1869 | typedef struct _ENABLE_LVDS_SS_PARAMETERS |
1720 | { |
1870 | { |
1721 | USHORT usSpreadSpectrumPercentage; |
1871 | USHORT usSpreadSpectrumPercentage; |
1722 | UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD |
1872 | UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD |
1723 | UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY |
1873 | UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY |
1724 | UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE |
1874 | UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE |
1725 | UCHAR ucPadding[3]; |
1875 | UCHAR ucPadding[3]; |
1726 | }ENABLE_LVDS_SS_PARAMETERS; |
1876 | }ENABLE_LVDS_SS_PARAMETERS; |
1727 | 1877 | ||
1728 | //ucTableFormatRevision=1,ucTableContentRevision=2 |
1878 | //ucTableFormatRevision=1,ucTableContentRevision=2 |
1729 | typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 |
1879 | typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 |
1730 | { |
1880 | { |
1731 | USHORT usSpreadSpectrumPercentage; |
1881 | USHORT usSpreadSpectrumPercentage; |
1732 | UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD |
1882 | UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD |
1733 | UCHAR ucSpreadSpectrumStep; // |
1883 | UCHAR ucSpreadSpectrumStep; // |
1734 | UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE |
1884 | UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE |
1735 | UCHAR ucSpreadSpectrumDelay; |
1885 | UCHAR ucSpreadSpectrumDelay; |
1736 | UCHAR ucSpreadSpectrumRange; |
1886 | UCHAR ucSpreadSpectrumRange; |
1737 | UCHAR ucPadding; |
1887 | UCHAR ucPadding; |
1738 | }ENABLE_LVDS_SS_PARAMETERS_V2; |
1888 | }ENABLE_LVDS_SS_PARAMETERS_V2; |
1739 | 1889 | ||
1740 | //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. |
1890 | //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. |
1741 | typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL |
1891 | typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL |
1742 | { |
1892 | { |
1743 | USHORT usSpreadSpectrumPercentage; |
1893 | USHORT usSpreadSpectrumPercentage; |
1744 | UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD |
1894 | UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD |
1745 | UCHAR ucSpreadSpectrumStep; // |
1895 | UCHAR ucSpreadSpectrumStep; // |
1746 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
1896 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
1747 | UCHAR ucSpreadSpectrumDelay; |
1897 | UCHAR ucSpreadSpectrumDelay; |
1748 | UCHAR ucSpreadSpectrumRange; |
1898 | UCHAR ucSpreadSpectrumRange; |
1749 | UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 |
1899 | UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 |
1750 | }ENABLE_SPREAD_SPECTRUM_ON_PPLL; |
1900 | }ENABLE_SPREAD_SPECTRUM_ON_PPLL; |
1751 | 1901 | ||
1752 | typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 |
1902 | typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 |
1753 | { |
1903 | { |
1754 | USHORT usSpreadSpectrumPercentage; |
1904 | USHORT usSpreadSpectrumPercentage; |
1755 | UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. |
1905 | UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. |
1756 | // Bit[1]: 1-Ext. 0-Int. |
1906 | // Bit[1]: 1-Ext. 0-Int. |
1757 | // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL |
1907 | // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL |
1758 | // Bits[7:4] reserved |
1908 | // Bits[7:4] reserved |
1759 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
1909 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
1760 | USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] |
1910 | USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] |
1761 | USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC |
1911 | USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC |
1762 | }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; |
1912 | }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; |
1763 | 1913 | ||
1764 | #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 |
1914 | #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 |
1765 | #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 |
1915 | #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 |
1766 | #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 |
1916 | #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 |
1767 | #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c |
1917 | #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c |
1768 | #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 |
1918 | #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 |
1769 | #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 |
1919 | #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 |
1770 | #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 |
1920 | #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 |
1771 | #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF |
1921 | #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF |
1772 | #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 |
1922 | #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 |
1773 | #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 |
1923 | #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 |
1774 | #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 |
1924 | #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 |
1775 | 1925 | ||
1776 | // Used by DCE5.0 |
1926 | // Used by DCE5.0 |
1777 | typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 |
1927 | typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 |
1778 | { |
1928 | { |
1779 | USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 |
1929 | USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 |
1780 | UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. |
1930 | UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. |
1781 | // Bit[1]: 1-Ext. 0-Int. |
1931 | // Bit[1]: 1-Ext. 0-Int. |
1782 | // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL |
1932 | // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL |
1783 | // Bits[7:4] reserved |
1933 | // Bits[7:4] reserved |
1784 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
1934 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
1785 | USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] |
1935 | USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] |
1786 | USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC |
1936 | USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC |
1787 | }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; |
1937 | }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; |
1788 | 1938 | ||
1789 | #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 |
1939 | #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 |
1790 | #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 |
1940 | #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 |
1791 | #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 |
1941 | #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 |
1792 | #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c |
1942 | #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c |
1793 | #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 |
1943 | #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 |
1794 | #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 |
1944 | #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 |
1795 | #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 |
1945 | #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 |
- | 1946 | #define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL |
|
1796 | #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF |
1947 | #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF |
1797 | #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 |
1948 | #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 |
1798 | #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 |
1949 | #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 |
1799 | #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 |
1950 | #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 |
1800 | 1951 | ||
1801 | #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL |
1952 | #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL |
1802 | 1953 | ||
1803 | /**************************************************************************/ |
1954 | /**************************************************************************/ |
1804 | 1955 | ||
1805 | typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION |
1956 | typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION |
1806 | { |
1957 | { |
1807 | PIXEL_CLOCK_PARAMETERS sPCLKInput; |
1958 | PIXEL_CLOCK_PARAMETERS sPCLKInput; |
1808 | ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion |
1959 | ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion |
1809 | }SET_PIXEL_CLOCK_PS_ALLOCATION; |
1960 | }SET_PIXEL_CLOCK_PS_ALLOCATION; |
1810 | 1961 | ||
1811 | #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION |
1962 | #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION |
1812 | 1963 | ||
1813 | /****************************************************************************/ |
1964 | /****************************************************************************/ |
1814 | // Structures used by ### |
1965 | // Structures used by ### |
1815 | /****************************************************************************/ |
1966 | /****************************************************************************/ |
1816 | typedef struct _MEMORY_TRAINING_PARAMETERS |
1967 | typedef struct _MEMORY_TRAINING_PARAMETERS |
1817 | { |
1968 | { |
1818 | ULONG ulTargetMemoryClock; //In 10Khz unit |
1969 | ULONG ulTargetMemoryClock; //In 10Khz unit |
1819 | }MEMORY_TRAINING_PARAMETERS; |
1970 | }MEMORY_TRAINING_PARAMETERS; |
1820 | #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS |
1971 | #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS |
1821 | 1972 | ||
1822 | 1973 | ||
1823 | /****************************LVDS and other encoder command table definitions **********************/ |
1974 | /****************************LVDS and other encoder command table definitions **********************/ |
1824 | 1975 | ||
1825 | 1976 | ||
1826 | /****************************************************************************/ |
1977 | /****************************************************************************/ |
1827 | // Structures used by LVDSEncoderControlTable (Before DCE30) |
1978 | // Structures used by LVDSEncoderControlTable (Before DCE30) |
1828 | // LVTMAEncoderControlTable (Before DCE30) |
1979 | // LVTMAEncoderControlTable (Before DCE30) |
1829 | // TMDSAEncoderControlTable (Before DCE30) |
1980 | // TMDSAEncoderControlTable (Before DCE30) |
1830 | /****************************************************************************/ |
1981 | /****************************************************************************/ |
1831 | typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS |
1982 | typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS |
1832 | { |
1983 | { |
1833 | USHORT usPixelClock; // in 10KHz; for bios convenient |
1984 | USHORT usPixelClock; // in 10KHz; for bios convenient |
1834 | UCHAR ucMisc; // bit0=0: Enable single link |
1985 | UCHAR ucMisc; // bit0=0: Enable single link |
1835 | // =1: Enable dual link |
1986 | // =1: Enable dual link |
1836 | // Bit1=0: 666RGB |
1987 | // Bit1=0: 666RGB |
1837 | // =1: 888RGB |
1988 | // =1: 888RGB |
1838 | UCHAR ucAction; // 0: turn off encoder |
1989 | UCHAR ucAction; // 0: turn off encoder |
1839 | // 1: setup and turn on encoder |
1990 | // 1: setup and turn on encoder |
1840 | }LVDS_ENCODER_CONTROL_PARAMETERS; |
1991 | }LVDS_ENCODER_CONTROL_PARAMETERS; |
1841 | 1992 | ||
1842 | #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS |
1993 | #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS |
1843 | 1994 | ||
1844 | #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS |
1995 | #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS |
1845 | #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS |
1996 | #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS |
1846 | 1997 | ||
1847 | #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS |
1998 | #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS |
1848 | #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS |
1999 | #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS |
1849 | 2000 | ||
1850 | 2001 | ||
1851 | //ucTableFormatRevision=1,ucTableContentRevision=2 |
2002 | //ucTableFormatRevision=1,ucTableContentRevision=2 |
1852 | typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
2003 | typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
1853 | { |
2004 | { |
1854 | USHORT usPixelClock; // in 10KHz; for bios convenient |
2005 | USHORT usPixelClock; // in 10KHz; for bios convenient |
1855 | UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below |
2006 | UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below |
1856 | UCHAR ucAction; // 0: turn off encoder |
2007 | UCHAR ucAction; // 0: turn off encoder |
1857 | // 1: setup and turn on encoder |
2008 | // 1: setup and turn on encoder |
1858 | UCHAR ucTruncate; // bit0=0: Disable truncate |
2009 | UCHAR ucTruncate; // bit0=0: Disable truncate |
1859 | // =1: Enable truncate |
2010 | // =1: Enable truncate |
1860 | // bit4=0: 666RGB |
2011 | // bit4=0: 666RGB |
1861 | // =1: 888RGB |
2012 | // =1: 888RGB |
1862 | UCHAR ucSpatial; // bit0=0: Disable spatial dithering |
2013 | UCHAR ucSpatial; // bit0=0: Disable spatial dithering |
1863 | // =1: Enable spatial dithering |
2014 | // =1: Enable spatial dithering |
1864 | // bit4=0: 666RGB |
2015 | // bit4=0: 666RGB |
1865 | // =1: 888RGB |
2016 | // =1: 888RGB |
1866 | UCHAR ucTemporal; // bit0=0: Disable temporal dithering |
2017 | UCHAR ucTemporal; // bit0=0: Disable temporal dithering |
1867 | // =1: Enable temporal dithering |
2018 | // =1: Enable temporal dithering |
1868 | // bit4=0: 666RGB |
2019 | // bit4=0: 666RGB |
1869 | // =1: 888RGB |
2020 | // =1: 888RGB |
1870 | // bit5=0: Gray level 2 |
2021 | // bit5=0: Gray level 2 |
1871 | // =1: Gray level 4 |
2022 | // =1: Gray level 4 |
1872 | UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E |
2023 | UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E |
1873 | // =1: 25FRC_SEL pattern F |
2024 | // =1: 25FRC_SEL pattern F |
1874 | // bit6:5=0: 50FRC_SEL pattern A |
2025 | // bit6:5=0: 50FRC_SEL pattern A |
1875 | // =1: 50FRC_SEL pattern B |
2026 | // =1: 50FRC_SEL pattern B |
1876 | // =2: 50FRC_SEL pattern C |
2027 | // =2: 50FRC_SEL pattern C |
1877 | // =3: 50FRC_SEL pattern D |
2028 | // =3: 50FRC_SEL pattern D |
1878 | // bit7=0: 75FRC_SEL pattern E |
2029 | // bit7=0: 75FRC_SEL pattern E |
1879 | // =1: 75FRC_SEL pattern F |
2030 | // =1: 75FRC_SEL pattern F |
1880 | }LVDS_ENCODER_CONTROL_PARAMETERS_V2; |
2031 | }LVDS_ENCODER_CONTROL_PARAMETERS_V2; |
1881 | 2032 | ||
1882 | #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
2033 | #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
1883 | 2034 | ||
1884 | #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
2035 | #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
1885 | #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 |
2036 | #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 |
1886 | 2037 | ||
1887 | #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 |
2038 | #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 |
1888 | #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 |
2039 | #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 |
1889 | 2040 | ||
1890 | #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
2041 | #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
1891 | #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
2042 | #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
1892 | 2043 | ||
1893 | #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
2044 | #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
1894 | #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 |
2045 | #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 |
1895 | 2046 | ||
1896 | #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
2047 | #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
1897 | #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 |
2048 | #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 |
1898 | 2049 | ||
1899 | /****************************************************************************/ |
2050 | /****************************************************************************/ |
1900 | // Structures used by ### |
2051 | // Structures used by ### |
1901 | /****************************************************************************/ |
2052 | /****************************************************************************/ |
1902 | typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS |
2053 | typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS |
1903 | { |
2054 | { |
1904 | UCHAR ucEnable; // Enable or Disable External TMDS encoder |
2055 | UCHAR ucEnable; // Enable or Disable External TMDS encoder |
1905 | UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} |
2056 | UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} |
1906 | UCHAR ucPadding[2]; |
2057 | UCHAR ucPadding[2]; |
1907 | }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; |
2058 | }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; |
1908 | 2059 | ||
1909 | typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION |
2060 | typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION |
1910 | { |
2061 | { |
1911 | ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; |
2062 | ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; |
1912 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion |
2063 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion |
1913 | }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; |
2064 | }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; |
1914 | 2065 | ||
1915 | #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
2066 | #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
1916 | 2067 | ||
1917 | typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 |
2068 | typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 |
1918 | { |
2069 | { |
1919 | ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; |
2070 | ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; |
1920 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion |
2071 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion |
1921 | }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; |
2072 | }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; |
1922 | 2073 | ||
1923 | typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION |
2074 | typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION |
1924 | { |
2075 | { |
1925 | DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; |
2076 | DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; |
1926 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; |
2077 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; |
1927 | }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; |
2078 | }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; |
1928 | 2079 | ||
1929 | /****************************************************************************/ |
2080 | /****************************************************************************/ |
1930 | // Structures used by DVOEncoderControlTable |
2081 | // Structures used by DVOEncoderControlTable |
1931 | /****************************************************************************/ |
2082 | /****************************************************************************/ |
1932 | //ucTableFormatRevision=1,ucTableContentRevision=3 |
2083 | //ucTableFormatRevision=1,ucTableContentRevision=3 |
1933 | 2084 | ||
1934 | //ucDVOConfig: |
2085 | //ucDVOConfig: |
1935 | #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 |
2086 | #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 |
1936 | #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 |
2087 | #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 |
1937 | #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 |
2088 | #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 |
1938 | #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c |
2089 | #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c |
1939 | #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 |
2090 | #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 |
1940 | #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 |
2091 | #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 |
1941 | #define DVO_ENCODER_CONFIG_24BIT 0x08 |
2092 | #define DVO_ENCODER_CONFIG_24BIT 0x08 |
1942 | 2093 | ||
1943 | typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 |
2094 | typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 |
1944 | { |
2095 | { |
1945 | USHORT usPixelClock; |
2096 | USHORT usPixelClock; |
1946 | UCHAR ucDVOConfig; |
2097 | UCHAR ucDVOConfig; |
1947 | UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT |
2098 | UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT |
1948 | UCHAR ucReseved[4]; |
2099 | UCHAR ucReseved[4]; |
1949 | }DVO_ENCODER_CONTROL_PARAMETERS_V3; |
2100 | }DVO_ENCODER_CONTROL_PARAMETERS_V3; |
1950 | #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 |
2101 | #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 |
1951 | 2102 | ||
1952 | //ucTableFormatRevision=1 |
2103 | //ucTableFormatRevision=1 |
1953 | //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for |
2104 | //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for |
1954 | // bit1=0: non-coherent mode |
2105 | // bit1=0: non-coherent mode |
1955 | // =1: coherent mode |
2106 | // =1: coherent mode |
1956 | 2107 | ||
1957 | //========================================================================================== |
2108 | //========================================================================================== |
1958 | //Only change is here next time when changing encoder parameter definitions again! |
2109 | //Only change is here next time when changing encoder parameter definitions again! |
1959 | #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
2110 | #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
1960 | #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST |
2111 | #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST |
1961 | 2112 | ||
1962 | #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
2113 | #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
1963 | #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST |
2114 | #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST |
1964 | 2115 | ||
1965 | #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
2116 | #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
1966 | #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST |
2117 | #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST |
1967 | 2118 | ||
1968 | #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS |
2119 | #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS |
1969 | #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION |
2120 | #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION |
1970 | 2121 | ||
1971 | //========================================================================================== |
2122 | //========================================================================================== |
1972 | #define PANEL_ENCODER_MISC_DUAL 0x01 |
2123 | #define PANEL_ENCODER_MISC_DUAL 0x01 |
1973 | #define PANEL_ENCODER_MISC_COHERENT 0x02 |
2124 | #define PANEL_ENCODER_MISC_COHERENT 0x02 |
1974 | #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 |
2125 | #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 |
1975 | #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 |
2126 | #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 |
1976 | 2127 | ||
1977 | #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE |
2128 | #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE |
1978 | #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE |
2129 | #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE |
1979 | #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) |
2130 | #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) |
1980 | 2131 | ||
1981 | #define PANEL_ENCODER_TRUNCATE_EN 0x01 |
2132 | #define PANEL_ENCODER_TRUNCATE_EN 0x01 |
1982 | #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 |
2133 | #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 |
1983 | #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 |
2134 | #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 |
1984 | #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 |
2135 | #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 |
1985 | #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 |
2136 | #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 |
1986 | #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 |
2137 | #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 |
1987 | #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 |
2138 | #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 |
1988 | #define PANEL_ENCODER_25FRC_MASK 0x10 |
2139 | #define PANEL_ENCODER_25FRC_MASK 0x10 |
1989 | #define PANEL_ENCODER_25FRC_E 0x00 |
2140 | #define PANEL_ENCODER_25FRC_E 0x00 |
1990 | #define PANEL_ENCODER_25FRC_F 0x10 |
2141 | #define PANEL_ENCODER_25FRC_F 0x10 |
1991 | #define PANEL_ENCODER_50FRC_MASK 0x60 |
2142 | #define PANEL_ENCODER_50FRC_MASK 0x60 |
1992 | #define PANEL_ENCODER_50FRC_A 0x00 |
2143 | #define PANEL_ENCODER_50FRC_A 0x00 |
1993 | #define PANEL_ENCODER_50FRC_B 0x20 |
2144 | #define PANEL_ENCODER_50FRC_B 0x20 |
1994 | #define PANEL_ENCODER_50FRC_C 0x40 |
2145 | #define PANEL_ENCODER_50FRC_C 0x40 |
1995 | #define PANEL_ENCODER_50FRC_D 0x60 |
2146 | #define PANEL_ENCODER_50FRC_D 0x60 |
1996 | #define PANEL_ENCODER_75FRC_MASK 0x80 |
2147 | #define PANEL_ENCODER_75FRC_MASK 0x80 |
1997 | #define PANEL_ENCODER_75FRC_E 0x00 |
2148 | #define PANEL_ENCODER_75FRC_E 0x00 |
1998 | #define PANEL_ENCODER_75FRC_F 0x80 |
2149 | #define PANEL_ENCODER_75FRC_F 0x80 |
1999 | 2150 | ||
2000 | /****************************************************************************/ |
2151 | /****************************************************************************/ |
2001 | // Structures used by SetVoltageTable |
2152 | // Structures used by SetVoltageTable |
2002 | /****************************************************************************/ |
2153 | /****************************************************************************/ |
2003 | #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 |
2154 | #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 |
2004 | #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 |
2155 | #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 |
2005 | #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 |
2156 | #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 |
2006 | #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 |
2157 | #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 |
2007 | #define SET_VOLTAGE_INIT_MODE 5 |
2158 | #define SET_VOLTAGE_INIT_MODE 5 |
2008 | #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic |
2159 | #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic |
2009 | 2160 | ||
2010 | #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 |
2161 | #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 |
2011 | #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 |
2162 | #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 |
2012 | #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 |
2163 | #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 |
2013 | 2164 | ||
2014 | #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 |
2165 | #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 |
2015 | #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 |
2166 | #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 |
2016 | #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 |
2167 | #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 |
2017 | 2168 | ||
2018 | typedef struct _SET_VOLTAGE_PARAMETERS |
2169 | typedef struct _SET_VOLTAGE_PARAMETERS |
2019 | { |
2170 | { |
2020 | UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ |
2171 | UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ |
2021 | UCHAR ucVoltageMode; // To set all, to set source A or source B or ... |
2172 | UCHAR ucVoltageMode; // To set all, to set source A or source B or ... |
2022 | UCHAR ucVoltageIndex; // An index to tell which voltage level |
2173 | UCHAR ucVoltageIndex; // An index to tell which voltage level |
2023 | UCHAR ucReserved; |
2174 | UCHAR ucReserved; |
2024 | }SET_VOLTAGE_PARAMETERS; |
2175 | }SET_VOLTAGE_PARAMETERS; |
2025 | 2176 | ||
2026 | typedef struct _SET_VOLTAGE_PARAMETERS_V2 |
2177 | typedef struct _SET_VOLTAGE_PARAMETERS_V2 |
2027 | { |
2178 | { |
2028 | UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ |
2179 | UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ |
2029 | UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode |
2180 | UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode |
2030 | USHORT usVoltageLevel; // real voltage level |
2181 | USHORT usVoltageLevel; // real voltage level |
2031 | }SET_VOLTAGE_PARAMETERS_V2; |
2182 | }SET_VOLTAGE_PARAMETERS_V2; |
- | 2183 | ||
- | 2184 | ||
- | 2185 | typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 |
|
- | 2186 | { |
|
- | 2187 | UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI |
|
- | 2188 | UCHAR ucVoltageMode; // Indicate action: Set voltage level |
|
- | 2189 | USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) |
|
- | 2190 | }SET_VOLTAGE_PARAMETERS_V1_3; |
|
- | 2191 | ||
- | 2192 | //ucVoltageType |
|
- | 2193 | #define VOLTAGE_TYPE_VDDC 1 |
|
- | 2194 | #define VOLTAGE_TYPE_MVDDC 2 |
|
- | 2195 | #define VOLTAGE_TYPE_MVDDQ 3 |
|
- | 2196 | #define VOLTAGE_TYPE_VDDCI 4 |
|
- | 2197 | ||
- | 2198 | //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode |
|
- | 2199 | #define ATOM_SET_VOLTAGE 0 //Set voltage Level |
|
- | 2200 | #define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator |
|
- | 2201 | #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase |
|
- | 2202 | #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used in SetVoltageTable v1.3 |
|
- | 2203 | #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID |
|
- | 2204 | ||
- | 2205 | // define vitual voltage id in usVoltageLevel |
|
- | 2206 | #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 |
|
- | 2207 | #define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 |
|
- | 2208 | #define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 |
|
- | 2209 | #define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 |
|
2032 | 2210 | ||
2033 | typedef struct _SET_VOLTAGE_PS_ALLOCATION |
2211 | typedef struct _SET_VOLTAGE_PS_ALLOCATION |
2034 | { |
2212 | { |
2035 | SET_VOLTAGE_PARAMETERS sASICSetVoltage; |
2213 | SET_VOLTAGE_PARAMETERS sASICSetVoltage; |
2036 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; |
2214 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; |
2037 | }SET_VOLTAGE_PS_ALLOCATION; |
2215 | }SET_VOLTAGE_PS_ALLOCATION; |
- | 2216 | ||
- | 2217 | // New Added from SI for GetVoltageInfoTable, input parameter structure |
|
- | 2218 | typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 |
|
- | 2219 | { |
|
- | 2220 | UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI |
|
- | 2221 | UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info |
|
- | 2222 | USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id |
|
- | 2223 | ULONG ulReserved; |
|
- | 2224 | }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; |
|
- | 2225 | ||
- | 2226 | // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID |
|
- | 2227 | typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 |
|
- | 2228 | { |
|
- | 2229 | ULONG ulVotlageGpioState; |
|
- | 2230 | ULONG ulVoltageGPioMask; |
|
- | 2231 | }GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; |
|
- | 2232 | ||
- | 2233 | // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID |
|
- | 2234 | typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 |
|
- | 2235 | { |
|
- | 2236 | USHORT usVoltageLevel; |
|
- | 2237 | USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator |
|
- | 2238 | ULONG ulReseved; |
|
- | 2239 | }GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; |
|
- | 2240 | ||
- | 2241 | ||
- | 2242 | // GetVoltageInfo v1.1 ucVoltageMode |
|
- | 2243 | #define ATOM_GET_VOLTAGE_VID 0x00 |
|
- | 2244 | #define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 |
|
- | 2245 | #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 |
|
- | 2246 | // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state |
|
- | 2247 | #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 |
|
- | 2248 | ||
- | 2249 | // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state |
|
- | 2250 | #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 |
|
- | 2251 | // undefined power state |
|
- | 2252 | #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 |
|
- | 2253 | #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 |
|
2038 | 2254 | ||
2039 | /****************************************************************************/ |
2255 | /****************************************************************************/ |
2040 | // Structures used by TVEncoderControlTable |
2256 | // Structures used by TVEncoderControlTable |
2041 | /****************************************************************************/ |
2257 | /****************************************************************************/ |
2042 | typedef struct _TV_ENCODER_CONTROL_PARAMETERS |
2258 | typedef struct _TV_ENCODER_CONTROL_PARAMETERS |
2043 | { |
2259 | { |
2044 | USHORT usPixelClock; // in 10KHz; for bios convenient |
2260 | USHORT usPixelClock; // in 10KHz; for bios convenient |
2045 | UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." |
2261 | UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." |
2046 | UCHAR ucAction; // 0: turn off encoder |
2262 | UCHAR ucAction; // 0: turn off encoder |
2047 | // 1: setup and turn on encoder |
2263 | // 1: setup and turn on encoder |
2048 | }TV_ENCODER_CONTROL_PARAMETERS; |
2264 | }TV_ENCODER_CONTROL_PARAMETERS; |
2049 | 2265 | ||
2050 | typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION |
2266 | typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION |
2051 | { |
2267 | { |
2052 | TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; |
2268 | TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; |
2053 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one |
2269 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one |
2054 | }TV_ENCODER_CONTROL_PS_ALLOCATION; |
2270 | }TV_ENCODER_CONTROL_PS_ALLOCATION; |
2055 | 2271 | ||
2056 | //==============================Data Table Portion==================================== |
2272 | //==============================Data Table Portion==================================== |
2057 | 2273 | ||
2058 | /****************************************************************************/ |
2274 | /****************************************************************************/ |
2059 | // Structure used in Data.mtb |
2275 | // Structure used in Data.mtb |
2060 | /****************************************************************************/ |
2276 | /****************************************************************************/ |
2061 | typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES |
2277 | typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES |
2062 | { |
2278 | { |
2063 | USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! |
2279 | USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! |
2064 | USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios |
2280 | USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios |
2065 | USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios |
2281 | USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios |
2066 | USHORT StandardVESA_Timing; // Only used by Bios |
2282 | USHORT StandardVESA_Timing; // Only used by Bios |
2067 | USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 |
2283 | USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 |
2068 | USHORT DAC_Info; // Will be obsolete from R600 |
2284 | USHORT PaletteData; // Only used by BIOS |
2069 | USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info |
2285 | USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info |
2070 | USHORT TMDS_Info; // Will be obsolete from R600 |
2286 | USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 |
2071 | USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 |
2287 | USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 |
2072 | USHORT SupportedDevicesInfo; // Will be obsolete from R600 |
2288 | USHORT SupportedDevicesInfo; // Will be obsolete from R600 |
2073 | USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 |
2289 | USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 |
2074 | USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 |
2290 | USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 |
2075 | USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 |
2291 | USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 |
2076 | USHORT VESA_ToInternalModeLUT; // Only used by Bios |
2292 | USHORT VESA_ToInternalModeLUT; // Only used by Bios |
2077 | USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 |
2293 | USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 |
2078 | USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 |
2294 | USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 |
2079 | USHORT CompassionateData; // Will be obsolete from R600 |
2295 | USHORT CompassionateData; // Will be obsolete from R600 |
2080 | USHORT SaveRestoreInfo; // Only used by Bios |
2296 | USHORT SaveRestoreInfo; // Only used by Bios |
2081 | USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info |
2297 | USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info |
2082 | USHORT OemInfo; // Defined and used by external SW, should be obsolete soon |
2298 | USHORT OemInfo; // Defined and used by external SW, should be obsolete soon |
2083 | USHORT XTMDS_Info; // Will be obsolete from R600 |
2299 | USHORT XTMDS_Info; // Will be obsolete from R600 |
2084 | USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used |
2300 | USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used |
2085 | USHORT Object_Header; // Shared by various SW components,latest version 1.1 |
2301 | USHORT Object_Header; // Shared by various SW components,latest version 1.1 |
2086 | USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! |
2302 | USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! |
2087 | USHORT MC_InitParameter; // Only used by command table |
2303 | USHORT MC_InitParameter; // Only used by command table |
2088 | USHORT ASIC_VDDC_Info; // Will be obsolete from R600 |
2304 | USHORT ASIC_VDDC_Info; // Will be obsolete from R600 |
2089 | USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" |
2305 | USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" |
2090 | USHORT TV_VideoMode; // Only used by command table |
2306 | USHORT TV_VideoMode; // Only used by command table |
2091 | USHORT VRAM_Info; // Only used by command table, latest version 1.3 |
2307 | USHORT VRAM_Info; // Only used by command table, latest version 1.3 |
2092 | USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 |
2308 | USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 |
2093 | USHORT IntegratedSystemInfo; // Shared by various SW components |
2309 | USHORT IntegratedSystemInfo; // Shared by various SW components |
2094 | USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 |
2310 | USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 |
2095 | USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 |
2311 | USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 |
2096 | USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 |
2312 | USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 |
2097 | }ATOM_MASTER_LIST_OF_DATA_TABLES; |
2313 | }ATOM_MASTER_LIST_OF_DATA_TABLES; |
2098 | - | ||
2099 | // For backward compatible |
- | |
2100 | #define LVDS_Info LCD_Info |
- | |
2101 | 2314 | ||
2102 | typedef struct _ATOM_MASTER_DATA_TABLE |
2315 | typedef struct _ATOM_MASTER_DATA_TABLE |
2103 | { |
2316 | { |
2104 | ATOM_COMMON_TABLE_HEADER sHeader; |
2317 | ATOM_COMMON_TABLE_HEADER sHeader; |
2105 | ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; |
2318 | ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; |
2106 | }ATOM_MASTER_DATA_TABLE; |
2319 | }ATOM_MASTER_DATA_TABLE; |
- | 2320 | ||
- | 2321 | // For backward compatible |
|
- | 2322 | #define LVDS_Info LCD_Info |
|
- | 2323 | #define DAC_Info PaletteData |
|
2107 | 2324 | #define TMDS_Info DIGTransmitterInfo |
|
2108 | 2325 | ||
2109 | /****************************************************************************/ |
2326 | /****************************************************************************/ |
2110 | // Structure used in MultimediaCapabilityInfoTable |
2327 | // Structure used in MultimediaCapabilityInfoTable |
2111 | /****************************************************************************/ |
2328 | /****************************************************************************/ |
2112 | typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO |
2329 | typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO |
2113 | { |
2330 | { |
2114 | ATOM_COMMON_TABLE_HEADER sHeader; |
2331 | ATOM_COMMON_TABLE_HEADER sHeader; |
2115 | ULONG ulSignature; // HW info table signature string "$ATI" |
2332 | ULONG ulSignature; // HW info table signature string "$ATI" |
2116 | UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) |
2333 | UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) |
2117 | UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) |
2334 | UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) |
2118 | UCHAR ucVideoPortInfo; // Provides the video port capabilities |
2335 | UCHAR ucVideoPortInfo; // Provides the video port capabilities |
2119 | UCHAR ucHostPortInfo; // Provides host port configuration information |
2336 | UCHAR ucHostPortInfo; // Provides host port configuration information |
2120 | }ATOM_MULTIMEDIA_CAPABILITY_INFO; |
2337 | }ATOM_MULTIMEDIA_CAPABILITY_INFO; |
2121 | 2338 | ||
2122 | /****************************************************************************/ |
2339 | /****************************************************************************/ |
2123 | // Structure used in MultimediaConfigInfoTable |
2340 | // Structure used in MultimediaConfigInfoTable |
2124 | /****************************************************************************/ |
2341 | /****************************************************************************/ |
2125 | typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO |
2342 | typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO |
2126 | { |
2343 | { |
2127 | ATOM_COMMON_TABLE_HEADER sHeader; |
2344 | ATOM_COMMON_TABLE_HEADER sHeader; |
2128 | ULONG ulSignature; // MM info table signature sting "$MMT" |
2345 | ULONG ulSignature; // MM info table signature sting "$MMT" |
2129 | UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) |
2346 | UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) |
2130 | UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) |
2347 | UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) |
2131 | UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting |
2348 | UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting |
2132 | UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) |
2349 | UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) |
2133 | UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) |
2350 | UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) |
2134 | UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) |
2351 | UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) |
2135 | UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) |
2352 | UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) |
2136 | UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
2353 | UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
2137 | UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
2354 | UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
2138 | UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
2355 | UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
2139 | UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
2356 | UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
2140 | UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
2357 | UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
2141 | }ATOM_MULTIMEDIA_CONFIG_INFO; |
2358 | }ATOM_MULTIMEDIA_CONFIG_INFO; |
2142 | 2359 | ||
2143 | 2360 | ||
2144 | /****************************************************************************/ |
2361 | /****************************************************************************/ |
2145 | // Structures used in FirmwareInfoTable |
2362 | // Structures used in FirmwareInfoTable |
2146 | /****************************************************************************/ |
2363 | /****************************************************************************/ |
2147 | 2364 | ||
2148 | // usBIOSCapability Definition: |
2365 | // usBIOSCapability Definition: |
2149 | // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; |
2366 | // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; |
2150 | // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; |
2367 | // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; |
2151 | // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; |
2368 | // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; |
2152 | // Others: Reserved |
2369 | // Others: Reserved |
2153 | #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 |
2370 | #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 |
2154 | #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 |
2371 | #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 |
2155 | #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 |
2372 | #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 |
2156 | #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. |
2373 | #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. |
2157 | #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. |
2374 | #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. |
2158 | #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 |
2375 | #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 |
2159 | #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 |
2376 | #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 |
2160 | #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 |
2377 | #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 |
2161 | #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 |
2378 | #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 |
2162 | #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 |
2379 | #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 |
2163 | #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 |
2380 | #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 |
2164 | #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 |
2381 | #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 |
2165 | #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip |
2382 | #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip |
2166 | #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip |
2383 | #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip |
2167 | 2384 | ||
2168 | #ifndef _H2INC |
2385 | #ifndef _H2INC |
2169 | 2386 | ||
2170 | //Please don't add or expand this bitfield structure below, this one will retire soon.! |
2387 | //Please don't add or expand this bitfield structure below, this one will retire soon.! |
2171 | typedef struct _ATOM_FIRMWARE_CAPABILITY |
2388 | typedef struct _ATOM_FIRMWARE_CAPABILITY |
2172 | { |
2389 | { |
2173 | #if ATOM_BIG_ENDIAN |
2390 | #if ATOM_BIG_ENDIAN |
2174 | USHORT Reserved:3; |
2391 | USHORT Reserved:1; |
- | 2392 | USHORT SCL2Redefined:1; |
|
- | 2393 | USHORT PostWithoutModeSet:1; |
|
2175 | USHORT HyperMemory_Size:4; |
2394 | USHORT HyperMemory_Size:4; |
2176 | USHORT HyperMemory_Support:1; |
2395 | USHORT HyperMemory_Support:1; |
2177 | USHORT PPMode_Assigned:1; |
2396 | USHORT PPMode_Assigned:1; |
2178 | USHORT WMI_SUPPORT:1; |
2397 | USHORT WMI_SUPPORT:1; |
2179 | USHORT GPUControlsBL:1; |
2398 | USHORT GPUControlsBL:1; |
2180 | USHORT EngineClockSS_Support:1; |
2399 | USHORT EngineClockSS_Support:1; |
2181 | USHORT MemoryClockSS_Support:1; |
2400 | USHORT MemoryClockSS_Support:1; |
2182 | USHORT ExtendedDesktopSupport:1; |
2401 | USHORT ExtendedDesktopSupport:1; |
2183 | USHORT DualCRTC_Support:1; |
2402 | USHORT DualCRTC_Support:1; |
2184 | USHORT FirmwarePosted:1; |
2403 | USHORT FirmwarePosted:1; |
2185 | #else |
2404 | #else |
2186 | USHORT FirmwarePosted:1; |
2405 | USHORT FirmwarePosted:1; |
2187 | USHORT DualCRTC_Support:1; |
2406 | USHORT DualCRTC_Support:1; |
2188 | USHORT ExtendedDesktopSupport:1; |
2407 | USHORT ExtendedDesktopSupport:1; |
2189 | USHORT MemoryClockSS_Support:1; |
2408 | USHORT MemoryClockSS_Support:1; |
2190 | USHORT EngineClockSS_Support:1; |
2409 | USHORT EngineClockSS_Support:1; |
2191 | USHORT GPUControlsBL:1; |
2410 | USHORT GPUControlsBL:1; |
2192 | USHORT WMI_SUPPORT:1; |
2411 | USHORT WMI_SUPPORT:1; |
2193 | USHORT PPMode_Assigned:1; |
2412 | USHORT PPMode_Assigned:1; |
2194 | USHORT HyperMemory_Support:1; |
2413 | USHORT HyperMemory_Support:1; |
2195 | USHORT HyperMemory_Size:4; |
2414 | USHORT HyperMemory_Size:4; |
- | 2415 | USHORT PostWithoutModeSet:1; |
|
- | 2416 | USHORT SCL2Redefined:1; |
|
2196 | USHORT Reserved:3; |
2417 | USHORT Reserved:1; |
2197 | #endif |
2418 | #endif |
2198 | }ATOM_FIRMWARE_CAPABILITY; |
2419 | }ATOM_FIRMWARE_CAPABILITY; |
2199 | 2420 | ||
2200 | typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS |
2421 | typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS |
2201 | { |
2422 | { |
2202 | ATOM_FIRMWARE_CAPABILITY sbfAccess; |
2423 | ATOM_FIRMWARE_CAPABILITY sbfAccess; |
2203 | USHORT susAccess; |
2424 | USHORT susAccess; |
2204 | }ATOM_FIRMWARE_CAPABILITY_ACCESS; |
2425 | }ATOM_FIRMWARE_CAPABILITY_ACCESS; |
2205 | 2426 | ||
2206 | #else |
2427 | #else |
2207 | 2428 | ||
2208 | typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS |
2429 | typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS |
2209 | { |
2430 | { |
2210 | USHORT susAccess; |
2431 | USHORT susAccess; |
2211 | }ATOM_FIRMWARE_CAPABILITY_ACCESS; |
2432 | }ATOM_FIRMWARE_CAPABILITY_ACCESS; |
2212 | 2433 | ||
2213 | #endif |
2434 | #endif |
2214 | 2435 | ||
2215 | typedef struct _ATOM_FIRMWARE_INFO |
2436 | typedef struct _ATOM_FIRMWARE_INFO |
2216 | { |
2437 | { |
2217 | ATOM_COMMON_TABLE_HEADER sHeader; |
2438 | ATOM_COMMON_TABLE_HEADER sHeader; |
2218 | ULONG ulFirmwareRevision; |
2439 | ULONG ulFirmwareRevision; |
2219 | ULONG ulDefaultEngineClock; //In 10Khz unit |
2440 | ULONG ulDefaultEngineClock; //In 10Khz unit |
2220 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
2441 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
2221 | ULONG ulDriverTargetEngineClock; //In 10Khz unit |
2442 | ULONG ulDriverTargetEngineClock; //In 10Khz unit |
2222 | ULONG ulDriverTargetMemoryClock; //In 10Khz unit |
2443 | ULONG ulDriverTargetMemoryClock; //In 10Khz unit |
2223 | ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit |
2444 | ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit |
2224 | ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit |
2445 | ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit |
2225 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
2446 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
2226 | ULONG ulASICMaxEngineClock; //In 10Khz unit |
2447 | ULONG ulASICMaxEngineClock; //In 10Khz unit |
2227 | ULONG ulASICMaxMemoryClock; //In 10Khz unit |
2448 | ULONG ulASICMaxMemoryClock; //In 10Khz unit |
2228 | UCHAR ucASICMaxTemperature; |
2449 | UCHAR ucASICMaxTemperature; |
2229 | UCHAR ucPadding[3]; //Don't use them |
2450 | UCHAR ucPadding[3]; //Don't use them |
2230 | ULONG aulReservedForBIOS[3]; //Don't use them |
2451 | ULONG aulReservedForBIOS[3]; //Don't use them |
2231 | USHORT usMinEngineClockPLL_Input; //In 10Khz unit |
2452 | USHORT usMinEngineClockPLL_Input; //In 10Khz unit |
2232 | USHORT usMaxEngineClockPLL_Input; //In 10Khz unit |
2453 | USHORT usMaxEngineClockPLL_Input; //In 10Khz unit |
2233 | USHORT usMinEngineClockPLL_Output; //In 10Khz unit |
2454 | USHORT usMinEngineClockPLL_Output; //In 10Khz unit |
2234 | USHORT usMinMemoryClockPLL_Input; //In 10Khz unit |
2455 | USHORT usMinMemoryClockPLL_Input; //In 10Khz unit |
2235 | USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit |
2456 | USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit |
2236 | USHORT usMinMemoryClockPLL_Output; //In 10Khz unit |
2457 | USHORT usMinMemoryClockPLL_Output; //In 10Khz unit |
2237 | USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk |
2458 | USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk |
2238 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit |
2459 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit |
2239 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit |
2460 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit |
2240 | USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! |
2461 | USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! |
2241 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
2462 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
2242 | USHORT usReferenceClock; //In 10Khz unit |
2463 | USHORT usReferenceClock; //In 10Khz unit |
2243 | USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit |
2464 | USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit |
2244 | UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit |
2465 | UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit |
2245 | UCHAR ucDesign_ID; //Indicate what is the board design |
2466 | UCHAR ucDesign_ID; //Indicate what is the board design |
2246 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2467 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2247 | }ATOM_FIRMWARE_INFO; |
2468 | }ATOM_FIRMWARE_INFO; |
2248 | 2469 | ||
2249 | typedef struct _ATOM_FIRMWARE_INFO_V1_2 |
2470 | typedef struct _ATOM_FIRMWARE_INFO_V1_2 |
2250 | { |
2471 | { |
2251 | ATOM_COMMON_TABLE_HEADER sHeader; |
2472 | ATOM_COMMON_TABLE_HEADER sHeader; |
2252 | ULONG ulFirmwareRevision; |
2473 | ULONG ulFirmwareRevision; |
2253 | ULONG ulDefaultEngineClock; //In 10Khz unit |
2474 | ULONG ulDefaultEngineClock; //In 10Khz unit |
2254 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
2475 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
2255 | ULONG ulDriverTargetEngineClock; //In 10Khz unit |
2476 | ULONG ulDriverTargetEngineClock; //In 10Khz unit |
2256 | ULONG ulDriverTargetMemoryClock; //In 10Khz unit |
2477 | ULONG ulDriverTargetMemoryClock; //In 10Khz unit |
2257 | ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit |
2478 | ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit |
2258 | ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit |
2479 | ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit |
2259 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
2480 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
2260 | ULONG ulASICMaxEngineClock; //In 10Khz unit |
2481 | ULONG ulASICMaxEngineClock; //In 10Khz unit |
2261 | ULONG ulASICMaxMemoryClock; //In 10Khz unit |
2482 | ULONG ulASICMaxMemoryClock; //In 10Khz unit |
2262 | UCHAR ucASICMaxTemperature; |
2483 | UCHAR ucASICMaxTemperature; |
2263 | UCHAR ucMinAllowedBL_Level; |
2484 | UCHAR ucMinAllowedBL_Level; |
2264 | UCHAR ucPadding[2]; //Don't use them |
2485 | UCHAR ucPadding[2]; //Don't use them |
2265 | ULONG aulReservedForBIOS[2]; //Don't use them |
2486 | ULONG aulReservedForBIOS[2]; //Don't use them |
2266 | ULONG ulMinPixelClockPLL_Output; //In 10Khz unit |
2487 | ULONG ulMinPixelClockPLL_Output; //In 10Khz unit |
2267 | USHORT usMinEngineClockPLL_Input; //In 10Khz unit |
2488 | USHORT usMinEngineClockPLL_Input; //In 10Khz unit |
2268 | USHORT usMaxEngineClockPLL_Input; //In 10Khz unit |
2489 | USHORT usMaxEngineClockPLL_Input; //In 10Khz unit |
2269 | USHORT usMinEngineClockPLL_Output; //In 10Khz unit |
2490 | USHORT usMinEngineClockPLL_Output; //In 10Khz unit |
2270 | USHORT usMinMemoryClockPLL_Input; //In 10Khz unit |
2491 | USHORT usMinMemoryClockPLL_Input; //In 10Khz unit |
2271 | USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit |
2492 | USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit |
2272 | USHORT usMinMemoryClockPLL_Output; //In 10Khz unit |
2493 | USHORT usMinMemoryClockPLL_Output; //In 10Khz unit |
2273 | USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk |
2494 | USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk |
2274 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit |
2495 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit |
2275 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit |
2496 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit |
2276 | USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output |
2497 | USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output |
2277 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
2498 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
2278 | USHORT usReferenceClock; //In 10Khz unit |
2499 | USHORT usReferenceClock; //In 10Khz unit |
2279 | USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit |
2500 | USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit |
2280 | UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit |
2501 | UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit |
2281 | UCHAR ucDesign_ID; //Indicate what is the board design |
2502 | UCHAR ucDesign_ID; //Indicate what is the board design |
2282 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2503 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2283 | }ATOM_FIRMWARE_INFO_V1_2; |
2504 | }ATOM_FIRMWARE_INFO_V1_2; |
2284 | 2505 | ||
2285 | typedef struct _ATOM_FIRMWARE_INFO_V1_3 |
2506 | typedef struct _ATOM_FIRMWARE_INFO_V1_3 |
2286 | { |
2507 | { |
2287 | ATOM_COMMON_TABLE_HEADER sHeader; |
2508 | ATOM_COMMON_TABLE_HEADER sHeader; |
2288 | ULONG ulFirmwareRevision; |
2509 | ULONG ulFirmwareRevision; |
2289 | ULONG ulDefaultEngineClock; //In 10Khz unit |
2510 | ULONG ulDefaultEngineClock; //In 10Khz unit |
2290 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
2511 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
2291 | ULONG ulDriverTargetEngineClock; //In 10Khz unit |
2512 | ULONG ulDriverTargetEngineClock; //In 10Khz unit |
2292 | ULONG ulDriverTargetMemoryClock; //In 10Khz unit |
2513 | ULONG ulDriverTargetMemoryClock; //In 10Khz unit |
2293 | ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit |
2514 | ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit |
2294 | ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit |
2515 | ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit |
2295 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
2516 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
2296 | ULONG ulASICMaxEngineClock; //In 10Khz unit |
2517 | ULONG ulASICMaxEngineClock; //In 10Khz unit |
2297 | ULONG ulASICMaxMemoryClock; //In 10Khz unit |
2518 | ULONG ulASICMaxMemoryClock; //In 10Khz unit |
2298 | UCHAR ucASICMaxTemperature; |
2519 | UCHAR ucASICMaxTemperature; |
2299 | UCHAR ucMinAllowedBL_Level; |
2520 | UCHAR ucMinAllowedBL_Level; |
2300 | UCHAR ucPadding[2]; //Don't use them |
2521 | UCHAR ucPadding[2]; //Don't use them |
2301 | ULONG aulReservedForBIOS; //Don't use them |
2522 | ULONG aulReservedForBIOS; //Don't use them |
2302 | ULONG ul3DAccelerationEngineClock;//In 10Khz unit |
2523 | ULONG ul3DAccelerationEngineClock;//In 10Khz unit |
2303 | ULONG ulMinPixelClockPLL_Output; //In 10Khz unit |
2524 | ULONG ulMinPixelClockPLL_Output; //In 10Khz unit |
2304 | USHORT usMinEngineClockPLL_Input; //In 10Khz unit |
2525 | USHORT usMinEngineClockPLL_Input; //In 10Khz unit |
2305 | USHORT usMaxEngineClockPLL_Input; //In 10Khz unit |
2526 | USHORT usMaxEngineClockPLL_Input; //In 10Khz unit |
2306 | USHORT usMinEngineClockPLL_Output; //In 10Khz unit |
2527 | USHORT usMinEngineClockPLL_Output; //In 10Khz unit |
2307 | USHORT usMinMemoryClockPLL_Input; //In 10Khz unit |
2528 | USHORT usMinMemoryClockPLL_Input; //In 10Khz unit |
2308 | USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit |
2529 | USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit |
2309 | USHORT usMinMemoryClockPLL_Output; //In 10Khz unit |
2530 | USHORT usMinMemoryClockPLL_Output; //In 10Khz unit |
2310 | USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk |
2531 | USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk |
2311 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit |
2532 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit |
2312 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit |
2533 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit |
2313 | USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output |
2534 | USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output |
2314 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
2535 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
2315 | USHORT usReferenceClock; //In 10Khz unit |
2536 | USHORT usReferenceClock; //In 10Khz unit |
2316 | USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit |
2537 | USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit |
2317 | UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit |
2538 | UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit |
2318 | UCHAR ucDesign_ID; //Indicate what is the board design |
2539 | UCHAR ucDesign_ID; //Indicate what is the board design |
2319 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2540 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2320 | }ATOM_FIRMWARE_INFO_V1_3; |
2541 | }ATOM_FIRMWARE_INFO_V1_3; |
2321 | 2542 | ||
2322 | typedef struct _ATOM_FIRMWARE_INFO_V1_4 |
2543 | typedef struct _ATOM_FIRMWARE_INFO_V1_4 |
2323 | { |
2544 | { |
2324 | ATOM_COMMON_TABLE_HEADER sHeader; |
2545 | ATOM_COMMON_TABLE_HEADER sHeader; |
2325 | ULONG ulFirmwareRevision; |
2546 | ULONG ulFirmwareRevision; |
2326 | ULONG ulDefaultEngineClock; //In 10Khz unit |
2547 | ULONG ulDefaultEngineClock; //In 10Khz unit |
2327 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
2548 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
2328 | ULONG ulDriverTargetEngineClock; //In 10Khz unit |
2549 | ULONG ulDriverTargetEngineClock; //In 10Khz unit |
2329 | ULONG ulDriverTargetMemoryClock; //In 10Khz unit |
2550 | ULONG ulDriverTargetMemoryClock; //In 10Khz unit |
2330 | ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit |
2551 | ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit |
2331 | ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit |
2552 | ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit |
2332 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
2553 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
2333 | ULONG ulASICMaxEngineClock; //In 10Khz unit |
2554 | ULONG ulASICMaxEngineClock; //In 10Khz unit |
2334 | ULONG ulASICMaxMemoryClock; //In 10Khz unit |
2555 | ULONG ulASICMaxMemoryClock; //In 10Khz unit |
2335 | UCHAR ucASICMaxTemperature; |
2556 | UCHAR ucASICMaxTemperature; |
2336 | UCHAR ucMinAllowedBL_Level; |
2557 | UCHAR ucMinAllowedBL_Level; |
2337 | USHORT usBootUpVDDCVoltage; //In MV unit |
2558 | USHORT usBootUpVDDCVoltage; //In MV unit |
2338 | USHORT usLcdMinPixelClockPLL_Output; // In MHz unit |
2559 | USHORT usLcdMinPixelClockPLL_Output; // In MHz unit |
2339 | USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit |
2560 | USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit |
2340 | ULONG ul3DAccelerationEngineClock;//In 10Khz unit |
2561 | ULONG ul3DAccelerationEngineClock;//In 10Khz unit |
2341 | ULONG ulMinPixelClockPLL_Output; //In 10Khz unit |
2562 | ULONG ulMinPixelClockPLL_Output; //In 10Khz unit |
2342 | USHORT usMinEngineClockPLL_Input; //In 10Khz unit |
2563 | USHORT usMinEngineClockPLL_Input; //In 10Khz unit |
2343 | USHORT usMaxEngineClockPLL_Input; //In 10Khz unit |
2564 | USHORT usMaxEngineClockPLL_Input; //In 10Khz unit |
2344 | USHORT usMinEngineClockPLL_Output; //In 10Khz unit |
2565 | USHORT usMinEngineClockPLL_Output; //In 10Khz unit |
2345 | USHORT usMinMemoryClockPLL_Input; //In 10Khz unit |
2566 | USHORT usMinMemoryClockPLL_Input; //In 10Khz unit |
2346 | USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit |
2567 | USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit |
2347 | USHORT usMinMemoryClockPLL_Output; //In 10Khz unit |
2568 | USHORT usMinMemoryClockPLL_Output; //In 10Khz unit |
2348 | USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk |
2569 | USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk |
2349 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit |
2570 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit |
2350 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit |
2571 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit |
2351 | USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output |
2572 | USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output |
2352 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
2573 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
2353 | USHORT usReferenceClock; //In 10Khz unit |
2574 | USHORT usReferenceClock; //In 10Khz unit |
2354 | USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit |
2575 | USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit |
2355 | UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit |
2576 | UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit |
2356 | UCHAR ucDesign_ID; //Indicate what is the board design |
2577 | UCHAR ucDesign_ID; //Indicate what is the board design |
2357 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2578 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2358 | }ATOM_FIRMWARE_INFO_V1_4; |
2579 | }ATOM_FIRMWARE_INFO_V1_4; |
2359 | 2580 | ||
2360 | //the structure below to be used from Cypress |
2581 | //the structure below to be used from Cypress |
2361 | typedef struct _ATOM_FIRMWARE_INFO_V2_1 |
2582 | typedef struct _ATOM_FIRMWARE_INFO_V2_1 |
2362 | { |
2583 | { |
2363 | ATOM_COMMON_TABLE_HEADER sHeader; |
2584 | ATOM_COMMON_TABLE_HEADER sHeader; |
2364 | ULONG ulFirmwareRevision; |
2585 | ULONG ulFirmwareRevision; |
2365 | ULONG ulDefaultEngineClock; //In 10Khz unit |
2586 | ULONG ulDefaultEngineClock; //In 10Khz unit |
2366 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
2587 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
2367 | ULONG ulReserved1; |
2588 | ULONG ulReserved1; |
2368 | ULONG ulReserved2; |
2589 | ULONG ulReserved2; |
2369 | ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit |
2590 | ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit |
2370 | ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit |
2591 | ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit |
2371 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
2592 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
2372 | ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock |
2593 | ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock |
2373 | ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit |
2594 | ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit |
2374 | UCHAR ucReserved1; //Was ucASICMaxTemperature; |
2595 | UCHAR ucReserved1; //Was ucASICMaxTemperature; |
2375 | UCHAR ucMinAllowedBL_Level; |
2596 | UCHAR ucMinAllowedBL_Level; |
2376 | USHORT usBootUpVDDCVoltage; //In MV unit |
2597 | USHORT usBootUpVDDCVoltage; //In MV unit |
2377 | USHORT usLcdMinPixelClockPLL_Output; // In MHz unit |
2598 | USHORT usLcdMinPixelClockPLL_Output; // In MHz unit |
2378 | USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit |
2599 | USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit |
2379 | ULONG ulReserved4; //Was ulAsicMaximumVoltage |
2600 | ULONG ulReserved4; //Was ulAsicMaximumVoltage |
2380 | ULONG ulMinPixelClockPLL_Output; //In 10Khz unit |
2601 | ULONG ulMinPixelClockPLL_Output; //In 10Khz unit |
2381 | USHORT usMinEngineClockPLL_Input; //In 10Khz unit |
2602 | USHORT usMinEngineClockPLL_Input; //In 10Khz unit |
2382 | USHORT usMaxEngineClockPLL_Input; //In 10Khz unit |
2603 | USHORT usMaxEngineClockPLL_Input; //In 10Khz unit |
2383 | USHORT usMinEngineClockPLL_Output; //In 10Khz unit |
2604 | USHORT usMinEngineClockPLL_Output; //In 10Khz unit |
2384 | USHORT usMinMemoryClockPLL_Input; //In 10Khz unit |
2605 | USHORT usMinMemoryClockPLL_Input; //In 10Khz unit |
2385 | USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit |
2606 | USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit |
2386 | USHORT usMinMemoryClockPLL_Output; //In 10Khz unit |
2607 | USHORT usMinMemoryClockPLL_Output; //In 10Khz unit |
2387 | USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk |
2608 | USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk |
2388 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit |
2609 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit |
2389 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit |
2610 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit |
2390 | USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output |
2611 | USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output |
2391 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
2612 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
2392 | USHORT usCoreReferenceClock; //In 10Khz unit |
2613 | USHORT usCoreReferenceClock; //In 10Khz unit |
2393 | USHORT usMemoryReferenceClock; //In 10Khz unit |
2614 | USHORT usMemoryReferenceClock; //In 10Khz unit |
2394 | USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock |
2615 | USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock |
2395 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2616 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2396 | UCHAR ucReserved4[3]; |
2617 | UCHAR ucReserved4[3]; |
2397 | }ATOM_FIRMWARE_INFO_V2_1; |
2618 | }ATOM_FIRMWARE_INFO_V2_1; |
2398 | 2619 | ||
2399 | //the structure below to be used from NI |
2620 | //the structure below to be used from NI |
2400 | //ucTableFormatRevision=2 |
2621 | //ucTableFormatRevision=2 |
2401 | //ucTableContentRevision=2 |
2622 | //ucTableContentRevision=2 |
2402 | typedef struct _ATOM_FIRMWARE_INFO_V2_2 |
2623 | typedef struct _ATOM_FIRMWARE_INFO_V2_2 |
2403 | { |
2624 | { |
2404 | ATOM_COMMON_TABLE_HEADER sHeader; |
2625 | ATOM_COMMON_TABLE_HEADER sHeader; |
2405 | ULONG ulFirmwareRevision; |
2626 | ULONG ulFirmwareRevision; |
2406 | ULONG ulDefaultEngineClock; //In 10Khz unit |
2627 | ULONG ulDefaultEngineClock; //In 10Khz unit |
2407 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
2628 | ULONG ulDefaultMemoryClock; //In 10Khz unit |
2408 | ULONG ulReserved[2]; |
2629 | ULONG ulReserved[2]; |
2409 | ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* |
2630 | ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* |
2410 | ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* |
2631 | ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* |
2411 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
2632 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
2412 | ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? |
2633 | ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? |
2413 | ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. |
2634 | ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. |
2414 | UCHAR ucReserved3; //Was ucASICMaxTemperature; |
2635 | UCHAR ucReserved3; //Was ucASICMaxTemperature; |
2415 | UCHAR ucMinAllowedBL_Level; |
2636 | UCHAR ucMinAllowedBL_Level; |
2416 | USHORT usBootUpVDDCVoltage; //In MV unit |
2637 | USHORT usBootUpVDDCVoltage; //In MV unit |
2417 | USHORT usLcdMinPixelClockPLL_Output; // In MHz unit |
2638 | USHORT usLcdMinPixelClockPLL_Output; // In MHz unit |
2418 | USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit |
2639 | USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit |
2419 | ULONG ulReserved4; //Was ulAsicMaximumVoltage |
2640 | ULONG ulReserved4; //Was ulAsicMaximumVoltage |
2420 | ULONG ulMinPixelClockPLL_Output; //In 10Khz unit |
2641 | ULONG ulMinPixelClockPLL_Output; //In 10Khz unit |
- | 2642 | UCHAR ucRemoteDisplayConfig; |
|
2421 | ULONG ulReserved5; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input |
2643 | UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input |
2422 | ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input |
2644 | ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input |
2423 | ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output |
2645 | ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output |
2424 | USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC |
2646 | USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC |
2425 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit |
2647 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit |
2426 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit |
2648 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit |
2427 | USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; |
2649 | USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; |
2428 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
2650 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
2429 | USHORT usCoreReferenceClock; //In 10Khz unit |
2651 | USHORT usCoreReferenceClock; //In 10Khz unit |
2430 | USHORT usMemoryReferenceClock; //In 10Khz unit |
2652 | USHORT usMemoryReferenceClock; //In 10Khz unit |
2431 | USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock |
2653 | USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock |
2432 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2654 | UCHAR ucMemoryModule_ID; //Indicate what is the board design |
2433 | UCHAR ucReserved9[3]; |
2655 | UCHAR ucReserved9[3]; |
2434 | USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; |
2656 | USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; |
2435 | USHORT usReserved12; |
2657 | USHORT usReserved12; |
2436 | ULONG ulReserved10[3]; // New added comparing to previous version |
2658 | ULONG ulReserved10[3]; // New added comparing to previous version |
2437 | }ATOM_FIRMWARE_INFO_V2_2; |
2659 | }ATOM_FIRMWARE_INFO_V2_2; |
2438 | 2660 | ||
2439 | #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 |
2661 | #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 |
- | 2662 | ||
- | 2663 | ||
- | 2664 | // definition of ucRemoteDisplayConfig |
|
- | 2665 | #define REMOTE_DISPLAY_DISABLE 0x00 |
|
- | 2666 | #define REMOTE_DISPLAY_ENABLE 0x01 |
|
2440 | 2667 | ||
2441 | /****************************************************************************/ |
2668 | /****************************************************************************/ |
2442 | // Structures used in IntegratedSystemInfoTable |
2669 | // Structures used in IntegratedSystemInfoTable |
2443 | /****************************************************************************/ |
2670 | /****************************************************************************/ |
2444 | #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 |
2671 | #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 |
2445 | #define IGP_CAP_FLAG_AC_CARD 0x4 |
2672 | #define IGP_CAP_FLAG_AC_CARD 0x4 |
2446 | #define IGP_CAP_FLAG_SDVO_CARD 0x8 |
2673 | #define IGP_CAP_FLAG_SDVO_CARD 0x8 |
2447 | #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 |
2674 | #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 |
2448 | 2675 | ||
2449 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO |
2676 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO |
2450 | { |
2677 | { |
2451 | ATOM_COMMON_TABLE_HEADER sHeader; |
2678 | ATOM_COMMON_TABLE_HEADER sHeader; |
2452 | ULONG ulBootUpEngineClock; //in 10kHz unit |
2679 | ULONG ulBootUpEngineClock; //in 10kHz unit |
2453 | ULONG ulBootUpMemoryClock; //in 10kHz unit |
2680 | ULONG ulBootUpMemoryClock; //in 10kHz unit |
2454 | ULONG ulMaxSystemMemoryClock; //in 10kHz unit |
2681 | ULONG ulMaxSystemMemoryClock; //in 10kHz unit |
2455 | ULONG ulMinSystemMemoryClock; //in 10kHz unit |
2682 | ULONG ulMinSystemMemoryClock; //in 10kHz unit |
2456 | UCHAR ucNumberOfCyclesInPeriodHi; |
2683 | UCHAR ucNumberOfCyclesInPeriodHi; |
2457 | UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. |
2684 | UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. |
2458 | USHORT usReserved1; |
2685 | USHORT usReserved1; |
2459 | USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage |
2686 | USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage |
2460 | USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage |
2687 | USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage |
2461 | ULONG ulReserved[2]; |
2688 | ULONG ulReserved[2]; |
2462 | 2689 | ||
2463 | USHORT usFSBClock; //In MHz unit |
2690 | USHORT usFSBClock; //In MHz unit |
2464 | USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable |
2691 | USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable |
2465 | //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card |
2692 | //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card |
2466 | //Bit[4]==1: P/2 mode, ==0: P/1 mode |
2693 | //Bit[4]==1: P/2 mode, ==0: P/1 mode |
2467 | USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal |
2694 | USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal |
2468 | USHORT usK8MemoryClock; //in MHz unit |
2695 | USHORT usK8MemoryClock; //in MHz unit |
2469 | USHORT usK8SyncStartDelay; //in 0.01 us unit |
2696 | USHORT usK8SyncStartDelay; //in 0.01 us unit |
2470 | USHORT usK8DataReturnTime; //in 0.01 us unit |
2697 | USHORT usK8DataReturnTime; //in 0.01 us unit |
2471 | UCHAR ucMaxNBVoltage; |
2698 | UCHAR ucMaxNBVoltage; |
2472 | UCHAR ucMinNBVoltage; |
2699 | UCHAR ucMinNBVoltage; |
2473 | UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved |
2700 | UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved |
2474 | UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod |
2701 | UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod |
2475 | UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime |
2702 | UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime |
2476 | UCHAR ucHTLinkWidth; //16 bit vs. 8 bit |
2703 | UCHAR ucHTLinkWidth; //16 bit vs. 8 bit |
2477 | UCHAR ucMaxNBVoltageHigh; |
2704 | UCHAR ucMaxNBVoltageHigh; |
2478 | UCHAR ucMinNBVoltageHigh; |
2705 | UCHAR ucMinNBVoltageHigh; |
2479 | }ATOM_INTEGRATED_SYSTEM_INFO; |
2706 | }ATOM_INTEGRATED_SYSTEM_INFO; |
2480 | 2707 | ||
2481 | /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO |
2708 | /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO |
2482 | ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock |
2709 | ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock |
2483 | For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock |
2710 | For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock |
2484 | ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 |
2711 | ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 |
2485 | For AMD IGP,for now this can be 0 |
2712 | For AMD IGP,for now this can be 0 |
2486 | ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 |
2713 | ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 |
2487 | For AMD IGP,for now this can be 0 |
2714 | For AMD IGP,for now this can be 0 |
2488 | 2715 | ||
2489 | usFSBClock: For Intel IGP,it's FSB Freq |
2716 | usFSBClock: For Intel IGP,it's FSB Freq |
2490 | For AMD IGP,it's HT Link Speed |
2717 | For AMD IGP,it's HT Link Speed |
2491 | 2718 | ||
2492 | usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 |
2719 | usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 |
2493 | usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation |
2720 | usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation |
2494 | usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation |
2721 | usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation |
2495 | 2722 | ||
2496 | VC:Voltage Control |
2723 | VC:Voltage Control |
2497 | ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. |
2724 | ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. |
2498 | ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. |
2725 | ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. |
2499 | 2726 | ||
2500 | ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. |
2727 | ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. |
2501 | ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 |
2728 | ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 |
2502 | 2729 | ||
2503 | ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. |
2730 | ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. |
2504 | ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. |
2731 | ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. |
2505 | 2732 | ||
2506 | 2733 | ||
2507 | usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. |
2734 | usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. |
2508 | usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. |
2735 | usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. |
2509 | */ |
2736 | */ |
2510 | 2737 | ||
2511 | 2738 | ||
2512 | /* |
2739 | /* |
2513 | The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; |
2740 | The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; |
2514 | Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. |
2741 | Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. |
2515 | The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. |
2742 | The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. |
2516 | 2743 | ||
2517 | SW components can access the IGP system infor structure in the same way as before |
2744 | SW components can access the IGP system infor structure in the same way as before |
2518 | */ |
2745 | */ |
2519 | 2746 | ||
2520 | 2747 | ||
2521 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 |
2748 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 |
2522 | { |
2749 | { |
2523 | ATOM_COMMON_TABLE_HEADER sHeader; |
2750 | ATOM_COMMON_TABLE_HEADER sHeader; |
2524 | ULONG ulBootUpEngineClock; //in 10kHz unit |
2751 | ULONG ulBootUpEngineClock; //in 10kHz unit |
2525 | ULONG ulReserved1[2]; //must be 0x0 for the reserved |
2752 | ULONG ulReserved1[2]; //must be 0x0 for the reserved |
2526 | ULONG ulBootUpUMAClock; //in 10kHz unit |
2753 | ULONG ulBootUpUMAClock; //in 10kHz unit |
2527 | ULONG ulBootUpSidePortClock; //in 10kHz unit |
2754 | ULONG ulBootUpSidePortClock; //in 10kHz unit |
2528 | ULONG ulMinSidePortClock; //in 10kHz unit |
2755 | ULONG ulMinSidePortClock; //in 10kHz unit |
2529 | ULONG ulReserved2[6]; //must be 0x0 for the reserved |
2756 | ULONG ulReserved2[6]; //must be 0x0 for the reserved |
2530 | ULONG ulSystemConfig; //see explanation below |
2757 | ULONG ulSystemConfig; //see explanation below |
2531 | ULONG ulBootUpReqDisplayVector; |
2758 | ULONG ulBootUpReqDisplayVector; |
2532 | ULONG ulOtherDisplayMisc; |
2759 | ULONG ulOtherDisplayMisc; |
2533 | ULONG ulDDISlot1Config; |
2760 | ULONG ulDDISlot1Config; |
2534 | ULONG ulDDISlot2Config; |
2761 | ULONG ulDDISlot2Config; |
2535 | UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved |
2762 | UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved |
2536 | UCHAR ucUMAChannelNumber; |
2763 | UCHAR ucUMAChannelNumber; |
2537 | UCHAR ucDockingPinBit; |
2764 | UCHAR ucDockingPinBit; |
2538 | UCHAR ucDockingPinPolarity; |
2765 | UCHAR ucDockingPinPolarity; |
2539 | ULONG ulDockingPinCFGInfo; |
2766 | ULONG ulDockingPinCFGInfo; |
2540 | ULONG ulCPUCapInfo; |
2767 | ULONG ulCPUCapInfo; |
2541 | USHORT usNumberOfCyclesInPeriod; |
2768 | USHORT usNumberOfCyclesInPeriod; |
2542 | USHORT usMaxNBVoltage; |
2769 | USHORT usMaxNBVoltage; |
2543 | USHORT usMinNBVoltage; |
2770 | USHORT usMinNBVoltage; |
2544 | USHORT usBootUpNBVoltage; |
2771 | USHORT usBootUpNBVoltage; |
2545 | ULONG ulHTLinkFreq; //in 10Khz |
2772 | ULONG ulHTLinkFreq; //in 10Khz |
2546 | USHORT usMinHTLinkWidth; |
2773 | USHORT usMinHTLinkWidth; |
2547 | USHORT usMaxHTLinkWidth; |
2774 | USHORT usMaxHTLinkWidth; |
2548 | USHORT usUMASyncStartDelay; |
2775 | USHORT usUMASyncStartDelay; |
2549 | USHORT usUMADataReturnTime; |
2776 | USHORT usUMADataReturnTime; |
2550 | USHORT usLinkStatusZeroTime; |
2777 | USHORT usLinkStatusZeroTime; |
2551 | USHORT usDACEfuse; //for storing badgap value (for RS880 only) |
2778 | USHORT usDACEfuse; //for storing badgap value (for RS880 only) |
2552 | ULONG ulHighVoltageHTLinkFreq; // in 10Khz |
2779 | ULONG ulHighVoltageHTLinkFreq; // in 10Khz |
2553 | ULONG ulLowVoltageHTLinkFreq; // in 10Khz |
2780 | ULONG ulLowVoltageHTLinkFreq; // in 10Khz |
2554 | USHORT usMaxUpStreamHTLinkWidth; |
2781 | USHORT usMaxUpStreamHTLinkWidth; |
2555 | USHORT usMaxDownStreamHTLinkWidth; |
2782 | USHORT usMaxDownStreamHTLinkWidth; |
2556 | USHORT usMinUpStreamHTLinkWidth; |
2783 | USHORT usMinUpStreamHTLinkWidth; |
2557 | USHORT usMinDownStreamHTLinkWidth; |
2784 | USHORT usMinDownStreamHTLinkWidth; |
2558 | USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. |
2785 | USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. |
2559 | USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. |
2786 | USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. |
2560 | ULONG ulReserved3[96]; //must be 0x0 |
2787 | ULONG ulReserved3[96]; //must be 0x0 |
2561 | }ATOM_INTEGRATED_SYSTEM_INFO_V2; |
2788 | }ATOM_INTEGRATED_SYSTEM_INFO_V2; |
2562 | 2789 | ||
2563 | /* |
2790 | /* |
2564 | ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; |
2791 | ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; |
2565 | ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present |
2792 | ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present |
2566 | ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock |
2793 | ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock |
2567 | 2794 | ||
2568 | ulSystemConfig: |
2795 | ulSystemConfig: |
2569 | Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; |
2796 | Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; |
2570 | Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state |
2797 | Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state |
2571 | =0: system boots up at driver control state. Power state depends on PowerPlay table. |
2798 | =0: system boots up at driver control state. Power state depends on PowerPlay table. |
2572 | Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. |
2799 | Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. |
2573 | Bit[3]=1: Only one power state(Performance) will be supported. |
2800 | Bit[3]=1: Only one power state(Performance) will be supported. |
2574 | =0: Multiple power states supported from PowerPlay table. |
2801 | =0: Multiple power states supported from PowerPlay table. |
2575 | Bit[4]=1: CLMC is supported and enabled on current system. |
2802 | Bit[4]=1: CLMC is supported and enabled on current system. |
2576 | =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. |
2803 | =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. |
2577 | Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. |
2804 | Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. |
2578 | =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. |
2805 | =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. |
2579 | Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. |
2806 | Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. |
2580 | =0: Voltage settings is determined by powerplay table. |
2807 | =0: Voltage settings is determined by powerplay table. |
2581 | Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. |
2808 | Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. |
2582 | =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. |
2809 | =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. |
2583 | Bit[8]=1: CDLF is supported and enabled on current system. |
2810 | Bit[8]=1: CDLF is supported and enabled on current system. |
2584 | =0: CDLF is not supported or enabled on current system. |
2811 | =0: CDLF is not supported or enabled on current system. |
2585 | Bit[9]=1: DLL Shut Down feature is enabled on current system. |
2812 | Bit[9]=1: DLL Shut Down feature is enabled on current system. |
2586 | =0: DLL Shut Down feature is not enabled or supported on current system. |
2813 | =0: DLL Shut Down feature is not enabled or supported on current system. |
2587 | 2814 | ||
2588 | ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. |
2815 | ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. |
2589 | 2816 | ||
2590 | ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; |
2817 | ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; |
2591 | [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition; |
2818 | [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition; |
2592 | 2819 | ||
2593 | ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). |
2820 | ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). |
2594 | [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) |
2821 | [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) |
2595 | [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) |
2822 | [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) |
2596 | When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. |
2823 | When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. |
2597 | in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: |
2824 | in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: |
2598 | one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. |
2825 | one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. |
2599 | 2826 | ||
2600 | [15:8] - Lane configuration attribute; |
2827 | [15:8] - Lane configuration attribute; |
2601 | [23:16]- Connector type, possible value: |
2828 | [23:16]- Connector type, possible value: |
2602 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D |
2829 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D |
2603 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D |
2830 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D |
2604 | CONNECTOR_OBJECT_ID_HDMI_TYPE_A |
2831 | CONNECTOR_OBJECT_ID_HDMI_TYPE_A |
2605 | CONNECTOR_OBJECT_ID_DISPLAYPORT |
2832 | CONNECTOR_OBJECT_ID_DISPLAYPORT |
2606 | CONNECTOR_OBJECT_ID_eDP |
2833 | CONNECTOR_OBJECT_ID_eDP |
2607 | [31:24]- Reserved |
2834 | [31:24]- Reserved |
2608 | 2835 | ||
2609 | ulDDISlot2Config: Same as Slot1. |
2836 | ulDDISlot2Config: Same as Slot1. |
2610 | ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. |
2837 | ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. |
2611 | For IGP, Hypermemory is the only memory type showed in CCC. |
2838 | For IGP, Hypermemory is the only memory type showed in CCC. |
2612 | 2839 | ||
2613 | ucUMAChannelNumber: how many channels for the UMA; |
2840 | ucUMAChannelNumber: how many channels for the UMA; |
2614 | 2841 | ||
2615 | ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin |
2842 | ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin |
2616 | ucDockingPinBit: which bit in this register to read the pin status; |
2843 | ucDockingPinBit: which bit in this register to read the pin status; |
2617 | ucDockingPinPolarity:Polarity of the pin when docked; |
2844 | ucDockingPinPolarity:Polarity of the pin when docked; |
2618 | 2845 | ||
2619 | ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 |
2846 | ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 |
2620 | 2847 | ||
2621 | usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. |
2848 | usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. |
2622 | 2849 | ||
2623 | usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. |
2850 | usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. |
2624 | usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. |
2851 | usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. |
2625 | GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 |
2852 | GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 |
2626 | PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 |
2853 | PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 |
2627 | GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE |
2854 | GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE |
2628 | 2855 | ||
2629 | usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. |
2856 | usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. |
2630 | 2857 | ||
2631 | ulHTLinkFreq: Bootup HT link Frequency in 10Khz. |
2858 | ulHTLinkFreq: Bootup HT link Frequency in 10Khz. |
2632 | usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. |
2859 | usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. |
2633 | If CDLW enabled, both upstream and downstream width should be the same during bootup. |
2860 | If CDLW enabled, both upstream and downstream width should be the same during bootup. |
2634 | usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. |
2861 | usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. |
2635 | If CDLW enabled, both upstream and downstream width should be the same during bootup. |
2862 | If CDLW enabled, both upstream and downstream width should be the same during bootup. |
2636 | 2863 | ||
2637 | usUMASyncStartDelay: Memory access latency, required for watermark calculation |
2864 | usUMASyncStartDelay: Memory access latency, required for watermark calculation |
2638 | usUMADataReturnTime: Memory access latency, required for watermark calculation |
2865 | usUMADataReturnTime: Memory access latency, required for watermark calculation |
2639 | usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us |
2866 | usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us |
2640 | for Griffin or Greyhound. SBIOS needs to convert to actual time by: |
2867 | for Griffin or Greyhound. SBIOS needs to convert to actual time by: |
2641 | if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) |
2868 | if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) |
2642 | if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) |
2869 | if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) |
2643 | if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) |
2870 | if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) |
2644 | if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) |
2871 | if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) |
2645 | 2872 | ||
2646 | ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. |
2873 | ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. |
2647 | This must be less than or equal to ulHTLinkFreq(bootup frequency). |
2874 | This must be less than or equal to ulHTLinkFreq(bootup frequency). |
2648 | ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. |
2875 | ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. |
2649 | This must be less than or equal to ulHighVoltageHTLinkFreq. |
2876 | This must be less than or equal to ulHighVoltageHTLinkFreq. |
2650 | 2877 | ||
2651 | usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. |
2878 | usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. |
2652 | usMaxDownStreamHTLinkWidth: same as above. |
2879 | usMaxDownStreamHTLinkWidth: same as above. |
2653 | usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. |
2880 | usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. |
2654 | usMinDownStreamHTLinkWidth: same as above. |
2881 | usMinDownStreamHTLinkWidth: same as above. |
2655 | */ |
2882 | */ |
2656 | 2883 | ||
2657 | // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition |
2884 | // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition |
2658 | #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 |
2885 | #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 |
2659 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 |
2886 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 |
2660 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 |
2887 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 |
2661 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 |
2888 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 |
2662 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 |
2889 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 |
- | 2890 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 |
|
2663 | 2891 | ||
2664 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH // this deff reflects max defined CPU code |
2892 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code |
2665 | 2893 | ||
2666 | #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 |
2894 | #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 |
2667 | #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 |
2895 | #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 |
2668 | #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 |
2896 | #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 |
2669 | #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 |
2897 | #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 |
2670 | #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 |
2898 | #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 |
2671 | #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 |
2899 | #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 |
2672 | #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 |
2900 | #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 |
2673 | #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 |
2901 | #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 |
2674 | #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 |
2902 | #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 |
2675 | #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 |
2903 | #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 |
2676 | 2904 | ||
2677 | #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF |
2905 | #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF |
2678 | 2906 | ||
2679 | #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F |
2907 | #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F |
2680 | #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 |
2908 | #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 |
2681 | #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 |
2909 | #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 |
2682 | #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 |
2910 | #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 |
2683 | #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 |
2911 | #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 |
2684 | #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 |
2912 | #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 |
2685 | 2913 | ||
2686 | #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 |
2914 | #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 |
2687 | #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 |
2915 | #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 |
2688 | #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 |
2916 | #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 |
2689 | 2917 | ||
2690 | #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 |
2918 | #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 |
2691 | 2919 | ||
2692 | // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR |
2920 | // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR |
2693 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 |
2921 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 |
2694 | { |
2922 | { |
2695 | ATOM_COMMON_TABLE_HEADER sHeader; |
2923 | ATOM_COMMON_TABLE_HEADER sHeader; |
2696 | ULONG ulBootUpEngineClock; //in 10kHz unit |
2924 | ULONG ulBootUpEngineClock; //in 10kHz unit |
2697 | ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. |
2925 | ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. |
2698 | ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge |
2926 | ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge |
2699 | ULONG ulBootUpUMAClock; //in 10kHz unit |
2927 | ULONG ulBootUpUMAClock; //in 10kHz unit |
2700 | ULONG ulReserved1[8]; //must be 0x0 for the reserved |
2928 | ULONG ulReserved1[8]; //must be 0x0 for the reserved |
2701 | ULONG ulBootUpReqDisplayVector; |
2929 | ULONG ulBootUpReqDisplayVector; |
2702 | ULONG ulOtherDisplayMisc; |
2930 | ULONG ulOtherDisplayMisc; |
2703 | ULONG ulReserved2[4]; //must be 0x0 for the reserved |
2931 | ULONG ulReserved2[4]; //must be 0x0 for the reserved |
2704 | ULONG ulSystemConfig; //TBD |
2932 | ULONG ulSystemConfig; //TBD |
2705 | ULONG ulCPUCapInfo; //TBD |
2933 | ULONG ulCPUCapInfo; //TBD |
2706 | USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; |
2934 | USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; |
2707 | USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; |
2935 | USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; |
2708 | USHORT usBootUpNBVoltage; //boot up NB voltage |
2936 | USHORT usBootUpNBVoltage; //boot up NB voltage |
2709 | UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD |
2937 | UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD |
2710 | UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD |
2938 | UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD |
2711 | ULONG ulReserved3[4]; //must be 0x0 for the reserved |
2939 | ULONG ulReserved3[4]; //must be 0x0 for the reserved |
2712 | ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition |
2940 | ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition |
2713 | ULONG ulDDISlot2Config; |
2941 | ULONG ulDDISlot2Config; |
2714 | ULONG ulDDISlot3Config; |
2942 | ULONG ulDDISlot3Config; |
2715 | ULONG ulDDISlot4Config; |
2943 | ULONG ulDDISlot4Config; |
2716 | ULONG ulReserved4[4]; //must be 0x0 for the reserved |
2944 | ULONG ulReserved4[4]; //must be 0x0 for the reserved |
2717 | UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved |
2945 | UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved |
2718 | UCHAR ucUMAChannelNumber; |
2946 | UCHAR ucUMAChannelNumber; |
2719 | USHORT usReserved; |
2947 | USHORT usReserved; |
2720 | ULONG ulReserved5[4]; //must be 0x0 for the reserved |
2948 | ULONG ulReserved5[4]; //must be 0x0 for the reserved |
2721 | ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default |
2949 | ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default |
2722 | ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback |
2950 | ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback |
2723 | ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications |
2951 | ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications |
2724 | ULONG ulReserved6[61]; //must be 0x0 |
2952 | ULONG ulReserved6[61]; //must be 0x0 |
2725 | }ATOM_INTEGRATED_SYSTEM_INFO_V5; |
2953 | }ATOM_INTEGRATED_SYSTEM_INFO_V5; |
2726 | 2954 | ||
2727 | #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 |
2955 | #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 |
2728 | #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 |
2956 | #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 |
2729 | #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 |
2957 | #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 |
2730 | #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 |
2958 | #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 |
2731 | #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 |
2959 | #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 |
2732 | #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 |
2960 | #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 |
2733 | #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 |
2961 | #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 |
2734 | #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 |
2962 | #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 |
2735 | #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 |
2963 | #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 |
2736 | #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 |
2964 | #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 |
2737 | #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A |
2965 | #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A |
2738 | #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B |
2966 | #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B |
2739 | #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C |
2967 | #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C |
2740 | #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D |
2968 | #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D |
2741 | 2969 | ||
2742 | // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable |
2970 | // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable |
2743 | #define ASIC_INT_DAC1_ENCODER_ID 0x00 |
2971 | #define ASIC_INT_DAC1_ENCODER_ID 0x00 |
2744 | #define ASIC_INT_TV_ENCODER_ID 0x02 |
2972 | #define ASIC_INT_TV_ENCODER_ID 0x02 |
2745 | #define ASIC_INT_DIG1_ENCODER_ID 0x03 |
2973 | #define ASIC_INT_DIG1_ENCODER_ID 0x03 |
2746 | #define ASIC_INT_DAC2_ENCODER_ID 0x04 |
2974 | #define ASIC_INT_DAC2_ENCODER_ID 0x04 |
2747 | #define ASIC_EXT_TV_ENCODER_ID 0x06 |
2975 | #define ASIC_EXT_TV_ENCODER_ID 0x06 |
2748 | #define ASIC_INT_DVO_ENCODER_ID 0x07 |
2976 | #define ASIC_INT_DVO_ENCODER_ID 0x07 |
2749 | #define ASIC_INT_DIG2_ENCODER_ID 0x09 |
2977 | #define ASIC_INT_DIG2_ENCODER_ID 0x09 |
2750 | #define ASIC_EXT_DIG_ENCODER_ID 0x05 |
2978 | #define ASIC_EXT_DIG_ENCODER_ID 0x05 |
2751 | #define ASIC_EXT_DIG2_ENCODER_ID 0x08 |
2979 | #define ASIC_EXT_DIG2_ENCODER_ID 0x08 |
2752 | #define ASIC_INT_DIG3_ENCODER_ID 0x0a |
2980 | #define ASIC_INT_DIG3_ENCODER_ID 0x0a |
2753 | #define ASIC_INT_DIG4_ENCODER_ID 0x0b |
2981 | #define ASIC_INT_DIG4_ENCODER_ID 0x0b |
2754 | #define ASIC_INT_DIG5_ENCODER_ID 0x0c |
2982 | #define ASIC_INT_DIG5_ENCODER_ID 0x0c |
2755 | #define ASIC_INT_DIG6_ENCODER_ID 0x0d |
2983 | #define ASIC_INT_DIG6_ENCODER_ID 0x0d |
- | 2984 | #define ASIC_INT_DIG7_ENCODER_ID 0x0e |
|
2756 | 2985 | ||
2757 | //define Encoder attribute |
2986 | //define Encoder attribute |
2758 | #define ATOM_ANALOG_ENCODER 0 |
2987 | #define ATOM_ANALOG_ENCODER 0 |
2759 | #define ATOM_DIGITAL_ENCODER 1 |
2988 | #define ATOM_DIGITAL_ENCODER 1 |
2760 | #define ATOM_DP_ENCODER 2 |
2989 | #define ATOM_DP_ENCODER 2 |
2761 | 2990 | ||
2762 | #define ATOM_ENCODER_ENUM_MASK 0x70 |
2991 | #define ATOM_ENCODER_ENUM_MASK 0x70 |
2763 | #define ATOM_ENCODER_ENUM_ID1 0x00 |
2992 | #define ATOM_ENCODER_ENUM_ID1 0x00 |
2764 | #define ATOM_ENCODER_ENUM_ID2 0x10 |
2993 | #define ATOM_ENCODER_ENUM_ID2 0x10 |
2765 | #define ATOM_ENCODER_ENUM_ID3 0x20 |
2994 | #define ATOM_ENCODER_ENUM_ID3 0x20 |
2766 | #define ATOM_ENCODER_ENUM_ID4 0x30 |
2995 | #define ATOM_ENCODER_ENUM_ID4 0x30 |
2767 | #define ATOM_ENCODER_ENUM_ID5 0x40 |
2996 | #define ATOM_ENCODER_ENUM_ID5 0x40 |
2768 | #define ATOM_ENCODER_ENUM_ID6 0x50 |
2997 | #define ATOM_ENCODER_ENUM_ID6 0x50 |
2769 | 2998 | ||
2770 | #define ATOM_DEVICE_CRT1_INDEX 0x00000000 |
2999 | #define ATOM_DEVICE_CRT1_INDEX 0x00000000 |
2771 | #define ATOM_DEVICE_LCD1_INDEX 0x00000001 |
3000 | #define ATOM_DEVICE_LCD1_INDEX 0x00000001 |
2772 | #define ATOM_DEVICE_TV1_INDEX 0x00000002 |
3001 | #define ATOM_DEVICE_TV1_INDEX 0x00000002 |
2773 | #define ATOM_DEVICE_DFP1_INDEX 0x00000003 |
3002 | #define ATOM_DEVICE_DFP1_INDEX 0x00000003 |
2774 | #define ATOM_DEVICE_CRT2_INDEX 0x00000004 |
3003 | #define ATOM_DEVICE_CRT2_INDEX 0x00000004 |
2775 | #define ATOM_DEVICE_LCD2_INDEX 0x00000005 |
3004 | #define ATOM_DEVICE_LCD2_INDEX 0x00000005 |
2776 | #define ATOM_DEVICE_DFP6_INDEX 0x00000006 |
3005 | #define ATOM_DEVICE_DFP6_INDEX 0x00000006 |
2777 | #define ATOM_DEVICE_DFP2_INDEX 0x00000007 |
3006 | #define ATOM_DEVICE_DFP2_INDEX 0x00000007 |
2778 | #define ATOM_DEVICE_CV_INDEX 0x00000008 |
3007 | #define ATOM_DEVICE_CV_INDEX 0x00000008 |
2779 | #define ATOM_DEVICE_DFP3_INDEX 0x00000009 |
3008 | #define ATOM_DEVICE_DFP3_INDEX 0x00000009 |
2780 | #define ATOM_DEVICE_DFP4_INDEX 0x0000000A |
3009 | #define ATOM_DEVICE_DFP4_INDEX 0x0000000A |
2781 | #define ATOM_DEVICE_DFP5_INDEX 0x0000000B |
3010 | #define ATOM_DEVICE_DFP5_INDEX 0x0000000B |
2782 | 3011 | ||
2783 | #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C |
3012 | #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C |
2784 | #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D |
3013 | #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D |
2785 | #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E |
3014 | #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E |
2786 | #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F |
3015 | #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F |
2787 | #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) |
3016 | #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) |
2788 | #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO |
3017 | #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO |
2789 | #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) |
3018 | #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) |
2790 | 3019 | ||
2791 | #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) |
3020 | #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) |
2792 | 3021 | ||
2793 | #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) |
3022 | #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) |
2794 | #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) |
3023 | #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) |
2795 | #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) |
3024 | #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) |
2796 | #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) |
3025 | #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) |
2797 | #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) |
3026 | #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) |
2798 | #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) |
3027 | #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) |
2799 | #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) |
3028 | #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) |
2800 | #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) |
3029 | #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) |
2801 | #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) |
3030 | #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) |
2802 | #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) |
3031 | #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) |
2803 | #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) |
3032 | #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) |
2804 | #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) |
3033 | #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) |
2805 | 3034 | ||
2806 | #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) |
3035 | #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) |
2807 | #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) |
3036 | #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) |
2808 | #define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT) |
3037 | #define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT) |
2809 | #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) |
3038 | #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) |
2810 | 3039 | ||
2811 | #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 |
3040 | #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 |
2812 | #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 |
3041 | #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 |
2813 | #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 |
3042 | #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 |
2814 | #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 |
3043 | #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 |
2815 | #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 |
3044 | #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 |
2816 | #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 |
3045 | #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 |
2817 | #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 |
3046 | #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 |
2818 | #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 |
3047 | #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 |
2819 | #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 |
3048 | #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 |
2820 | #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 |
3049 | #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 |
2821 | #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 |
3050 | #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 |
2822 | #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A |
3051 | #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A |
2823 | #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B |
3052 | #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B |
2824 | #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E |
3053 | #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E |
2825 | #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F |
3054 | #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F |
2826 | 3055 | ||
2827 | 3056 | ||
2828 | #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F |
3057 | #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F |
2829 | #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 |
3058 | #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 |
2830 | #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 |
3059 | #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 |
2831 | #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 |
3060 | #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 |
2832 | #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 |
3061 | #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 |
2833 | #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 |
3062 | #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 |
2834 | 3063 | ||
2835 | #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 |
3064 | #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 |
2836 | 3065 | ||
2837 | #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F |
3066 | #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F |
2838 | #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 |
3067 | #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 |
2839 | 3068 | ||
2840 | #define ATOM_DEVICE_I2C_ID_MASK 0x00000070 |
3069 | #define ATOM_DEVICE_I2C_ID_MASK 0x00000070 |
2841 | #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 |
3070 | #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 |
2842 | #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 |
3071 | #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 |
2843 | #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 |
3072 | #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 |
2844 | #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 |
3073 | #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 |
2845 | #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 |
3074 | #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 |
2846 | 3075 | ||
2847 | #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 |
3076 | #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 |
2848 | #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 |
3077 | #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 |
2849 | #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 |
3078 | #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 |
2850 | #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 |
3079 | #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 |
2851 | 3080 | ||
2852 | // usDeviceSupport: |
3081 | // usDeviceSupport: |
2853 | // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported |
3082 | // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported |
2854 | // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported |
3083 | // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported |
2855 | // Bit 2 = 0 - no TV1 support= 1- TV1 is supported |
3084 | // Bit 2 = 0 - no TV1 support= 1- TV1 is supported |
2856 | // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported |
3085 | // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported |
2857 | // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported |
3086 | // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported |
2858 | // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported |
3087 | // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported |
2859 | // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported |
3088 | // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported |
2860 | // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported |
3089 | // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported |
2861 | // Bit 8 = 0 - no CV support= 1- CV is supported |
3090 | // Bit 8 = 0 - no CV support= 1- CV is supported |
2862 | // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported |
3091 | // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported |
2863 | // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported |
3092 | // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported |
2864 | // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported |
3093 | // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported |
2865 | // |
3094 | // |
2866 | // |
3095 | // |
2867 | 3096 | ||
2868 | /****************************************************************************/ |
3097 | /****************************************************************************/ |
2869 | /* Structure used in MclkSS_InfoTable */ |
3098 | /* Structure used in MclkSS_InfoTable */ |
2870 | /****************************************************************************/ |
3099 | /****************************************************************************/ |
2871 | // ucI2C_ConfigID |
3100 | // ucI2C_ConfigID |
2872 | // [7:0] - I2C LINE Associate ID |
3101 | // [7:0] - I2C LINE Associate ID |
2873 | // = 0 - no I2C |
3102 | // = 0 - no I2C |
2874 | // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) |
3103 | // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) |
2875 | // = 0, [6:0]=SW assisted I2C ID |
3104 | // = 0, [6:0]=SW assisted I2C ID |
2876 | // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use |
3105 | // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use |
2877 | // = 2, HW engine for Multimedia use |
3106 | // = 2, HW engine for Multimedia use |
2878 | // = 3-7 Reserved for future I2C engines |
3107 | // = 3-7 Reserved for future I2C engines |
2879 | // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C |
3108 | // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C |
2880 | 3109 | ||
2881 | typedef struct _ATOM_I2C_ID_CONFIG |
3110 | typedef struct _ATOM_I2C_ID_CONFIG |
2882 | { |
3111 | { |
2883 | #if ATOM_BIG_ENDIAN |
3112 | #if ATOM_BIG_ENDIAN |
2884 | UCHAR bfHW_Capable:1; |
3113 | UCHAR bfHW_Capable:1; |
2885 | UCHAR bfHW_EngineID:3; |
3114 | UCHAR bfHW_EngineID:3; |
2886 | UCHAR bfI2C_LineMux:4; |
3115 | UCHAR bfI2C_LineMux:4; |
2887 | #else |
3116 | #else |
2888 | UCHAR bfI2C_LineMux:4; |
3117 | UCHAR bfI2C_LineMux:4; |
2889 | UCHAR bfHW_EngineID:3; |
3118 | UCHAR bfHW_EngineID:3; |
2890 | UCHAR bfHW_Capable:1; |
3119 | UCHAR bfHW_Capable:1; |
2891 | #endif |
3120 | #endif |
2892 | }ATOM_I2C_ID_CONFIG; |
3121 | }ATOM_I2C_ID_CONFIG; |
2893 | 3122 | ||
2894 | typedef union _ATOM_I2C_ID_CONFIG_ACCESS |
3123 | typedef union _ATOM_I2C_ID_CONFIG_ACCESS |
2895 | { |
3124 | { |
2896 | ATOM_I2C_ID_CONFIG sbfAccess; |
3125 | ATOM_I2C_ID_CONFIG sbfAccess; |
2897 | UCHAR ucAccess; |
3126 | UCHAR ucAccess; |
2898 | }ATOM_I2C_ID_CONFIG_ACCESS; |
3127 | }ATOM_I2C_ID_CONFIG_ACCESS; |
2899 | 3128 | ||
2900 | 3129 | ||
2901 | /****************************************************************************/ |
3130 | /****************************************************************************/ |
2902 | // Structure used in GPIO_I2C_InfoTable |
3131 | // Structure used in GPIO_I2C_InfoTable |
2903 | /****************************************************************************/ |
3132 | /****************************************************************************/ |
2904 | typedef struct _ATOM_GPIO_I2C_ASSIGMENT |
3133 | typedef struct _ATOM_GPIO_I2C_ASSIGMENT |
2905 | { |
3134 | { |
2906 | USHORT usClkMaskRegisterIndex; |
3135 | USHORT usClkMaskRegisterIndex; |
2907 | USHORT usClkEnRegisterIndex; |
3136 | USHORT usClkEnRegisterIndex; |
2908 | USHORT usClkY_RegisterIndex; |
3137 | USHORT usClkY_RegisterIndex; |
2909 | USHORT usClkA_RegisterIndex; |
3138 | USHORT usClkA_RegisterIndex; |
2910 | USHORT usDataMaskRegisterIndex; |
3139 | USHORT usDataMaskRegisterIndex; |
2911 | USHORT usDataEnRegisterIndex; |
3140 | USHORT usDataEnRegisterIndex; |
2912 | USHORT usDataY_RegisterIndex; |
3141 | USHORT usDataY_RegisterIndex; |
2913 | USHORT usDataA_RegisterIndex; |
3142 | USHORT usDataA_RegisterIndex; |
2914 | ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; |
3143 | ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; |
2915 | UCHAR ucClkMaskShift; |
3144 | UCHAR ucClkMaskShift; |
2916 | UCHAR ucClkEnShift; |
3145 | UCHAR ucClkEnShift; |
2917 | UCHAR ucClkY_Shift; |
3146 | UCHAR ucClkY_Shift; |
2918 | UCHAR ucClkA_Shift; |
3147 | UCHAR ucClkA_Shift; |
2919 | UCHAR ucDataMaskShift; |
3148 | UCHAR ucDataMaskShift; |
2920 | UCHAR ucDataEnShift; |
3149 | UCHAR ucDataEnShift; |
2921 | UCHAR ucDataY_Shift; |
3150 | UCHAR ucDataY_Shift; |
2922 | UCHAR ucDataA_Shift; |
3151 | UCHAR ucDataA_Shift; |
2923 | UCHAR ucReserved1; |
3152 | UCHAR ucReserved1; |
2924 | UCHAR ucReserved2; |
3153 | UCHAR ucReserved2; |
2925 | }ATOM_GPIO_I2C_ASSIGMENT; |
3154 | }ATOM_GPIO_I2C_ASSIGMENT; |
2926 | 3155 | ||
2927 | typedef struct _ATOM_GPIO_I2C_INFO |
3156 | typedef struct _ATOM_GPIO_I2C_INFO |
2928 | { |
3157 | { |
2929 | ATOM_COMMON_TABLE_HEADER sHeader; |
3158 | ATOM_COMMON_TABLE_HEADER sHeader; |
2930 | ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; |
3159 | ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; |
2931 | }ATOM_GPIO_I2C_INFO; |
3160 | }ATOM_GPIO_I2C_INFO; |
2932 | 3161 | ||
2933 | /****************************************************************************/ |
3162 | /****************************************************************************/ |
2934 | // Common Structure used in other structures |
3163 | // Common Structure used in other structures |
2935 | /****************************************************************************/ |
3164 | /****************************************************************************/ |
2936 | 3165 | ||
2937 | #ifndef _H2INC |
3166 | #ifndef _H2INC |
2938 | 3167 | ||
2939 | //Please don't add or expand this bitfield structure below, this one will retire soon.! |
3168 | //Please don't add or expand this bitfield structure below, this one will retire soon.! |
2940 | typedef struct _ATOM_MODE_MISC_INFO |
3169 | typedef struct _ATOM_MODE_MISC_INFO |
2941 | { |
3170 | { |
2942 | #if ATOM_BIG_ENDIAN |
3171 | #if ATOM_BIG_ENDIAN |
2943 | USHORT Reserved:6; |
3172 | USHORT Reserved:6; |
2944 | USHORT RGB888:1; |
3173 | USHORT RGB888:1; |
2945 | USHORT DoubleClock:1; |
3174 | USHORT DoubleClock:1; |
2946 | USHORT Interlace:1; |
3175 | USHORT Interlace:1; |
2947 | USHORT CompositeSync:1; |
3176 | USHORT CompositeSync:1; |
2948 | USHORT V_ReplicationBy2:1; |
3177 | USHORT V_ReplicationBy2:1; |
2949 | USHORT H_ReplicationBy2:1; |
3178 | USHORT H_ReplicationBy2:1; |
2950 | USHORT VerticalCutOff:1; |
3179 | USHORT VerticalCutOff:1; |
2951 | USHORT VSyncPolarity:1; //0=Active High, 1=Active Low |
3180 | USHORT VSyncPolarity:1; //0=Active High, 1=Active Low |
2952 | USHORT HSyncPolarity:1; //0=Active High, 1=Active Low |
3181 | USHORT HSyncPolarity:1; //0=Active High, 1=Active Low |
2953 | USHORT HorizontalCutOff:1; |
3182 | USHORT HorizontalCutOff:1; |
2954 | #else |
3183 | #else |
2955 | USHORT HorizontalCutOff:1; |
3184 | USHORT HorizontalCutOff:1; |
2956 | USHORT HSyncPolarity:1; //0=Active High, 1=Active Low |
3185 | USHORT HSyncPolarity:1; //0=Active High, 1=Active Low |
2957 | USHORT VSyncPolarity:1; //0=Active High, 1=Active Low |
3186 | USHORT VSyncPolarity:1; //0=Active High, 1=Active Low |
2958 | USHORT VerticalCutOff:1; |
3187 | USHORT VerticalCutOff:1; |
2959 | USHORT H_ReplicationBy2:1; |
3188 | USHORT H_ReplicationBy2:1; |
2960 | USHORT V_ReplicationBy2:1; |
3189 | USHORT V_ReplicationBy2:1; |
2961 | USHORT CompositeSync:1; |
3190 | USHORT CompositeSync:1; |
2962 | USHORT Interlace:1; |
3191 | USHORT Interlace:1; |
2963 | USHORT DoubleClock:1; |
3192 | USHORT DoubleClock:1; |
2964 | USHORT RGB888:1; |
3193 | USHORT RGB888:1; |
2965 | USHORT Reserved:6; |
3194 | USHORT Reserved:6; |
2966 | #endif |
3195 | #endif |
2967 | }ATOM_MODE_MISC_INFO; |
3196 | }ATOM_MODE_MISC_INFO; |
2968 | 3197 | ||
2969 | typedef union _ATOM_MODE_MISC_INFO_ACCESS |
3198 | typedef union _ATOM_MODE_MISC_INFO_ACCESS |
2970 | { |
3199 | { |
2971 | ATOM_MODE_MISC_INFO sbfAccess; |
3200 | ATOM_MODE_MISC_INFO sbfAccess; |
2972 | USHORT usAccess; |
3201 | USHORT usAccess; |
2973 | }ATOM_MODE_MISC_INFO_ACCESS; |
3202 | }ATOM_MODE_MISC_INFO_ACCESS; |
2974 | 3203 | ||
2975 | #else |
3204 | #else |
2976 | 3205 | ||
2977 | typedef union _ATOM_MODE_MISC_INFO_ACCESS |
3206 | typedef union _ATOM_MODE_MISC_INFO_ACCESS |
2978 | { |
3207 | { |
2979 | USHORT usAccess; |
3208 | USHORT usAccess; |
2980 | }ATOM_MODE_MISC_INFO_ACCESS; |
3209 | }ATOM_MODE_MISC_INFO_ACCESS; |
2981 | 3210 | ||
2982 | #endif |
3211 | #endif |
2983 | 3212 | ||
2984 | // usModeMiscInfo- |
3213 | // usModeMiscInfo- |
2985 | #define ATOM_H_CUTOFF 0x01 |
3214 | #define ATOM_H_CUTOFF 0x01 |
2986 | #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low |
3215 | #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low |
2987 | #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low |
3216 | #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low |
2988 | #define ATOM_V_CUTOFF 0x08 |
3217 | #define ATOM_V_CUTOFF 0x08 |
2989 | #define ATOM_H_REPLICATIONBY2 0x10 |
3218 | #define ATOM_H_REPLICATIONBY2 0x10 |
2990 | #define ATOM_V_REPLICATIONBY2 0x20 |
3219 | #define ATOM_V_REPLICATIONBY2 0x20 |
2991 | #define ATOM_COMPOSITESYNC 0x40 |
3220 | #define ATOM_COMPOSITESYNC 0x40 |
2992 | #define ATOM_INTERLACE 0x80 |
3221 | #define ATOM_INTERLACE 0x80 |
2993 | #define ATOM_DOUBLE_CLOCK_MODE 0x100 |
3222 | #define ATOM_DOUBLE_CLOCK_MODE 0x100 |
2994 | #define ATOM_RGB888_MODE 0x200 |
3223 | #define ATOM_RGB888_MODE 0x200 |
2995 | 3224 | ||
2996 | //usRefreshRate- |
3225 | //usRefreshRate- |
2997 | #define ATOM_REFRESH_43 43 |
3226 | #define ATOM_REFRESH_43 43 |
2998 | #define ATOM_REFRESH_47 47 |
3227 | #define ATOM_REFRESH_47 47 |
2999 | #define ATOM_REFRESH_56 56 |
3228 | #define ATOM_REFRESH_56 56 |
3000 | #define ATOM_REFRESH_60 60 |
3229 | #define ATOM_REFRESH_60 60 |
3001 | #define ATOM_REFRESH_65 65 |
3230 | #define ATOM_REFRESH_65 65 |
3002 | #define ATOM_REFRESH_70 70 |
3231 | #define ATOM_REFRESH_70 70 |
3003 | #define ATOM_REFRESH_72 72 |
3232 | #define ATOM_REFRESH_72 72 |
3004 | #define ATOM_REFRESH_75 75 |
3233 | #define ATOM_REFRESH_75 75 |
3005 | #define ATOM_REFRESH_85 85 |
3234 | #define ATOM_REFRESH_85 85 |
3006 | 3235 | ||
3007 | // ATOM_MODE_TIMING data are exactly the same as VESA timing data. |
3236 | // ATOM_MODE_TIMING data are exactly the same as VESA timing data. |
3008 | // Translation from EDID to ATOM_MODE_TIMING, use the following formula. |
3237 | // Translation from EDID to ATOM_MODE_TIMING, use the following formula. |
3009 | // |
3238 | // |
3010 | // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK |
3239 | // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK |
3011 | // = EDID_HA + EDID_HBL |
3240 | // = EDID_HA + EDID_HBL |
3012 | // VESA_HDISP = VESA_ACTIVE = EDID_HA |
3241 | // VESA_HDISP = VESA_ACTIVE = EDID_HA |
3013 | // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH |
3242 | // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH |
3014 | // = EDID_HA + EDID_HSO |
3243 | // = EDID_HA + EDID_HSO |
3015 | // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW |
3244 | // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW |
3016 | // VESA_BORDER = EDID_BORDER |
3245 | // VESA_BORDER = EDID_BORDER |
3017 | 3246 | ||
3018 | /****************************************************************************/ |
3247 | /****************************************************************************/ |
3019 | // Structure used in SetCRTC_UsingDTDTimingTable |
3248 | // Structure used in SetCRTC_UsingDTDTimingTable |
3020 | /****************************************************************************/ |
3249 | /****************************************************************************/ |
3021 | typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS |
3250 | typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS |
3022 | { |
3251 | { |
3023 | USHORT usH_Size; |
3252 | USHORT usH_Size; |
3024 | USHORT usH_Blanking_Time; |
3253 | USHORT usH_Blanking_Time; |
3025 | USHORT usV_Size; |
3254 | USHORT usV_Size; |
3026 | USHORT usV_Blanking_Time; |
3255 | USHORT usV_Blanking_Time; |
3027 | USHORT usH_SyncOffset; |
3256 | USHORT usH_SyncOffset; |
3028 | USHORT usH_SyncWidth; |
3257 | USHORT usH_SyncWidth; |
3029 | USHORT usV_SyncOffset; |
3258 | USHORT usV_SyncOffset; |
3030 | USHORT usV_SyncWidth; |
3259 | USHORT usV_SyncWidth; |
3031 | ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; |
3260 | ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; |
3032 | UCHAR ucH_Border; // From DFP EDID |
3261 | UCHAR ucH_Border; // From DFP EDID |
3033 | UCHAR ucV_Border; |
3262 | UCHAR ucV_Border; |
3034 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
3263 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
3035 | UCHAR ucPadding[3]; |
3264 | UCHAR ucPadding[3]; |
3036 | }SET_CRTC_USING_DTD_TIMING_PARAMETERS; |
3265 | }SET_CRTC_USING_DTD_TIMING_PARAMETERS; |
3037 | 3266 | ||
3038 | /****************************************************************************/ |
3267 | /****************************************************************************/ |
3039 | // Structure used in SetCRTC_TimingTable |
3268 | // Structure used in SetCRTC_TimingTable |
3040 | /****************************************************************************/ |
3269 | /****************************************************************************/ |
3041 | typedef struct _SET_CRTC_TIMING_PARAMETERS |
3270 | typedef struct _SET_CRTC_TIMING_PARAMETERS |
3042 | { |
3271 | { |
3043 | USHORT usH_Total; // horizontal total |
3272 | USHORT usH_Total; // horizontal total |
3044 | USHORT usH_Disp; // horizontal display |
3273 | USHORT usH_Disp; // horizontal display |
3045 | USHORT usH_SyncStart; // horozontal Sync start |
3274 | USHORT usH_SyncStart; // horozontal Sync start |
3046 | USHORT usH_SyncWidth; // horizontal Sync width |
3275 | USHORT usH_SyncWidth; // horizontal Sync width |
3047 | USHORT usV_Total; // vertical total |
3276 | USHORT usV_Total; // vertical total |
3048 | USHORT usV_Disp; // vertical display |
3277 | USHORT usV_Disp; // vertical display |
3049 | USHORT usV_SyncStart; // vertical Sync start |
3278 | USHORT usV_SyncStart; // vertical Sync start |
3050 | USHORT usV_SyncWidth; // vertical Sync width |
3279 | USHORT usV_SyncWidth; // vertical Sync width |
3051 | ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; |
3280 | ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; |
3052 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
3281 | UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 |
3053 | UCHAR ucOverscanRight; // right |
3282 | UCHAR ucOverscanRight; // right |
3054 | UCHAR ucOverscanLeft; // left |
3283 | UCHAR ucOverscanLeft; // left |
3055 | UCHAR ucOverscanBottom; // bottom |
3284 | UCHAR ucOverscanBottom; // bottom |
3056 | UCHAR ucOverscanTop; // top |
3285 | UCHAR ucOverscanTop; // top |
3057 | UCHAR ucReserved; |
3286 | UCHAR ucReserved; |
3058 | }SET_CRTC_TIMING_PARAMETERS; |
3287 | }SET_CRTC_TIMING_PARAMETERS; |
3059 | #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS |
3288 | #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS |
3060 | 3289 | ||
3061 | /****************************************************************************/ |
3290 | /****************************************************************************/ |
3062 | // Structure used in StandardVESA_TimingTable |
3291 | // Structure used in StandardVESA_TimingTable |
3063 | // AnalogTV_InfoTable |
3292 | // AnalogTV_InfoTable |
3064 | // ComponentVideoInfoTable |
3293 | // ComponentVideoInfoTable |
3065 | /****************************************************************************/ |
3294 | /****************************************************************************/ |
3066 | typedef struct _ATOM_MODE_TIMING |
3295 | typedef struct _ATOM_MODE_TIMING |
3067 | { |
3296 | { |
3068 | USHORT usCRTC_H_Total; |
3297 | USHORT usCRTC_H_Total; |
3069 | USHORT usCRTC_H_Disp; |
3298 | USHORT usCRTC_H_Disp; |
3070 | USHORT usCRTC_H_SyncStart; |
3299 | USHORT usCRTC_H_SyncStart; |
3071 | USHORT usCRTC_H_SyncWidth; |
3300 | USHORT usCRTC_H_SyncWidth; |
3072 | USHORT usCRTC_V_Total; |
3301 | USHORT usCRTC_V_Total; |
3073 | USHORT usCRTC_V_Disp; |
3302 | USHORT usCRTC_V_Disp; |
3074 | USHORT usCRTC_V_SyncStart; |
3303 | USHORT usCRTC_V_SyncStart; |
3075 | USHORT usCRTC_V_SyncWidth; |
3304 | USHORT usCRTC_V_SyncWidth; |
3076 | USHORT usPixelClock; //in 10Khz unit |
3305 | USHORT usPixelClock; //in 10Khz unit |
3077 | ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; |
3306 | ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; |
3078 | USHORT usCRTC_OverscanRight; |
3307 | USHORT usCRTC_OverscanRight; |
3079 | USHORT usCRTC_OverscanLeft; |
3308 | USHORT usCRTC_OverscanLeft; |
3080 | USHORT usCRTC_OverscanBottom; |
3309 | USHORT usCRTC_OverscanBottom; |
3081 | USHORT usCRTC_OverscanTop; |
3310 | USHORT usCRTC_OverscanTop; |
3082 | USHORT usReserve; |
3311 | USHORT usReserve; |
3083 | UCHAR ucInternalModeNumber; |
3312 | UCHAR ucInternalModeNumber; |
3084 | UCHAR ucRefreshRate; |
3313 | UCHAR ucRefreshRate; |
3085 | }ATOM_MODE_TIMING; |
3314 | }ATOM_MODE_TIMING; |
3086 | 3315 | ||
3087 | typedef struct _ATOM_DTD_FORMAT |
3316 | typedef struct _ATOM_DTD_FORMAT |
3088 | { |
3317 | { |
3089 | USHORT usPixClk; |
3318 | USHORT usPixClk; |
3090 | USHORT usHActive; |
3319 | USHORT usHActive; |
3091 | USHORT usHBlanking_Time; |
3320 | USHORT usHBlanking_Time; |
3092 | USHORT usVActive; |
3321 | USHORT usVActive; |
3093 | USHORT usVBlanking_Time; |
3322 | USHORT usVBlanking_Time; |
3094 | USHORT usHSyncOffset; |
3323 | USHORT usHSyncOffset; |
3095 | USHORT usHSyncWidth; |
3324 | USHORT usHSyncWidth; |
3096 | USHORT usVSyncOffset; |
3325 | USHORT usVSyncOffset; |
3097 | USHORT usVSyncWidth; |
3326 | USHORT usVSyncWidth; |
3098 | USHORT usImageHSize; |
3327 | USHORT usImageHSize; |
3099 | USHORT usImageVSize; |
3328 | USHORT usImageVSize; |
3100 | UCHAR ucHBorder; |
3329 | UCHAR ucHBorder; |
3101 | UCHAR ucVBorder; |
3330 | UCHAR ucVBorder; |
3102 | ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; |
3331 | ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; |
3103 | UCHAR ucInternalModeNumber; |
3332 | UCHAR ucInternalModeNumber; |
3104 | UCHAR ucRefreshRate; |
3333 | UCHAR ucRefreshRate; |
3105 | }ATOM_DTD_FORMAT; |
3334 | }ATOM_DTD_FORMAT; |
3106 | 3335 | ||
3107 | /****************************************************************************/ |
3336 | /****************************************************************************/ |
3108 | // Structure used in LVDS_InfoTable |
3337 | // Structure used in LVDS_InfoTable |
3109 | // * Need a document to describe this table |
3338 | // * Need a document to describe this table |
3110 | /****************************************************************************/ |
3339 | /****************************************************************************/ |
3111 | #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 |
3340 | #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 |
3112 | #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 |
3341 | #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 |
3113 | #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 |
3342 | #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 |
3114 | #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 |
3343 | #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 |
3115 | 3344 | ||
3116 | //ucTableFormatRevision=1 |
3345 | //ucTableFormatRevision=1 |
3117 | //ucTableContentRevision=1 |
3346 | //ucTableContentRevision=1 |
3118 | typedef struct _ATOM_LVDS_INFO |
3347 | typedef struct _ATOM_LVDS_INFO |
3119 | { |
3348 | { |
3120 | ATOM_COMMON_TABLE_HEADER sHeader; |
3349 | ATOM_COMMON_TABLE_HEADER sHeader; |
3121 | ATOM_DTD_FORMAT sLCDTiming; |
3350 | ATOM_DTD_FORMAT sLCDTiming; |
3122 | USHORT usModePatchTableOffset; |
3351 | USHORT usModePatchTableOffset; |
3123 | USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. |
3352 | USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. |
3124 | USHORT usOffDelayInMs; |
3353 | USHORT usOffDelayInMs; |
3125 | UCHAR ucPowerSequenceDigOntoDEin10Ms; |
3354 | UCHAR ucPowerSequenceDigOntoDEin10Ms; |
3126 | UCHAR ucPowerSequenceDEtoBLOnin10Ms; |
3355 | UCHAR ucPowerSequenceDEtoBLOnin10Ms; |
3127 | UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} |
3356 | UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} |
3128 | // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} |
3357 | // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} |
3129 | // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} |
3358 | // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} |
3130 | // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} |
3359 | // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} |
3131 | UCHAR ucPanelDefaultRefreshRate; |
3360 | UCHAR ucPanelDefaultRefreshRate; |
3132 | UCHAR ucPanelIdentification; |
3361 | UCHAR ucPanelIdentification; |
3133 | UCHAR ucSS_Id; |
3362 | UCHAR ucSS_Id; |
3134 | }ATOM_LVDS_INFO; |
3363 | }ATOM_LVDS_INFO; |
3135 | 3364 | ||
3136 | //ucTableFormatRevision=1 |
3365 | //ucTableFormatRevision=1 |
3137 | //ucTableContentRevision=2 |
3366 | //ucTableContentRevision=2 |
3138 | typedef struct _ATOM_LVDS_INFO_V12 |
3367 | typedef struct _ATOM_LVDS_INFO_V12 |
3139 | { |
3368 | { |
3140 | ATOM_COMMON_TABLE_HEADER sHeader; |
3369 | ATOM_COMMON_TABLE_HEADER sHeader; |
3141 | ATOM_DTD_FORMAT sLCDTiming; |
3370 | ATOM_DTD_FORMAT sLCDTiming; |
3142 | USHORT usExtInfoTableOffset; |
3371 | USHORT usExtInfoTableOffset; |
3143 | USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. |
3372 | USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. |
3144 | USHORT usOffDelayInMs; |
3373 | USHORT usOffDelayInMs; |
3145 | UCHAR ucPowerSequenceDigOntoDEin10Ms; |
3374 | UCHAR ucPowerSequenceDigOntoDEin10Ms; |
3146 | UCHAR ucPowerSequenceDEtoBLOnin10Ms; |
3375 | UCHAR ucPowerSequenceDEtoBLOnin10Ms; |
3147 | UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} |
3376 | UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} |
3148 | // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} |
3377 | // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} |
3149 | // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} |
3378 | // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} |
3150 | // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} |
3379 | // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} |
3151 | UCHAR ucPanelDefaultRefreshRate; |
3380 | UCHAR ucPanelDefaultRefreshRate; |
3152 | UCHAR ucPanelIdentification; |
3381 | UCHAR ucPanelIdentification; |
3153 | UCHAR ucSS_Id; |
3382 | UCHAR ucSS_Id; |
3154 | USHORT usLCDVenderID; |
3383 | USHORT usLCDVenderID; |
3155 | USHORT usLCDProductID; |
3384 | USHORT usLCDProductID; |
3156 | UCHAR ucLCDPanel_SpecialHandlingCap; |
3385 | UCHAR ucLCDPanel_SpecialHandlingCap; |
3157 | UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable |
3386 | UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable |
3158 | UCHAR ucReserved[2]; |
3387 | UCHAR ucReserved[2]; |
3159 | }ATOM_LVDS_INFO_V12; |
3388 | }ATOM_LVDS_INFO_V12; |
3160 | 3389 | ||
3161 | //Definitions for ucLCDPanel_SpecialHandlingCap: |
3390 | //Definitions for ucLCDPanel_SpecialHandlingCap: |
3162 | 3391 | ||
3163 | //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. |
3392 | //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. |
3164 | //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL |
3393 | //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL |
3165 | #define LCDPANEL_CAP_READ_EDID 0x1 |
3394 | #define LCDPANEL_CAP_READ_EDID 0x1 |
3166 | 3395 | ||
3167 | //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together |
3396 | //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together |
3168 | //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static |
3397 | //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static |
3169 | //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 |
3398 | //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 |
3170 | #define LCDPANEL_CAP_DRR_SUPPORTED 0x2 |
3399 | #define LCDPANEL_CAP_DRR_SUPPORTED 0x2 |
3171 | 3400 | ||
3172 | //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. |
3401 | //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. |
3173 | #define LCDPANEL_CAP_eDP 0x4 |
3402 | #define LCDPANEL_CAP_eDP 0x4 |
3174 | 3403 | ||
3175 | 3404 | ||
3176 | //Color Bit Depth definition in EDID V1.4 @BYTE 14h |
3405 | //Color Bit Depth definition in EDID V1.4 @BYTE 14h |
3177 | //Bit 6 5 4 |
3406 | //Bit 6 5 4 |
3178 | // 0 0 0 - Color bit depth is undefined |
3407 | // 0 0 0 - Color bit depth is undefined |
3179 | // 0 0 1 - 6 Bits per Primary Color |
3408 | // 0 0 1 - 6 Bits per Primary Color |
3180 | // 0 1 0 - 8 Bits per Primary Color |
3409 | // 0 1 0 - 8 Bits per Primary Color |
3181 | // 0 1 1 - 10 Bits per Primary Color |
3410 | // 0 1 1 - 10 Bits per Primary Color |
3182 | // 1 0 0 - 12 Bits per Primary Color |
3411 | // 1 0 0 - 12 Bits per Primary Color |
3183 | // 1 0 1 - 14 Bits per Primary Color |
3412 | // 1 0 1 - 14 Bits per Primary Color |
3184 | // 1 1 0 - 16 Bits per Primary Color |
3413 | // 1 1 0 - 16 Bits per Primary Color |
3185 | // 1 1 1 - Reserved |
3414 | // 1 1 1 - Reserved |
3186 | 3415 | ||
3187 | #define PANEL_COLOR_BIT_DEPTH_MASK 0x70 |
3416 | #define PANEL_COLOR_BIT_DEPTH_MASK 0x70 |
3188 | 3417 | ||
3189 | // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} |
3418 | // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} |
3190 | #define PANEL_RANDOM_DITHER 0x80 |
3419 | #define PANEL_RANDOM_DITHER 0x80 |
3191 | #define PANEL_RANDOM_DITHER_MASK 0x80 |
3420 | #define PANEL_RANDOM_DITHER_MASK 0x80 |
3192 | 3421 | ||
3193 | #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this |
3422 | #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this |
3194 | 3423 | ||
3195 | /****************************************************************************/ |
3424 | /****************************************************************************/ |
3196 | // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 |
3425 | // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 |
3197 | // ASIC Families: NI |
3426 | // ASIC Families: NI |
3198 | // ucTableFormatRevision=1 |
3427 | // ucTableFormatRevision=1 |
3199 | // ucTableContentRevision=3 |
3428 | // ucTableContentRevision=3 |
3200 | /****************************************************************************/ |
3429 | /****************************************************************************/ |
3201 | typedef struct _ATOM_LCD_INFO_V13 |
3430 | typedef struct _ATOM_LCD_INFO_V13 |
3202 | { |
3431 | { |
3203 | ATOM_COMMON_TABLE_HEADER sHeader; |
3432 | ATOM_COMMON_TABLE_HEADER sHeader; |
3204 | ATOM_DTD_FORMAT sLCDTiming; |
3433 | ATOM_DTD_FORMAT sLCDTiming; |
3205 | USHORT usExtInfoTableOffset; |
3434 | USHORT usExtInfoTableOffset; |
3206 | USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. |
3435 | USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. |
3207 | ULONG ulReserved0; |
3436 | ULONG ulReserved0; |
3208 | UCHAR ucLCD_Misc; // Reorganized in V13 |
3437 | UCHAR ucLCD_Misc; // Reorganized in V13 |
3209 | // Bit0: {=0:single, =1:dual}, |
3438 | // Bit0: {=0:single, =1:dual}, |
3210 | // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, |
3439 | // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, |
3211 | // Bit3:2: {Grey level} |
3440 | // Bit3:2: {Grey level} |
3212 | // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) |
3441 | // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) |
3213 | // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? |
3442 | // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? |
3214 | UCHAR ucPanelDefaultRefreshRate; |
3443 | UCHAR ucPanelDefaultRefreshRate; |
3215 | UCHAR ucPanelIdentification; |
3444 | UCHAR ucPanelIdentification; |
3216 | UCHAR ucSS_Id; |
3445 | UCHAR ucSS_Id; |
3217 | USHORT usLCDVenderID; |
3446 | USHORT usLCDVenderID; |
3218 | USHORT usLCDProductID; |
3447 | USHORT usLCDProductID; |
3219 | UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 |
3448 | UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 |
3220 | // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own |
3449 | // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own |
3221 | // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED |
3450 | // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED |
3222 | // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) |
3451 | // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) |
3223 | // Bit7-3: Reserved |
3452 | // Bit7-3: Reserved |
3224 | UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable |
3453 | UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable |
3225 | USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 |
3454 | USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 |
3226 | 3455 | ||
3227 | UCHAR ucPowerSequenceDIGONtoDE_in4Ms; |
3456 | UCHAR ucPowerSequenceDIGONtoDE_in4Ms; |
3228 | UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; |
3457 | UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; |
3229 | UCHAR ucPowerSequenceDEtoDIGON_in4Ms; |
- | |
3230 | UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; |
3458 | UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; |
- | 3459 | UCHAR ucPowerSequenceDEtoDIGON_in4Ms; |
|
3231 | 3460 | ||
3232 | UCHAR ucOffDelay_in4Ms; |
3461 | UCHAR ucOffDelay_in4Ms; |
3233 | UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; |
3462 | UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; |
3234 | UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; |
3463 | UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; |
3235 | UCHAR ucReserved1; |
3464 | UCHAR ucReserved1; |
- | 3465 | ||
- | 3466 | UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh |
|
- | 3467 | UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h |
|
- | 3468 | UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h |
|
- | 3469 | UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h |
|
- | 3470 | ||
- | 3471 | USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. |
|
- | 3472 | UCHAR uceDPToLVDSRxId; |
|
3236 | 3473 | UCHAR ucLcdReservd; |
|
3237 | ULONG ulReserved[4]; |
3474 | ULONG ulReserved[2]; |
3238 | }ATOM_LCD_INFO_V13; |
3475 | }ATOM_LCD_INFO_V13; |
3239 | 3476 | ||
3240 | #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 |
3477 | #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 |
3241 | 3478 | ||
3242 | //Definitions for ucLCD_Misc |
3479 | //Definitions for ucLCD_Misc |
3243 | #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 |
3480 | #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 |
3244 | #define ATOM_PANEL_MISC_V13_FPDI 0x00000002 |
3481 | #define ATOM_PANEL_MISC_V13_FPDI 0x00000002 |
3245 | #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C |
3482 | #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C |
3246 | #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 |
3483 | #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 |
3247 | #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 |
3484 | #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 |
3248 | #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 |
3485 | #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 |
3249 | #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 |
3486 | #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 |
3250 | 3487 | ||
3251 | //Color Bit Depth definition in EDID V1.4 @BYTE 14h |
3488 | //Color Bit Depth definition in EDID V1.4 @BYTE 14h |
3252 | //Bit 6 5 4 |
3489 | //Bit 6 5 4 |
3253 | // 0 0 0 - Color bit depth is undefined |
3490 | // 0 0 0 - Color bit depth is undefined |
3254 | // 0 0 1 - 6 Bits per Primary Color |
3491 | // 0 0 1 - 6 Bits per Primary Color |
3255 | // 0 1 0 - 8 Bits per Primary Color |
3492 | // 0 1 0 - 8 Bits per Primary Color |
3256 | // 0 1 1 - 10 Bits per Primary Color |
3493 | // 0 1 1 - 10 Bits per Primary Color |
3257 | // 1 0 0 - 12 Bits per Primary Color |
3494 | // 1 0 0 - 12 Bits per Primary Color |
3258 | // 1 0 1 - 14 Bits per Primary Color |
3495 | // 1 0 1 - 14 Bits per Primary Color |
3259 | // 1 1 0 - 16 Bits per Primary Color |
3496 | // 1 1 0 - 16 Bits per Primary Color |
3260 | // 1 1 1 - Reserved |
3497 | // 1 1 1 - Reserved |
3261 | 3498 | ||
3262 | //Definitions for ucLCDPanel_SpecialHandlingCap: |
3499 | //Definitions for ucLCDPanel_SpecialHandlingCap: |
3263 | 3500 | ||
3264 | //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. |
3501 | //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. |
3265 | //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL |
3502 | //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL |
3266 | #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version |
3503 | #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version |
3267 | 3504 | ||
3268 | //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together |
3505 | //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together |
3269 | //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static |
3506 | //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static |
3270 | //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 |
3507 | //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 |
3271 | #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version |
3508 | #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version |
3272 | 3509 | ||
3273 | //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. |
3510 | //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. |
3274 | #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version |
3511 | #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version |
- | 3512 | ||
- | 3513 | //uceDPToLVDSRxId |
|
- | 3514 | #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip |
|
- | 3515 | #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init |
|
- | 3516 | #define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init |
|
3275 | 3517 | ||
3276 | typedef struct _ATOM_PATCH_RECORD_MODE |
3518 | typedef struct _ATOM_PATCH_RECORD_MODE |
3277 | { |
3519 | { |
3278 | UCHAR ucRecordType; |
3520 | UCHAR ucRecordType; |
3279 | USHORT usHDisp; |
3521 | USHORT usHDisp; |
3280 | USHORT usVDisp; |
3522 | USHORT usVDisp; |
3281 | }ATOM_PATCH_RECORD_MODE; |
3523 | }ATOM_PATCH_RECORD_MODE; |
3282 | 3524 | ||
3283 | typedef struct _ATOM_LCD_RTS_RECORD |
3525 | typedef struct _ATOM_LCD_RTS_RECORD |
3284 | { |
3526 | { |
3285 | UCHAR ucRecordType; |
3527 | UCHAR ucRecordType; |
3286 | UCHAR ucRTSValue; |
3528 | UCHAR ucRTSValue; |
3287 | }ATOM_LCD_RTS_RECORD; |
3529 | }ATOM_LCD_RTS_RECORD; |
3288 | 3530 | ||
3289 | //!! If the record below exits, it shoud always be the first record for easy use in command table!!! |
3531 | //!! If the record below exits, it shoud always be the first record for easy use in command table!!! |
3290 | // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. |
3532 | // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. |
3291 | typedef struct _ATOM_LCD_MODE_CONTROL_CAP |
3533 | typedef struct _ATOM_LCD_MODE_CONTROL_CAP |
3292 | { |
3534 | { |
3293 | UCHAR ucRecordType; |
3535 | UCHAR ucRecordType; |
3294 | USHORT usLCDCap; |
3536 | USHORT usLCDCap; |
3295 | }ATOM_LCD_MODE_CONTROL_CAP; |
3537 | }ATOM_LCD_MODE_CONTROL_CAP; |
3296 | 3538 | ||
3297 | #define LCD_MODE_CAP_BL_OFF 1 |
3539 | #define LCD_MODE_CAP_BL_OFF 1 |
3298 | #define LCD_MODE_CAP_CRTC_OFF 2 |
3540 | #define LCD_MODE_CAP_CRTC_OFF 2 |
3299 | #define LCD_MODE_CAP_PANEL_OFF 4 |
3541 | #define LCD_MODE_CAP_PANEL_OFF 4 |
3300 | 3542 | ||
3301 | typedef struct _ATOM_FAKE_EDID_PATCH_RECORD |
3543 | typedef struct _ATOM_FAKE_EDID_PATCH_RECORD |
3302 | { |
3544 | { |
3303 | UCHAR ucRecordType; |
3545 | UCHAR ucRecordType; |
3304 | UCHAR ucFakeEDIDLength; |
3546 | UCHAR ucFakeEDIDLength; |
3305 | UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. |
3547 | UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. |
3306 | } ATOM_FAKE_EDID_PATCH_RECORD; |
3548 | } ATOM_FAKE_EDID_PATCH_RECORD; |
3307 | 3549 | ||
3308 | typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD |
3550 | typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD |
3309 | { |
3551 | { |
3310 | UCHAR ucRecordType; |
3552 | UCHAR ucRecordType; |
3311 | USHORT usHSize; |
3553 | USHORT usHSize; |
3312 | USHORT usVSize; |
3554 | USHORT usVSize; |
3313 | }ATOM_PANEL_RESOLUTION_PATCH_RECORD; |
3555 | }ATOM_PANEL_RESOLUTION_PATCH_RECORD; |
3314 | 3556 | ||
3315 | #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 |
3557 | #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 |
3316 | #define LCD_RTS_RECORD_TYPE 2 |
3558 | #define LCD_RTS_RECORD_TYPE 2 |
3317 | #define LCD_CAP_RECORD_TYPE 3 |
3559 | #define LCD_CAP_RECORD_TYPE 3 |
3318 | #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 |
3560 | #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 |
3319 | #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 |
3561 | #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 |
- | 3562 | #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 |
|
3320 | #define ATOM_RECORD_END_TYPE 0xFF |
3563 | #define ATOM_RECORD_END_TYPE 0xFF |
3321 | 3564 | ||
3322 | /****************************Spread Spectrum Info Table Definitions **********************/ |
3565 | /****************************Spread Spectrum Info Table Definitions **********************/ |
3323 | 3566 | ||
3324 | //ucTableFormatRevision=1 |
3567 | //ucTableFormatRevision=1 |
3325 | //ucTableContentRevision=2 |
3568 | //ucTableContentRevision=2 |
3326 | typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT |
3569 | typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT |
3327 | { |
3570 | { |
3328 | USHORT usSpreadSpectrumPercentage; |
3571 | USHORT usSpreadSpectrumPercentage; |
3329 | UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD |
3572 | UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD |
3330 | UCHAR ucSS_Step; |
3573 | UCHAR ucSS_Step; |
3331 | UCHAR ucSS_Delay; |
3574 | UCHAR ucSS_Delay; |
3332 | UCHAR ucSS_Id; |
3575 | UCHAR ucSS_Id; |
3333 | UCHAR ucRecommendedRef_Div; |
3576 | UCHAR ucRecommendedRef_Div; |
3334 | UCHAR ucSS_Range; //it was reserved for V11 |
3577 | UCHAR ucSS_Range; //it was reserved for V11 |
3335 | }ATOM_SPREAD_SPECTRUM_ASSIGNMENT; |
3578 | }ATOM_SPREAD_SPECTRUM_ASSIGNMENT; |
3336 | 3579 | ||
3337 | #define ATOM_MAX_SS_ENTRY 16 |
3580 | #define ATOM_MAX_SS_ENTRY 16 |
3338 | #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. |
3581 | #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. |
3339 | #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. |
3582 | #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. |
3340 | #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz |
3583 | #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz |
3341 | #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz |
3584 | #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz |
3342 | 3585 | ||
3343 | 3586 | ||
3344 | #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 |
3587 | #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 |
3345 | #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 |
3588 | #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 |
3346 | #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 |
3589 | #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 |
3347 | #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 |
3590 | #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 |
3348 | #define ATOM_INTERNAL_SS_MASK 0x00000000 |
3591 | #define ATOM_INTERNAL_SS_MASK 0x00000000 |
3349 | #define ATOM_EXTERNAL_SS_MASK 0x00000002 |
3592 | #define ATOM_EXTERNAL_SS_MASK 0x00000002 |
3350 | #define EXEC_SS_STEP_SIZE_SHIFT 2 |
3593 | #define EXEC_SS_STEP_SIZE_SHIFT 2 |
3351 | #define EXEC_SS_DELAY_SHIFT 4 |
3594 | #define EXEC_SS_DELAY_SHIFT 4 |
3352 | #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 |
3595 | #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 |
3353 | 3596 | ||
3354 | typedef struct _ATOM_SPREAD_SPECTRUM_INFO |
3597 | typedef struct _ATOM_SPREAD_SPECTRUM_INFO |
3355 | { |
3598 | { |
3356 | ATOM_COMMON_TABLE_HEADER sHeader; |
3599 | ATOM_COMMON_TABLE_HEADER sHeader; |
3357 | ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; |
3600 | ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; |
3358 | }ATOM_SPREAD_SPECTRUM_INFO; |
3601 | }ATOM_SPREAD_SPECTRUM_INFO; |
3359 | 3602 | ||
3360 | /****************************************************************************/ |
3603 | /****************************************************************************/ |
3361 | // Structure used in AnalogTV_InfoTable (Top level) |
3604 | // Structure used in AnalogTV_InfoTable (Top level) |
3362 | /****************************************************************************/ |
3605 | /****************************************************************************/ |
3363 | //ucTVBootUpDefaultStd definition: |
3606 | //ucTVBootUpDefaultStd definition: |
3364 | 3607 | ||
3365 | //ATOM_TV_NTSC 1 |
3608 | //ATOM_TV_NTSC 1 |
3366 | //ATOM_TV_NTSCJ 2 |
3609 | //ATOM_TV_NTSCJ 2 |
3367 | //ATOM_TV_PAL 3 |
3610 | //ATOM_TV_PAL 3 |
3368 | //ATOM_TV_PALM 4 |
3611 | //ATOM_TV_PALM 4 |
3369 | //ATOM_TV_PALCN 5 |
3612 | //ATOM_TV_PALCN 5 |
3370 | //ATOM_TV_PALN 6 |
3613 | //ATOM_TV_PALN 6 |
3371 | //ATOM_TV_PAL60 7 |
3614 | //ATOM_TV_PAL60 7 |
3372 | //ATOM_TV_SECAM 8 |
3615 | //ATOM_TV_SECAM 8 |
3373 | 3616 | ||
3374 | //ucTVSupportedStd definition: |
3617 | //ucTVSupportedStd definition: |
3375 | #define NTSC_SUPPORT 0x1 |
3618 | #define NTSC_SUPPORT 0x1 |
3376 | #define NTSCJ_SUPPORT 0x2 |
3619 | #define NTSCJ_SUPPORT 0x2 |
3377 | 3620 | ||
3378 | #define PAL_SUPPORT 0x4 |
3621 | #define PAL_SUPPORT 0x4 |
3379 | #define PALM_SUPPORT 0x8 |
3622 | #define PALM_SUPPORT 0x8 |
3380 | #define PALCN_SUPPORT 0x10 |
3623 | #define PALCN_SUPPORT 0x10 |
3381 | #define PALN_SUPPORT 0x20 |
3624 | #define PALN_SUPPORT 0x20 |
3382 | #define PAL60_SUPPORT 0x40 |
3625 | #define PAL60_SUPPORT 0x40 |
3383 | #define SECAM_SUPPORT 0x80 |
3626 | #define SECAM_SUPPORT 0x80 |
3384 | 3627 | ||
3385 | #define MAX_SUPPORTED_TV_TIMING 2 |
3628 | #define MAX_SUPPORTED_TV_TIMING 2 |
3386 | 3629 | ||
3387 | typedef struct _ATOM_ANALOG_TV_INFO |
3630 | typedef struct _ATOM_ANALOG_TV_INFO |
3388 | { |
3631 | { |
3389 | ATOM_COMMON_TABLE_HEADER sHeader; |
3632 | ATOM_COMMON_TABLE_HEADER sHeader; |
3390 | UCHAR ucTV_SupportedStandard; |
3633 | UCHAR ucTV_SupportedStandard; |
3391 | UCHAR ucTV_BootUpDefaultStandard; |
3634 | UCHAR ucTV_BootUpDefaultStandard; |
3392 | UCHAR ucExt_TV_ASIC_ID; |
3635 | UCHAR ucExt_TV_ASIC_ID; |
3393 | UCHAR ucExt_TV_ASIC_SlaveAddr; |
3636 | UCHAR ucExt_TV_ASIC_SlaveAddr; |
3394 | /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ |
3637 | /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ |
3395 | ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; |
3638 | ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; |
3396 | }ATOM_ANALOG_TV_INFO; |
3639 | }ATOM_ANALOG_TV_INFO; |
3397 | 3640 | ||
3398 | #define MAX_SUPPORTED_TV_TIMING_V1_2 3 |
3641 | #define MAX_SUPPORTED_TV_TIMING_V1_2 3 |
3399 | 3642 | ||
3400 | typedef struct _ATOM_ANALOG_TV_INFO_V1_2 |
3643 | typedef struct _ATOM_ANALOG_TV_INFO_V1_2 |
3401 | { |
3644 | { |
3402 | ATOM_COMMON_TABLE_HEADER sHeader; |
3645 | ATOM_COMMON_TABLE_HEADER sHeader; |
3403 | UCHAR ucTV_SupportedStandard; |
3646 | UCHAR ucTV_SupportedStandard; |
3404 | UCHAR ucTV_BootUpDefaultStandard; |
3647 | UCHAR ucTV_BootUpDefaultStandard; |
3405 | UCHAR ucExt_TV_ASIC_ID; |
3648 | UCHAR ucExt_TV_ASIC_ID; |
3406 | UCHAR ucExt_TV_ASIC_SlaveAddr; |
3649 | UCHAR ucExt_TV_ASIC_SlaveAddr; |
3407 | ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; |
3650 | ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; |
3408 | }ATOM_ANALOG_TV_INFO_V1_2; |
3651 | }ATOM_ANALOG_TV_INFO_V1_2; |
3409 | 3652 | ||
3410 | typedef struct _ATOM_DPCD_INFO |
3653 | typedef struct _ATOM_DPCD_INFO |
3411 | { |
3654 | { |
3412 | UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 |
3655 | UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 |
3413 | UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane |
3656 | UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane |
3414 | UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP |
3657 | UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP |
3415 | UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) |
3658 | UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) |
3416 | }ATOM_DPCD_INFO; |
3659 | }ATOM_DPCD_INFO; |
3417 | 3660 | ||
3418 | #define ATOM_DPCD_MAX_LANE_MASK 0x1F |
3661 | #define ATOM_DPCD_MAX_LANE_MASK 0x1F |
3419 | 3662 | ||
3420 | /**************************************************************************/ |
3663 | /**************************************************************************/ |
3421 | // VRAM usage and their defintions |
3664 | // VRAM usage and their defintions |
3422 | 3665 | ||
3423 | // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. |
3666 | // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. |
3424 | // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. |
3667 | // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. |
3425 | // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! |
3668 | // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! |
3426 | // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR |
3669 | // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR |
3427 | // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX |
3670 | // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX |
3428 | 3671 | ||
3429 | #ifndef VESA_MEMORY_IN_64K_BLOCK |
3672 | #ifndef VESA_MEMORY_IN_64K_BLOCK |
3430 | #define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) |
3673 | #define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) |
3431 | #endif |
3674 | #endif |
3432 | 3675 | ||
3433 | #define ATOM_EDID_RAW_DATASIZE 256 //In Bytes |
3676 | #define ATOM_EDID_RAW_DATASIZE 256 //In Bytes |
3434 | #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes |
3677 | #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes |
3435 | #define ATOM_HWICON_INFOTABLE_SIZE 32 |
3678 | #define ATOM_HWICON_INFOTABLE_SIZE 32 |
3436 | #define MAX_DTD_MODE_IN_VRAM 6 |
3679 | #define MAX_DTD_MODE_IN_VRAM 6 |
3437 | #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) |
3680 | #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) |
3438 | #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) |
3681 | #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) |
3439 | //20 bytes for Encoder Type and DPCD in STD EDID area |
3682 | //20 bytes for Encoder Type and DPCD in STD EDID area |
3440 | #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) |
3683 | #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) |
3441 | #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) |
3684 | #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) |
3442 | 3685 | ||
3443 | #define ATOM_HWICON1_SURFACE_ADDR 0 |
3686 | #define ATOM_HWICON1_SURFACE_ADDR 0 |
3444 | #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) |
3687 | #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) |
3445 | #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) |
3688 | #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) |
3446 | #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) |
3689 | #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) |
3447 | #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3690 | #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3448 | #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3691 | #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3449 | 3692 | ||
3450 | #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3693 | #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3451 | #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3694 | #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3452 | #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3695 | #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3453 | 3696 | ||
3454 | #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3697 | #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3455 | 3698 | ||
3456 | #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3699 | #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3457 | #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3700 | #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3458 | #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3701 | #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3459 | 3702 | ||
3460 | #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3703 | #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3461 | #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3704 | #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3462 | #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3705 | #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3463 | 3706 | ||
3464 | #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3707 | #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3465 | #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3708 | #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3466 | #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3709 | #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3467 | 3710 | ||
3468 | #define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3711 | #define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3469 | #define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3712 | #define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3470 | #define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3713 | #define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3471 | 3714 | ||
3472 | #define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3715 | #define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3473 | #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3716 | #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3474 | #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3717 | #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3475 | 3718 | ||
3476 | #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3719 | #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3477 | #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3720 | #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3478 | #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3721 | #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3479 | 3722 | ||
3480 | #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3723 | #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3481 | #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3724 | #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3482 | #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3725 | #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3483 | 3726 | ||
3484 | #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3727 | #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3485 | #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3728 | #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3486 | #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3729 | #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3487 | 3730 | ||
3488 | #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3731 | #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3489 | #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3732 | #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
3490 | #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3733 | #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
3491 | 3734 | ||
3492 | #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3735 | #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3493 | 3736 | ||
3494 | #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) |
3737 | #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) |
3495 | #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 |
3738 | #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 |
3496 | 3739 | ||
3497 | //The size below is in Kb! |
3740 | //The size below is in Kb! |
3498 | #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) |
3741 | #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) |
3499 | 3742 | ||
3500 | #define ATOM_VRAM_RESERVE_V2_SIZE 32 |
3743 | #define ATOM_VRAM_RESERVE_V2_SIZE 32 |
3501 | 3744 | ||
3502 | #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L |
3745 | #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L |
3503 | #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 |
3746 | #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 |
3504 | #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 |
3747 | #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 |
3505 | #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 |
3748 | #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 |
3506 | 3749 | ||
3507 | /***********************************************************************************/ |
3750 | /***********************************************************************************/ |
3508 | // Structure used in VRAM_UsageByFirmwareTable |
3751 | // Structure used in VRAM_UsageByFirmwareTable |
3509 | // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm |
3752 | // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm |
3510 | // at running time. |
3753 | // at running time. |
3511 | // note2: From RV770, the memory is more than 32bit addressable, so we will change |
3754 | // note2: From RV770, the memory is more than 32bit addressable, so we will change |
3512 | // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains |
3755 | // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains |
3513 | // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware |
3756 | // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware |
3514 | // (in offset to start of memory address) is KB aligned instead of byte aligend. |
3757 | // (in offset to start of memory address) is KB aligned instead of byte aligend. |
3515 | /***********************************************************************************/ |
3758 | /***********************************************************************************/ |
3516 | // Note3: |
3759 | // Note3: |
3517 | /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, |
3760 | /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, |
3518 | for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: |
3761 | for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: |
3519 | 3762 | ||
3520 | If (ulStartAddrUsedByFirmware!=0) |
3763 | If (ulStartAddrUsedByFirmware!=0) |
3521 | FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; |
3764 | FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; |
3522 | Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose |
3765 | Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose |
3523 | else //Non VGA case |
3766 | else //Non VGA case |
3524 | if (FB_Size<=2Gb) |
3767 | if (FB_Size<=2Gb) |
3525 | FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; |
3768 | FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; |
3526 | else |
3769 | else |
3527 | FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB |
3770 | FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB |
3528 | 3771 | ||
3529 | CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ |
3772 | CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ |
- | 3773 | ||
3530 | 3774 | /***********************************************************************************/ |
|
3531 | #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 |
3775 | #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 |
3532 | 3776 | ||
3533 | typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO |
3777 | typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO |
3534 | { |
3778 | { |
3535 | ULONG ulStartAddrUsedByFirmware; |
3779 | ULONG ulStartAddrUsedByFirmware; |
3536 | USHORT usFirmwareUseInKb; |
3780 | USHORT usFirmwareUseInKb; |
3537 | USHORT usReserved; |
3781 | USHORT usReserved; |
3538 | }ATOM_FIRMWARE_VRAM_RESERVE_INFO; |
3782 | }ATOM_FIRMWARE_VRAM_RESERVE_INFO; |
3539 | 3783 | ||
3540 | typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE |
3784 | typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE |
3541 | { |
3785 | { |
3542 | ATOM_COMMON_TABLE_HEADER sHeader; |
3786 | ATOM_COMMON_TABLE_HEADER sHeader; |
3543 | ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; |
3787 | ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; |
3544 | }ATOM_VRAM_USAGE_BY_FIRMWARE; |
3788 | }ATOM_VRAM_USAGE_BY_FIRMWARE; |
3545 | 3789 | ||
3546 | // change verion to 1.5, when allow driver to allocate the vram area for command table access. |
3790 | // change verion to 1.5, when allow driver to allocate the vram area for command table access. |
3547 | typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 |
3791 | typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 |
3548 | { |
3792 | { |
3549 | ULONG ulStartAddrUsedByFirmware; |
3793 | ULONG ulStartAddrUsedByFirmware; |
3550 | USHORT usFirmwareUseInKb; |
3794 | USHORT usFirmwareUseInKb; |
3551 | USHORT usFBUsedByDrvInKb; |
3795 | USHORT usFBUsedByDrvInKb; |
3552 | }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; |
3796 | }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; |
3553 | 3797 | ||
3554 | typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 |
3798 | typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 |
3555 | { |
3799 | { |
3556 | ATOM_COMMON_TABLE_HEADER sHeader; |
3800 | ATOM_COMMON_TABLE_HEADER sHeader; |
3557 | ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; |
3801 | ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; |
3558 | }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; |
3802 | }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; |
3559 | 3803 | ||
3560 | /****************************************************************************/ |
3804 | /****************************************************************************/ |
3561 | // Structure used in GPIO_Pin_LUTTable |
3805 | // Structure used in GPIO_Pin_LUTTable |
3562 | /****************************************************************************/ |
3806 | /****************************************************************************/ |
3563 | typedef struct _ATOM_GPIO_PIN_ASSIGNMENT |
3807 | typedef struct _ATOM_GPIO_PIN_ASSIGNMENT |
3564 | { |
3808 | { |
3565 | USHORT usGpioPin_AIndex; |
3809 | USHORT usGpioPin_AIndex; |
3566 | UCHAR ucGpioPinBitShift; |
3810 | UCHAR ucGpioPinBitShift; |
3567 | UCHAR ucGPIO_ID; |
3811 | UCHAR ucGPIO_ID; |
3568 | }ATOM_GPIO_PIN_ASSIGNMENT; |
3812 | }ATOM_GPIO_PIN_ASSIGNMENT; |
3569 | 3813 | ||
3570 | typedef struct _ATOM_GPIO_PIN_LUT |
3814 | typedef struct _ATOM_GPIO_PIN_LUT |
3571 | { |
3815 | { |
3572 | ATOM_COMMON_TABLE_HEADER sHeader; |
3816 | ATOM_COMMON_TABLE_HEADER sHeader; |
3573 | ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; |
3817 | ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; |
3574 | }ATOM_GPIO_PIN_LUT; |
3818 | }ATOM_GPIO_PIN_LUT; |
3575 | 3819 | ||
3576 | /****************************************************************************/ |
3820 | /****************************************************************************/ |
3577 | // Structure used in ComponentVideoInfoTable |
3821 | // Structure used in ComponentVideoInfoTable |
3578 | /****************************************************************************/ |
3822 | /****************************************************************************/ |
3579 | #define GPIO_PIN_ACTIVE_HIGH 0x1 |
3823 | #define GPIO_PIN_ACTIVE_HIGH 0x1 |
3580 | 3824 | ||
3581 | #define MAX_SUPPORTED_CV_STANDARDS 5 |
3825 | #define MAX_SUPPORTED_CV_STANDARDS 5 |
3582 | 3826 | ||
3583 | // definitions for ATOM_D_INFO.ucSettings |
3827 | // definitions for ATOM_D_INFO.ucSettings |
3584 | #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] |
3828 | #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] |
3585 | #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out |
3829 | #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out |
3586 | #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] |
3830 | #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] |
3587 | 3831 | ||
3588 | typedef struct _ATOM_GPIO_INFO |
3832 | typedef struct _ATOM_GPIO_INFO |
3589 | { |
3833 | { |
3590 | USHORT usAOffset; |
3834 | USHORT usAOffset; |
3591 | UCHAR ucSettings; |
3835 | UCHAR ucSettings; |
3592 | UCHAR ucReserved; |
3836 | UCHAR ucReserved; |
3593 | }ATOM_GPIO_INFO; |
3837 | }ATOM_GPIO_INFO; |
3594 | 3838 | ||
3595 | // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) |
3839 | // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) |
3596 | #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 |
3840 | #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 |
3597 | 3841 | ||
3598 | // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i |
3842 | // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i |
3599 | #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; |
3843 | #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; |
3600 | #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] |
3844 | #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] |
3601 | 3845 | ||
3602 | // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode |
3846 | // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode |
3603 | //Line 3 out put 5V. |
3847 | //Line 3 out put 5V. |
3604 | #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 |
3848 | #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 |
3605 | #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 |
3849 | #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 |
3606 | #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 |
3850 | #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 |
3607 | 3851 | ||
3608 | //Line 3 out put 2.2V |
3852 | //Line 3 out put 2.2V |
3609 | #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box |
3853 | #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box |
3610 | #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box |
3854 | #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box |
3611 | #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 |
3855 | #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 |
3612 | 3856 | ||
3613 | //Line 3 out put 0V |
3857 | //Line 3 out put 0V |
3614 | #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 |
3858 | #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 |
3615 | #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 |
3859 | #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 |
3616 | #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 |
3860 | #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 |
3617 | 3861 | ||
3618 | #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] |
3862 | #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] |
3619 | 3863 | ||
3620 | #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 |
3864 | #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 |
3621 | 3865 | ||
3622 | //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. |
3866 | //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. |
3623 | #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. |
3867 | #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. |
3624 | #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. |
3868 | #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. |
3625 | 3869 | ||
3626 | 3870 | ||
3627 | typedef struct _ATOM_COMPONENT_VIDEO_INFO |
3871 | typedef struct _ATOM_COMPONENT_VIDEO_INFO |
3628 | { |
3872 | { |
3629 | ATOM_COMMON_TABLE_HEADER sHeader; |
3873 | ATOM_COMMON_TABLE_HEADER sHeader; |
3630 | USHORT usMask_PinRegisterIndex; |
3874 | USHORT usMask_PinRegisterIndex; |
3631 | USHORT usEN_PinRegisterIndex; |
3875 | USHORT usEN_PinRegisterIndex; |
3632 | USHORT usY_PinRegisterIndex; |
3876 | USHORT usY_PinRegisterIndex; |
3633 | USHORT usA_PinRegisterIndex; |
3877 | USHORT usA_PinRegisterIndex; |
3634 | UCHAR ucBitShift; |
3878 | UCHAR ucBitShift; |
3635 | UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low |
3879 | UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low |
3636 | ATOM_DTD_FORMAT sReserved; // must be zeroed out |
3880 | ATOM_DTD_FORMAT sReserved; // must be zeroed out |
3637 | UCHAR ucMiscInfo; |
3881 | UCHAR ucMiscInfo; |
3638 | UCHAR uc480i; |
3882 | UCHAR uc480i; |
3639 | UCHAR uc480p; |
3883 | UCHAR uc480p; |
3640 | UCHAR uc720p; |
3884 | UCHAR uc720p; |
3641 | UCHAR uc1080i; |
3885 | UCHAR uc1080i; |
3642 | UCHAR ucLetterBoxMode; |
3886 | UCHAR ucLetterBoxMode; |
3643 | UCHAR ucReserved[3]; |
3887 | UCHAR ucReserved[3]; |
3644 | UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector |
3888 | UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector |
3645 | ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; |
3889 | ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; |
3646 | ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; |
3890 | ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; |
3647 | }ATOM_COMPONENT_VIDEO_INFO; |
3891 | }ATOM_COMPONENT_VIDEO_INFO; |
3648 | 3892 | ||
3649 | //ucTableFormatRevision=2 |
3893 | //ucTableFormatRevision=2 |
3650 | //ucTableContentRevision=1 |
3894 | //ucTableContentRevision=1 |
3651 | typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 |
3895 | typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 |
3652 | { |
3896 | { |
3653 | ATOM_COMMON_TABLE_HEADER sHeader; |
3897 | ATOM_COMMON_TABLE_HEADER sHeader; |
3654 | UCHAR ucMiscInfo; |
3898 | UCHAR ucMiscInfo; |
3655 | UCHAR uc480i; |
3899 | UCHAR uc480i; |
3656 | UCHAR uc480p; |
3900 | UCHAR uc480p; |
3657 | UCHAR uc720p; |
3901 | UCHAR uc720p; |
3658 | UCHAR uc1080i; |
3902 | UCHAR uc1080i; |
3659 | UCHAR ucReserved; |
3903 | UCHAR ucReserved; |
3660 | UCHAR ucLetterBoxMode; |
3904 | UCHAR ucLetterBoxMode; |
3661 | UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector |
3905 | UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector |
3662 | ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; |
3906 | ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; |
3663 | ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; |
3907 | ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; |
3664 | }ATOM_COMPONENT_VIDEO_INFO_V21; |
3908 | }ATOM_COMPONENT_VIDEO_INFO_V21; |
3665 | 3909 | ||
3666 | #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 |
3910 | #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 |
3667 | 3911 | ||
3668 | /****************************************************************************/ |
3912 | /****************************************************************************/ |
3669 | // Structure used in object_InfoTable |
3913 | // Structure used in object_InfoTable |
3670 | /****************************************************************************/ |
3914 | /****************************************************************************/ |
3671 | typedef struct _ATOM_OBJECT_HEADER |
3915 | typedef struct _ATOM_OBJECT_HEADER |
3672 | { |
3916 | { |
3673 | ATOM_COMMON_TABLE_HEADER sHeader; |
3917 | ATOM_COMMON_TABLE_HEADER sHeader; |
3674 | USHORT usDeviceSupport; |
3918 | USHORT usDeviceSupport; |
3675 | USHORT usConnectorObjectTableOffset; |
3919 | USHORT usConnectorObjectTableOffset; |
3676 | USHORT usRouterObjectTableOffset; |
3920 | USHORT usRouterObjectTableOffset; |
3677 | USHORT usEncoderObjectTableOffset; |
3921 | USHORT usEncoderObjectTableOffset; |
3678 | USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. |
3922 | USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. |
3679 | USHORT usDisplayPathTableOffset; |
3923 | USHORT usDisplayPathTableOffset; |
3680 | }ATOM_OBJECT_HEADER; |
3924 | }ATOM_OBJECT_HEADER; |
3681 | 3925 | ||
3682 | typedef struct _ATOM_OBJECT_HEADER_V3 |
3926 | typedef struct _ATOM_OBJECT_HEADER_V3 |
3683 | { |
3927 | { |
3684 | ATOM_COMMON_TABLE_HEADER sHeader; |
3928 | ATOM_COMMON_TABLE_HEADER sHeader; |
3685 | USHORT usDeviceSupport; |
3929 | USHORT usDeviceSupport; |
3686 | USHORT usConnectorObjectTableOffset; |
3930 | USHORT usConnectorObjectTableOffset; |
3687 | USHORT usRouterObjectTableOffset; |
3931 | USHORT usRouterObjectTableOffset; |
3688 | USHORT usEncoderObjectTableOffset; |
3932 | USHORT usEncoderObjectTableOffset; |
3689 | USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. |
3933 | USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. |
3690 | USHORT usDisplayPathTableOffset; |
3934 | USHORT usDisplayPathTableOffset; |
3691 | USHORT usMiscObjectTableOffset; |
3935 | USHORT usMiscObjectTableOffset; |
3692 | }ATOM_OBJECT_HEADER_V3; |
3936 | }ATOM_OBJECT_HEADER_V3; |
3693 | 3937 | ||
3694 | typedef struct _ATOM_DISPLAY_OBJECT_PATH |
3938 | typedef struct _ATOM_DISPLAY_OBJECT_PATH |
3695 | { |
3939 | { |
3696 | USHORT usDeviceTag; //supported device |
3940 | USHORT usDeviceTag; //supported device |
3697 | USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH |
3941 | USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH |
3698 | USHORT usConnObjectId; //Connector Object ID |
3942 | USHORT usConnObjectId; //Connector Object ID |
3699 | USHORT usGPUObjectId; //GPU ID |
3943 | USHORT usGPUObjectId; //GPU ID |
3700 | USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. |
3944 | USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. |
3701 | }ATOM_DISPLAY_OBJECT_PATH; |
3945 | }ATOM_DISPLAY_OBJECT_PATH; |
3702 | 3946 | ||
3703 | typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH |
3947 | typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH |
3704 | { |
3948 | { |
3705 | USHORT usDeviceTag; //supported device |
3949 | USHORT usDeviceTag; //supported device |
3706 | USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH |
3950 | USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH |
3707 | USHORT usConnObjectId; //Connector Object ID |
3951 | USHORT usConnObjectId; //Connector Object ID |
3708 | USHORT usGPUObjectId; //GPU ID |
3952 | USHORT usGPUObjectId; //GPU ID |
3709 | USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder |
3953 | USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder |
3710 | }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; |
3954 | }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; |
3711 | 3955 | ||
3712 | typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE |
3956 | typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE |
3713 | { |
3957 | { |
3714 | UCHAR ucNumOfDispPath; |
3958 | UCHAR ucNumOfDispPath; |
3715 | UCHAR ucVersion; |
3959 | UCHAR ucVersion; |
3716 | UCHAR ucPadding[2]; |
3960 | UCHAR ucPadding[2]; |
3717 | ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; |
3961 | ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; |
3718 | }ATOM_DISPLAY_OBJECT_PATH_TABLE; |
3962 | }ATOM_DISPLAY_OBJECT_PATH_TABLE; |
3719 | 3963 | ||
3720 | 3964 | ||
3721 | typedef struct _ATOM_OBJECT //each object has this structure |
3965 | typedef struct _ATOM_OBJECT //each object has this structure |
3722 | { |
3966 | { |
3723 | USHORT usObjectID; |
3967 | USHORT usObjectID; |
3724 | USHORT usSrcDstTableOffset; |
3968 | USHORT usSrcDstTableOffset; |
3725 | USHORT usRecordOffset; //this pointing to a bunch of records defined below |
3969 | USHORT usRecordOffset; //this pointing to a bunch of records defined below |
3726 | USHORT usReserved; |
3970 | USHORT usReserved; |
3727 | }ATOM_OBJECT; |
3971 | }ATOM_OBJECT; |
3728 | 3972 | ||
3729 | typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure |
3973 | typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure |
3730 | { |
3974 | { |
3731 | UCHAR ucNumberOfObjects; |
3975 | UCHAR ucNumberOfObjects; |
3732 | UCHAR ucPadding[3]; |
3976 | UCHAR ucPadding[3]; |
3733 | ATOM_OBJECT asObjects[1]; |
3977 | ATOM_OBJECT asObjects[1]; |
3734 | }ATOM_OBJECT_TABLE; |
3978 | }ATOM_OBJECT_TABLE; |
3735 | 3979 | ||
3736 | typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure |
3980 | typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure |
3737 | { |
3981 | { |
3738 | UCHAR ucNumberOfSrc; |
3982 | UCHAR ucNumberOfSrc; |
3739 | USHORT usSrcObjectID[1]; |
3983 | USHORT usSrcObjectID[1]; |
3740 | UCHAR ucNumberOfDst; |
3984 | UCHAR ucNumberOfDst; |
3741 | USHORT usDstObjectID[1]; |
3985 | USHORT usDstObjectID[1]; |
3742 | }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; |
3986 | }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; |
3743 | 3987 | ||
3744 | 3988 | ||
3745 | //Two definitions below are for OPM on MXM module designs |
3989 | //Two definitions below are for OPM on MXM module designs |
3746 | 3990 | ||
3747 | #define EXT_HPDPIN_LUTINDEX_0 0 |
3991 | #define EXT_HPDPIN_LUTINDEX_0 0 |
3748 | #define EXT_HPDPIN_LUTINDEX_1 1 |
3992 | #define EXT_HPDPIN_LUTINDEX_1 1 |
3749 | #define EXT_HPDPIN_LUTINDEX_2 2 |
3993 | #define EXT_HPDPIN_LUTINDEX_2 2 |
3750 | #define EXT_HPDPIN_LUTINDEX_3 3 |
3994 | #define EXT_HPDPIN_LUTINDEX_3 3 |
3751 | #define EXT_HPDPIN_LUTINDEX_4 4 |
3995 | #define EXT_HPDPIN_LUTINDEX_4 4 |
3752 | #define EXT_HPDPIN_LUTINDEX_5 5 |
3996 | #define EXT_HPDPIN_LUTINDEX_5 5 |
3753 | #define EXT_HPDPIN_LUTINDEX_6 6 |
3997 | #define EXT_HPDPIN_LUTINDEX_6 6 |
3754 | #define EXT_HPDPIN_LUTINDEX_7 7 |
3998 | #define EXT_HPDPIN_LUTINDEX_7 7 |
3755 | #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) |
3999 | #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) |
3756 | 4000 | ||
3757 | #define EXT_AUXDDC_LUTINDEX_0 0 |
4001 | #define EXT_AUXDDC_LUTINDEX_0 0 |
3758 | #define EXT_AUXDDC_LUTINDEX_1 1 |
4002 | #define EXT_AUXDDC_LUTINDEX_1 1 |
3759 | #define EXT_AUXDDC_LUTINDEX_2 2 |
4003 | #define EXT_AUXDDC_LUTINDEX_2 2 |
3760 | #define EXT_AUXDDC_LUTINDEX_3 3 |
4004 | #define EXT_AUXDDC_LUTINDEX_3 3 |
3761 | #define EXT_AUXDDC_LUTINDEX_4 4 |
4005 | #define EXT_AUXDDC_LUTINDEX_4 4 |
3762 | #define EXT_AUXDDC_LUTINDEX_5 5 |
4006 | #define EXT_AUXDDC_LUTINDEX_5 5 |
3763 | #define EXT_AUXDDC_LUTINDEX_6 6 |
4007 | #define EXT_AUXDDC_LUTINDEX_6 6 |
3764 | #define EXT_AUXDDC_LUTINDEX_7 7 |
4008 | #define EXT_AUXDDC_LUTINDEX_7 7 |
3765 | #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) |
4009 | #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) |
3766 | 4010 | ||
3767 | //ucChannelMapping are defined as following |
4011 | //ucChannelMapping are defined as following |
3768 | //for DP connector, eDP, DP to VGA/LVDS |
4012 | //for DP connector, eDP, DP to VGA/LVDS |
3769 | //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
4013 | //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
3770 | //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
4014 | //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
3771 | //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
4015 | //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
3772 | //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
4016 | //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
3773 | typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING |
4017 | typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING |
3774 | { |
4018 | { |
3775 | #if ATOM_BIG_ENDIAN |
4019 | #if ATOM_BIG_ENDIAN |
3776 | UCHAR ucDP_Lane3_Source:2; |
4020 | UCHAR ucDP_Lane3_Source:2; |
3777 | UCHAR ucDP_Lane2_Source:2; |
4021 | UCHAR ucDP_Lane2_Source:2; |
3778 | UCHAR ucDP_Lane1_Source:2; |
4022 | UCHAR ucDP_Lane1_Source:2; |
3779 | UCHAR ucDP_Lane0_Source:2; |
4023 | UCHAR ucDP_Lane0_Source:2; |
3780 | #else |
4024 | #else |
3781 | UCHAR ucDP_Lane0_Source:2; |
4025 | UCHAR ucDP_Lane0_Source:2; |
3782 | UCHAR ucDP_Lane1_Source:2; |
4026 | UCHAR ucDP_Lane1_Source:2; |
3783 | UCHAR ucDP_Lane2_Source:2; |
4027 | UCHAR ucDP_Lane2_Source:2; |
3784 | UCHAR ucDP_Lane3_Source:2; |
4028 | UCHAR ucDP_Lane3_Source:2; |
3785 | #endif |
4029 | #endif |
3786 | }ATOM_DP_CONN_CHANNEL_MAPPING; |
4030 | }ATOM_DP_CONN_CHANNEL_MAPPING; |
3787 | 4031 | ||
3788 | //for DVI/HDMI, in dual link case, both links have to have same mapping. |
4032 | //for DVI/HDMI, in dual link case, both links have to have same mapping. |
3789 | //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
4033 | //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
3790 | //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
4034 | //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
3791 | //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
4035 | //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
3792 | //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
4036 | //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
3793 | typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING |
4037 | typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING |
3794 | { |
4038 | { |
3795 | #if ATOM_BIG_ENDIAN |
4039 | #if ATOM_BIG_ENDIAN |
3796 | UCHAR ucDVI_CLK_Source:2; |
4040 | UCHAR ucDVI_CLK_Source:2; |
3797 | UCHAR ucDVI_DATA0_Source:2; |
4041 | UCHAR ucDVI_DATA0_Source:2; |
3798 | UCHAR ucDVI_DATA1_Source:2; |
4042 | UCHAR ucDVI_DATA1_Source:2; |
3799 | UCHAR ucDVI_DATA2_Source:2; |
4043 | UCHAR ucDVI_DATA2_Source:2; |
3800 | #else |
4044 | #else |
3801 | UCHAR ucDVI_DATA2_Source:2; |
4045 | UCHAR ucDVI_DATA2_Source:2; |
3802 | UCHAR ucDVI_DATA1_Source:2; |
4046 | UCHAR ucDVI_DATA1_Source:2; |
3803 | UCHAR ucDVI_DATA0_Source:2; |
4047 | UCHAR ucDVI_DATA0_Source:2; |
3804 | UCHAR ucDVI_CLK_Source:2; |
4048 | UCHAR ucDVI_CLK_Source:2; |
3805 | #endif |
4049 | #endif |
3806 | }ATOM_DVI_CONN_CHANNEL_MAPPING; |
4050 | }ATOM_DVI_CONN_CHANNEL_MAPPING; |
3807 | 4051 | ||
3808 | typedef struct _EXT_DISPLAY_PATH |
4052 | typedef struct _EXT_DISPLAY_PATH |
3809 | { |
4053 | { |
3810 | USHORT usDeviceTag; //A bit vector to show what devices are supported |
4054 | USHORT usDeviceTag; //A bit vector to show what devices are supported |
3811 | USHORT usDeviceACPIEnum; //16bit device ACPI id. |
4055 | USHORT usDeviceACPIEnum; //16bit device ACPI id. |
3812 | USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions |
4056 | USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions |
3813 | UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT |
4057 | UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT |
3814 | UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT |
4058 | UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT |
3815 | USHORT usExtEncoderObjId; //external encoder object id |
4059 | USHORT usExtEncoderObjId; //external encoder object id |
3816 | union{ |
4060 | union{ |
3817 | UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping |
4061 | UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping |
3818 | ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; |
4062 | ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; |
3819 | ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; |
4063 | ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; |
3820 | }; |
4064 | }; |
- | 4065 | UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted |
|
3821 | UCHAR ucReserved; |
4066 | USHORT usCaps; |
3822 | USHORT usReserved[2]; |
4067 | USHORT usReserved; |
3823 | }EXT_DISPLAY_PATH; |
4068 | }EXT_DISPLAY_PATH; |
3824 | 4069 | ||
3825 | #define NUMBER_OF_UCHAR_FOR_GUID 16 |
4070 | #define NUMBER_OF_UCHAR_FOR_GUID 16 |
3826 | #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 |
4071 | #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 |
- | 4072 | ||
- | 4073 | //usCaps |
|
- | 4074 | #define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01 |
|
3827 | 4075 | ||
3828 | typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO |
4076 | typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO |
3829 | { |
4077 | { |
3830 | ATOM_COMMON_TABLE_HEADER sHeader; |
4078 | ATOM_COMMON_TABLE_HEADER sHeader; |
3831 | UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string |
4079 | UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string |
3832 | EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. |
4080 | EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. |
3833 | UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. |
4081 | UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. |
3834 | UCHAR uc3DStereoPinId; // use for eDP panel |
4082 | UCHAR uc3DStereoPinId; // use for eDP panel |
- | 4083 | UCHAR ucRemoteDisplayConfig; |
|
- | 4084 | UCHAR uceDPToLVDSRxId; |
|
3835 | UCHAR Reserved [6]; // for potential expansion |
4085 | UCHAR Reserved[4]; // for potential expansion |
3836 | }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; |
4086 | }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; |
3837 | 4087 | ||
3838 | //Related definitions, all records are different but they have a commond header |
4088 | //Related definitions, all records are different but they have a commond header |
3839 | typedef struct _ATOM_COMMON_RECORD_HEADER |
4089 | typedef struct _ATOM_COMMON_RECORD_HEADER |
3840 | { |
4090 | { |
3841 | UCHAR ucRecordType; //An emun to indicate the record type |
4091 | UCHAR ucRecordType; //An emun to indicate the record type |
3842 | UCHAR ucRecordSize; //The size of the whole record in byte |
4092 | UCHAR ucRecordSize; //The size of the whole record in byte |
3843 | }ATOM_COMMON_RECORD_HEADER; |
4093 | }ATOM_COMMON_RECORD_HEADER; |
3844 | 4094 | ||
3845 | 4095 | ||
3846 | #define ATOM_I2C_RECORD_TYPE 1 |
4096 | #define ATOM_I2C_RECORD_TYPE 1 |
3847 | #define ATOM_HPD_INT_RECORD_TYPE 2 |
4097 | #define ATOM_HPD_INT_RECORD_TYPE 2 |
3848 | #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 |
4098 | #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 |
3849 | #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 |
4099 | #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 |
3850 | #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE |
4100 | #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE |
3851 | #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE |
4101 | #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE |
3852 | #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 |
4102 | #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 |
3853 | #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE |
4103 | #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE |
3854 | #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 |
4104 | #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 |
3855 | #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 |
4105 | #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 |
3856 | #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 |
4106 | #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 |
3857 | #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 |
4107 | #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 |
3858 | #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 |
4108 | #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 |
3859 | #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 |
4109 | #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 |
3860 | #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 |
4110 | #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 |
3861 | #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table |
4111 | #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table |
3862 | #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table |
4112 | #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table |
3863 | #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record |
4113 | #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record |
3864 | #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 |
4114 | #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 |
3865 | #define ATOM_ENCODER_CAP_RECORD_TYPE 20 |
4115 | #define ATOM_ENCODER_CAP_RECORD_TYPE 20 |
3866 | 4116 | ||
3867 | 4117 | ||
3868 | //Must be updated when new record type is added,equal to that record definition! |
4118 | //Must be updated when new record type is added,equal to that record definition! |
3869 | #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE |
4119 | #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE |
3870 | 4120 | ||
3871 | typedef struct _ATOM_I2C_RECORD |
4121 | typedef struct _ATOM_I2C_RECORD |
3872 | { |
4122 | { |
3873 | ATOM_COMMON_RECORD_HEADER sheader; |
4123 | ATOM_COMMON_RECORD_HEADER sheader; |
3874 | ATOM_I2C_ID_CONFIG sucI2cId; |
4124 | ATOM_I2C_ID_CONFIG sucI2cId; |
3875 | UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC |
4125 | UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC |
3876 | }ATOM_I2C_RECORD; |
4126 | }ATOM_I2C_RECORD; |
3877 | 4127 | ||
3878 | typedef struct _ATOM_HPD_INT_RECORD |
4128 | typedef struct _ATOM_HPD_INT_RECORD |
3879 | { |
4129 | { |
3880 | ATOM_COMMON_RECORD_HEADER sheader; |
4130 | ATOM_COMMON_RECORD_HEADER sheader; |
3881 | UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info |
4131 | UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info |
3882 | UCHAR ucPlugged_PinState; |
4132 | UCHAR ucPlugged_PinState; |
3883 | }ATOM_HPD_INT_RECORD; |
4133 | }ATOM_HPD_INT_RECORD; |
3884 | 4134 | ||
3885 | 4135 | ||
3886 | typedef struct _ATOM_OUTPUT_PROTECTION_RECORD |
4136 | typedef struct _ATOM_OUTPUT_PROTECTION_RECORD |
3887 | { |
4137 | { |
3888 | ATOM_COMMON_RECORD_HEADER sheader; |
4138 | ATOM_COMMON_RECORD_HEADER sheader; |
3889 | UCHAR ucProtectionFlag; |
4139 | UCHAR ucProtectionFlag; |
3890 | UCHAR ucReserved; |
4140 | UCHAR ucReserved; |
3891 | }ATOM_OUTPUT_PROTECTION_RECORD; |
4141 | }ATOM_OUTPUT_PROTECTION_RECORD; |
3892 | 4142 | ||
3893 | typedef struct _ATOM_CONNECTOR_DEVICE_TAG |
4143 | typedef struct _ATOM_CONNECTOR_DEVICE_TAG |
3894 | { |
4144 | { |
3895 | ULONG ulACPIDeviceEnum; //Reserved for now |
4145 | ULONG ulACPIDeviceEnum; //Reserved for now |
3896 | USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" |
4146 | USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" |
3897 | USHORT usPadding; |
4147 | USHORT usPadding; |
3898 | }ATOM_CONNECTOR_DEVICE_TAG; |
4148 | }ATOM_CONNECTOR_DEVICE_TAG; |
3899 | 4149 | ||
3900 | typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD |
4150 | typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD |
3901 | { |
4151 | { |
3902 | ATOM_COMMON_RECORD_HEADER sheader; |
4152 | ATOM_COMMON_RECORD_HEADER sheader; |
3903 | UCHAR ucNumberOfDevice; |
4153 | UCHAR ucNumberOfDevice; |
3904 | UCHAR ucReserved; |
4154 | UCHAR ucReserved; |
3905 | ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation |
4155 | ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation |
3906 | }ATOM_CONNECTOR_DEVICE_TAG_RECORD; |
4156 | }ATOM_CONNECTOR_DEVICE_TAG_RECORD; |
3907 | 4157 | ||
3908 | 4158 | ||
3909 | typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD |
4159 | typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD |
3910 | { |
4160 | { |
3911 | ATOM_COMMON_RECORD_HEADER sheader; |
4161 | ATOM_COMMON_RECORD_HEADER sheader; |
3912 | UCHAR ucConfigGPIOID; |
4162 | UCHAR ucConfigGPIOID; |
3913 | UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in |
4163 | UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in |
3914 | UCHAR ucFlowinGPIPID; |
4164 | UCHAR ucFlowinGPIPID; |
3915 | UCHAR ucExtInGPIPID; |
4165 | UCHAR ucExtInGPIPID; |
3916 | }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; |
4166 | }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; |
3917 | 4167 | ||
3918 | typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD |
4168 | typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD |
3919 | { |
4169 | { |
3920 | ATOM_COMMON_RECORD_HEADER sheader; |
4170 | ATOM_COMMON_RECORD_HEADER sheader; |
3921 | UCHAR ucCTL1GPIO_ID; |
4171 | UCHAR ucCTL1GPIO_ID; |
3922 | UCHAR ucCTL1GPIOState; //Set to 1 when it's active high |
4172 | UCHAR ucCTL1GPIOState; //Set to 1 when it's active high |
3923 | UCHAR ucCTL2GPIO_ID; |
4173 | UCHAR ucCTL2GPIO_ID; |
3924 | UCHAR ucCTL2GPIOState; //Set to 1 when it's active high |
4174 | UCHAR ucCTL2GPIOState; //Set to 1 when it's active high |
3925 | UCHAR ucCTL3GPIO_ID; |
4175 | UCHAR ucCTL3GPIO_ID; |
3926 | UCHAR ucCTL3GPIOState; //Set to 1 when it's active high |
4176 | UCHAR ucCTL3GPIOState; //Set to 1 when it's active high |
3927 | UCHAR ucCTLFPGA_IN_ID; |
4177 | UCHAR ucCTLFPGA_IN_ID; |
3928 | UCHAR ucPadding[3]; |
4178 | UCHAR ucPadding[3]; |
3929 | }ATOM_ENCODER_FPGA_CONTROL_RECORD; |
4179 | }ATOM_ENCODER_FPGA_CONTROL_RECORD; |
3930 | 4180 | ||
3931 | typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD |
4181 | typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD |
3932 | { |
4182 | { |
3933 | ATOM_COMMON_RECORD_HEADER sheader; |
4183 | ATOM_COMMON_RECORD_HEADER sheader; |
3934 | UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info |
4184 | UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info |
3935 | UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected |
4185 | UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected |
3936 | }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; |
4186 | }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; |
3937 | 4187 | ||
3938 | typedef struct _ATOM_JTAG_RECORD |
4188 | typedef struct _ATOM_JTAG_RECORD |
3939 | { |
4189 | { |
3940 | ATOM_COMMON_RECORD_HEADER sheader; |
4190 | ATOM_COMMON_RECORD_HEADER sheader; |
3941 | UCHAR ucTMSGPIO_ID; |
4191 | UCHAR ucTMSGPIO_ID; |
3942 | UCHAR ucTMSGPIOState; //Set to 1 when it's active high |
4192 | UCHAR ucTMSGPIOState; //Set to 1 when it's active high |
3943 | UCHAR ucTCKGPIO_ID; |
4193 | UCHAR ucTCKGPIO_ID; |
3944 | UCHAR ucTCKGPIOState; //Set to 1 when it's active high |
4194 | UCHAR ucTCKGPIOState; //Set to 1 when it's active high |
3945 | UCHAR ucTDOGPIO_ID; |
4195 | UCHAR ucTDOGPIO_ID; |
3946 | UCHAR ucTDOGPIOState; //Set to 1 when it's active high |
4196 | UCHAR ucTDOGPIOState; //Set to 1 when it's active high |
3947 | UCHAR ucTDIGPIO_ID; |
4197 | UCHAR ucTDIGPIO_ID; |
3948 | UCHAR ucTDIGPIOState; //Set to 1 when it's active high |
4198 | UCHAR ucTDIGPIOState; //Set to 1 when it's active high |
3949 | UCHAR ucPadding[2]; |
4199 | UCHAR ucPadding[2]; |
3950 | }ATOM_JTAG_RECORD; |
4200 | }ATOM_JTAG_RECORD; |
3951 | 4201 | ||
3952 | 4202 | ||
3953 | //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually |
4203 | //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually |
3954 | typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR |
4204 | typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR |
3955 | { |
4205 | { |
3956 | UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table |
4206 | UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table |
3957 | UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin |
4207 | UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin |
3958 | }ATOM_GPIO_PIN_CONTROL_PAIR; |
4208 | }ATOM_GPIO_PIN_CONTROL_PAIR; |
3959 | 4209 | ||
3960 | typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD |
4210 | typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD |
3961 | { |
4211 | { |
3962 | ATOM_COMMON_RECORD_HEADER sheader; |
4212 | ATOM_COMMON_RECORD_HEADER sheader; |
3963 | UCHAR ucFlags; // Future expnadibility |
4213 | UCHAR ucFlags; // Future expnadibility |
3964 | UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object |
4214 | UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object |
3965 | ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins |
4215 | ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins |
3966 | }ATOM_OBJECT_GPIO_CNTL_RECORD; |
4216 | }ATOM_OBJECT_GPIO_CNTL_RECORD; |
3967 | 4217 | ||
3968 | //Definitions for GPIO pin state |
4218 | //Definitions for GPIO pin state |
3969 | #define GPIO_PIN_TYPE_INPUT 0x00 |
4219 | #define GPIO_PIN_TYPE_INPUT 0x00 |
3970 | #define GPIO_PIN_TYPE_OUTPUT 0x10 |
4220 | #define GPIO_PIN_TYPE_OUTPUT 0x10 |
3971 | #define GPIO_PIN_TYPE_HW_CONTROL 0x20 |
4221 | #define GPIO_PIN_TYPE_HW_CONTROL 0x20 |
3972 | 4222 | ||
3973 | //For GPIO_PIN_TYPE_OUTPUT the following is defined |
4223 | //For GPIO_PIN_TYPE_OUTPUT the following is defined |
3974 | #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 |
4224 | #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 |
3975 | #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 |
4225 | #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 |
3976 | #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 |
4226 | #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 |
3977 | #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 |
4227 | #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 |
3978 | 4228 | ||
3979 | // Indexes to GPIO array in GLSync record |
4229 | // Indexes to GPIO array in GLSync record |
- | 4230 | // GLSync record is for Frame Lock/Gen Lock feature. |
|
3980 | #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 |
4231 | #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 |
3981 | #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 |
4232 | #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 |
3982 | #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 |
4233 | #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 |
3983 | #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 |
4234 | #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 |
3984 | #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 |
4235 | #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 |
3985 | #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 |
4236 | #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 |
3986 | #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 |
4237 | #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 |
- | 4238 | #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 |
|
- | 4239 | #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 |
|
3987 | #define ATOM_GPIO_INDEX_GLSYNC_MAX 7 |
4240 | #define ATOM_GPIO_INDEX_GLSYNC_MAX 9 |
3988 | 4241 | ||
3989 | typedef struct _ATOM_ENCODER_DVO_CF_RECORD |
4242 | typedef struct _ATOM_ENCODER_DVO_CF_RECORD |
3990 | { |
4243 | { |
3991 | ATOM_COMMON_RECORD_HEADER sheader; |
4244 | ATOM_COMMON_RECORD_HEADER sheader; |
3992 | ULONG ulStrengthControl; // DVOA strength control for CF |
4245 | ULONG ulStrengthControl; // DVOA strength control for CF |
3993 | UCHAR ucPadding[2]; |
4246 | UCHAR ucPadding[2]; |
3994 | }ATOM_ENCODER_DVO_CF_RECORD; |
4247 | }ATOM_ENCODER_DVO_CF_RECORD; |
3995 | 4248 | ||
3996 | // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap |
4249 | // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap |
3997 | #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by this path |
4250 | #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder |
- | 4251 | #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled |
|
3998 | 4252 | ||
3999 | typedef struct _ATOM_ENCODER_CAP_RECORD |
4253 | typedef struct _ATOM_ENCODER_CAP_RECORD |
4000 | { |
4254 | { |
4001 | ATOM_COMMON_RECORD_HEADER sheader; |
4255 | ATOM_COMMON_RECORD_HEADER sheader; |
4002 | union { |
4256 | union { |
4003 | USHORT usEncoderCap; |
4257 | USHORT usEncoderCap; |
4004 | struct { |
4258 | struct { |
4005 | #if ATOM_BIG_ENDIAN |
4259 | #if ATOM_BIG_ENDIAN |
4006 | USHORT usReserved:15; // Bit1-15 may be defined for other capability in future |
4260 | USHORT usReserved:14; // Bit1-15 may be defined for other capability in future |
- | 4261 | USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable |
|
4007 | USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. |
4262 | USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. |
4008 | #else |
4263 | #else |
4009 | USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. |
4264 | USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. |
- | 4265 | USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable |
|
4010 | USHORT usReserved:15; // Bit1-15 may be defined for other capability in future |
4266 | USHORT usReserved:14; // Bit1-15 may be defined for other capability in future |
4011 | #endif |
4267 | #endif |
4012 | }; |
4268 | }; |
4013 | }; |
4269 | }; |
4014 | }ATOM_ENCODER_CAP_RECORD; |
4270 | }ATOM_ENCODER_CAP_RECORD; |
4015 | 4271 | ||
4016 | // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle |
4272 | // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle |
4017 | #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 |
4273 | #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 |
4018 | #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 |
4274 | #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 |
4019 | 4275 | ||
4020 | typedef struct _ATOM_CONNECTOR_CF_RECORD |
4276 | typedef struct _ATOM_CONNECTOR_CF_RECORD |
4021 | { |
4277 | { |
4022 | ATOM_COMMON_RECORD_HEADER sheader; |
4278 | ATOM_COMMON_RECORD_HEADER sheader; |
4023 | USHORT usMaxPixClk; |
4279 | USHORT usMaxPixClk; |
4024 | UCHAR ucFlowCntlGpioId; |
4280 | UCHAR ucFlowCntlGpioId; |
4025 | UCHAR ucSwapCntlGpioId; |
4281 | UCHAR ucSwapCntlGpioId; |
4026 | UCHAR ucConnectedDvoBundle; |
4282 | UCHAR ucConnectedDvoBundle; |
4027 | UCHAR ucPadding; |
4283 | UCHAR ucPadding; |
4028 | }ATOM_CONNECTOR_CF_RECORD; |
4284 | }ATOM_CONNECTOR_CF_RECORD; |
4029 | 4285 | ||
4030 | typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD |
4286 | typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD |
4031 | { |
4287 | { |
4032 | ATOM_COMMON_RECORD_HEADER sheader; |
4288 | ATOM_COMMON_RECORD_HEADER sheader; |
4033 | ATOM_DTD_FORMAT asTiming; |
4289 | ATOM_DTD_FORMAT asTiming; |
4034 | }ATOM_CONNECTOR_HARDCODE_DTD_RECORD; |
4290 | }ATOM_CONNECTOR_HARDCODE_DTD_RECORD; |
4035 | 4291 | ||
4036 | typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD |
4292 | typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD |
4037 | { |
4293 | { |
4038 | ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE |
4294 | ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE |
4039 | UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A |
4295 | UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A |
4040 | UCHAR ucReserved; |
4296 | UCHAR ucReserved; |
4041 | }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; |
4297 | }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; |
4042 | 4298 | ||
4043 | 4299 | ||
4044 | typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD |
4300 | typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD |
4045 | { |
4301 | { |
4046 | ATOM_COMMON_RECORD_HEADER sheader; |
4302 | ATOM_COMMON_RECORD_HEADER sheader; |
4047 | UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state |
4303 | UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state |
4048 | UCHAR ucMuxControlPin; |
4304 | UCHAR ucMuxControlPin; |
4049 | UCHAR ucMuxState[2]; //for alligment purpose |
4305 | UCHAR ucMuxState[2]; //for alligment purpose |
4050 | }ATOM_ROUTER_DDC_PATH_SELECT_RECORD; |
4306 | }ATOM_ROUTER_DDC_PATH_SELECT_RECORD; |
4051 | 4307 | ||
4052 | typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD |
4308 | typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD |
4053 | { |
4309 | { |
4054 | ATOM_COMMON_RECORD_HEADER sheader; |
4310 | ATOM_COMMON_RECORD_HEADER sheader; |
4055 | UCHAR ucMuxType; |
4311 | UCHAR ucMuxType; |
4056 | UCHAR ucMuxControlPin; |
4312 | UCHAR ucMuxControlPin; |
4057 | UCHAR ucMuxState[2]; //for alligment purpose |
4313 | UCHAR ucMuxState[2]; //for alligment purpose |
4058 | }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; |
4314 | }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; |
4059 | 4315 | ||
4060 | // define ucMuxType |
4316 | // define ucMuxType |
4061 | #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f |
4317 | #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f |
4062 | #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 |
4318 | #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 |
4063 | 4319 | ||
4064 | typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE |
4320 | typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE |
4065 | { |
4321 | { |
4066 | ATOM_COMMON_RECORD_HEADER sheader; |
4322 | ATOM_COMMON_RECORD_HEADER sheader; |
4067 | UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table |
4323 | UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table |
4068 | }ATOM_CONNECTOR_HPDPIN_LUT_RECORD; |
4324 | }ATOM_CONNECTOR_HPDPIN_LUT_RECORD; |
4069 | 4325 | ||
4070 | typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE |
4326 | typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE |
4071 | { |
4327 | { |
4072 | ATOM_COMMON_RECORD_HEADER sheader; |
4328 | ATOM_COMMON_RECORD_HEADER sheader; |
4073 | ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID |
4329 | ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID |
4074 | }ATOM_CONNECTOR_AUXDDC_LUT_RECORD; |
4330 | }ATOM_CONNECTOR_AUXDDC_LUT_RECORD; |
4075 | 4331 | ||
4076 | typedef struct _ATOM_OBJECT_LINK_RECORD |
4332 | typedef struct _ATOM_OBJECT_LINK_RECORD |
4077 | { |
4333 | { |
4078 | ATOM_COMMON_RECORD_HEADER sheader; |
4334 | ATOM_COMMON_RECORD_HEADER sheader; |
4079 | USHORT usObjectID; //could be connector, encorder or other object in object.h |
4335 | USHORT usObjectID; //could be connector, encorder or other object in object.h |
4080 | }ATOM_OBJECT_LINK_RECORD; |
4336 | }ATOM_OBJECT_LINK_RECORD; |
4081 | 4337 | ||
4082 | typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD |
4338 | typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD |
4083 | { |
4339 | { |
4084 | ATOM_COMMON_RECORD_HEADER sheader; |
4340 | ATOM_COMMON_RECORD_HEADER sheader; |
4085 | USHORT usReserved; |
4341 | USHORT usReserved; |
4086 | }ATOM_CONNECTOR_REMOTE_CAP_RECORD; |
4342 | }ATOM_CONNECTOR_REMOTE_CAP_RECORD; |
4087 | 4343 | ||
4088 | /****************************************************************************/ |
4344 | /****************************************************************************/ |
4089 | // ASIC voltage data table |
4345 | // ASIC voltage data table |
4090 | /****************************************************************************/ |
4346 | /****************************************************************************/ |
4091 | typedef struct _ATOM_VOLTAGE_INFO_HEADER |
4347 | typedef struct _ATOM_VOLTAGE_INFO_HEADER |
4092 | { |
4348 | { |
4093 | USHORT usVDDCBaseLevel; //In number of 50mv unit |
4349 | USHORT usVDDCBaseLevel; //In number of 50mv unit |
4094 | USHORT usReserved; //For possible extension table offset |
4350 | USHORT usReserved; //For possible extension table offset |
4095 | UCHAR ucNumOfVoltageEntries; |
4351 | UCHAR ucNumOfVoltageEntries; |
4096 | UCHAR ucBytesPerVoltageEntry; |
4352 | UCHAR ucBytesPerVoltageEntry; |
4097 | UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit |
4353 | UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit |
4098 | UCHAR ucDefaultVoltageEntry; |
4354 | UCHAR ucDefaultVoltageEntry; |
4099 | UCHAR ucVoltageControlI2cLine; |
4355 | UCHAR ucVoltageControlI2cLine; |
4100 | UCHAR ucVoltageControlAddress; |
4356 | UCHAR ucVoltageControlAddress; |
4101 | UCHAR ucVoltageControlOffset; |
4357 | UCHAR ucVoltageControlOffset; |
4102 | }ATOM_VOLTAGE_INFO_HEADER; |
4358 | }ATOM_VOLTAGE_INFO_HEADER; |
4103 | 4359 | ||
4104 | typedef struct _ATOM_VOLTAGE_INFO |
4360 | typedef struct _ATOM_VOLTAGE_INFO |
4105 | { |
4361 | { |
4106 | ATOM_COMMON_TABLE_HEADER sHeader; |
4362 | ATOM_COMMON_TABLE_HEADER sHeader; |
4107 | ATOM_VOLTAGE_INFO_HEADER viHeader; |
4363 | ATOM_VOLTAGE_INFO_HEADER viHeader; |
4108 | UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry |
4364 | UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry |
4109 | }ATOM_VOLTAGE_INFO; |
4365 | }ATOM_VOLTAGE_INFO; |
4110 | 4366 | ||
4111 | 4367 | ||
4112 | typedef struct _ATOM_VOLTAGE_FORMULA |
4368 | typedef struct _ATOM_VOLTAGE_FORMULA |
4113 | { |
4369 | { |
4114 | USHORT usVoltageBaseLevel; // In number of 1mv unit |
4370 | USHORT usVoltageBaseLevel; // In number of 1mv unit |
4115 | USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit |
4371 | USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit |
4116 | UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage |
4372 | UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage |
4117 | UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv |
4373 | UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv |
4118 | UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep |
4374 | UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep |
4119 | UCHAR ucReserved; |
4375 | UCHAR ucReserved; |
4120 | UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries |
4376 | UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries |
4121 | }ATOM_VOLTAGE_FORMULA; |
4377 | }ATOM_VOLTAGE_FORMULA; |
4122 | 4378 | ||
4123 | typedef struct _VOLTAGE_LUT_ENTRY |
4379 | typedef struct _VOLTAGE_LUT_ENTRY |
4124 | { |
4380 | { |
4125 | USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code |
4381 | USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code |
4126 | USHORT usVoltageValue; // The corresponding Voltage Value, in mV |
4382 | USHORT usVoltageValue; // The corresponding Voltage Value, in mV |
4127 | }VOLTAGE_LUT_ENTRY; |
4383 | }VOLTAGE_LUT_ENTRY; |
4128 | 4384 | ||
4129 | typedef struct _ATOM_VOLTAGE_FORMULA_V2 |
4385 | typedef struct _ATOM_VOLTAGE_FORMULA_V2 |
4130 | { |
4386 | { |
4131 | UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage |
4387 | UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage |
4132 | UCHAR ucReserved[3]; |
4388 | UCHAR ucReserved[3]; |
4133 | VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries |
4389 | VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries |
4134 | }ATOM_VOLTAGE_FORMULA_V2; |
4390 | }ATOM_VOLTAGE_FORMULA_V2; |
4135 | 4391 | ||
4136 | typedef struct _ATOM_VOLTAGE_CONTROL |
4392 | typedef struct _ATOM_VOLTAGE_CONTROL |
4137 | { |
4393 | { |
4138 | UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine |
4394 | UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine |
4139 | UCHAR ucVoltageControlI2cLine; |
4395 | UCHAR ucVoltageControlI2cLine; |
4140 | UCHAR ucVoltageControlAddress; |
4396 | UCHAR ucVoltageControlAddress; |
4141 | UCHAR ucVoltageControlOffset; |
4397 | UCHAR ucVoltageControlOffset; |
4142 | USHORT usGpioPin_AIndex; //GPIO_PAD register index |
4398 | USHORT usGpioPin_AIndex; //GPIO_PAD register index |
4143 | UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff |
4399 | UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff |
4144 | UCHAR ucReserved; |
4400 | UCHAR ucReserved; |
4145 | }ATOM_VOLTAGE_CONTROL; |
4401 | }ATOM_VOLTAGE_CONTROL; |
4146 | 4402 | ||
4147 | // Define ucVoltageControlId |
4403 | // Define ucVoltageControlId |
4148 | #define VOLTAGE_CONTROLLED_BY_HW 0x00 |
4404 | #define VOLTAGE_CONTROLLED_BY_HW 0x00 |
4149 | #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F |
4405 | #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F |
4150 | #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 |
4406 | #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 |
4151 | #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage |
4407 | #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage |
4152 | #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI |
4408 | #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI |
4153 | #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage |
4409 | #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage |
4154 | #define VOLTAGE_CONTROL_ID_DS4402 0x04 |
4410 | #define VOLTAGE_CONTROL_ID_DS4402 0x04 |
4155 | #define VOLTAGE_CONTROL_ID_UP6266 0x05 |
4411 | #define VOLTAGE_CONTROL_ID_UP6266 0x05 |
4156 | #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 |
4412 | #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 |
4157 | #define VOLTAGE_CONTROL_ID_VT1556M 0x07 |
4413 | #define VOLTAGE_CONTROL_ID_VT1556M 0x07 |
4158 | #define VOLTAGE_CONTROL_ID_CHL822x 0x08 |
4414 | #define VOLTAGE_CONTROL_ID_CHL822x 0x08 |
4159 | #define VOLTAGE_CONTROL_ID_VT1586M 0x09 |
4415 | #define VOLTAGE_CONTROL_ID_VT1586M 0x09 |
- | 4416 | #define VOLTAGE_CONTROL_ID_UP1637 0x0A |
|
4160 | 4417 | ||
4161 | typedef struct _ATOM_VOLTAGE_OBJECT |
4418 | typedef struct _ATOM_VOLTAGE_OBJECT |
4162 | { |
4419 | { |
4163 | UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI |
4420 | UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI |
4164 | UCHAR ucSize; //Size of Object |
4421 | UCHAR ucSize; //Size of Object |
4165 | ATOM_VOLTAGE_CONTROL asControl; //describ how to control |
4422 | ATOM_VOLTAGE_CONTROL asControl; //describ how to control |
4166 | ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID |
4423 | ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID |
4167 | }ATOM_VOLTAGE_OBJECT; |
4424 | }ATOM_VOLTAGE_OBJECT; |
4168 | 4425 | ||
4169 | typedef struct _ATOM_VOLTAGE_OBJECT_V2 |
4426 | typedef struct _ATOM_VOLTAGE_OBJECT_V2 |
4170 | { |
4427 | { |
4171 | UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI |
4428 | UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI |
4172 | UCHAR ucSize; //Size of Object |
4429 | UCHAR ucSize; //Size of Object |
4173 | ATOM_VOLTAGE_CONTROL asControl; //describ how to control |
4430 | ATOM_VOLTAGE_CONTROL asControl; //describ how to control |
4174 | ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID |
4431 | ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID |
4175 | }ATOM_VOLTAGE_OBJECT_V2; |
4432 | }ATOM_VOLTAGE_OBJECT_V2; |
4176 | 4433 | ||
4177 | typedef struct _ATOM_VOLTAGE_OBJECT_INFO |
4434 | typedef struct _ATOM_VOLTAGE_OBJECT_INFO |
4178 | { |
4435 | { |
4179 | ATOM_COMMON_TABLE_HEADER sHeader; |
4436 | ATOM_COMMON_TABLE_HEADER sHeader; |
4180 | ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control |
4437 | ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control |
4181 | }ATOM_VOLTAGE_OBJECT_INFO; |
4438 | }ATOM_VOLTAGE_OBJECT_INFO; |
4182 | 4439 | ||
4183 | typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 |
4440 | typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 |
4184 | { |
4441 | { |
4185 | ATOM_COMMON_TABLE_HEADER sHeader; |
4442 | ATOM_COMMON_TABLE_HEADER sHeader; |
4186 | ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control |
4443 | ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control |
4187 | }ATOM_VOLTAGE_OBJECT_INFO_V2; |
4444 | }ATOM_VOLTAGE_OBJECT_INFO_V2; |
4188 | 4445 | ||
4189 | typedef struct _ATOM_LEAKID_VOLTAGE |
4446 | typedef struct _ATOM_LEAKID_VOLTAGE |
4190 | { |
4447 | { |
4191 | UCHAR ucLeakageId; |
4448 | UCHAR ucLeakageId; |
4192 | UCHAR ucReserved; |
4449 | UCHAR ucReserved; |
4193 | USHORT usVoltage; |
4450 | USHORT usVoltage; |
4194 | }ATOM_LEAKID_VOLTAGE; |
4451 | }ATOM_LEAKID_VOLTAGE; |
- | 4452 | ||
- | 4453 | typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ |
|
- | 4454 | UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI |
|
- | 4455 | UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase |
|
- | 4456 | USHORT usSize; //Size of Object |
|
- | 4457 | }ATOM_VOLTAGE_OBJECT_HEADER_V3; |
|
- | 4458 | ||
- | 4459 | typedef struct _VOLTAGE_LUT_ENTRY_V2 |
|
- | 4460 | { |
|
- | 4461 | ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register |
|
- | 4462 | USHORT usVoltageValue; // The corresponding Voltage Value, in mV |
|
- | 4463 | }VOLTAGE_LUT_ENTRY_V2; |
|
- | 4464 | ||
- | 4465 | typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 |
|
- | 4466 | { |
|
- | 4467 | USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register |
|
- | 4468 | USHORT usVoltageId; |
|
- | 4469 | USHORT usLeakageId; // The corresponding Voltage Value, in mV |
|
- | 4470 | }LEAKAGE_VOLTAGE_LUT_ENTRY_V2; |
|
- | 4471 | ||
- | 4472 | typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 |
|
- | 4473 | { |
|
- | 4474 | ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; |
|
- | 4475 | UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id |
|
- | 4476 | UCHAR ucVoltageControlI2cLine; |
|
- | 4477 | UCHAR ucVoltageControlAddress; |
|
- | 4478 | UCHAR ucVoltageControlOffset; |
|
- | 4479 | ULONG ulReserved; |
|
- | 4480 | VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff |
|
- | 4481 | }ATOM_I2C_VOLTAGE_OBJECT_V3; |
|
- | 4482 | ||
- | 4483 | typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 |
|
- | 4484 | { |
|
- | 4485 | ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; |
|
- | 4486 | UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode |
|
- | 4487 | UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table |
|
- | 4488 | UCHAR ucPhaseDelay; // phase delay in unit of micro second |
|
- | 4489 | UCHAR ucReserved; |
|
- | 4490 | ULONG ulGpioMaskVal; // GPIO Mask value |
|
- | 4491 | VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; |
|
- | 4492 | }ATOM_GPIO_VOLTAGE_OBJECT_V3; |
|
- | 4493 | ||
- | 4494 | typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 |
|
- | 4495 | { |
|
- | 4496 | ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; |
|
- | 4497 | UCHAR ucLeakageCntlId; // default is 0 |
|
- | 4498 | UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table |
|
- | 4499 | UCHAR ucReserved[2]; |
|
- | 4500 | ULONG ulMaxVoltageLevel; |
|
- | 4501 | LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; |
|
- | 4502 | }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; |
|
- | 4503 | ||
- | 4504 | typedef union _ATOM_VOLTAGE_OBJECT_V3{ |
|
- | 4505 | ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; |
|
- | 4506 | ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; |
|
- | 4507 | ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; |
|
- | 4508 | }ATOM_VOLTAGE_OBJECT_V3; |
|
- | 4509 | ||
- | 4510 | typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 |
|
- | 4511 | { |
|
- | 4512 | ATOM_COMMON_TABLE_HEADER sHeader; |
|
- | 4513 | ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control |
|
- | 4514 | }ATOM_VOLTAGE_OBJECT_INFO_V3_1; |
|
4195 | 4515 | ||
4196 | typedef struct _ATOM_ASIC_PROFILE_VOLTAGE |
4516 | typedef struct _ATOM_ASIC_PROFILE_VOLTAGE |
4197 | { |
4517 | { |
4198 | UCHAR ucProfileId; |
4518 | UCHAR ucProfileId; |
4199 | UCHAR ucReserved; |
4519 | UCHAR ucReserved; |
4200 | USHORT usSize; |
4520 | USHORT usSize; |
4201 | USHORT usEfuseSpareStartAddr; |
4521 | USHORT usEfuseSpareStartAddr; |
4202 | USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, |
4522 | USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, |
4203 | ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage |
4523 | ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage |
4204 | }ATOM_ASIC_PROFILE_VOLTAGE; |
4524 | }ATOM_ASIC_PROFILE_VOLTAGE; |
4205 | 4525 | ||
4206 | //ucProfileId |
4526 | //ucProfileId |
4207 | #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 |
4527 | #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 |
4208 | #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 |
4528 | #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 |
4209 | #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 |
4529 | #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 |
4210 | 4530 | ||
4211 | typedef struct _ATOM_ASIC_PROFILING_INFO |
4531 | typedef struct _ATOM_ASIC_PROFILING_INFO |
4212 | { |
4532 | { |
4213 | ATOM_COMMON_TABLE_HEADER asHeader; |
4533 | ATOM_COMMON_TABLE_HEADER asHeader; |
4214 | ATOM_ASIC_PROFILE_VOLTAGE asVoltage; |
4534 | ATOM_ASIC_PROFILE_VOLTAGE asVoltage; |
4215 | }ATOM_ASIC_PROFILING_INFO; |
4535 | }ATOM_ASIC_PROFILING_INFO; |
4216 | 4536 | ||
4217 | typedef struct _ATOM_POWER_SOURCE_OBJECT |
4537 | typedef struct _ATOM_POWER_SOURCE_OBJECT |
4218 | { |
4538 | { |
4219 | UCHAR ucPwrSrcId; // Power source |
4539 | UCHAR ucPwrSrcId; // Power source |
4220 | UCHAR ucPwrSensorType; // GPIO, I2C or none |
4540 | UCHAR ucPwrSensorType; // GPIO, I2C or none |
4221 | UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id |
4541 | UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id |
4222 | UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect |
4542 | UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect |
4223 | UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect |
4543 | UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect |
4224 | UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect |
4544 | UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect |
4225 | UCHAR ucPwrSensActiveState; // high active or low active |
4545 | UCHAR ucPwrSensActiveState; // high active or low active |
4226 | UCHAR ucReserve[3]; // reserve |
4546 | UCHAR ucReserve[3]; // reserve |
4227 | USHORT usSensPwr; // in unit of watt |
4547 | USHORT usSensPwr; // in unit of watt |
4228 | }ATOM_POWER_SOURCE_OBJECT; |
4548 | }ATOM_POWER_SOURCE_OBJECT; |
4229 | 4549 | ||
4230 | typedef struct _ATOM_POWER_SOURCE_INFO |
4550 | typedef struct _ATOM_POWER_SOURCE_INFO |
4231 | { |
4551 | { |
4232 | ATOM_COMMON_TABLE_HEADER asHeader; |
4552 | ATOM_COMMON_TABLE_HEADER asHeader; |
4233 | UCHAR asPwrbehave[16]; |
4553 | UCHAR asPwrbehave[16]; |
4234 | ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; |
4554 | ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; |
4235 | }ATOM_POWER_SOURCE_INFO; |
4555 | }ATOM_POWER_SOURCE_INFO; |
4236 | 4556 | ||
4237 | 4557 | ||
4238 | //Define ucPwrSrcId |
4558 | //Define ucPwrSrcId |
4239 | #define POWERSOURCE_PCIE_ID1 0x00 |
4559 | #define POWERSOURCE_PCIE_ID1 0x00 |
4240 | #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 |
4560 | #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 |
4241 | #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 |
4561 | #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 |
4242 | #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 |
4562 | #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 |
4243 | #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 |
4563 | #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 |
4244 | 4564 | ||
4245 | //define ucPwrSensorId |
4565 | //define ucPwrSensorId |
4246 | #define POWER_SENSOR_ALWAYS 0x00 |
4566 | #define POWER_SENSOR_ALWAYS 0x00 |
4247 | #define POWER_SENSOR_GPIO 0x01 |
4567 | #define POWER_SENSOR_GPIO 0x01 |
4248 | #define POWER_SENSOR_I2C 0x02 |
4568 | #define POWER_SENSOR_I2C 0x02 |
4249 | 4569 | ||
4250 | typedef struct _ATOM_CLK_VOLT_CAPABILITY |
4570 | typedef struct _ATOM_CLK_VOLT_CAPABILITY |
4251 | { |
4571 | { |
4252 | ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table |
4572 | ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table |
4253 | ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz |
4573 | ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz |
4254 | }ATOM_CLK_VOLT_CAPABILITY; |
4574 | }ATOM_CLK_VOLT_CAPABILITY; |
4255 | 4575 | ||
4256 | typedef struct _ATOM_AVAILABLE_SCLK_LIST |
4576 | typedef struct _ATOM_AVAILABLE_SCLK_LIST |
4257 | { |
4577 | { |
4258 | ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz |
4578 | ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz |
4259 | USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK |
4579 | USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK |
4260 | USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK |
4580 | USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK |
4261 | }ATOM_AVAILABLE_SCLK_LIST; |
4581 | }ATOM_AVAILABLE_SCLK_LIST; |
4262 | 4582 | ||
4263 | // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition |
4583 | // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition |
4264 | #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] |
4584 | #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] |
4265 | 4585 | ||
4266 | // this IntegrateSystemInfoTable is used for Liano/Ontario APU |
4586 | // this IntegrateSystemInfoTable is used for Liano/Ontario APU |
4267 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 |
4587 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 |
4268 | { |
4588 | { |
4269 | ATOM_COMMON_TABLE_HEADER sHeader; |
4589 | ATOM_COMMON_TABLE_HEADER sHeader; |
4270 | ULONG ulBootUpEngineClock; |
4590 | ULONG ulBootUpEngineClock; |
4271 | ULONG ulDentistVCOFreq; |
4591 | ULONG ulDentistVCOFreq; |
4272 | ULONG ulBootUpUMAClock; |
4592 | ULONG ulBootUpUMAClock; |
4273 | ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; |
4593 | ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; |
4274 | ULONG ulBootUpReqDisplayVector; |
4594 | ULONG ulBootUpReqDisplayVector; |
4275 | ULONG ulOtherDisplayMisc; |
4595 | ULONG ulOtherDisplayMisc; |
4276 | ULONG ulGPUCapInfo; |
4596 | ULONG ulGPUCapInfo; |
4277 | ULONG ulSB_MMIO_Base_Addr; |
4597 | ULONG ulSB_MMIO_Base_Addr; |
4278 | USHORT usRequestedPWMFreqInHz; |
4598 | USHORT usRequestedPWMFreqInHz; |
4279 | UCHAR ucHtcTmpLmt; |
4599 | UCHAR ucHtcTmpLmt; |
4280 | UCHAR ucHtcHystLmt; |
4600 | UCHAR ucHtcHystLmt; |
4281 | ULONG ulMinEngineClock; |
4601 | ULONG ulMinEngineClock; |
4282 | ULONG ulSystemConfig; |
4602 | ULONG ulSystemConfig; |
4283 | ULONG ulCPUCapInfo; |
4603 | ULONG ulCPUCapInfo; |
4284 | USHORT usNBP0Voltage; |
4604 | USHORT usNBP0Voltage; |
4285 | USHORT usNBP1Voltage; |
4605 | USHORT usNBP1Voltage; |
4286 | USHORT usBootUpNBVoltage; |
4606 | USHORT usBootUpNBVoltage; |
4287 | USHORT usExtDispConnInfoOffset; |
4607 | USHORT usExtDispConnInfoOffset; |
4288 | USHORT usPanelRefreshRateRange; |
4608 | USHORT usPanelRefreshRateRange; |
4289 | UCHAR ucMemoryType; |
4609 | UCHAR ucMemoryType; |
4290 | UCHAR ucUMAChannelNumber; |
4610 | UCHAR ucUMAChannelNumber; |
4291 | ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; |
4611 | ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; |
4292 | ULONG ulCSR_M3_ARB_CNTL_UVD[10]; |
4612 | ULONG ulCSR_M3_ARB_CNTL_UVD[10]; |
4293 | ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; |
4613 | ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; |
4294 | ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; |
4614 | ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; |
4295 | ULONG ulGMCRestoreResetTime; |
4615 | ULONG ulGMCRestoreResetTime; |
4296 | ULONG ulMinimumNClk; |
4616 | ULONG ulMinimumNClk; |
4297 | ULONG ulIdleNClk; |
4617 | ULONG ulIdleNClk; |
4298 | ULONG ulDDR_DLL_PowerUpTime; |
4618 | ULONG ulDDR_DLL_PowerUpTime; |
4299 | ULONG ulDDR_PLL_PowerUpTime; |
4619 | ULONG ulDDR_PLL_PowerUpTime; |
4300 | USHORT usPCIEClkSSPercentage; |
4620 | USHORT usPCIEClkSSPercentage; |
4301 | USHORT usPCIEClkSSType; |
4621 | USHORT usPCIEClkSSType; |
4302 | USHORT usLvdsSSPercentage; |
4622 | USHORT usLvdsSSPercentage; |
4303 | USHORT usLvdsSSpreadRateIn10Hz; |
4623 | USHORT usLvdsSSpreadRateIn10Hz; |
4304 | USHORT usHDMISSPercentage; |
4624 | USHORT usHDMISSPercentage; |
4305 | USHORT usHDMISSpreadRateIn10Hz; |
4625 | USHORT usHDMISSpreadRateIn10Hz; |
4306 | USHORT usDVISSPercentage; |
4626 | USHORT usDVISSPercentage; |
4307 | USHORT usDVISSpreadRateIn10Hz; |
4627 | USHORT usDVISSpreadRateIn10Hz; |
- | 4628 | ULONG SclkDpmBoostMargin; |
|
- | 4629 | ULONG SclkDpmThrottleMargin; |
|
- | 4630 | USHORT SclkDpmTdpLimitPG; |
|
- | 4631 | USHORT SclkDpmTdpLimitBoost; |
|
- | 4632 | ULONG ulBoostEngineCLock; |
|
- | 4633 | UCHAR ulBoostVid_2bit; |
|
- | 4634 | UCHAR EnableBoost; |
|
- | 4635 | USHORT GnbTdpLimit; |
|
- | 4636 | USHORT usMaxLVDSPclkFreqInSingleLink; |
|
- | 4637 | UCHAR ucLvdsMisc; |
|
- | 4638 | UCHAR ucLVDSReserved; |
|
4308 | ULONG ulReserved3[21]; |
4639 | ULONG ulReserved3[15]; |
4309 | ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; |
4640 | ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; |
4310 | }ATOM_INTEGRATED_SYSTEM_INFO_V6; |
4641 | }ATOM_INTEGRATED_SYSTEM_INFO_V6; |
4311 | 4642 | ||
4312 | // ulGPUCapInfo |
4643 | // ulGPUCapInfo |
4313 | #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 |
4644 | #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 |
4314 | #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 |
4645 | #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 |
4315 | 4646 | ||
4316 | // ulOtherDisplayMisc |
4647 | //ucLVDSMisc: |
- | 4648 | #define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 |
|
- | 4649 | #define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 |
|
- | 4650 | #define SYS_INFO_LVDSMISC__888_BPC 0x04 |
|
- | 4651 | #define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 |
|
4317 | #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 |
4652 | #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 |
- | 4653 | ||
- | 4654 | // not used any more |
|
- | 4655 | #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 |
|
4318 | 4656 | #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 |
|
4319 | 4657 | ||
4320 | /********************************************************************************************************************** |
4658 | /********************************************************************************************************************** |
4321 | ATOM_INTEGRATED_SYSTEM_INFO_V6 Description |
4659 | ATOM_INTEGRATED_SYSTEM_INFO_V6 Description |
4322 | ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock |
4660 | ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock |
4323 | ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. |
4661 | ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. |
4324 | ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. |
4662 | ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. |
4325 | sDISPCLK_Voltage: Report Display clock voltage requirement. |
4663 | sDISPCLK_Voltage: Report Display clock voltage requirement. |
4326 | 4664 | ||
4327 | ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: |
4665 | ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: |
4328 | ATOM_DEVICE_CRT1_SUPPORT 0x0001 |
4666 | ATOM_DEVICE_CRT1_SUPPORT 0x0001 |
4329 | ATOM_DEVICE_CRT2_SUPPORT 0x0010 |
4667 | ATOM_DEVICE_CRT2_SUPPORT 0x0010 |
4330 | ATOM_DEVICE_DFP1_SUPPORT 0x0008 |
4668 | ATOM_DEVICE_DFP1_SUPPORT 0x0008 |
4331 | ATOM_DEVICE_DFP6_SUPPORT 0x0040 |
4669 | ATOM_DEVICE_DFP6_SUPPORT 0x0040 |
4332 | ATOM_DEVICE_DFP2_SUPPORT 0x0080 |
4670 | ATOM_DEVICE_DFP2_SUPPORT 0x0080 |
4333 | ATOM_DEVICE_DFP3_SUPPORT 0x0200 |
4671 | ATOM_DEVICE_DFP3_SUPPORT 0x0200 |
4334 | ATOM_DEVICE_DFP4_SUPPORT 0x0400 |
4672 | ATOM_DEVICE_DFP4_SUPPORT 0x0400 |
4335 | ATOM_DEVICE_DFP5_SUPPORT 0x0800 |
4673 | ATOM_DEVICE_DFP5_SUPPORT 0x0800 |
4336 | ATOM_DEVICE_LCD1_SUPPORT 0x0002 |
4674 | ATOM_DEVICE_LCD1_SUPPORT 0x0002 |
4337 | ulOtherDisplayMisc: Other display related flags, not defined yet. |
4675 | ulOtherDisplayMisc: Other display related flags, not defined yet. |
4338 | ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. |
4676 | ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. |
4339 | =1: TMDS/HDMI Coherent Mode use signel PLL mode. |
4677 | =1: TMDS/HDMI Coherent Mode use signel PLL mode. |
4340 | bit[3]=0: Enable HW AUX mode detection logic |
4678 | bit[3]=0: Enable HW AUX mode detection logic |
4341 | =1: Disable HW AUX mode dettion logic |
4679 | =1: Disable HW AUX mode dettion logic |
4342 | ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. |
4680 | ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. |
4343 | 4681 | ||
4344 | usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). |
4682 | usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). |
4345 | Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; |
4683 | Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; |
4346 | 4684 | ||
4347 | When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: |
4685 | When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: |
4348 | 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; |
4686 | 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; |
4349 | VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, |
4687 | VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, |
4350 | Changing BL using VBIOS function is functional in both driver and non-driver present environment; |
4688 | Changing BL using VBIOS function is functional in both driver and non-driver present environment; |
4351 | and enabling VariBri under the driver environment from PP table is optional. |
4689 | and enabling VariBri under the driver environment from PP table is optional. |
4352 | 4690 | ||
4353 | 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating |
4691 | 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating |
4354 | that BL control from GPU is expected. |
4692 | that BL control from GPU is expected. |
4355 | VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 |
4693 | VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 |
4356 | Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but |
4694 | Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but |
4357 | it's per platform |
4695 | it's per platform |
4358 | and enabling VariBri under the driver environment from PP table is optional. |
4696 | and enabling VariBri under the driver environment from PP table is optional. |
4359 | 4697 | ||
4360 | ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. |
4698 | ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. |
4361 | Threshold on value to enter HTC_active state. |
4699 | Threshold on value to enter HTC_active state. |
4362 | ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. |
4700 | ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. |
4363 | To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. |
4701 | To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. |
4364 | ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. |
4702 | ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. |
4365 | ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled |
4703 | ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled |
4366 | =1: PCIE Power Gating Enabled |
4704 | =1: PCIE Power Gating Enabled |
4367 | Bit[1]=0: DDR-DLL shut-down feature disabled. |
4705 | Bit[1]=0: DDR-DLL shut-down feature disabled. |
4368 | 1: DDR-DLL shut-down feature enabled. |
4706 | 1: DDR-DLL shut-down feature enabled. |
4369 | Bit[2]=0: DDR-PLL Power down feature disabled. |
4707 | Bit[2]=0: DDR-PLL Power down feature disabled. |
4370 | 1: DDR-PLL Power down feature enabled. |
4708 | 1: DDR-PLL Power down feature enabled. |
4371 | ulCPUCapInfo: TBD |
4709 | ulCPUCapInfo: TBD |
4372 | usNBP0Voltage: VID for voltage on NB P0 State |
4710 | usNBP0Voltage: VID for voltage on NB P0 State |
4373 | usNBP1Voltage: VID for voltage on NB P1 State |
4711 | usNBP1Voltage: VID for voltage on NB P1 State |
4374 | usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. |
4712 | usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. |
4375 | usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure |
4713 | usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure |
4376 | usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set |
4714 | usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set |
4377 | to indicate a range. |
4715 | to indicate a range. |
4378 | SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 |
4716 | SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 |
4379 | SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 |
4717 | SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 |
4380 | SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 |
4718 | SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 |
4381 | SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 |
4719 | SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 |
4382 | ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. |
4720 | ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. |
4383 | ucUMAChannelNumber: System memory channel numbers. |
4721 | ucUMAChannelNumber: System memory channel numbers. |
4384 | ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default |
4722 | ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default |
4385 | ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. |
4723 | ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. |
4386 | ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. |
4724 | ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. |
4387 | sAvail_SCLK[5]: Arrays to provide available list of SLCK and corresponding voltage, order from low to high |
4725 | sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high |
- | 4726 | ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. |
|
- | 4727 | ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. |
|
- | 4728 | ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. |
|
- | 4729 | ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. |
|
- | 4730 | ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. |
|
- | 4731 | usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. |
|
- | 4732 | usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. |
|
- | 4733 | usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. |
|
- | 4734 | usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
|
- | 4735 | usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. |
|
- | 4736 | usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
|
- | 4737 | usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. |
|
- | 4738 | usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
|
- | 4739 | usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz |
|
- | 4740 | ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode |
|
- | 4741 | [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped |
|
- | 4742 | [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color |
|
- | 4743 | [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used |
|
- | 4744 | [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) |
|
- | 4745 | **********************************************************************************************************************/ |
|
- | 4746 | ||
- | 4747 | // this Table is used for Liano/Ontario APU |
|
- | 4748 | typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 |
|
- | 4749 | { |
|
- | 4750 | ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; |
|
- | 4751 | ULONG ulPowerplayTable[128]; |
|
- | 4752 | }ATOM_FUSION_SYSTEM_INFO_V1; |
|
- | 4753 | /********************************************************************************************************************** |
|
- | 4754 | ATOM_FUSION_SYSTEM_INFO_V1 Description |
|
- | 4755 | sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. |
|
- | 4756 | ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] |
|
- | 4757 | **********************************************************************************************************************/ |
|
- | 4758 | ||
- | 4759 | // this IntegrateSystemInfoTable is used for Trinity APU |
|
- | 4760 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 |
|
- | 4761 | { |
|
- | 4762 | ATOM_COMMON_TABLE_HEADER sHeader; |
|
- | 4763 | ULONG ulBootUpEngineClock; |
|
- | 4764 | ULONG ulDentistVCOFreq; |
|
- | 4765 | ULONG ulBootUpUMAClock; |
|
- | 4766 | ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; |
|
- | 4767 | ULONG ulBootUpReqDisplayVector; |
|
- | 4768 | ULONG ulOtherDisplayMisc; |
|
- | 4769 | ULONG ulGPUCapInfo; |
|
- | 4770 | ULONG ulSB_MMIO_Base_Addr; |
|
- | 4771 | USHORT usRequestedPWMFreqInHz; |
|
- | 4772 | UCHAR ucHtcTmpLmt; |
|
- | 4773 | UCHAR ucHtcHystLmt; |
|
- | 4774 | ULONG ulMinEngineClock; |
|
- | 4775 | ULONG ulSystemConfig; |
|
- | 4776 | ULONG ulCPUCapInfo; |
|
- | 4777 | USHORT usNBP0Voltage; |
|
- | 4778 | USHORT usNBP1Voltage; |
|
- | 4779 | USHORT usBootUpNBVoltage; |
|
- | 4780 | USHORT usExtDispConnInfoOffset; |
|
- | 4781 | USHORT usPanelRefreshRateRange; |
|
- | 4782 | UCHAR ucMemoryType; |
|
- | 4783 | UCHAR ucUMAChannelNumber; |
|
- | 4784 | UCHAR strVBIOSMsg[40]; |
|
- | 4785 | ULONG ulReserved[20]; |
|
- | 4786 | ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; |
|
- | 4787 | ULONG ulGMCRestoreResetTime; |
|
- | 4788 | ULONG ulMinimumNClk; |
|
- | 4789 | ULONG ulIdleNClk; |
|
- | 4790 | ULONG ulDDR_DLL_PowerUpTime; |
|
- | 4791 | ULONG ulDDR_PLL_PowerUpTime; |
|
- | 4792 | USHORT usPCIEClkSSPercentage; |
|
- | 4793 | USHORT usPCIEClkSSType; |
|
- | 4794 | USHORT usLvdsSSPercentage; |
|
- | 4795 | USHORT usLvdsSSpreadRateIn10Hz; |
|
- | 4796 | USHORT usHDMISSPercentage; |
|
- | 4797 | USHORT usHDMISSpreadRateIn10Hz; |
|
- | 4798 | USHORT usDVISSPercentage; |
|
- | 4799 | USHORT usDVISSpreadRateIn10Hz; |
|
- | 4800 | ULONG SclkDpmBoostMargin; |
|
- | 4801 | ULONG SclkDpmThrottleMargin; |
|
- | 4802 | USHORT SclkDpmTdpLimitPG; |
|
- | 4803 | USHORT SclkDpmTdpLimitBoost; |
|
- | 4804 | ULONG ulBoostEngineCLock; |
|
- | 4805 | UCHAR ulBoostVid_2bit; |
|
- | 4806 | UCHAR EnableBoost; |
|
- | 4807 | USHORT GnbTdpLimit; |
|
- | 4808 | USHORT usMaxLVDSPclkFreqInSingleLink; |
|
- | 4809 | UCHAR ucLvdsMisc; |
|
- | 4810 | UCHAR ucLVDSReserved; |
|
- | 4811 | UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; |
|
- | 4812 | UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; |
|
- | 4813 | UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; |
|
- | 4814 | UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; |
|
- | 4815 | UCHAR ucLVDSOffToOnDelay_in4Ms; |
|
- | 4816 | UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; |
|
- | 4817 | UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; |
|
- | 4818 | UCHAR ucLVDSReserved1; |
|
- | 4819 | ULONG ulLCDBitDepthControlVal; |
|
- | 4820 | ULONG ulNbpStateMemclkFreq[4]; |
|
- | 4821 | USHORT usNBP2Voltage; |
|
- | 4822 | USHORT usNBP3Voltage; |
|
- | 4823 | ULONG ulNbpStateNClkFreq[4]; |
|
- | 4824 | UCHAR ucNBDPMEnable; |
|
- | 4825 | UCHAR ucReserved[3]; |
|
- | 4826 | UCHAR ucDPMState0VclkFid; |
|
- | 4827 | UCHAR ucDPMState0DclkFid; |
|
- | 4828 | UCHAR ucDPMState1VclkFid; |
|
- | 4829 | UCHAR ucDPMState1DclkFid; |
|
- | 4830 | UCHAR ucDPMState2VclkFid; |
|
- | 4831 | UCHAR ucDPMState2DclkFid; |
|
- | 4832 | UCHAR ucDPMState3VclkFid; |
|
- | 4833 | UCHAR ucDPMState3DclkFid; |
|
- | 4834 | ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; |
|
- | 4835 | }ATOM_INTEGRATED_SYSTEM_INFO_V1_7; |
|
- | 4836 | ||
- | 4837 | // ulOtherDisplayMisc |
|
- | 4838 | #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 |
|
- | 4839 | #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 |
|
- | 4840 | #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 |
|
- | 4841 | #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 |
|
- | 4842 | ||
- | 4843 | // ulGPUCapInfo |
|
- | 4844 | #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 |
|
- | 4845 | #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 |
|
- | 4846 | #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 |
|
- | 4847 | ||
- | 4848 | /********************************************************************************************************************** |
|
- | 4849 | ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description |
|
- | 4850 | ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock |
|
- | 4851 | ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. |
|
- | 4852 | ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. |
|
- | 4853 | sDISPCLK_Voltage: Report Display clock voltage requirement. |
|
- | 4854 | ||
- | 4855 | ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: |
|
- | 4856 | ATOM_DEVICE_CRT1_SUPPORT 0x0001 |
|
- | 4857 | ATOM_DEVICE_DFP1_SUPPORT 0x0008 |
|
- | 4858 | ATOM_DEVICE_DFP6_SUPPORT 0x0040 |
|
- | 4859 | ATOM_DEVICE_DFP2_SUPPORT 0x0080 |
|
- | 4860 | ATOM_DEVICE_DFP3_SUPPORT 0x0200 |
|
- | 4861 | ATOM_DEVICE_DFP4_SUPPORT 0x0400 |
|
- | 4862 | ATOM_DEVICE_DFP5_SUPPORT 0x0800 |
|
- | 4863 | ATOM_DEVICE_LCD1_SUPPORT 0x0002 |
|
- | 4864 | ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. |
|
- | 4865 | =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. |
|
- | 4866 | bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS |
|
- | 4867 | =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS |
|
- | 4868 | bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS |
|
- | 4869 | =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS |
|
- | 4870 | bit[3]=0: VBIOS fast boot is disable |
|
- | 4871 | =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) |
|
- | 4872 | ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. |
|
- | 4873 | =1: TMDS/HDMI Coherent Mode use signel PLL mode. |
|
- | 4874 | bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) |
|
- | 4875 | =1: DP mode use single PLL mode |
|
- | 4876 | bit[3]=0: Enable AUX HW mode detection logic |
|
- | 4877 | =1: Disable AUX HW mode detection logic |
|
- | 4878 | ||
- | 4879 | ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. |
|
- | 4880 | ||
- | 4881 | usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). |
|
- | 4882 | Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; |
|
- | 4883 | ||
- | 4884 | When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: |
|
- | 4885 | 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; |
|
- | 4886 | VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, |
|
- | 4887 | Changing BL using VBIOS function is functional in both driver and non-driver present environment; |
|
- | 4888 | and enabling VariBri under the driver environment from PP table is optional. |
|
- | 4889 | ||
- | 4890 | 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating |
|
- | 4891 | that BL control from GPU is expected. |
|
- | 4892 | VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 |
|
- | 4893 | Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but |
|
- | 4894 | it's per platform |
|
- | 4895 | and enabling VariBri under the driver environment from PP table is optional. |
|
- | 4896 | ||
- | 4897 | ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. |
|
- | 4898 | Threshold on value to enter HTC_active state. |
|
- | 4899 | ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. |
|
- | 4900 | To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. |
|
- | 4901 | ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. |
|
- | 4902 | ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled |
|
- | 4903 | =1: PCIE Power Gating Enabled |
|
- | 4904 | Bit[1]=0: DDR-DLL shut-down feature disabled. |
|
- | 4905 | 1: DDR-DLL shut-down feature enabled. |
|
- | 4906 | Bit[2]=0: DDR-PLL Power down feature disabled. |
|
- | 4907 | 1: DDR-PLL Power down feature enabled. |
|
- | 4908 | ulCPUCapInfo: TBD |
|
- | 4909 | usNBP0Voltage: VID for voltage on NB P0 State |
|
- | 4910 | usNBP1Voltage: VID for voltage on NB P1 State |
|
- | 4911 | usNBP2Voltage: VID for voltage on NB P2 State |
|
- | 4912 | usNBP3Voltage: VID for voltage on NB P3 State |
|
- | 4913 | usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. |
|
- | 4914 | usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure |
|
- | 4915 | usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set |
|
- | 4916 | to indicate a range. |
|
- | 4917 | SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 |
|
- | 4918 | SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 |
|
- | 4919 | SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 |
|
- | 4920 | SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 |
|
- | 4921 | ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. |
|
- | 4922 | ucUMAChannelNumber: System memory channel numbers. |
|
- | 4923 | ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default |
|
- | 4924 | ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. |
|
- | 4925 | ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. |
|
- | 4926 | sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high |
|
4388 | ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. |
4927 | ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. |
4389 | ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. |
4928 | ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. |
4390 | ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. |
4929 | ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. |
4391 | ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. |
4930 | ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. |
4392 | ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. |
4931 | ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. |
4393 | usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. |
4932 | usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. |
4394 | usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. |
4933 | usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. |
4395 | usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. |
4934 | usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. |
4396 | usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
4935 | usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
4397 | usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. |
4936 | usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. |
4398 | usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
4937 | usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
4399 | usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. |
4938 | usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. |
4400 | usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
4939 | usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
- | 4940 | usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz |
|
- | 4941 | ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode |
|
- | 4942 | [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped |
|
- | 4943 | [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color |
|
- | 4944 | [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used |
|
- | 4945 | [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) |
|
- | 4946 | ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). |
|
- | 4947 | =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. |
|
- | 4948 | This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
|
- | 4949 | ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). |
|
- | 4950 | =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. |
|
- | 4951 | This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
|
- | 4952 | ||
- | 4953 | ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. |
|
- | 4954 | =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON |
|
- | 4955 | This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
|
- | 4956 | ||
- | 4957 | ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. |
|
- | 4958 | =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON |
|
- | 4959 | This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
|
- | 4960 | ||
- | 4961 | ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. |
|
- | 4962 | =0 means to use VBIOS default delay which is 125 ( 500ms ). |
|
- | 4963 | This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
|
- | 4964 | ||
- | 4965 | ucLVDSPwrOnVARY_BLtoBLON_in4Ms: LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. |
|
- | 4966 | =0 means to use VBIOS default delay which is 0 ( 0ms ). |
|
- | 4967 | This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
|
- | 4968 | ||
- | 4969 | ucLVDSPwrOffBLONtoVARY_BL_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. |
|
- | 4970 | =0 means to use VBIOS default delay which is 0 ( 0ms ). |
|
- | 4971 | This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
|
- | 4972 | ||
- | 4973 | ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. |
|
- | 4974 | ||
4401 | **********************************************************************************************************************/ |
4975 | **********************************************************************************************************************/ |
4402 | 4976 | ||
4403 | /**************************************************************************/ |
4977 | /**************************************************************************/ |
4404 | // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design |
4978 | // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design |
4405 | //Memory SS Info Table |
4979 | //Memory SS Info Table |
4406 | //Define Memory Clock SS chip ID |
4980 | //Define Memory Clock SS chip ID |
4407 | #define ICS91719 1 |
4981 | #define ICS91719 1 |
4408 | #define ICS91720 2 |
4982 | #define ICS91720 2 |
4409 | 4983 | ||
4410 | //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol |
4984 | //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol |
4411 | typedef struct _ATOM_I2C_DATA_RECORD |
4985 | typedef struct _ATOM_I2C_DATA_RECORD |
4412 | { |
4986 | { |
4413 | UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" |
4987 | UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" |
4414 | UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually |
4988 | UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually |
4415 | }ATOM_I2C_DATA_RECORD; |
4989 | }ATOM_I2C_DATA_RECORD; |
4416 | 4990 | ||
4417 | 4991 | ||
4418 | //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information |
4992 | //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information |
4419 | typedef struct _ATOM_I2C_DEVICE_SETUP_INFO |
4993 | typedef struct _ATOM_I2C_DEVICE_SETUP_INFO |
4420 | { |
4994 | { |
4421 | ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. |
4995 | ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. |
4422 | UCHAR ucSSChipID; //SS chip being used |
4996 | UCHAR ucSSChipID; //SS chip being used |
4423 | UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip |
4997 | UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip |
4424 | UCHAR ucNumOfI2CDataRecords; //number of data block |
4998 | UCHAR ucNumOfI2CDataRecords; //number of data block |
4425 | ATOM_I2C_DATA_RECORD asI2CData[1]; |
4999 | ATOM_I2C_DATA_RECORD asI2CData[1]; |
4426 | }ATOM_I2C_DEVICE_SETUP_INFO; |
5000 | }ATOM_I2C_DEVICE_SETUP_INFO; |
4427 | 5001 | ||
4428 | //========================================================================================== |
5002 | //========================================================================================== |
4429 | typedef struct _ATOM_ASIC_MVDD_INFO |
5003 | typedef struct _ATOM_ASIC_MVDD_INFO |
4430 | { |
5004 | { |
4431 | ATOM_COMMON_TABLE_HEADER sHeader; |
5005 | ATOM_COMMON_TABLE_HEADER sHeader; |
4432 | ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; |
5006 | ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; |
4433 | }ATOM_ASIC_MVDD_INFO; |
5007 | }ATOM_ASIC_MVDD_INFO; |
4434 | 5008 | ||
4435 | //========================================================================================== |
5009 | //========================================================================================== |
4436 | #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO |
5010 | #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO |
4437 | 5011 | ||
4438 | //========================================================================================== |
5012 | //========================================================================================== |
4439 | /**************************************************************************/ |
5013 | /**************************************************************************/ |
4440 | 5014 | ||
4441 | typedef struct _ATOM_ASIC_SS_ASSIGNMENT |
5015 | typedef struct _ATOM_ASIC_SS_ASSIGNMENT |
4442 | { |
5016 | { |
4443 | ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz |
5017 | ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz |
4444 | USHORT usSpreadSpectrumPercentage; //in unit of 0.01% |
5018 | USHORT usSpreadSpectrumPercentage; //in unit of 0.01% |
4445 | USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq |
5019 | USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq |
4446 | UCHAR ucClockIndication; //Indicate which clock source needs SS |
5020 | UCHAR ucClockIndication; //Indicate which clock source needs SS |
4447 | UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. |
5021 | UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. |
4448 | UCHAR ucReserved[2]; |
5022 | UCHAR ucReserved[2]; |
4449 | }ATOM_ASIC_SS_ASSIGNMENT; |
5023 | }ATOM_ASIC_SS_ASSIGNMENT; |
4450 | 5024 | ||
4451 | //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type. |
5025 | //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type. |
4452 | //SS is not required or enabled if a match is not found. |
5026 | //SS is not required or enabled if a match is not found. |
4453 | #define ASIC_INTERNAL_MEMORY_SS 1 |
5027 | #define ASIC_INTERNAL_MEMORY_SS 1 |
4454 | #define ASIC_INTERNAL_ENGINE_SS 2 |
5028 | #define ASIC_INTERNAL_ENGINE_SS 2 |
4455 | #define ASIC_INTERNAL_UVD_SS 3 |
5029 | #define ASIC_INTERNAL_UVD_SS 3 |
4456 | #define ASIC_INTERNAL_SS_ON_TMDS 4 |
5030 | #define ASIC_INTERNAL_SS_ON_TMDS 4 |
4457 | #define ASIC_INTERNAL_SS_ON_HDMI 5 |
5031 | #define ASIC_INTERNAL_SS_ON_HDMI 5 |
4458 | #define ASIC_INTERNAL_SS_ON_LVDS 6 |
5032 | #define ASIC_INTERNAL_SS_ON_LVDS 6 |
4459 | #define ASIC_INTERNAL_SS_ON_DP 7 |
5033 | #define ASIC_INTERNAL_SS_ON_DP 7 |
4460 | #define ASIC_INTERNAL_SS_ON_DCPLL 8 |
5034 | #define ASIC_INTERNAL_SS_ON_DCPLL 8 |
4461 | #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 |
5035 | #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 |
- | 5036 | #define ASIC_INTERNAL_VCE_SS 10 |
|
4462 | 5037 | ||
4463 | typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 |
5038 | typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 |
4464 | { |
5039 | { |
4465 | ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz |
5040 | ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz |
4466 | //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) |
5041 | //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) |
4467 | USHORT usSpreadSpectrumPercentage; //in unit of 0.01% |
5042 | USHORT usSpreadSpectrumPercentage; //in unit of 0.01% |
4468 | USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq |
5043 | USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq |
4469 | UCHAR ucClockIndication; //Indicate which clock source needs SS |
5044 | UCHAR ucClockIndication; //Indicate which clock source needs SS |
4470 | UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS |
5045 | UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS |
4471 | UCHAR ucReserved[2]; |
5046 | UCHAR ucReserved[2]; |
4472 | }ATOM_ASIC_SS_ASSIGNMENT_V2; |
5047 | }ATOM_ASIC_SS_ASSIGNMENT_V2; |
4473 | 5048 | ||
4474 | //ucSpreadSpectrumMode |
5049 | //ucSpreadSpectrumMode |
4475 | //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 |
5050 | //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 |
4476 | //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 |
5051 | //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 |
4477 | //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 |
5052 | //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 |
4478 | //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 |
5053 | //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 |
4479 | //#define ATOM_INTERNAL_SS_MASK 0x00000000 |
5054 | //#define ATOM_INTERNAL_SS_MASK 0x00000000 |
4480 | //#define ATOM_EXTERNAL_SS_MASK 0x00000002 |
5055 | //#define ATOM_EXTERNAL_SS_MASK 0x00000002 |
4481 | 5056 | ||
4482 | typedef struct _ATOM_ASIC_INTERNAL_SS_INFO |
5057 | typedef struct _ATOM_ASIC_INTERNAL_SS_INFO |
4483 | { |
5058 | { |
4484 | ATOM_COMMON_TABLE_HEADER sHeader; |
5059 | ATOM_COMMON_TABLE_HEADER sHeader; |
4485 | ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; |
5060 | ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; |
4486 | }ATOM_ASIC_INTERNAL_SS_INFO; |
5061 | }ATOM_ASIC_INTERNAL_SS_INFO; |
4487 | 5062 | ||
4488 | typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 |
5063 | typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 |
4489 | { |
5064 | { |
4490 | ATOM_COMMON_TABLE_HEADER sHeader; |
5065 | ATOM_COMMON_TABLE_HEADER sHeader; |
4491 | ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. |
5066 | ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. |
4492 | }ATOM_ASIC_INTERNAL_SS_INFO_V2; |
5067 | }ATOM_ASIC_INTERNAL_SS_INFO_V2; |
4493 | 5068 | ||
4494 | typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 |
5069 | typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 |
4495 | { |
5070 | { |
4496 | ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz |
5071 | ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz |
4497 | //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) |
5072 | //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) |
4498 | USHORT usSpreadSpectrumPercentage; //in unit of 0.01% |
5073 | USHORT usSpreadSpectrumPercentage; //in unit of 0.01% |
4499 | USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq |
5074 | USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq |
4500 | UCHAR ucClockIndication; //Indicate which clock source needs SS |
5075 | UCHAR ucClockIndication; //Indicate which clock source needs SS |
4501 | UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS |
5076 | UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS |
4502 | UCHAR ucReserved[2]; |
5077 | UCHAR ucReserved[2]; |
4503 | }ATOM_ASIC_SS_ASSIGNMENT_V3; |
5078 | }ATOM_ASIC_SS_ASSIGNMENT_V3; |
4504 | 5079 | ||
4505 | typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 |
5080 | typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 |
4506 | { |
5081 | { |
4507 | ATOM_COMMON_TABLE_HEADER sHeader; |
5082 | ATOM_COMMON_TABLE_HEADER sHeader; |
4508 | ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. |
5083 | ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. |
4509 | }ATOM_ASIC_INTERNAL_SS_INFO_V3; |
5084 | }ATOM_ASIC_INTERNAL_SS_INFO_V3; |
4510 | 5085 | ||
4511 | 5086 | ||
4512 | //==============================Scratch Pad Definition Portion=============================== |
5087 | //==============================Scratch Pad Definition Portion=============================== |
4513 | #define ATOM_DEVICE_CONNECT_INFO_DEF 0 |
5088 | #define ATOM_DEVICE_CONNECT_INFO_DEF 0 |
4514 | #define ATOM_ROM_LOCATION_DEF 1 |
5089 | #define ATOM_ROM_LOCATION_DEF 1 |
4515 | #define ATOM_TV_STANDARD_DEF 2 |
5090 | #define ATOM_TV_STANDARD_DEF 2 |
4516 | #define ATOM_ACTIVE_INFO_DEF 3 |
5091 | #define ATOM_ACTIVE_INFO_DEF 3 |
4517 | #define ATOM_LCD_INFO_DEF 4 |
5092 | #define ATOM_LCD_INFO_DEF 4 |
4518 | #define ATOM_DOS_REQ_INFO_DEF 5 |
5093 | #define ATOM_DOS_REQ_INFO_DEF 5 |
4519 | #define ATOM_ACC_CHANGE_INFO_DEF 6 |
5094 | #define ATOM_ACC_CHANGE_INFO_DEF 6 |
4520 | #define ATOM_DOS_MODE_INFO_DEF 7 |
5095 | #define ATOM_DOS_MODE_INFO_DEF 7 |
4521 | #define ATOM_I2C_CHANNEL_STATUS_DEF 8 |
5096 | #define ATOM_I2C_CHANNEL_STATUS_DEF 8 |
4522 | #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 |
5097 | #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 |
4523 | - | ||
- | 5098 | #define ATOM_INTERNAL_TIMER_DEF 10 |
|
4524 | 5099 | ||
4525 | // BIOS_0_SCRATCH Definition |
5100 | // BIOS_0_SCRATCH Definition |
4526 | #define ATOM_S0_CRT1_MONO 0x00000001L |
5101 | #define ATOM_S0_CRT1_MONO 0x00000001L |
4527 | #define ATOM_S0_CRT1_COLOR 0x00000002L |
5102 | #define ATOM_S0_CRT1_COLOR 0x00000002L |
4528 | #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) |
5103 | #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) |
4529 | 5104 | ||
4530 | #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L |
5105 | #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L |
4531 | #define ATOM_S0_TV1_SVIDEO_A 0x00000008L |
5106 | #define ATOM_S0_TV1_SVIDEO_A 0x00000008L |
4532 | #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) |
5107 | #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) |
4533 | 5108 | ||
4534 | #define ATOM_S0_CV_A 0x00000010L |
5109 | #define ATOM_S0_CV_A 0x00000010L |
4535 | #define ATOM_S0_CV_DIN_A 0x00000020L |
5110 | #define ATOM_S0_CV_DIN_A 0x00000020L |
4536 | #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) |
5111 | #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) |
4537 | 5112 | ||
4538 | 5113 | ||
4539 | #define ATOM_S0_CRT2_MONO 0x00000100L |
5114 | #define ATOM_S0_CRT2_MONO 0x00000100L |
4540 | #define ATOM_S0_CRT2_COLOR 0x00000200L |
5115 | #define ATOM_S0_CRT2_COLOR 0x00000200L |
4541 | #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) |
5116 | #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) |
4542 | 5117 | ||
4543 | #define ATOM_S0_TV1_COMPOSITE 0x00000400L |
5118 | #define ATOM_S0_TV1_COMPOSITE 0x00000400L |
4544 | #define ATOM_S0_TV1_SVIDEO 0x00000800L |
5119 | #define ATOM_S0_TV1_SVIDEO 0x00000800L |
4545 | #define ATOM_S0_TV1_SCART 0x00004000L |
5120 | #define ATOM_S0_TV1_SCART 0x00004000L |
4546 | #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) |
5121 | #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) |
4547 | 5122 | ||
4548 | #define ATOM_S0_CV 0x00001000L |
5123 | #define ATOM_S0_CV 0x00001000L |
4549 | #define ATOM_S0_CV_DIN 0x00002000L |
5124 | #define ATOM_S0_CV_DIN 0x00002000L |
4550 | #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) |
5125 | #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) |
4551 | 5126 | ||
4552 | #define ATOM_S0_DFP1 0x00010000L |
5127 | #define ATOM_S0_DFP1 0x00010000L |
4553 | #define ATOM_S0_DFP2 0x00020000L |
5128 | #define ATOM_S0_DFP2 0x00020000L |
4554 | #define ATOM_S0_LCD1 0x00040000L |
5129 | #define ATOM_S0_LCD1 0x00040000L |
4555 | #define ATOM_S0_LCD2 0x00080000L |
5130 | #define ATOM_S0_LCD2 0x00080000L |
4556 | #define ATOM_S0_DFP6 0x00100000L |
5131 | #define ATOM_S0_DFP6 0x00100000L |
4557 | #define ATOM_S0_DFP3 0x00200000L |
5132 | #define ATOM_S0_DFP3 0x00200000L |
4558 | #define ATOM_S0_DFP4 0x00400000L |
5133 | #define ATOM_S0_DFP4 0x00400000L |
4559 | #define ATOM_S0_DFP5 0x00800000L |
5134 | #define ATOM_S0_DFP5 0x00800000L |
4560 | 5135 | ||
4561 | #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 |
5136 | #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 |
4562 | 5137 | ||
4563 | #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with |
5138 | #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with |
4564 | // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx |
5139 | // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx |
4565 | 5140 | ||
4566 | #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L |
5141 | #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L |
4567 | #define ATOM_S0_THERMAL_STATE_SHIFT 26 |
5142 | #define ATOM_S0_THERMAL_STATE_SHIFT 26 |
4568 | 5143 | ||
4569 | #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L |
5144 | #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L |
4570 | #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 |
5145 | #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 |
4571 | 5146 | ||
4572 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 |
5147 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 |
4573 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 |
5148 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 |
4574 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 |
5149 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 |
4575 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 |
5150 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 |
4576 | 5151 | ||
4577 | //Byte aligned definition for BIOS usage |
5152 | //Byte aligned definition for BIOS usage |
4578 | #define ATOM_S0_CRT1_MONOb0 0x01 |
5153 | #define ATOM_S0_CRT1_MONOb0 0x01 |
4579 | #define ATOM_S0_CRT1_COLORb0 0x02 |
5154 | #define ATOM_S0_CRT1_COLORb0 0x02 |
4580 | #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) |
5155 | #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) |
4581 | 5156 | ||
4582 | #define ATOM_S0_TV1_COMPOSITEb0 0x04 |
5157 | #define ATOM_S0_TV1_COMPOSITEb0 0x04 |
4583 | #define ATOM_S0_TV1_SVIDEOb0 0x08 |
5158 | #define ATOM_S0_TV1_SVIDEOb0 0x08 |
4584 | #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) |
5159 | #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) |
4585 | 5160 | ||
4586 | #define ATOM_S0_CVb0 0x10 |
5161 | #define ATOM_S0_CVb0 0x10 |
4587 | #define ATOM_S0_CV_DINb0 0x20 |
5162 | #define ATOM_S0_CV_DINb0 0x20 |
4588 | #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) |
5163 | #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) |
4589 | 5164 | ||
4590 | #define ATOM_S0_CRT2_MONOb1 0x01 |
5165 | #define ATOM_S0_CRT2_MONOb1 0x01 |
4591 | #define ATOM_S0_CRT2_COLORb1 0x02 |
5166 | #define ATOM_S0_CRT2_COLORb1 0x02 |
4592 | #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) |
5167 | #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) |
4593 | 5168 | ||
4594 | #define ATOM_S0_TV1_COMPOSITEb1 0x04 |
5169 | #define ATOM_S0_TV1_COMPOSITEb1 0x04 |
4595 | #define ATOM_S0_TV1_SVIDEOb1 0x08 |
5170 | #define ATOM_S0_TV1_SVIDEOb1 0x08 |
4596 | #define ATOM_S0_TV1_SCARTb1 0x40 |
5171 | #define ATOM_S0_TV1_SCARTb1 0x40 |
4597 | #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) |
5172 | #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) |
4598 | 5173 | ||
4599 | #define ATOM_S0_CVb1 0x10 |
5174 | #define ATOM_S0_CVb1 0x10 |
4600 | #define ATOM_S0_CV_DINb1 0x20 |
5175 | #define ATOM_S0_CV_DINb1 0x20 |
4601 | #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) |
5176 | #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) |
4602 | 5177 | ||
4603 | #define ATOM_S0_DFP1b2 0x01 |
5178 | #define ATOM_S0_DFP1b2 0x01 |
4604 | #define ATOM_S0_DFP2b2 0x02 |
5179 | #define ATOM_S0_DFP2b2 0x02 |
4605 | #define ATOM_S0_LCD1b2 0x04 |
5180 | #define ATOM_S0_LCD1b2 0x04 |
4606 | #define ATOM_S0_LCD2b2 0x08 |
5181 | #define ATOM_S0_LCD2b2 0x08 |
4607 | #define ATOM_S0_DFP6b2 0x10 |
5182 | #define ATOM_S0_DFP6b2 0x10 |
4608 | #define ATOM_S0_DFP3b2 0x20 |
5183 | #define ATOM_S0_DFP3b2 0x20 |
4609 | #define ATOM_S0_DFP4b2 0x40 |
5184 | #define ATOM_S0_DFP4b2 0x40 |
4610 | #define ATOM_S0_DFP5b2 0x80 |
5185 | #define ATOM_S0_DFP5b2 0x80 |
4611 | 5186 | ||
4612 | 5187 | ||
4613 | #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C |
5188 | #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C |
4614 | #define ATOM_S0_THERMAL_STATE_SHIFTb3 2 |
5189 | #define ATOM_S0_THERMAL_STATE_SHIFTb3 2 |
4615 | 5190 | ||
4616 | #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 |
5191 | #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 |
4617 | #define ATOM_S0_LCD1_SHIFT 18 |
5192 | #define ATOM_S0_LCD1_SHIFT 18 |
4618 | 5193 | ||
4619 | // BIOS_1_SCRATCH Definition |
5194 | // BIOS_1_SCRATCH Definition |
4620 | #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL |
5195 | #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL |
4621 | #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L |
5196 | #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L |
4622 | 5197 | ||
4623 | // BIOS_2_SCRATCH Definition |
5198 | // BIOS_2_SCRATCH Definition |
4624 | #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL |
5199 | #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL |
4625 | #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L |
5200 | #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L |
4626 | #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 |
5201 | #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 |
4627 | 5202 | ||
4628 | #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L |
5203 | #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L |
4629 | #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 |
5204 | #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 |
4630 | #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L |
5205 | #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L |
4631 | 5206 | ||
4632 | #define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L |
5207 | #define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L |
4633 | #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L |
5208 | #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L |
4634 | 5209 | ||
4635 | #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 |
5210 | #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 |
4636 | #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 |
5211 | #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 |
4637 | #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 |
5212 | #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 |
4638 | #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 |
5213 | #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 |
4639 | #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 |
5214 | #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 |
4640 | #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L |
5215 | #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L |
4641 | 5216 | ||
4642 | 5217 | ||
4643 | //Byte aligned definition for BIOS usage |
5218 | //Byte aligned definition for BIOS usage |
4644 | #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F |
5219 | #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F |
4645 | #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF |
5220 | #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF |
4646 | #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 |
5221 | #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 |
4647 | 5222 | ||
4648 | #define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF |
5223 | #define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF |
4649 | #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C |
5224 | #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C |
4650 | #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 |
5225 | #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 |
- | 5226 | #define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode |
|
4651 | #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 |
5227 | #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 |
4652 | #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 |
5228 | #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 |
4653 | 5229 | ||
4654 | 5230 | ||
4655 | // BIOS_3_SCRATCH Definition |
5231 | // BIOS_3_SCRATCH Definition |
4656 | #define ATOM_S3_CRT1_ACTIVE 0x00000001L |
5232 | #define ATOM_S3_CRT1_ACTIVE 0x00000001L |
4657 | #define ATOM_S3_LCD1_ACTIVE 0x00000002L |
5233 | #define ATOM_S3_LCD1_ACTIVE 0x00000002L |
4658 | #define ATOM_S3_TV1_ACTIVE 0x00000004L |
5234 | #define ATOM_S3_TV1_ACTIVE 0x00000004L |
4659 | #define ATOM_S3_DFP1_ACTIVE 0x00000008L |
5235 | #define ATOM_S3_DFP1_ACTIVE 0x00000008L |
4660 | #define ATOM_S3_CRT2_ACTIVE 0x00000010L |
5236 | #define ATOM_S3_CRT2_ACTIVE 0x00000010L |
4661 | #define ATOM_S3_LCD2_ACTIVE 0x00000020L |
5237 | #define ATOM_S3_LCD2_ACTIVE 0x00000020L |
4662 | #define ATOM_S3_DFP6_ACTIVE 0x00000040L |
5238 | #define ATOM_S3_DFP6_ACTIVE 0x00000040L |
4663 | #define ATOM_S3_DFP2_ACTIVE 0x00000080L |
5239 | #define ATOM_S3_DFP2_ACTIVE 0x00000080L |
4664 | #define ATOM_S3_CV_ACTIVE 0x00000100L |
5240 | #define ATOM_S3_CV_ACTIVE 0x00000100L |
4665 | #define ATOM_S3_DFP3_ACTIVE 0x00000200L |
5241 | #define ATOM_S3_DFP3_ACTIVE 0x00000200L |
4666 | #define ATOM_S3_DFP4_ACTIVE 0x00000400L |
5242 | #define ATOM_S3_DFP4_ACTIVE 0x00000400L |
4667 | #define ATOM_S3_DFP5_ACTIVE 0x00000800L |
5243 | #define ATOM_S3_DFP5_ACTIVE 0x00000800L |
4668 | 5244 | ||
4669 | #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL |
5245 | #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL |
4670 | 5246 | ||
4671 | #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L |
5247 | #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L |
4672 | #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L |
5248 | #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L |
4673 | 5249 | ||
4674 | #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L |
5250 | #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L |
4675 | #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L |
5251 | #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L |
4676 | #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L |
5252 | #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L |
4677 | #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L |
5253 | #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L |
4678 | #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L |
5254 | #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L |
4679 | #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L |
5255 | #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L |
4680 | #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L |
5256 | #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L |
4681 | #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L |
5257 | #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L |
4682 | #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L |
5258 | #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L |
4683 | #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L |
5259 | #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L |
4684 | #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L |
5260 | #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L |
4685 | #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L |
5261 | #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L |
4686 | 5262 | ||
4687 | #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L |
5263 | #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L |
4688 | #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L |
5264 | #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L |
4689 | //Below two definitions are not supported in pplib, but in the old powerplay in DAL |
5265 | //Below two definitions are not supported in pplib, but in the old powerplay in DAL |
4690 | #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L |
5266 | #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L |
4691 | #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L |
5267 | #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L |
4692 | 5268 | ||
4693 | //Byte aligned definition for BIOS usage |
5269 | //Byte aligned definition for BIOS usage |
4694 | #define ATOM_S3_CRT1_ACTIVEb0 0x01 |
5270 | #define ATOM_S3_CRT1_ACTIVEb0 0x01 |
4695 | #define ATOM_S3_LCD1_ACTIVEb0 0x02 |
5271 | #define ATOM_S3_LCD1_ACTIVEb0 0x02 |
4696 | #define ATOM_S3_TV1_ACTIVEb0 0x04 |
5272 | #define ATOM_S3_TV1_ACTIVEb0 0x04 |
4697 | #define ATOM_S3_DFP1_ACTIVEb0 0x08 |
5273 | #define ATOM_S3_DFP1_ACTIVEb0 0x08 |
4698 | #define ATOM_S3_CRT2_ACTIVEb0 0x10 |
5274 | #define ATOM_S3_CRT2_ACTIVEb0 0x10 |
4699 | #define ATOM_S3_LCD2_ACTIVEb0 0x20 |
5275 | #define ATOM_S3_LCD2_ACTIVEb0 0x20 |
4700 | #define ATOM_S3_DFP6_ACTIVEb0 0x40 |
5276 | #define ATOM_S3_DFP6_ACTIVEb0 0x40 |
4701 | #define ATOM_S3_DFP2_ACTIVEb0 0x80 |
5277 | #define ATOM_S3_DFP2_ACTIVEb0 0x80 |
4702 | #define ATOM_S3_CV_ACTIVEb1 0x01 |
5278 | #define ATOM_S3_CV_ACTIVEb1 0x01 |
4703 | #define ATOM_S3_DFP3_ACTIVEb1 0x02 |
5279 | #define ATOM_S3_DFP3_ACTIVEb1 0x02 |
4704 | #define ATOM_S3_DFP4_ACTIVEb1 0x04 |
5280 | #define ATOM_S3_DFP4_ACTIVEb1 0x04 |
4705 | #define ATOM_S3_DFP5_ACTIVEb1 0x08 |
5281 | #define ATOM_S3_DFP5_ACTIVEb1 0x08 |
4706 | 5282 | ||
4707 | #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF |
5283 | #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF |
4708 | 5284 | ||
4709 | #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 |
5285 | #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 |
4710 | #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 |
5286 | #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 |
4711 | #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 |
5287 | #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 |
4712 | #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 |
5288 | #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 |
4713 | #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 |
5289 | #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 |
4714 | #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 |
5290 | #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 |
4715 | #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 |
5291 | #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 |
4716 | #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 |
5292 | #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 |
4717 | #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 |
5293 | #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 |
4718 | #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 |
5294 | #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 |
4719 | #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 |
5295 | #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 |
4720 | #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 |
5296 | #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 |
4721 | 5297 | ||
4722 | #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF |
5298 | #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF |
4723 | 5299 | ||
4724 | // BIOS_4_SCRATCH Definition |
5300 | // BIOS_4_SCRATCH Definition |
4725 | #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL |
5301 | #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL |
4726 | #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L |
5302 | #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L |
4727 | #define ATOM_S4_LCD1_REFRESH_SHIFT 8 |
5303 | #define ATOM_S4_LCD1_REFRESH_SHIFT 8 |
4728 | 5304 | ||
4729 | //Byte aligned definition for BIOS usage |
5305 | //Byte aligned definition for BIOS usage |
4730 | #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF |
5306 | #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF |
4731 | #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
5307 | #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
4732 | #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
5308 | #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
4733 | 5309 | ||
4734 | // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! |
5310 | // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! |
4735 | #define ATOM_S5_DOS_REQ_CRT1b0 0x01 |
5311 | #define ATOM_S5_DOS_REQ_CRT1b0 0x01 |
4736 | #define ATOM_S5_DOS_REQ_LCD1b0 0x02 |
5312 | #define ATOM_S5_DOS_REQ_LCD1b0 0x02 |
4737 | #define ATOM_S5_DOS_REQ_TV1b0 0x04 |
5313 | #define ATOM_S5_DOS_REQ_TV1b0 0x04 |
4738 | #define ATOM_S5_DOS_REQ_DFP1b0 0x08 |
5314 | #define ATOM_S5_DOS_REQ_DFP1b0 0x08 |
4739 | #define ATOM_S5_DOS_REQ_CRT2b0 0x10 |
5315 | #define ATOM_S5_DOS_REQ_CRT2b0 0x10 |
4740 | #define ATOM_S5_DOS_REQ_LCD2b0 0x20 |
5316 | #define ATOM_S5_DOS_REQ_LCD2b0 0x20 |
4741 | #define ATOM_S5_DOS_REQ_DFP6b0 0x40 |
5317 | #define ATOM_S5_DOS_REQ_DFP6b0 0x40 |
4742 | #define ATOM_S5_DOS_REQ_DFP2b0 0x80 |
5318 | #define ATOM_S5_DOS_REQ_DFP2b0 0x80 |
4743 | #define ATOM_S5_DOS_REQ_CVb1 0x01 |
5319 | #define ATOM_S5_DOS_REQ_CVb1 0x01 |
4744 | #define ATOM_S5_DOS_REQ_DFP3b1 0x02 |
5320 | #define ATOM_S5_DOS_REQ_DFP3b1 0x02 |
4745 | #define ATOM_S5_DOS_REQ_DFP4b1 0x04 |
5321 | #define ATOM_S5_DOS_REQ_DFP4b1 0x04 |
4746 | #define ATOM_S5_DOS_REQ_DFP5b1 0x08 |
5322 | #define ATOM_S5_DOS_REQ_DFP5b1 0x08 |
4747 | 5323 | ||
4748 | #define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF |
5324 | #define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF |
4749 | 5325 | ||
4750 | #define ATOM_S5_DOS_REQ_CRT1 0x0001 |
5326 | #define ATOM_S5_DOS_REQ_CRT1 0x0001 |
4751 | #define ATOM_S5_DOS_REQ_LCD1 0x0002 |
5327 | #define ATOM_S5_DOS_REQ_LCD1 0x0002 |
4752 | #define ATOM_S5_DOS_REQ_TV1 0x0004 |
5328 | #define ATOM_S5_DOS_REQ_TV1 0x0004 |
4753 | #define ATOM_S5_DOS_REQ_DFP1 0x0008 |
5329 | #define ATOM_S5_DOS_REQ_DFP1 0x0008 |
4754 | #define ATOM_S5_DOS_REQ_CRT2 0x0010 |
5330 | #define ATOM_S5_DOS_REQ_CRT2 0x0010 |
4755 | #define ATOM_S5_DOS_REQ_LCD2 0x0020 |
5331 | #define ATOM_S5_DOS_REQ_LCD2 0x0020 |
4756 | #define ATOM_S5_DOS_REQ_DFP6 0x0040 |
5332 | #define ATOM_S5_DOS_REQ_DFP6 0x0040 |
4757 | #define ATOM_S5_DOS_REQ_DFP2 0x0080 |
5333 | #define ATOM_S5_DOS_REQ_DFP2 0x0080 |
4758 | #define ATOM_S5_DOS_REQ_CV 0x0100 |
5334 | #define ATOM_S5_DOS_REQ_CV 0x0100 |
4759 | #define ATOM_S5_DOS_REQ_DFP3 0x0200 |
5335 | #define ATOM_S5_DOS_REQ_DFP3 0x0200 |
4760 | #define ATOM_S5_DOS_REQ_DFP4 0x0400 |
5336 | #define ATOM_S5_DOS_REQ_DFP4 0x0400 |
4761 | #define ATOM_S5_DOS_REQ_DFP5 0x0800 |
5337 | #define ATOM_S5_DOS_REQ_DFP5 0x0800 |
4762 | 5338 | ||
4763 | #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 |
5339 | #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 |
4764 | #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 |
5340 | #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 |
4765 | #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 |
5341 | #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 |
4766 | #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 |
5342 | #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 |
4767 | #define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ |
5343 | #define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ |
4768 | (ATOM_S5_DOS_FORCE_CVb3<<8)) |
5344 | (ATOM_S5_DOS_FORCE_CVb3<<8)) |
4769 | 5345 | ||
4770 | // BIOS_6_SCRATCH Definition |
5346 | // BIOS_6_SCRATCH Definition |
4771 | #define ATOM_S6_DEVICE_CHANGE 0x00000001L |
5347 | #define ATOM_S6_DEVICE_CHANGE 0x00000001L |
4772 | #define ATOM_S6_SCALER_CHANGE 0x00000002L |
5348 | #define ATOM_S6_SCALER_CHANGE 0x00000002L |
4773 | #define ATOM_S6_LID_CHANGE 0x00000004L |
5349 | #define ATOM_S6_LID_CHANGE 0x00000004L |
4774 | #define ATOM_S6_DOCKING_CHANGE 0x00000008L |
5350 | #define ATOM_S6_DOCKING_CHANGE 0x00000008L |
4775 | #define ATOM_S6_ACC_MODE 0x00000010L |
5351 | #define ATOM_S6_ACC_MODE 0x00000010L |
4776 | #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L |
5352 | #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L |
4777 | #define ATOM_S6_LID_STATE 0x00000040L |
5353 | #define ATOM_S6_LID_STATE 0x00000040L |
4778 | #define ATOM_S6_DOCK_STATE 0x00000080L |
5354 | #define ATOM_S6_DOCK_STATE 0x00000080L |
4779 | #define ATOM_S6_CRITICAL_STATE 0x00000100L |
5355 | #define ATOM_S6_CRITICAL_STATE 0x00000100L |
4780 | #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L |
5356 | #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L |
4781 | #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L |
5357 | #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L |
4782 | #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L |
5358 | #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L |
4783 | #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD |
5359 | #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD |
4784 | #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD |
5360 | #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD |
4785 | 5361 | ||
4786 | #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion |
5362 | #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion |
4787 | #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion |
5363 | #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion |
4788 | 5364 | ||
4789 | #define ATOM_S6_ACC_REQ_CRT1 0x00010000L |
5365 | #define ATOM_S6_ACC_REQ_CRT1 0x00010000L |
4790 | #define ATOM_S6_ACC_REQ_LCD1 0x00020000L |
5366 | #define ATOM_S6_ACC_REQ_LCD1 0x00020000L |
4791 | #define ATOM_S6_ACC_REQ_TV1 0x00040000L |
5367 | #define ATOM_S6_ACC_REQ_TV1 0x00040000L |
4792 | #define ATOM_S6_ACC_REQ_DFP1 0x00080000L |
5368 | #define ATOM_S6_ACC_REQ_DFP1 0x00080000L |
4793 | #define ATOM_S6_ACC_REQ_CRT2 0x00100000L |
5369 | #define ATOM_S6_ACC_REQ_CRT2 0x00100000L |
4794 | #define ATOM_S6_ACC_REQ_LCD2 0x00200000L |
5370 | #define ATOM_S6_ACC_REQ_LCD2 0x00200000L |
4795 | #define ATOM_S6_ACC_REQ_DFP6 0x00400000L |
5371 | #define ATOM_S6_ACC_REQ_DFP6 0x00400000L |
4796 | #define ATOM_S6_ACC_REQ_DFP2 0x00800000L |
5372 | #define ATOM_S6_ACC_REQ_DFP2 0x00800000L |
4797 | #define ATOM_S6_ACC_REQ_CV 0x01000000L |
5373 | #define ATOM_S6_ACC_REQ_CV 0x01000000L |
4798 | #define ATOM_S6_ACC_REQ_DFP3 0x02000000L |
5374 | #define ATOM_S6_ACC_REQ_DFP3 0x02000000L |
4799 | #define ATOM_S6_ACC_REQ_DFP4 0x04000000L |
5375 | #define ATOM_S6_ACC_REQ_DFP4 0x04000000L |
4800 | #define ATOM_S6_ACC_REQ_DFP5 0x08000000L |
5376 | #define ATOM_S6_ACC_REQ_DFP5 0x08000000L |
4801 | 5377 | ||
4802 | #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L |
5378 | #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L |
4803 | #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L |
5379 | #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L |
4804 | #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L |
5380 | #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L |
4805 | #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L |
5381 | #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L |
4806 | #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L |
5382 | #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L |
4807 | 5383 | ||
4808 | //Byte aligned definition for BIOS usage |
5384 | //Byte aligned definition for BIOS usage |
4809 | #define ATOM_S6_DEVICE_CHANGEb0 0x01 |
5385 | #define ATOM_S6_DEVICE_CHANGEb0 0x01 |
4810 | #define ATOM_S6_SCALER_CHANGEb0 0x02 |
5386 | #define ATOM_S6_SCALER_CHANGEb0 0x02 |
4811 | #define ATOM_S6_LID_CHANGEb0 0x04 |
5387 | #define ATOM_S6_LID_CHANGEb0 0x04 |
4812 | #define ATOM_S6_DOCKING_CHANGEb0 0x08 |
5388 | #define ATOM_S6_DOCKING_CHANGEb0 0x08 |
4813 | #define ATOM_S6_ACC_MODEb0 0x10 |
5389 | #define ATOM_S6_ACC_MODEb0 0x10 |
4814 | #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 |
5390 | #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 |
4815 | #define ATOM_S6_LID_STATEb0 0x40 |
5391 | #define ATOM_S6_LID_STATEb0 0x40 |
4816 | #define ATOM_S6_DOCK_STATEb0 0x80 |
5392 | #define ATOM_S6_DOCK_STATEb0 0x80 |
4817 | #define ATOM_S6_CRITICAL_STATEb1 0x01 |
5393 | #define ATOM_S6_CRITICAL_STATEb1 0x01 |
4818 | #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 |
5394 | #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 |
4819 | #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 |
5395 | #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 |
4820 | #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 |
5396 | #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 |
4821 | #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 |
5397 | #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 |
4822 | #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 |
5398 | #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 |
4823 | 5399 | ||
4824 | #define ATOM_S6_ACC_REQ_CRT1b2 0x01 |
5400 | #define ATOM_S6_ACC_REQ_CRT1b2 0x01 |
4825 | #define ATOM_S6_ACC_REQ_LCD1b2 0x02 |
5401 | #define ATOM_S6_ACC_REQ_LCD1b2 0x02 |
4826 | #define ATOM_S6_ACC_REQ_TV1b2 0x04 |
5402 | #define ATOM_S6_ACC_REQ_TV1b2 0x04 |
4827 | #define ATOM_S6_ACC_REQ_DFP1b2 0x08 |
5403 | #define ATOM_S6_ACC_REQ_DFP1b2 0x08 |
4828 | #define ATOM_S6_ACC_REQ_CRT2b2 0x10 |
5404 | #define ATOM_S6_ACC_REQ_CRT2b2 0x10 |
4829 | #define ATOM_S6_ACC_REQ_LCD2b2 0x20 |
5405 | #define ATOM_S6_ACC_REQ_LCD2b2 0x20 |
4830 | #define ATOM_S6_ACC_REQ_DFP6b2 0x40 |
5406 | #define ATOM_S6_ACC_REQ_DFP6b2 0x40 |
4831 | #define ATOM_S6_ACC_REQ_DFP2b2 0x80 |
5407 | #define ATOM_S6_ACC_REQ_DFP2b2 0x80 |
4832 | #define ATOM_S6_ACC_REQ_CVb3 0x01 |
5408 | #define ATOM_S6_ACC_REQ_CVb3 0x01 |
4833 | #define ATOM_S6_ACC_REQ_DFP3b3 0x02 |
5409 | #define ATOM_S6_ACC_REQ_DFP3b3 0x02 |
4834 | #define ATOM_S6_ACC_REQ_DFP4b3 0x04 |
5410 | #define ATOM_S6_ACC_REQ_DFP4b3 0x04 |
4835 | #define ATOM_S6_ACC_REQ_DFP5b3 0x08 |
5411 | #define ATOM_S6_ACC_REQ_DFP5b3 0x08 |
4836 | 5412 | ||
4837 | #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 |
5413 | #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 |
4838 | #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 |
5414 | #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 |
4839 | #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 |
5415 | #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 |
4840 | #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 |
5416 | #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 |
4841 | #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 |
5417 | #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 |
4842 | 5418 | ||
4843 | #define ATOM_S6_DEVICE_CHANGE_SHIFT 0 |
5419 | #define ATOM_S6_DEVICE_CHANGE_SHIFT 0 |
4844 | #define ATOM_S6_SCALER_CHANGE_SHIFT 1 |
5420 | #define ATOM_S6_SCALER_CHANGE_SHIFT 1 |
4845 | #define ATOM_S6_LID_CHANGE_SHIFT 2 |
5421 | #define ATOM_S6_LID_CHANGE_SHIFT 2 |
4846 | #define ATOM_S6_DOCKING_CHANGE_SHIFT 3 |
5422 | #define ATOM_S6_DOCKING_CHANGE_SHIFT 3 |
4847 | #define ATOM_S6_ACC_MODE_SHIFT 4 |
5423 | #define ATOM_S6_ACC_MODE_SHIFT 4 |
4848 | #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 |
5424 | #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 |
4849 | #define ATOM_S6_LID_STATE_SHIFT 6 |
5425 | #define ATOM_S6_LID_STATE_SHIFT 6 |
4850 | #define ATOM_S6_DOCK_STATE_SHIFT 7 |
5426 | #define ATOM_S6_DOCK_STATE_SHIFT 7 |
4851 | #define ATOM_S6_CRITICAL_STATE_SHIFT 8 |
5427 | #define ATOM_S6_CRITICAL_STATE_SHIFT 8 |
4852 | #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 |
5428 | #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 |
4853 | #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 |
5429 | #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 |
4854 | #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 |
5430 | #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 |
4855 | #define ATOM_S6_REQ_SCALER_SHIFT 12 |
5431 | #define ATOM_S6_REQ_SCALER_SHIFT 12 |
4856 | #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 |
5432 | #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 |
4857 | #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 |
5433 | #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 |
4858 | #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 |
5434 | #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 |
4859 | #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 |
5435 | #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 |
4860 | #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 |
5436 | #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 |
4861 | #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 |
5437 | #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 |
4862 | #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 |
5438 | #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 |
4863 | 5439 | ||
4864 | // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! |
5440 | // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! |
4865 | #define ATOM_S7_DOS_MODE_TYPEb0 0x03 |
5441 | #define ATOM_S7_DOS_MODE_TYPEb0 0x03 |
4866 | #define ATOM_S7_DOS_MODE_VGAb0 0x00 |
5442 | #define ATOM_S7_DOS_MODE_VGAb0 0x00 |
4867 | #define ATOM_S7_DOS_MODE_VESAb0 0x01 |
5443 | #define ATOM_S7_DOS_MODE_VESAb0 0x01 |
4868 | #define ATOM_S7_DOS_MODE_EXTb0 0x02 |
5444 | #define ATOM_S7_DOS_MODE_EXTb0 0x02 |
4869 | #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C |
5445 | #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C |
4870 | #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 |
5446 | #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 |
4871 | #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 |
5447 | #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 |
4872 | #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF |
5448 | #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF |
4873 | 5449 | ||
4874 | #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 |
5450 | #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 |
4875 | 5451 | ||
4876 | // BIOS_8_SCRATCH Definition |
5452 | // BIOS_8_SCRATCH Definition |
4877 | #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF |
5453 | #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF |
4878 | #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 |
5454 | #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 |
4879 | 5455 | ||
4880 | #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 |
5456 | #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 |
4881 | #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 |
5457 | #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 |
4882 | 5458 | ||
4883 | // BIOS_9_SCRATCH Definition |
5459 | // BIOS_9_SCRATCH Definition |
4884 | #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK |
5460 | #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK |
4885 | #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF |
5461 | #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF |
4886 | #endif |
5462 | #endif |
4887 | #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK |
5463 | #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK |
4888 | #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 |
5464 | #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 |
4889 | #endif |
5465 | #endif |
4890 | #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT |
5466 | #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT |
4891 | #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 |
5467 | #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 |
4892 | #endif |
5468 | #endif |
4893 | #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT |
5469 | #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT |
4894 | #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 |
5470 | #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 |
4895 | #endif |
5471 | #endif |
4896 | 5472 | ||
4897 | 5473 | ||
4898 | #define ATOM_FLAG_SET 0x20 |
5474 | #define ATOM_FLAG_SET 0x20 |
4899 | #define ATOM_FLAG_CLEAR 0 |
5475 | #define ATOM_FLAG_CLEAR 0 |
4900 | #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) |
5476 | #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) |
4901 | #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) |
5477 | #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) |
4902 | #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) |
5478 | #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) |
4903 | #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) |
5479 | #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) |
4904 | #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) |
5480 | #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) |
4905 | 5481 | ||
4906 | #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) |
5482 | #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) |
4907 | #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) |
5483 | #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) |
4908 | 5484 | ||
4909 | #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) |
5485 | #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) |
4910 | #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) |
5486 | #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) |
4911 | #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) |
5487 | #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) |
4912 | 5488 | ||
4913 | #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) |
5489 | #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) |
4914 | #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) |
5490 | #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) |
4915 | #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) |
5491 | #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) |
4916 | 5492 | ||
4917 | #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) |
5493 | #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) |
4918 | #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) |
5494 | #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) |
4919 | 5495 | ||
4920 | #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) |
5496 | #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) |
4921 | #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) |
5497 | #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) |
4922 | 5498 | ||
4923 | #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) |
5499 | #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) |
4924 | #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) |
5500 | #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) |
4925 | 5501 | ||
4926 | #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) |
5502 | #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) |
4927 | 5503 | ||
4928 | #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) |
5504 | #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) |
4929 | 5505 | ||
4930 | #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) |
5506 | #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) |
4931 | #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) |
5507 | #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) |
4932 | #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) |
5508 | #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) |
4933 | #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) |
5509 | #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) |
4934 | 5510 | ||
4935 | /****************************************************************************/ |
5511 | /****************************************************************************/ |
4936 | //Portion II: Definitinos only used in Driver |
5512 | //Portion II: Definitinos only used in Driver |
4937 | /****************************************************************************/ |
5513 | /****************************************************************************/ |
4938 | 5514 | ||
4939 | // Macros used by driver |
5515 | // Macros used by driver |
4940 | #ifdef __cplusplus |
5516 | #ifdef __cplusplus |
4941 | #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast |
5517 | #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast |
4942 | 5518 | ||
4943 | #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast |
5519 | #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast |
4944 | #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast |
5520 | #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast |
4945 | #else // not __cplusplus |
5521 | #else // not __cplusplus |
4946 | #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) |
5522 | #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) |
4947 | 5523 | ||
4948 | #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) |
5524 | #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) |
4949 | #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) |
5525 | #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) |
4950 | #endif // __cplusplus |
5526 | #endif // __cplusplus |
4951 | 5527 | ||
4952 | #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION |
5528 | #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION |
4953 | #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION |
5529 | #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION |
4954 | 5530 | ||
4955 | /****************************************************************************/ |
5531 | /****************************************************************************/ |
4956 | //Portion III: Definitinos only used in VBIOS |
5532 | //Portion III: Definitinos only used in VBIOS |
4957 | /****************************************************************************/ |
5533 | /****************************************************************************/ |
4958 | #define ATOM_DAC_SRC 0x80 |
5534 | #define ATOM_DAC_SRC 0x80 |
4959 | #define ATOM_SRC_DAC1 0 |
5535 | #define ATOM_SRC_DAC1 0 |
4960 | #define ATOM_SRC_DAC2 0x80 |
5536 | #define ATOM_SRC_DAC2 0x80 |
4961 | 5537 | ||
4962 | typedef struct _MEMORY_PLLINIT_PARAMETERS |
5538 | typedef struct _MEMORY_PLLINIT_PARAMETERS |
4963 | { |
5539 | { |
4964 | ULONG ulTargetMemoryClock; //In 10Khz unit |
5540 | ULONG ulTargetMemoryClock; //In 10Khz unit |
4965 | UCHAR ucAction; //not define yet |
5541 | UCHAR ucAction; //not define yet |
4966 | UCHAR ucFbDiv_Hi; //Fbdiv Hi byte |
5542 | UCHAR ucFbDiv_Hi; //Fbdiv Hi byte |
4967 | UCHAR ucFbDiv; //FB value |
5543 | UCHAR ucFbDiv; //FB value |
4968 | UCHAR ucPostDiv; //Post div |
5544 | UCHAR ucPostDiv; //Post div |
4969 | }MEMORY_PLLINIT_PARAMETERS; |
5545 | }MEMORY_PLLINIT_PARAMETERS; |
4970 | 5546 | ||
4971 | #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS |
5547 | #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS |
4972 | 5548 | ||
4973 | 5549 | ||
4974 | #define GPIO_PIN_WRITE 0x01 |
5550 | #define GPIO_PIN_WRITE 0x01 |
4975 | #define GPIO_PIN_READ 0x00 |
5551 | #define GPIO_PIN_READ 0x00 |
4976 | 5552 | ||
4977 | typedef struct _GPIO_PIN_CONTROL_PARAMETERS |
5553 | typedef struct _GPIO_PIN_CONTROL_PARAMETERS |
4978 | { |
5554 | { |
4979 | UCHAR ucGPIO_ID; //return value, read from GPIO pins |
5555 | UCHAR ucGPIO_ID; //return value, read from GPIO pins |
4980 | UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update |
5556 | UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update |
4981 | UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask |
5557 | UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask |
4982 | UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write |
5558 | UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write |
4983 | }GPIO_PIN_CONTROL_PARAMETERS; |
5559 | }GPIO_PIN_CONTROL_PARAMETERS; |
4984 | 5560 | ||
4985 | typedef struct _ENABLE_SCALER_PARAMETERS |
5561 | typedef struct _ENABLE_SCALER_PARAMETERS |
4986 | { |
5562 | { |
4987 | UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 |
5563 | UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 |
4988 | UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION |
5564 | UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION |
4989 | UCHAR ucTVStandard; // |
5565 | UCHAR ucTVStandard; // |
4990 | UCHAR ucPadding[1]; |
5566 | UCHAR ucPadding[1]; |
4991 | }ENABLE_SCALER_PARAMETERS; |
5567 | }ENABLE_SCALER_PARAMETERS; |
4992 | #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS |
5568 | #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS |
4993 | 5569 | ||
4994 | //ucEnable: |
5570 | //ucEnable: |
4995 | #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 |
5571 | #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 |
4996 | #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 |
5572 | #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 |
4997 | #define SCALER_ENABLE_2TAP_ALPHA_MODE 2 |
5573 | #define SCALER_ENABLE_2TAP_ALPHA_MODE 2 |
4998 | #define SCALER_ENABLE_MULTITAP_MODE 3 |
5574 | #define SCALER_ENABLE_MULTITAP_MODE 3 |
4999 | 5575 | ||
5000 | typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS |
5576 | typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS |
5001 | { |
5577 | { |
5002 | ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position |
5578 | ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position |
5003 | UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset |
5579 | UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset |
5004 | UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset |
5580 | UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset |
5005 | UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 |
5581 | UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 |
5006 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
5582 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
5007 | }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; |
5583 | }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; |
5008 | 5584 | ||
5009 | typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION |
5585 | typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION |
5010 | { |
5586 | { |
5011 | ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; |
5587 | ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; |
5012 | ENABLE_CRTC_PARAMETERS sReserved; |
5588 | ENABLE_CRTC_PARAMETERS sReserved; |
5013 | }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; |
5589 | }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; |
5014 | 5590 | ||
5015 | typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS |
5591 | typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS |
5016 | { |
5592 | { |
5017 | USHORT usHight; // Image Hight |
5593 | USHORT usHight; // Image Hight |
5018 | USHORT usWidth; // Image Width |
5594 | USHORT usWidth; // Image Width |
5019 | UCHAR ucSurface; // Surface 1 or 2 |
5595 | UCHAR ucSurface; // Surface 1 or 2 |
5020 | UCHAR ucPadding[3]; |
5596 | UCHAR ucPadding[3]; |
5021 | }ENABLE_GRAPH_SURFACE_PARAMETERS; |
5597 | }ENABLE_GRAPH_SURFACE_PARAMETERS; |
5022 | 5598 | ||
5023 | typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 |
5599 | typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 |
5024 | { |
5600 | { |
5025 | USHORT usHight; // Image Hight |
5601 | USHORT usHight; // Image Hight |
5026 | USHORT usWidth; // Image Width |
5602 | USHORT usWidth; // Image Width |
5027 | UCHAR ucSurface; // Surface 1 or 2 |
5603 | UCHAR ucSurface; // Surface 1 or 2 |
5028 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
5604 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
5029 | UCHAR ucPadding[2]; |
5605 | UCHAR ucPadding[2]; |
5030 | }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; |
5606 | }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; |
5031 | 5607 | ||
5032 | typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 |
5608 | typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 |
5033 | { |
5609 | { |
5034 | USHORT usHight; // Image Hight |
5610 | USHORT usHight; // Image Hight |
5035 | USHORT usWidth; // Image Width |
5611 | USHORT usWidth; // Image Width |
5036 | UCHAR ucSurface; // Surface 1 or 2 |
5612 | UCHAR ucSurface; // Surface 1 or 2 |
5037 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
5613 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
5038 | USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. |
5614 | USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. |
5039 | }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; |
5615 | }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; |
- | 5616 | ||
- | 5617 | typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 |
|
- | 5618 | { |
|
- | 5619 | USHORT usHight; // Image Hight |
|
- | 5620 | USHORT usWidth; // Image Width |
|
- | 5621 | USHORT usGraphPitch; |
|
- | 5622 | UCHAR ucColorDepth; |
|
- | 5623 | UCHAR ucPixelFormat; |
|
- | 5624 | UCHAR ucSurface; // Surface 1 or 2 |
|
- | 5625 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE |
|
- | 5626 | UCHAR ucModeType; |
|
- | 5627 | UCHAR ucReserved; |
|
- | 5628 | }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; |
|
- | 5629 | ||
- | 5630 | // ucEnable |
|
- | 5631 | #define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f |
|
- | 5632 | #define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 |
|
5040 | 5633 | ||
5041 | typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION |
5634 | typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION |
5042 | { |
5635 | { |
5043 | ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; |
5636 | ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; |
5044 | ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one |
5637 | ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one |
5045 | }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; |
5638 | }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; |
5046 | 5639 | ||
5047 | typedef struct _MEMORY_CLEAN_UP_PARAMETERS |
5640 | typedef struct _MEMORY_CLEAN_UP_PARAMETERS |
5048 | { |
5641 | { |
5049 | USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address |
5642 | USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address |
5050 | USHORT usMemorySize; //8Kb blocks aligned |
5643 | USHORT usMemorySize; //8Kb blocks aligned |
5051 | }MEMORY_CLEAN_UP_PARAMETERS; |
5644 | }MEMORY_CLEAN_UP_PARAMETERS; |
5052 | #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS |
5645 | #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS |
5053 | 5646 | ||
5054 | typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS |
5647 | typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS |
5055 | { |
5648 | { |
5056 | USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC |
5649 | USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC |
5057 | USHORT usY_Size; |
5650 | USHORT usY_Size; |
5058 | }GET_DISPLAY_SURFACE_SIZE_PARAMETERS; |
5651 | }GET_DISPLAY_SURFACE_SIZE_PARAMETERS; |
- | 5652 | ||
- | 5653 | typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 |
|
- | 5654 | { |
|
- | 5655 | union{ |
|
- | 5656 | USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC |
|
- | 5657 | USHORT usSurface; |
|
- | 5658 | }; |
|
- | 5659 | USHORT usY_Size; |
|
- | 5660 | USHORT usDispXStart; |
|
- | 5661 | USHORT usDispYStart; |
|
- | 5662 | }GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; |
|
- | 5663 | ||
- | 5664 | ||
- | 5665 | typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 |
|
- | 5666 | { |
|
- | 5667 | UCHAR ucLutId; |
|
- | 5668 | UCHAR ucAction; |
|
- | 5669 | USHORT usLutStartIndex; |
|
- | 5670 | USHORT usLutLength; |
|
- | 5671 | USHORT usLutOffsetInVram; |
|
- | 5672 | }PALETTE_DATA_CONTROL_PARAMETERS_V3; |
|
- | 5673 | ||
- | 5674 | // ucAction: |
|
- | 5675 | #define PALETTE_DATA_AUTO_FILL 1 |
|
- | 5676 | #define PALETTE_DATA_READ 2 |
|
- | 5677 | #define PALETTE_DATA_WRITE 3 |
|
- | 5678 | ||
- | 5679 | ||
- | 5680 | typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 |
|
- | 5681 | { |
|
- | 5682 | UCHAR ucInterruptId; |
|
- | 5683 | UCHAR ucServiceId; |
|
- | 5684 | UCHAR ucStatus; |
|
- | 5685 | UCHAR ucReserved; |
|
- | 5686 | }INTERRUPT_SERVICE_PARAMETER_V2; |
|
- | 5687 | ||
- | 5688 | // ucInterruptId |
|
- | 5689 | #define HDP1_INTERRUPT_ID 1 |
|
- | 5690 | #define HDP2_INTERRUPT_ID 2 |
|
- | 5691 | #define HDP3_INTERRUPT_ID 3 |
|
- | 5692 | #define HDP4_INTERRUPT_ID 4 |
|
- | 5693 | #define HDP5_INTERRUPT_ID 5 |
|
- | 5694 | #define HDP6_INTERRUPT_ID 6 |
|
- | 5695 | #define SW_INTERRUPT_ID 11 |
|
- | 5696 | ||
- | 5697 | // ucAction |
|
- | 5698 | #define INTERRUPT_SERVICE_GEN_SW_INT 1 |
|
- | 5699 | #define INTERRUPT_SERVICE_GET_STATUS 2 |
|
- | 5700 | ||
- | 5701 | // ucStatus |
|
- | 5702 | #define INTERRUPT_STATUS__INT_TRIGGER 1 |
|
- | 5703 | #define INTERRUPT_STATUS__HPD_HIGH 2 |
|
5059 | 5704 | ||
5060 | typedef struct _INDIRECT_IO_ACCESS |
5705 | typedef struct _INDIRECT_IO_ACCESS |
5061 | { |
5706 | { |
5062 | ATOM_COMMON_TABLE_HEADER sHeader; |
5707 | ATOM_COMMON_TABLE_HEADER sHeader; |
5063 | UCHAR IOAccessSequence[256]; |
5708 | UCHAR IOAccessSequence[256]; |
5064 | } INDIRECT_IO_ACCESS; |
5709 | } INDIRECT_IO_ACCESS; |
5065 | 5710 | ||
5066 | #define INDIRECT_READ 0x00 |
5711 | #define INDIRECT_READ 0x00 |
5067 | #define INDIRECT_WRITE 0x80 |
5712 | #define INDIRECT_WRITE 0x80 |
5068 | 5713 | ||
5069 | #define INDIRECT_IO_MM 0 |
5714 | #define INDIRECT_IO_MM 0 |
5070 | #define INDIRECT_IO_PLL 1 |
5715 | #define INDIRECT_IO_PLL 1 |
5071 | #define INDIRECT_IO_MC 2 |
5716 | #define INDIRECT_IO_MC 2 |
5072 | #define INDIRECT_IO_PCIE 3 |
5717 | #define INDIRECT_IO_PCIE 3 |
5073 | #define INDIRECT_IO_PCIEP 4 |
5718 | #define INDIRECT_IO_PCIEP 4 |
5074 | #define INDIRECT_IO_NBMISC 5 |
5719 | #define INDIRECT_IO_NBMISC 5 |
5075 | 5720 | ||
5076 | #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ |
5721 | #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ |
5077 | #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE |
5722 | #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE |
5078 | #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ |
5723 | #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ |
5079 | #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE |
5724 | #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE |
5080 | #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ |
5725 | #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ |
5081 | #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE |
5726 | #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE |
5082 | #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ |
5727 | #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ |
5083 | #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE |
5728 | #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE |
5084 | #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ |
5729 | #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ |
5085 | #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE |
5730 | #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE |
5086 | 5731 | ||
5087 | typedef struct _ATOM_OEM_INFO |
5732 | typedef struct _ATOM_OEM_INFO |
5088 | { |
5733 | { |
5089 | ATOM_COMMON_TABLE_HEADER sHeader; |
5734 | ATOM_COMMON_TABLE_HEADER sHeader; |
5090 | ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; |
5735 | ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; |
5091 | }ATOM_OEM_INFO; |
5736 | }ATOM_OEM_INFO; |
5092 | 5737 | ||
5093 | typedef struct _ATOM_TV_MODE |
5738 | typedef struct _ATOM_TV_MODE |
5094 | { |
5739 | { |
5095 | UCHAR ucVMode_Num; //Video mode number |
5740 | UCHAR ucVMode_Num; //Video mode number |
5096 | UCHAR ucTV_Mode_Num; //Internal TV mode number |
5741 | UCHAR ucTV_Mode_Num; //Internal TV mode number |
5097 | }ATOM_TV_MODE; |
5742 | }ATOM_TV_MODE; |
5098 | 5743 | ||
5099 | typedef struct _ATOM_BIOS_INT_TVSTD_MODE |
5744 | typedef struct _ATOM_BIOS_INT_TVSTD_MODE |
5100 | { |
5745 | { |
5101 | ATOM_COMMON_TABLE_HEADER sHeader; |
5746 | ATOM_COMMON_TABLE_HEADER sHeader; |
5102 | USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table |
5747 | USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table |
5103 | USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table |
5748 | USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table |
5104 | USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table |
5749 | USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table |
5105 | USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table |
5750 | USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table |
5106 | USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table |
5751 | USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table |
5107 | }ATOM_BIOS_INT_TVSTD_MODE; |
5752 | }ATOM_BIOS_INT_TVSTD_MODE; |
5108 | 5753 | ||
5109 | 5754 | ||
5110 | typedef struct _ATOM_TV_MODE_SCALER_PTR |
5755 | typedef struct _ATOM_TV_MODE_SCALER_PTR |
5111 | { |
5756 | { |
5112 | USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients |
5757 | USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients |
5113 | USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients |
5758 | USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients |
5114 | UCHAR ucTV_Mode_Num; |
5759 | UCHAR ucTV_Mode_Num; |
5115 | }ATOM_TV_MODE_SCALER_PTR; |
5760 | }ATOM_TV_MODE_SCALER_PTR; |
5116 | 5761 | ||
5117 | typedef struct _ATOM_STANDARD_VESA_TIMING |
5762 | typedef struct _ATOM_STANDARD_VESA_TIMING |
5118 | { |
5763 | { |
5119 | ATOM_COMMON_TABLE_HEADER sHeader; |
5764 | ATOM_COMMON_TABLE_HEADER sHeader; |
5120 | ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation |
5765 | ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation |
5121 | }ATOM_STANDARD_VESA_TIMING; |
5766 | }ATOM_STANDARD_VESA_TIMING; |
5122 | 5767 | ||
5123 | 5768 | ||
5124 | typedef struct _ATOM_STD_FORMAT |
5769 | typedef struct _ATOM_STD_FORMAT |
5125 | { |
5770 | { |
5126 | USHORT usSTD_HDisp; |
5771 | USHORT usSTD_HDisp; |
5127 | USHORT usSTD_VDisp; |
5772 | USHORT usSTD_VDisp; |
5128 | USHORT usSTD_RefreshRate; |
5773 | USHORT usSTD_RefreshRate; |
5129 | USHORT usReserved; |
5774 | USHORT usReserved; |
5130 | }ATOM_STD_FORMAT; |
5775 | }ATOM_STD_FORMAT; |
5131 | 5776 | ||
5132 | typedef struct _ATOM_VESA_TO_EXTENDED_MODE |
5777 | typedef struct _ATOM_VESA_TO_EXTENDED_MODE |
5133 | { |
5778 | { |
5134 | USHORT usVESA_ModeNumber; |
5779 | USHORT usVESA_ModeNumber; |
5135 | USHORT usExtendedModeNumber; |
5780 | USHORT usExtendedModeNumber; |
5136 | }ATOM_VESA_TO_EXTENDED_MODE; |
5781 | }ATOM_VESA_TO_EXTENDED_MODE; |
5137 | 5782 | ||
5138 | typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT |
5783 | typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT |
5139 | { |
5784 | { |
5140 | ATOM_COMMON_TABLE_HEADER sHeader; |
5785 | ATOM_COMMON_TABLE_HEADER sHeader; |
5141 | ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; |
5786 | ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; |
5142 | }ATOM_VESA_TO_INTENAL_MODE_LUT; |
5787 | }ATOM_VESA_TO_INTENAL_MODE_LUT; |
5143 | 5788 | ||
5144 | /*************** ATOM Memory Related Data Structure ***********************/ |
5789 | /*************** ATOM Memory Related Data Structure ***********************/ |
5145 | typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ |
5790 | typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ |
5146 | UCHAR ucMemoryType; |
5791 | UCHAR ucMemoryType; |
5147 | UCHAR ucMemoryVendor; |
5792 | UCHAR ucMemoryVendor; |
5148 | UCHAR ucAdjMCId; |
5793 | UCHAR ucAdjMCId; |
5149 | UCHAR ucDynClkId; |
5794 | UCHAR ucDynClkId; |
5150 | ULONG ulDllResetClkRange; |
5795 | ULONG ulDllResetClkRange; |
5151 | }ATOM_MEMORY_VENDOR_BLOCK; |
5796 | }ATOM_MEMORY_VENDOR_BLOCK; |
5152 | 5797 | ||
5153 | 5798 | ||
5154 | typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ |
5799 | typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ |
5155 | #if ATOM_BIG_ENDIAN |
5800 | #if ATOM_BIG_ENDIAN |
5156 | ULONG ucMemBlkId:8; |
5801 | ULONG ucMemBlkId:8; |
5157 | ULONG ulMemClockRange:24; |
5802 | ULONG ulMemClockRange:24; |
5158 | #else |
5803 | #else |
5159 | ULONG ulMemClockRange:24; |
5804 | ULONG ulMemClockRange:24; |
5160 | ULONG ucMemBlkId:8; |
5805 | ULONG ucMemBlkId:8; |
5161 | #endif |
5806 | #endif |
5162 | }ATOM_MEMORY_SETTING_ID_CONFIG; |
5807 | }ATOM_MEMORY_SETTING_ID_CONFIG; |
5163 | 5808 | ||
5164 | typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS |
5809 | typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS |
5165 | { |
5810 | { |
5166 | ATOM_MEMORY_SETTING_ID_CONFIG slAccess; |
5811 | ATOM_MEMORY_SETTING_ID_CONFIG slAccess; |
5167 | ULONG ulAccess; |
5812 | ULONG ulAccess; |
5168 | }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; |
5813 | }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; |
5169 | 5814 | ||
5170 | 5815 | ||
5171 | typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ |
5816 | typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ |
5172 | ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; |
5817 | ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; |
5173 | ULONG aulMemData[1]; |
5818 | ULONG aulMemData[1]; |
5174 | }ATOM_MEMORY_SETTING_DATA_BLOCK; |
5819 | }ATOM_MEMORY_SETTING_DATA_BLOCK; |
5175 | 5820 | ||
5176 | 5821 | ||
5177 | typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ |
5822 | typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ |
5178 | USHORT usRegIndex; // MC register index |
5823 | USHORT usRegIndex; // MC register index |
5179 | UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf |
5824 | UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf |
5180 | }ATOM_INIT_REG_INDEX_FORMAT; |
5825 | }ATOM_INIT_REG_INDEX_FORMAT; |
5181 | 5826 | ||
5182 | 5827 | ||
5183 | typedef struct _ATOM_INIT_REG_BLOCK{ |
5828 | typedef struct _ATOM_INIT_REG_BLOCK{ |
5184 | USHORT usRegIndexTblSize; //size of asRegIndexBuf |
5829 | USHORT usRegIndexTblSize; //size of asRegIndexBuf |
5185 | USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK |
5830 | USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK |
5186 | ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; |
5831 | ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; |
5187 | ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; |
5832 | ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; |
5188 | }ATOM_INIT_REG_BLOCK; |
5833 | }ATOM_INIT_REG_BLOCK; |
5189 | 5834 | ||
5190 | #define END_OF_REG_INDEX_BLOCK 0x0ffff |
5835 | #define END_OF_REG_INDEX_BLOCK 0x0ffff |
5191 | #define END_OF_REG_DATA_BLOCK 0x00000000 |
5836 | #define END_OF_REG_DATA_BLOCK 0x00000000 |
5192 | #define ATOM_INIT_REG_MASK_FLAG 0x80 |
5837 | #define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS |
5193 | #define CLOCK_RANGE_HIGHEST 0x00ffffff |
5838 | #define CLOCK_RANGE_HIGHEST 0x00ffffff |
5194 | 5839 | ||
5195 | #define VALUE_DWORD SIZEOF ULONG |
5840 | #define VALUE_DWORD SIZEOF ULONG |
5196 | #define VALUE_SAME_AS_ABOVE 0 |
5841 | #define VALUE_SAME_AS_ABOVE 0 |
5197 | #define VALUE_MASK_DWORD 0x84 |
5842 | #define VALUE_MASK_DWORD 0x84 |
5198 | 5843 | ||
5199 | #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) |
5844 | #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) |
5200 | #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) |
5845 | #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) |
5201 | #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) |
5846 | #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) |
5202 | //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code |
5847 | //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code |
5203 | #define ACCESS_PLACEHOLDER 0x80 |
5848 | #define ACCESS_PLACEHOLDER 0x80 |
5204 | 5849 | ||
5205 | typedef struct _ATOM_MC_INIT_PARAM_TABLE |
5850 | typedef struct _ATOM_MC_INIT_PARAM_TABLE |
5206 | { |
5851 | { |
5207 | ATOM_COMMON_TABLE_HEADER sHeader; |
5852 | ATOM_COMMON_TABLE_HEADER sHeader; |
5208 | USHORT usAdjustARB_SEQDataOffset; |
5853 | USHORT usAdjustARB_SEQDataOffset; |
5209 | USHORT usMCInitMemTypeTblOffset; |
5854 | USHORT usMCInitMemTypeTblOffset; |
5210 | USHORT usMCInitCommonTblOffset; |
5855 | USHORT usMCInitCommonTblOffset; |
5211 | USHORT usMCInitPowerDownTblOffset; |
5856 | USHORT usMCInitPowerDownTblOffset; |
5212 | ULONG ulARB_SEQDataBuf[32]; |
5857 | ULONG ulARB_SEQDataBuf[32]; |
5213 | ATOM_INIT_REG_BLOCK asMCInitMemType; |
5858 | ATOM_INIT_REG_BLOCK asMCInitMemType; |
5214 | ATOM_INIT_REG_BLOCK asMCInitCommon; |
5859 | ATOM_INIT_REG_BLOCK asMCInitCommon; |
5215 | }ATOM_MC_INIT_PARAM_TABLE; |
5860 | }ATOM_MC_INIT_PARAM_TABLE; |
5216 | 5861 | ||
5217 | 5862 | ||
5218 | #define _4Mx16 0x2 |
5863 | #define _4Mx16 0x2 |
5219 | #define _4Mx32 0x3 |
5864 | #define _4Mx32 0x3 |
5220 | #define _8Mx16 0x12 |
5865 | #define _8Mx16 0x12 |
5221 | #define _8Mx32 0x13 |
5866 | #define _8Mx32 0x13 |
5222 | #define _16Mx16 0x22 |
5867 | #define _16Mx16 0x22 |
5223 | #define _16Mx32 0x23 |
5868 | #define _16Mx32 0x23 |
5224 | #define _32Mx16 0x32 |
5869 | #define _32Mx16 0x32 |
5225 | #define _32Mx32 0x33 |
5870 | #define _32Mx32 0x33 |
5226 | #define _64Mx8 0x41 |
5871 | #define _64Mx8 0x41 |
5227 | #define _64Mx16 0x42 |
5872 | #define _64Mx16 0x42 |
5228 | #define _64Mx32 0x43 |
5873 | #define _64Mx32 0x43 |
5229 | #define _128Mx8 0x51 |
5874 | #define _128Mx8 0x51 |
5230 | #define _128Mx16 0x52 |
5875 | #define _128Mx16 0x52 |
5231 | #define _256Mx8 0x61 |
5876 | #define _256Mx8 0x61 |
- | 5877 | #define _256Mx16 0x62 |
|
5232 | 5878 | ||
5233 | #define SAMSUNG 0x1 |
5879 | #define SAMSUNG 0x1 |
5234 | #define INFINEON 0x2 |
5880 | #define INFINEON 0x2 |
5235 | #define ELPIDA 0x3 |
5881 | #define ELPIDA 0x3 |
5236 | #define ETRON 0x4 |
5882 | #define ETRON 0x4 |
5237 | #define NANYA 0x5 |
5883 | #define NANYA 0x5 |
5238 | #define HYNIX 0x6 |
5884 | #define HYNIX 0x6 |
5239 | #define MOSEL 0x7 |
5885 | #define MOSEL 0x7 |
5240 | #define WINBOND 0x8 |
5886 | #define WINBOND 0x8 |
5241 | #define ESMT 0x9 |
5887 | #define ESMT 0x9 |
5242 | #define MICRON 0xF |
5888 | #define MICRON 0xF |
5243 | 5889 | ||
5244 | #define QIMONDA INFINEON |
5890 | #define QIMONDA INFINEON |
5245 | #define PROMOS MOSEL |
5891 | #define PROMOS MOSEL |
5246 | #define KRETON INFINEON |
5892 | #define KRETON INFINEON |
5247 | #define ELIXIR NANYA |
5893 | #define ELIXIR NANYA |
5248 | 5894 | ||
5249 | /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// |
5895 | /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// |
5250 | 5896 | ||
5251 | #define UCODE_ROM_START_ADDRESS 0x1b800 |
5897 | #define UCODE_ROM_START_ADDRESS 0x1b800 |
5252 | #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode |
5898 | #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode |
5253 | 5899 | ||
5254 | //uCode block header for reference |
5900 | //uCode block header for reference |
5255 | 5901 | ||
5256 | typedef struct _MCuCodeHeader |
5902 | typedef struct _MCuCodeHeader |
5257 | { |
5903 | { |
5258 | ULONG ulSignature; |
5904 | ULONG ulSignature; |
5259 | UCHAR ucRevision; |
5905 | UCHAR ucRevision; |
5260 | UCHAR ucChecksum; |
5906 | UCHAR ucChecksum; |
5261 | UCHAR ucReserved1; |
5907 | UCHAR ucReserved1; |
5262 | UCHAR ucReserved2; |
5908 | UCHAR ucReserved2; |
5263 | USHORT usParametersLength; |
5909 | USHORT usParametersLength; |
5264 | USHORT usUCodeLength; |
5910 | USHORT usUCodeLength; |
5265 | USHORT usReserved1; |
5911 | USHORT usReserved1; |
5266 | USHORT usReserved2; |
5912 | USHORT usReserved2; |
5267 | } MCuCodeHeader; |
5913 | } MCuCodeHeader; |
5268 | 5914 | ||
5269 | ////////////////////////////////////////////////////////////////////////////////// |
5915 | ////////////////////////////////////////////////////////////////////////////////// |
5270 | 5916 | ||
5271 | #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 |
5917 | #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 |
5272 | 5918 | ||
5273 | #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF |
5919 | #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF |
5274 | typedef struct _ATOM_VRAM_MODULE_V1 |
5920 | typedef struct _ATOM_VRAM_MODULE_V1 |
5275 | { |
5921 | { |
5276 | ULONG ulReserved; |
5922 | ULONG ulReserved; |
5277 | USHORT usEMRSValue; |
5923 | USHORT usEMRSValue; |
5278 | USHORT usMRSValue; |
5924 | USHORT usMRSValue; |
5279 | USHORT usReserved; |
5925 | USHORT usReserved; |
5280 | UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module |
5926 | UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module |
5281 | UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; |
5927 | UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; |
5282 | UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender |
5928 | UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender |
5283 | UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... |
5929 | UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... |
5284 | UCHAR ucRow; // Number of Row,in power of 2; |
5930 | UCHAR ucRow; // Number of Row,in power of 2; |
5285 | UCHAR ucColumn; // Number of Column,in power of 2; |
5931 | UCHAR ucColumn; // Number of Column,in power of 2; |
5286 | UCHAR ucBank; // Nunber of Bank; |
5932 | UCHAR ucBank; // Nunber of Bank; |
5287 | UCHAR ucRank; // Number of Rank, in power of 2 |
5933 | UCHAR ucRank; // Number of Rank, in power of 2 |
5288 | UCHAR ucChannelNum; // Number of channel; |
5934 | UCHAR ucChannelNum; // Number of channel; |
5289 | UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 |
5935 | UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 |
5290 | UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; |
5936 | UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; |
5291 | UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; |
5937 | UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; |
5292 | UCHAR ucReserved[2]; |
5938 | UCHAR ucReserved[2]; |
5293 | }ATOM_VRAM_MODULE_V1; |
5939 | }ATOM_VRAM_MODULE_V1; |
5294 | 5940 | ||
5295 | 5941 | ||
5296 | typedef struct _ATOM_VRAM_MODULE_V2 |
5942 | typedef struct _ATOM_VRAM_MODULE_V2 |
5297 | { |
5943 | { |
5298 | ULONG ulReserved; |
5944 | ULONG ulReserved; |
5299 | ULONG ulFlags; // To enable/disable functionalities based on memory type |
5945 | ULONG ulFlags; // To enable/disable functionalities based on memory type |
5300 | ULONG ulEngineClock; // Override of default engine clock for particular memory type |
5946 | ULONG ulEngineClock; // Override of default engine clock for particular memory type |
5301 | ULONG ulMemoryClock; // Override of default memory clock for particular memory type |
5947 | ULONG ulMemoryClock; // Override of default memory clock for particular memory type |
5302 | USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type |
5948 | USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type |
5303 | USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type |
5949 | USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type |
5304 | USHORT usEMRSValue; |
5950 | USHORT usEMRSValue; |
5305 | USHORT usMRSValue; |
5951 | USHORT usMRSValue; |
5306 | USHORT usReserved; |
5952 | USHORT usReserved; |
5307 | UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module |
5953 | UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module |
5308 | UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; |
5954 | UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; |
5309 | UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed |
5955 | UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed |
5310 | UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... |
5956 | UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... |
5311 | UCHAR ucRow; // Number of Row,in power of 2; |
5957 | UCHAR ucRow; // Number of Row,in power of 2; |
5312 | UCHAR ucColumn; // Number of Column,in power of 2; |
5958 | UCHAR ucColumn; // Number of Column,in power of 2; |
5313 | UCHAR ucBank; // Nunber of Bank; |
5959 | UCHAR ucBank; // Nunber of Bank; |
5314 | UCHAR ucRank; // Number of Rank, in power of 2 |
5960 | UCHAR ucRank; // Number of Rank, in power of 2 |
5315 | UCHAR ucChannelNum; // Number of channel; |
5961 | UCHAR ucChannelNum; // Number of channel; |
5316 | UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 |
5962 | UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 |
5317 | UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; |
5963 | UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; |
5318 | UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; |
5964 | UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; |
5319 | UCHAR ucRefreshRateFactor; |
5965 | UCHAR ucRefreshRateFactor; |
5320 | UCHAR ucReserved[3]; |
5966 | UCHAR ucReserved[3]; |
5321 | }ATOM_VRAM_MODULE_V2; |
5967 | }ATOM_VRAM_MODULE_V2; |
5322 | 5968 | ||
5323 | 5969 | ||
5324 | typedef struct _ATOM_MEMORY_TIMING_FORMAT |
5970 | typedef struct _ATOM_MEMORY_TIMING_FORMAT |
5325 | { |
5971 | { |
5326 | ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing |
5972 | ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing |
5327 | union{ |
5973 | union{ |
5328 | USHORT usMRS; // mode register |
5974 | USHORT usMRS; // mode register |
5329 | USHORT usDDR3_MR0; |
5975 | USHORT usDDR3_MR0; |
5330 | }; |
5976 | }; |
5331 | union{ |
5977 | union{ |
5332 | USHORT usEMRS; // extended mode register |
5978 | USHORT usEMRS; // extended mode register |
5333 | USHORT usDDR3_MR1; |
5979 | USHORT usDDR3_MR1; |
5334 | }; |
5980 | }; |
5335 | UCHAR ucCL; // CAS latency |
5981 | UCHAR ucCL; // CAS latency |
5336 | UCHAR ucWL; // WRITE Latency |
5982 | UCHAR ucWL; // WRITE Latency |
5337 | UCHAR uctRAS; // tRAS |
5983 | UCHAR uctRAS; // tRAS |
5338 | UCHAR uctRC; // tRC |
5984 | UCHAR uctRC; // tRC |
5339 | UCHAR uctRFC; // tRFC |
5985 | UCHAR uctRFC; // tRFC |
5340 | UCHAR uctRCDR; // tRCDR |
5986 | UCHAR uctRCDR; // tRCDR |
5341 | UCHAR uctRCDW; // tRCDW |
5987 | UCHAR uctRCDW; // tRCDW |
5342 | UCHAR uctRP; // tRP |
5988 | UCHAR uctRP; // tRP |
5343 | UCHAR uctRRD; // tRRD |
5989 | UCHAR uctRRD; // tRRD |
5344 | UCHAR uctWR; // tWR |
5990 | UCHAR uctWR; // tWR |
5345 | UCHAR uctWTR; // tWTR |
5991 | UCHAR uctWTR; // tWTR |
5346 | UCHAR uctPDIX; // tPDIX |
5992 | UCHAR uctPDIX; // tPDIX |
5347 | UCHAR uctFAW; // tFAW |
5993 | UCHAR uctFAW; // tFAW |
5348 | UCHAR uctAOND; // tAOND |
5994 | UCHAR uctAOND; // tAOND |
5349 | union |
5995 | union |
5350 | { |
5996 | { |
5351 | struct { |
5997 | struct { |
5352 | UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon |
5998 | UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon |
5353 | UCHAR ucReserved; |
5999 | UCHAR ucReserved; |
5354 | }; |
6000 | }; |
5355 | USHORT usDDR3_MR2; |
6001 | USHORT usDDR3_MR2; |
5356 | }; |
6002 | }; |
5357 | }ATOM_MEMORY_TIMING_FORMAT; |
6003 | }ATOM_MEMORY_TIMING_FORMAT; |
5358 | 6004 | ||
5359 | 6005 | ||
5360 | typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 |
6006 | typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 |
5361 | { |
6007 | { |
5362 | ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing |
6008 | ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing |
5363 | USHORT usMRS; // mode register |
6009 | USHORT usMRS; // mode register |
5364 | USHORT usEMRS; // extended mode register |
6010 | USHORT usEMRS; // extended mode register |
5365 | UCHAR ucCL; // CAS latency |
6011 | UCHAR ucCL; // CAS latency |
5366 | UCHAR ucWL; // WRITE Latency |
6012 | UCHAR ucWL; // WRITE Latency |
5367 | UCHAR uctRAS; // tRAS |
6013 | UCHAR uctRAS; // tRAS |
5368 | UCHAR uctRC; // tRC |
6014 | UCHAR uctRC; // tRC |
5369 | UCHAR uctRFC; // tRFC |
6015 | UCHAR uctRFC; // tRFC |
5370 | UCHAR uctRCDR; // tRCDR |
6016 | UCHAR uctRCDR; // tRCDR |
5371 | UCHAR uctRCDW; // tRCDW |
6017 | UCHAR uctRCDW; // tRCDW |
5372 | UCHAR uctRP; // tRP |
6018 | UCHAR uctRP; // tRP |
5373 | UCHAR uctRRD; // tRRD |
6019 | UCHAR uctRRD; // tRRD |
5374 | UCHAR uctWR; // tWR |
6020 | UCHAR uctWR; // tWR |
5375 | UCHAR uctWTR; // tWTR |
6021 | UCHAR uctWTR; // tWTR |
5376 | UCHAR uctPDIX; // tPDIX |
6022 | UCHAR uctPDIX; // tPDIX |
5377 | UCHAR uctFAW; // tFAW |
6023 | UCHAR uctFAW; // tFAW |
5378 | UCHAR uctAOND; // tAOND |
6024 | UCHAR uctAOND; // tAOND |
5379 | UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon |
6025 | UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon |
5380 | ////////////////////////////////////GDDR parameters/////////////////////////////////// |
6026 | ////////////////////////////////////GDDR parameters/////////////////////////////////// |
5381 | UCHAR uctCCDL; // |
6027 | UCHAR uctCCDL; // |
5382 | UCHAR uctCRCRL; // |
6028 | UCHAR uctCRCRL; // |
5383 | UCHAR uctCRCWL; // |
6029 | UCHAR uctCRCWL; // |
5384 | UCHAR uctCKE; // |
6030 | UCHAR uctCKE; // |
5385 | UCHAR uctCKRSE; // |
6031 | UCHAR uctCKRSE; // |
5386 | UCHAR uctCKRSX; // |
6032 | UCHAR uctCKRSX; // |
5387 | UCHAR uctFAW32; // |
6033 | UCHAR uctFAW32; // |
5388 | UCHAR ucMR5lo; // |
6034 | UCHAR ucMR5lo; // |
5389 | UCHAR ucMR5hi; // |
6035 | UCHAR ucMR5hi; // |
5390 | UCHAR ucTerminator; |
6036 | UCHAR ucTerminator; |
5391 | }ATOM_MEMORY_TIMING_FORMAT_V1; |
6037 | }ATOM_MEMORY_TIMING_FORMAT_V1; |
5392 | 6038 | ||
5393 | typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 |
6039 | typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 |
5394 | { |
6040 | { |
5395 | ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing |
6041 | ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing |
5396 | USHORT usMRS; // mode register |
6042 | USHORT usMRS; // mode register |
5397 | USHORT usEMRS; // extended mode register |
6043 | USHORT usEMRS; // extended mode register |
5398 | UCHAR ucCL; // CAS latency |
6044 | UCHAR ucCL; // CAS latency |
5399 | UCHAR ucWL; // WRITE Latency |
6045 | UCHAR ucWL; // WRITE Latency |
5400 | UCHAR uctRAS; // tRAS |
6046 | UCHAR uctRAS; // tRAS |
5401 | UCHAR uctRC; // tRC |
6047 | UCHAR uctRC; // tRC |
5402 | UCHAR uctRFC; // tRFC |
6048 | UCHAR uctRFC; // tRFC |
5403 | UCHAR uctRCDR; // tRCDR |
6049 | UCHAR uctRCDR; // tRCDR |
5404 | UCHAR uctRCDW; // tRCDW |
6050 | UCHAR uctRCDW; // tRCDW |
5405 | UCHAR uctRP; // tRP |
6051 | UCHAR uctRP; // tRP |
5406 | UCHAR uctRRD; // tRRD |
6052 | UCHAR uctRRD; // tRRD |
5407 | UCHAR uctWR; // tWR |
6053 | UCHAR uctWR; // tWR |
5408 | UCHAR uctWTR; // tWTR |
6054 | UCHAR uctWTR; // tWTR |
5409 | UCHAR uctPDIX; // tPDIX |
6055 | UCHAR uctPDIX; // tPDIX |
5410 | UCHAR uctFAW; // tFAW |
6056 | UCHAR uctFAW; // tFAW |
5411 | UCHAR uctAOND; // tAOND |
6057 | UCHAR uctAOND; // tAOND |
5412 | UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon |
6058 | UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon |
5413 | ////////////////////////////////////GDDR parameters/////////////////////////////////// |
6059 | ////////////////////////////////////GDDR parameters/////////////////////////////////// |
5414 | UCHAR uctCCDL; // |
6060 | UCHAR uctCCDL; // |
5415 | UCHAR uctCRCRL; // |
6061 | UCHAR uctCRCRL; // |
5416 | UCHAR uctCRCWL; // |
6062 | UCHAR uctCRCWL; // |
5417 | UCHAR uctCKE; // |
6063 | UCHAR uctCKE; // |
5418 | UCHAR uctCKRSE; // |
6064 | UCHAR uctCKRSE; // |
5419 | UCHAR uctCKRSX; // |
6065 | UCHAR uctCKRSX; // |
5420 | UCHAR uctFAW32; // |
6066 | UCHAR uctFAW32; // |
5421 | UCHAR ucMR4lo; // |
6067 | UCHAR ucMR4lo; // |
5422 | UCHAR ucMR4hi; // |
6068 | UCHAR ucMR4hi; // |
5423 | UCHAR ucMR5lo; // |
6069 | UCHAR ucMR5lo; // |
5424 | UCHAR ucMR5hi; // |
6070 | UCHAR ucMR5hi; // |
5425 | UCHAR ucTerminator; |
6071 | UCHAR ucTerminator; |
5426 | UCHAR ucReserved; |
6072 | UCHAR ucReserved; |
5427 | }ATOM_MEMORY_TIMING_FORMAT_V2; |
6073 | }ATOM_MEMORY_TIMING_FORMAT_V2; |
5428 | 6074 | ||
5429 | typedef struct _ATOM_MEMORY_FORMAT |
6075 | typedef struct _ATOM_MEMORY_FORMAT |
5430 | { |
6076 | { |
5431 | ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock |
6077 | ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock |
5432 | union{ |
6078 | union{ |
5433 | USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type |
6079 | USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type |
5434 | USHORT usDDR3_Reserved; // Not used for DDR3 memory |
6080 | USHORT usDDR3_Reserved; // Not used for DDR3 memory |
5435 | }; |
6081 | }; |
5436 | union{ |
6082 | union{ |
5437 | USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type |
6083 | USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type |
5438 | USHORT usDDR3_MR3; // Used for DDR3 memory |
6084 | USHORT usDDR3_MR3; // Used for DDR3 memory |
5439 | }; |
6085 | }; |
5440 | UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; |
6086 | UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; |
5441 | UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed |
6087 | UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed |
5442 | UCHAR ucRow; // Number of Row,in power of 2; |
6088 | UCHAR ucRow; // Number of Row,in power of 2; |
5443 | UCHAR ucColumn; // Number of Column,in power of 2; |
6089 | UCHAR ucColumn; // Number of Column,in power of 2; |
5444 | UCHAR ucBank; // Nunber of Bank; |
6090 | UCHAR ucBank; // Nunber of Bank; |
5445 | UCHAR ucRank; // Number of Rank, in power of 2 |
6091 | UCHAR ucRank; // Number of Rank, in power of 2 |
5446 | UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 |
6092 | UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 |
5447 | UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) |
6093 | UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) |
5448 | UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms |
6094 | UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms |
5449 | UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 |
6095 | UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 |
5450 | UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble |
6096 | UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble |
5451 | UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc |
6097 | UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc |
5452 | ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock |
6098 | ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock |
5453 | }ATOM_MEMORY_FORMAT; |
6099 | }ATOM_MEMORY_FORMAT; |
5454 | 6100 | ||
5455 | 6101 | ||
5456 | typedef struct _ATOM_VRAM_MODULE_V3 |
6102 | typedef struct _ATOM_VRAM_MODULE_V3 |
5457 | { |
6103 | { |
5458 | ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination |
6104 | ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination |
5459 | USHORT usSize; // size of ATOM_VRAM_MODULE_V3 |
6105 | USHORT usSize; // size of ATOM_VRAM_MODULE_V3 |
5460 | USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage |
6106 | USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage |
5461 | USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage |
6107 | USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage |
5462 | UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module |
6108 | UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module |
5463 | UCHAR ucChannelNum; // board dependent parameter:Number of channel; |
6109 | UCHAR ucChannelNum; // board dependent parameter:Number of channel; |
5464 | UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit |
6110 | UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit |
5465 | UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv |
6111 | UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv |
5466 | UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters |
6112 | UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters |
5467 | UCHAR ucFlag; // To enable/disable functionalities based on memory type |
6113 | UCHAR ucFlag; // To enable/disable functionalities based on memory type |
5468 | ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec |
6114 | ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec |
5469 | }ATOM_VRAM_MODULE_V3; |
6115 | }ATOM_VRAM_MODULE_V3; |
5470 | 6116 | ||
5471 | 6117 | ||
5472 | //ATOM_VRAM_MODULE_V3.ucNPL_RT |
6118 | //ATOM_VRAM_MODULE_V3.ucNPL_RT |
5473 | #define NPL_RT_MASK 0x0f |
6119 | #define NPL_RT_MASK 0x0f |
5474 | #define BATTERY_ODT_MASK 0xc0 |
6120 | #define BATTERY_ODT_MASK 0xc0 |
5475 | 6121 | ||
5476 | #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 |
6122 | #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 |
5477 | 6123 | ||
5478 | typedef struct _ATOM_VRAM_MODULE_V4 |
6124 | typedef struct _ATOM_VRAM_MODULE_V4 |
5479 | { |
6125 | { |
5480 | ULONG ulChannelMapCfg; // board dependent parameter: Channel combination |
6126 | ULONG ulChannelMapCfg; // board dependent parameter: Channel combination |
5481 | USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE |
6127 | USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE |
5482 | USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! |
6128 | USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! |
5483 | // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) |
6129 | // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) |
5484 | USHORT usReserved; |
6130 | USHORT usReserved; |
5485 | UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module |
6131 | UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module |
5486 | UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; |
6132 | UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; |
5487 | UCHAR ucChannelNum; // Number of channels present in this module config |
6133 | UCHAR ucChannelNum; // Number of channels present in this module config |
5488 | UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits |
6134 | UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits |
5489 | UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 |
6135 | UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 |
5490 | UCHAR ucFlag; // To enable/disable functionalities based on memory type |
6136 | UCHAR ucFlag; // To enable/disable functionalities based on memory type |
5491 | UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 |
6137 | UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 |
5492 | UCHAR ucVREFI; // board dependent parameter |
6138 | UCHAR ucVREFI; // board dependent parameter |
5493 | UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters |
6139 | UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters |
5494 | UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble |
6140 | UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble |
5495 | UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! |
6141 | UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! |
5496 | // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros |
6142 | // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros |
5497 | UCHAR ucReserved[3]; |
6143 | UCHAR ucReserved[3]; |
5498 | 6144 | ||
5499 | //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level |
6145 | //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level |
5500 | union{ |
6146 | union{ |
5501 | USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type |
6147 | USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type |
5502 | USHORT usDDR3_Reserved; |
6148 | USHORT usDDR3_Reserved; |
5503 | }; |
6149 | }; |
5504 | union{ |
6150 | union{ |
5505 | USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type |
6151 | USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type |
5506 | USHORT usDDR3_MR3; // Used for DDR3 memory |
6152 | USHORT usDDR3_MR3; // Used for DDR3 memory |
5507 | }; |
6153 | }; |
5508 | UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed |
6154 | UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed |
5509 | UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) |
6155 | UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) |
5510 | UCHAR ucReserved2[2]; |
6156 | UCHAR ucReserved2[2]; |
5511 | ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock |
6157 | ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock |
5512 | }ATOM_VRAM_MODULE_V4; |
6158 | }ATOM_VRAM_MODULE_V4; |
5513 | 6159 | ||
5514 | #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 |
6160 | #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 |
5515 | #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 |
6161 | #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 |
5516 | #define VRAM_MODULE_V4_MISC_BL_MASK 0x4 |
6162 | #define VRAM_MODULE_V4_MISC_BL_MASK 0x4 |
5517 | #define VRAM_MODULE_V4_MISC_BL8 0x4 |
6163 | #define VRAM_MODULE_V4_MISC_BL8 0x4 |
5518 | #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 |
6164 | #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 |
5519 | 6165 | ||
5520 | typedef struct _ATOM_VRAM_MODULE_V5 |
6166 | typedef struct _ATOM_VRAM_MODULE_V5 |
5521 | { |
6167 | { |
5522 | ULONG ulChannelMapCfg; // board dependent parameter: Channel combination |
6168 | ULONG ulChannelMapCfg; // board dependent parameter: Channel combination |
5523 | USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE |
6169 | USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE |
5524 | USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! |
6170 | USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! |
5525 | // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) |
6171 | // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) |
5526 | USHORT usReserved; |
6172 | USHORT usReserved; |
5527 | UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module |
6173 | UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module |
5528 | UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; |
6174 | UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; |
5529 | UCHAR ucChannelNum; // Number of channels present in this module config |
6175 | UCHAR ucChannelNum; // Number of channels present in this module config |
5530 | UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits |
6176 | UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits |
5531 | UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 |
6177 | UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 |
5532 | UCHAR ucFlag; // To enable/disable functionalities based on memory type |
6178 | UCHAR ucFlag; // To enable/disable functionalities based on memory type |
5533 | UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 |
6179 | UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 |
5534 | UCHAR ucVREFI; // board dependent parameter |
6180 | UCHAR ucVREFI; // board dependent parameter |
5535 | UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters |
6181 | UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters |
5536 | UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble |
6182 | UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble |
5537 | UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! |
6183 | UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! |
5538 | // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros |
6184 | // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros |
5539 | UCHAR ucReserved[3]; |
6185 | UCHAR ucReserved[3]; |
5540 | 6186 | ||
5541 | //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level |
6187 | //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level |
5542 | USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type |
6188 | USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type |
5543 | USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type |
6189 | USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type |
5544 | UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed |
6190 | UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed |
5545 | UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) |
6191 | UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) |
5546 | UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth |
6192 | UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth |
5547 | UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth |
6193 | UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth |
5548 | ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock |
6194 | ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock |
5549 | }ATOM_VRAM_MODULE_V5; |
6195 | }ATOM_VRAM_MODULE_V5; |
5550 | 6196 | ||
5551 | typedef struct _ATOM_VRAM_MODULE_V6 |
6197 | typedef struct _ATOM_VRAM_MODULE_V6 |
5552 | { |
6198 | { |
5553 | ULONG ulChannelMapCfg; // board dependent parameter: Channel combination |
6199 | ULONG ulChannelMapCfg; // board dependent parameter: Channel combination |
5554 | USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE |
6200 | USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE |
5555 | USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! |
6201 | USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! |
5556 | // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) |
6202 | // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) |
5557 | USHORT usReserved; |
6203 | USHORT usReserved; |
5558 | UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module |
6204 | UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module |
5559 | UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; |
6205 | UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; |
5560 | UCHAR ucChannelNum; // Number of channels present in this module config |
6206 | UCHAR ucChannelNum; // Number of channels present in this module config |
5561 | UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits |
6207 | UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits |
5562 | UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 |
6208 | UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 |
5563 | UCHAR ucFlag; // To enable/disable functionalities based on memory type |
6209 | UCHAR ucFlag; // To enable/disable functionalities based on memory type |
5564 | UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 |
6210 | UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 |
5565 | UCHAR ucVREFI; // board dependent parameter |
6211 | UCHAR ucVREFI; // board dependent parameter |
5566 | UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters |
6212 | UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters |
5567 | UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble |
6213 | UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble |
5568 | UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! |
6214 | UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! |
5569 | // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros |
6215 | // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros |
5570 | UCHAR ucReserved[3]; |
6216 | UCHAR ucReserved[3]; |
5571 | 6217 | ||
5572 | //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level |
6218 | //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level |
5573 | USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type |
6219 | USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type |
5574 | USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type |
6220 | USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type |
5575 | UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed |
6221 | UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed |
5576 | UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) |
6222 | UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) |
5577 | UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth |
6223 | UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth |
5578 | UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth |
6224 | UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth |
5579 | ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock |
6225 | ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock |
5580 | }ATOM_VRAM_MODULE_V6; |
6226 | }ATOM_VRAM_MODULE_V6; |
5581 | 6227 | ||
5582 | typedef struct _ATOM_VRAM_MODULE_V7 |
6228 | typedef struct _ATOM_VRAM_MODULE_V7 |
5583 | { |
6229 | { |
5584 | // Design Specific Values |
6230 | // Design Specific Values |
5585 | ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP |
6231 | ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP |
5586 | USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 |
6232 | USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 |
5587 | USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) |
6233 | USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) |
5588 | USHORT usReserved; |
6234 | USHORT usEnableChannels; // bit vector which indicate which channels are enabled |
5589 | UCHAR ucExtMemoryID; // Current memory module ID |
6235 | UCHAR ucExtMemoryID; // Current memory module ID |
5590 | UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 |
6236 | UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 |
5591 | UCHAR ucChannelNum; // Number of mem. channels supported in this module |
6237 | UCHAR ucChannelNum; // Number of mem. channels supported in this module |
5592 | UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT |
6238 | UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT |
5593 | UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 |
6239 | UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 |
5594 | UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now. |
6240 | UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now. |
5595 | UCHAR ucMisc; // RANK_OF_THISMEMORY etc. |
6241 | UCHAR ucMisc; // RANK_OF_THISMEMORY etc. |
5596 | UCHAR ucVREFI; // Not used. |
6242 | UCHAR ucVREFI; // Not used. |
5597 | UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. |
6243 | UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. |
5598 | UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble |
6244 | UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble |
5599 | UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros |
6245 | UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros |
- | 6246 | USHORT usSEQSettingOffset; |
|
5600 | UCHAR ucReserved[3]; |
6247 | UCHAR ucReserved; |
5601 | // Memory Module specific values |
6248 | // Memory Module specific values |
5602 | USHORT usEMRS2Value; // EMRS2/MR2 Value. |
6249 | USHORT usEMRS2Value; // EMRS2/MR2 Value. |
5603 | USHORT usEMRS3Value; // EMRS3/MR3 Value. |
6250 | USHORT usEMRS3Value; // EMRS3/MR3 Value. |
5604 | UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code |
6251 | UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code |
5605 | UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) |
6252 | UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) |
5606 | UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory |
6253 | UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory |
5607 | UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth |
6254 | UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth |
5608 | char strMemPNString[20]; // part number end with '0'. |
6255 | char strMemPNString[20]; // part number end with '0'. |
5609 | }ATOM_VRAM_MODULE_V7; |
6256 | }ATOM_VRAM_MODULE_V7; |
5610 | 6257 | ||
5611 | typedef struct _ATOM_VRAM_INFO_V2 |
6258 | typedef struct _ATOM_VRAM_INFO_V2 |
5612 | { |
6259 | { |
5613 | ATOM_COMMON_TABLE_HEADER sHeader; |
6260 | ATOM_COMMON_TABLE_HEADER sHeader; |
5614 | UCHAR ucNumOfVRAMModule; |
6261 | UCHAR ucNumOfVRAMModule; |
5615 | ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; |
6262 | ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; |
5616 | }ATOM_VRAM_INFO_V2; |
6263 | }ATOM_VRAM_INFO_V2; |
5617 | 6264 | ||
5618 | typedef struct _ATOM_VRAM_INFO_V3 |
6265 | typedef struct _ATOM_VRAM_INFO_V3 |
5619 | { |
6266 | { |
5620 | ATOM_COMMON_TABLE_HEADER sHeader; |
6267 | ATOM_COMMON_TABLE_HEADER sHeader; |
5621 | USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting |
6268 | USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting |
5622 | USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting |
6269 | USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting |
5623 | USHORT usRerseved; |
6270 | USHORT usRerseved; |
5624 | UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator |
6271 | UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator |
5625 | UCHAR ucNumOfVRAMModule; |
6272 | UCHAR ucNumOfVRAMModule; |
5626 | ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; |
6273 | ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; |
5627 | ATOM_INIT_REG_BLOCK asMemPatch; // for allocation |
6274 | ATOM_INIT_REG_BLOCK asMemPatch; // for allocation |
5628 | // ATOM_INIT_REG_BLOCK aMemAdjust; |
6275 | // ATOM_INIT_REG_BLOCK aMemAdjust; |
5629 | }ATOM_VRAM_INFO_V3; |
6276 | }ATOM_VRAM_INFO_V3; |
5630 | 6277 | ||
5631 | #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 |
6278 | #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 |
5632 | 6279 | ||
5633 | typedef struct _ATOM_VRAM_INFO_V4 |
6280 | typedef struct _ATOM_VRAM_INFO_V4 |
5634 | { |
6281 | { |
5635 | ATOM_COMMON_TABLE_HEADER sHeader; |
6282 | ATOM_COMMON_TABLE_HEADER sHeader; |
5636 | USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting |
6283 | USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting |
5637 | USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting |
6284 | USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting |
5638 | USHORT usRerseved; |
6285 | USHORT usRerseved; |
5639 | UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 |
6286 | UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 |
5640 | ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] |
6287 | ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] |
5641 | UCHAR ucReservde[4]; |
6288 | UCHAR ucReservde[4]; |
5642 | UCHAR ucNumOfVRAMModule; |
6289 | UCHAR ucNumOfVRAMModule; |
5643 | ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; |
6290 | ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; |
5644 | ATOM_INIT_REG_BLOCK asMemPatch; // for allocation |
6291 | ATOM_INIT_REG_BLOCK asMemPatch; // for allocation |
5645 | // ATOM_INIT_REG_BLOCK aMemAdjust; |
6292 | // ATOM_INIT_REG_BLOCK aMemAdjust; |
5646 | }ATOM_VRAM_INFO_V4; |
6293 | }ATOM_VRAM_INFO_V4; |
5647 | 6294 | ||
5648 | typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 |
6295 | typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 |
5649 | { |
6296 | { |
5650 | ATOM_COMMON_TABLE_HEADER sHeader; |
6297 | ATOM_COMMON_TABLE_HEADER sHeader; |
5651 | USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting |
6298 | USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting |
5652 | USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting |
6299 | USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting |
- | 6300 | USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings |
|
5653 | USHORT usReserved[4]; |
6301 | USHORT usReserved[3]; |
5654 | UCHAR ucNumOfVRAMModule; // indicate number of VRAM module |
6302 | UCHAR ucNumOfVRAMModule; // indicate number of VRAM module |
5655 | UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list |
6303 | UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list |
5656 | UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version |
6304 | UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version |
5657 | UCHAR ucReserved; |
6305 | UCHAR ucReserved; |
5658 | ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; |
6306 | ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; |
5659 | }ATOM_VRAM_INFO_HEADER_V2_1; |
6307 | }ATOM_VRAM_INFO_HEADER_V2_1; |
5660 | 6308 | ||
5661 | 6309 | ||
5662 | typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO |
6310 | typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO |
5663 | { |
6311 | { |
5664 | ATOM_COMMON_TABLE_HEADER sHeader; |
6312 | ATOM_COMMON_TABLE_HEADER sHeader; |
5665 | UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator |
6313 | UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator |
5666 | }ATOM_VRAM_GPIO_DETECTION_INFO; |
6314 | }ATOM_VRAM_GPIO_DETECTION_INFO; |
5667 | 6315 | ||
5668 | 6316 | ||
5669 | typedef struct _ATOM_MEMORY_TRAINING_INFO |
6317 | typedef struct _ATOM_MEMORY_TRAINING_INFO |
5670 | { |
6318 | { |
5671 | ATOM_COMMON_TABLE_HEADER sHeader; |
6319 | ATOM_COMMON_TABLE_HEADER sHeader; |
5672 | UCHAR ucTrainingLoop; |
6320 | UCHAR ucTrainingLoop; |
5673 | UCHAR ucReserved[3]; |
6321 | UCHAR ucReserved[3]; |
5674 | ATOM_INIT_REG_BLOCK asMemTrainingSetting; |
6322 | ATOM_INIT_REG_BLOCK asMemTrainingSetting; |
5675 | }ATOM_MEMORY_TRAINING_INFO; |
6323 | }ATOM_MEMORY_TRAINING_INFO; |
5676 | 6324 | ||
5677 | 6325 | ||
5678 | typedef struct SW_I2C_CNTL_DATA_PARAMETERS |
6326 | typedef struct SW_I2C_CNTL_DATA_PARAMETERS |
5679 | { |
6327 | { |
5680 | UCHAR ucControl; |
6328 | UCHAR ucControl; |
5681 | UCHAR ucData; |
6329 | UCHAR ucData; |
5682 | UCHAR ucSatus; |
6330 | UCHAR ucSatus; |
5683 | UCHAR ucTemp; |
6331 | UCHAR ucTemp; |
5684 | } SW_I2C_CNTL_DATA_PARAMETERS; |
6332 | } SW_I2C_CNTL_DATA_PARAMETERS; |
5685 | 6333 | ||
5686 | #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS |
6334 | #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS |
5687 | 6335 | ||
5688 | typedef struct _SW_I2C_IO_DATA_PARAMETERS |
6336 | typedef struct _SW_I2C_IO_DATA_PARAMETERS |
5689 | { |
6337 | { |
5690 | USHORT GPIO_Info; |
6338 | USHORT GPIO_Info; |
5691 | UCHAR ucAct; |
6339 | UCHAR ucAct; |
5692 | UCHAR ucData; |
6340 | UCHAR ucData; |
5693 | } SW_I2C_IO_DATA_PARAMETERS; |
6341 | } SW_I2C_IO_DATA_PARAMETERS; |
5694 | 6342 | ||
5695 | #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS |
6343 | #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS |
5696 | 6344 | ||
5697 | /****************************SW I2C CNTL DEFINITIONS**********************/ |
6345 | /****************************SW I2C CNTL DEFINITIONS**********************/ |
5698 | #define SW_I2C_IO_RESET 0 |
6346 | #define SW_I2C_IO_RESET 0 |
5699 | #define SW_I2C_IO_GET 1 |
6347 | #define SW_I2C_IO_GET 1 |
5700 | #define SW_I2C_IO_DRIVE 2 |
6348 | #define SW_I2C_IO_DRIVE 2 |
5701 | #define SW_I2C_IO_SET 3 |
6349 | #define SW_I2C_IO_SET 3 |
5702 | #define SW_I2C_IO_START 4 |
6350 | #define SW_I2C_IO_START 4 |
5703 | 6351 | ||
5704 | #define SW_I2C_IO_CLOCK 0 |
6352 | #define SW_I2C_IO_CLOCK 0 |
5705 | #define SW_I2C_IO_DATA 0x80 |
6353 | #define SW_I2C_IO_DATA 0x80 |
5706 | 6354 | ||
5707 | #define SW_I2C_IO_ZERO 0 |
6355 | #define SW_I2C_IO_ZERO 0 |
5708 | #define SW_I2C_IO_ONE 0x100 |
6356 | #define SW_I2C_IO_ONE 0x100 |
5709 | 6357 | ||
5710 | #define SW_I2C_CNTL_READ 0 |
6358 | #define SW_I2C_CNTL_READ 0 |
5711 | #define SW_I2C_CNTL_WRITE 1 |
6359 | #define SW_I2C_CNTL_WRITE 1 |
5712 | #define SW_I2C_CNTL_START 2 |
6360 | #define SW_I2C_CNTL_START 2 |
5713 | #define SW_I2C_CNTL_STOP 3 |
6361 | #define SW_I2C_CNTL_STOP 3 |
5714 | #define SW_I2C_CNTL_OPEN 4 |
6362 | #define SW_I2C_CNTL_OPEN 4 |
5715 | #define SW_I2C_CNTL_CLOSE 5 |
6363 | #define SW_I2C_CNTL_CLOSE 5 |
5716 | #define SW_I2C_CNTL_WRITE1BIT 6 |
6364 | #define SW_I2C_CNTL_WRITE1BIT 6 |
5717 | 6365 | ||
5718 | //==============================VESA definition Portion=============================== |
6366 | //==============================VESA definition Portion=============================== |
5719 | #define VESA_OEM_PRODUCT_REV "01.00" |
6367 | #define VESA_OEM_PRODUCT_REV "01.00" |
5720 | #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support |
6368 | #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support |
5721 | #define VESA_MODE_WIN_ATTRIBUTE 7 |
6369 | #define VESA_MODE_WIN_ATTRIBUTE 7 |
5722 | #define VESA_WIN_SIZE 64 |
6370 | #define VESA_WIN_SIZE 64 |
5723 | 6371 | ||
5724 | typedef struct _PTR_32_BIT_STRUCTURE |
6372 | typedef struct _PTR_32_BIT_STRUCTURE |
5725 | { |
6373 | { |
5726 | USHORT Offset16; |
6374 | USHORT Offset16; |
5727 | USHORT Segment16; |
6375 | USHORT Segment16; |
5728 | } PTR_32_BIT_STRUCTURE; |
6376 | } PTR_32_BIT_STRUCTURE; |
5729 | 6377 | ||
5730 | typedef union _PTR_32_BIT_UNION |
6378 | typedef union _PTR_32_BIT_UNION |
5731 | { |
6379 | { |
5732 | PTR_32_BIT_STRUCTURE SegmentOffset; |
6380 | PTR_32_BIT_STRUCTURE SegmentOffset; |
5733 | ULONG Ptr32_Bit; |
6381 | ULONG Ptr32_Bit; |
5734 | } PTR_32_BIT_UNION; |
6382 | } PTR_32_BIT_UNION; |
5735 | 6383 | ||
5736 | typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE |
6384 | typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE |
5737 | { |
6385 | { |
5738 | UCHAR VbeSignature[4]; |
6386 | UCHAR VbeSignature[4]; |
5739 | USHORT VbeVersion; |
6387 | USHORT VbeVersion; |
5740 | PTR_32_BIT_UNION OemStringPtr; |
6388 | PTR_32_BIT_UNION OemStringPtr; |
5741 | UCHAR Capabilities[4]; |
6389 | UCHAR Capabilities[4]; |
5742 | PTR_32_BIT_UNION VideoModePtr; |
6390 | PTR_32_BIT_UNION VideoModePtr; |
5743 | USHORT TotalMemory; |
6391 | USHORT TotalMemory; |
5744 | } VBE_1_2_INFO_BLOCK_UPDATABLE; |
6392 | } VBE_1_2_INFO_BLOCK_UPDATABLE; |
5745 | 6393 | ||
5746 | 6394 | ||
5747 | typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE |
6395 | typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE |
5748 | { |
6396 | { |
5749 | VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; |
6397 | VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; |
5750 | USHORT OemSoftRev; |
6398 | USHORT OemSoftRev; |
5751 | PTR_32_BIT_UNION OemVendorNamePtr; |
6399 | PTR_32_BIT_UNION OemVendorNamePtr; |
5752 | PTR_32_BIT_UNION OemProductNamePtr; |
6400 | PTR_32_BIT_UNION OemProductNamePtr; |
5753 | PTR_32_BIT_UNION OemProductRevPtr; |
6401 | PTR_32_BIT_UNION OemProductRevPtr; |
5754 | } VBE_2_0_INFO_BLOCK_UPDATABLE; |
6402 | } VBE_2_0_INFO_BLOCK_UPDATABLE; |
5755 | 6403 | ||
5756 | typedef union _VBE_VERSION_UNION |
6404 | typedef union _VBE_VERSION_UNION |
5757 | { |
6405 | { |
5758 | VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; |
6406 | VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; |
5759 | VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; |
6407 | VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; |
5760 | } VBE_VERSION_UNION; |
6408 | } VBE_VERSION_UNION; |
5761 | 6409 | ||
5762 | typedef struct _VBE_INFO_BLOCK |
6410 | typedef struct _VBE_INFO_BLOCK |
5763 | { |
6411 | { |
5764 | VBE_VERSION_UNION UpdatableVBE_Info; |
6412 | VBE_VERSION_UNION UpdatableVBE_Info; |
5765 | UCHAR Reserved[222]; |
6413 | UCHAR Reserved[222]; |
5766 | UCHAR OemData[256]; |
6414 | UCHAR OemData[256]; |
5767 | } VBE_INFO_BLOCK; |
6415 | } VBE_INFO_BLOCK; |
5768 | 6416 | ||
5769 | typedef struct _VBE_FP_INFO |
6417 | typedef struct _VBE_FP_INFO |
5770 | { |
6418 | { |
5771 | USHORT HSize; |
6419 | USHORT HSize; |
5772 | USHORT VSize; |
6420 | USHORT VSize; |
5773 | USHORT FPType; |
6421 | USHORT FPType; |
5774 | UCHAR RedBPP; |
6422 | UCHAR RedBPP; |
5775 | UCHAR GreenBPP; |
6423 | UCHAR GreenBPP; |
5776 | UCHAR BlueBPP; |
6424 | UCHAR BlueBPP; |
5777 | UCHAR ReservedBPP; |
6425 | UCHAR ReservedBPP; |
5778 | ULONG RsvdOffScrnMemSize; |
6426 | ULONG RsvdOffScrnMemSize; |
5779 | ULONG RsvdOffScrnMEmPtr; |
6427 | ULONG RsvdOffScrnMEmPtr; |
5780 | UCHAR Reserved[14]; |
6428 | UCHAR Reserved[14]; |
5781 | } VBE_FP_INFO; |
6429 | } VBE_FP_INFO; |
5782 | 6430 | ||
5783 | typedef struct _VESA_MODE_INFO_BLOCK |
6431 | typedef struct _VESA_MODE_INFO_BLOCK |
5784 | { |
6432 | { |
5785 | // Mandatory information for all VBE revisions |
6433 | // Mandatory information for all VBE revisions |
5786 | USHORT ModeAttributes; // dw ? ; mode attributes |
6434 | USHORT ModeAttributes; // dw ? ; mode attributes |
5787 | UCHAR WinAAttributes; // db ? ; window A attributes |
6435 | UCHAR WinAAttributes; // db ? ; window A attributes |
5788 | UCHAR WinBAttributes; // db ? ; window B attributes |
6436 | UCHAR WinBAttributes; // db ? ; window B attributes |
5789 | USHORT WinGranularity; // dw ? ; window granularity |
6437 | USHORT WinGranularity; // dw ? ; window granularity |
5790 | USHORT WinSize; // dw ? ; window size |
6438 | USHORT WinSize; // dw ? ; window size |
5791 | USHORT WinASegment; // dw ? ; window A start segment |
6439 | USHORT WinASegment; // dw ? ; window A start segment |
5792 | USHORT WinBSegment; // dw ? ; window B start segment |
6440 | USHORT WinBSegment; // dw ? ; window B start segment |
5793 | ULONG WinFuncPtr; // dd ? ; real mode pointer to window function |
6441 | ULONG WinFuncPtr; // dd ? ; real mode pointer to window function |
5794 | USHORT BytesPerScanLine;// dw ? ; bytes per scan line |
6442 | USHORT BytesPerScanLine;// dw ? ; bytes per scan line |
5795 | 6443 | ||
5796 | //; Mandatory information for VBE 1.2 and above |
6444 | //; Mandatory information for VBE 1.2 and above |
5797 | USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters |
6445 | USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters |
5798 | USHORT YResolution; // dw ? ; vertical resolution in pixels or characters |
6446 | USHORT YResolution; // dw ? ; vertical resolution in pixels or characters |
5799 | UCHAR XCharSize; // db ? ; character cell width in pixels |
6447 | UCHAR XCharSize; // db ? ; character cell width in pixels |
5800 | UCHAR YCharSize; // db ? ; character cell height in pixels |
6448 | UCHAR YCharSize; // db ? ; character cell height in pixels |
5801 | UCHAR NumberOfPlanes; // db ? ; number of memory planes |
6449 | UCHAR NumberOfPlanes; // db ? ; number of memory planes |
5802 | UCHAR BitsPerPixel; // db ? ; bits per pixel |
6450 | UCHAR BitsPerPixel; // db ? ; bits per pixel |
5803 | UCHAR NumberOfBanks; // db ? ; number of banks |
6451 | UCHAR NumberOfBanks; // db ? ; number of banks |
5804 | UCHAR MemoryModel; // db ? ; memory model type |
6452 | UCHAR MemoryModel; // db ? ; memory model type |
5805 | UCHAR BankSize; // db ? ; bank size in KB |
6453 | UCHAR BankSize; // db ? ; bank size in KB |
5806 | UCHAR NumberOfImagePages;// db ? ; number of images |
6454 | UCHAR NumberOfImagePages;// db ? ; number of images |
5807 | UCHAR ReservedForPageFunction;//db 1 ; reserved for page function |
6455 | UCHAR ReservedForPageFunction;//db 1 ; reserved for page function |
5808 | 6456 | ||
5809 | //; Direct Color fields(required for direct/6 and YUV/7 memory models) |
6457 | //; Direct Color fields(required for direct/6 and YUV/7 memory models) |
5810 | UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits |
6458 | UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits |
5811 | UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask |
6459 | UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask |
5812 | UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits |
6460 | UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits |
5813 | UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask |
6461 | UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask |
5814 | UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits |
6462 | UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits |
5815 | UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask |
6463 | UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask |
5816 | UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits |
6464 | UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits |
5817 | UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask |
6465 | UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask |
5818 | UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes |
6466 | UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes |
5819 | 6467 | ||
5820 | //; Mandatory information for VBE 2.0 and above |
6468 | //; Mandatory information for VBE 2.0 and above |
5821 | ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer |
6469 | ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer |
5822 | ULONG Reserved_1; // dd 0 ; reserved - always set to 0 |
6470 | ULONG Reserved_1; // dd 0 ; reserved - always set to 0 |
5823 | USHORT Reserved_2; // dw 0 ; reserved - always set to 0 |
6471 | USHORT Reserved_2; // dw 0 ; reserved - always set to 0 |
5824 | 6472 | ||
5825 | //; Mandatory information for VBE 3.0 and above |
6473 | //; Mandatory information for VBE 3.0 and above |
5826 | USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes |
6474 | USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes |
5827 | UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes |
6475 | UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes |
5828 | UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes |
6476 | UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes |
5829 | UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) |
6477 | UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) |
5830 | UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) |
6478 | UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) |
5831 | UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) |
6479 | UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) |
5832 | UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) |
6480 | UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) |
5833 | UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) |
6481 | UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) |
5834 | UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) |
6482 | UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) |
5835 | UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) |
6483 | UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) |
5836 | UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) |
6484 | UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) |
5837 | ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode |
6485 | ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode |
5838 | UCHAR Reserved; // db 190 dup (0) |
6486 | UCHAR Reserved; // db 190 dup (0) |
5839 | } VESA_MODE_INFO_BLOCK; |
6487 | } VESA_MODE_INFO_BLOCK; |
5840 | 6488 | ||
5841 | // BIOS function CALLS |
6489 | // BIOS function CALLS |
5842 | #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code |
6490 | #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code |
5843 | #define ATOM_BIOS_FUNCTION_COP_MODE 0x00 |
6491 | #define ATOM_BIOS_FUNCTION_COP_MODE 0x00 |
5844 | #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 |
6492 | #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 |
5845 | #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 |
6493 | #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 |
5846 | #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 |
6494 | #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 |
5847 | #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B |
6495 | #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B |
5848 | #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E |
6496 | #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E |
5849 | #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F |
6497 | #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F |
5850 | #define ATOM_BIOS_FUNCTION_STV_STD 0x16 |
6498 | #define ATOM_BIOS_FUNCTION_STV_STD 0x16 |
5851 | #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 |
6499 | #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 |
5852 | #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 |
6500 | #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 |
5853 | 6501 | ||
5854 | #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 |
6502 | #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 |
5855 | #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 |
6503 | #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 |
5856 | #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 |
6504 | #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 |
5857 | #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A |
6505 | #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A |
5858 | #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B |
6506 | #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B |
5859 | #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 |
6507 | #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 |
5860 | #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 |
6508 | #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 |
5861 | 6509 | ||
5862 | #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D |
6510 | #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D |
5863 | #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E |
6511 | #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E |
5864 | #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F |
6512 | #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F |
5865 | #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 |
6513 | #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 |
5866 | #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 |
6514 | #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 |
5867 | #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state |
6515 | #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state |
5868 | #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state |
6516 | #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state |
5869 | #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 |
6517 | #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 |
5870 | #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 |
6518 | #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 |
5871 | #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported |
6519 | #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported |
5872 | 6520 | ||
5873 | 6521 | ||
5874 | #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS |
6522 | #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS |
5875 | #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 |
6523 | #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 |
5876 | #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 |
6524 | #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 |
5877 | #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. |
6525 | #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. |
5878 | #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY |
6526 | #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY |
5879 | #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND |
6527 | #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND |
5880 | #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF |
6528 | #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF |
5881 | #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) |
6529 | #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) |
5882 | 6530 | ||
5883 | #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L |
6531 | #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L |
5884 | #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L |
6532 | #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L |
5885 | #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL |
6533 | #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL |
5886 | 6534 | ||
5887 | // structure used for VBIOS only |
6535 | // structure used for VBIOS only |
5888 | 6536 | ||
5889 | //DispOutInfoTable |
6537 | //DispOutInfoTable |
5890 | typedef struct _ASIC_TRANSMITTER_INFO |
6538 | typedef struct _ASIC_TRANSMITTER_INFO |
5891 | { |
6539 | { |
5892 | USHORT usTransmitterObjId; |
6540 | USHORT usTransmitterObjId; |
5893 | USHORT usSupportDevice; |
6541 | USHORT usSupportDevice; |
5894 | UCHAR ucTransmitterCmdTblId; |
6542 | UCHAR ucTransmitterCmdTblId; |
5895 | UCHAR ucConfig; |
6543 | UCHAR ucConfig; |
5896 | UCHAR ucEncoderID; //available 1st encoder ( default ) |
6544 | UCHAR ucEncoderID; //available 1st encoder ( default ) |
5897 | UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) |
6545 | UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) |
5898 | UCHAR uc2ndEncoderID; |
6546 | UCHAR uc2ndEncoderID; |
5899 | UCHAR ucReserved; |
6547 | UCHAR ucReserved; |
5900 | }ASIC_TRANSMITTER_INFO; |
6548 | }ASIC_TRANSMITTER_INFO; |
5901 | 6549 | ||
5902 | #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 |
6550 | #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 |
5903 | #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 |
6551 | #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 |
5904 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 |
6552 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 |
5905 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 |
6553 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 |
5906 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 |
6554 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 |
5907 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 |
6555 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 |
5908 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 |
6556 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 |
5909 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 |
6557 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 |
5910 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 |
6558 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 |
5911 | 6559 | ||
5912 | typedef struct _ASIC_ENCODER_INFO |
6560 | typedef struct _ASIC_ENCODER_INFO |
5913 | { |
6561 | { |
5914 | UCHAR ucEncoderID; |
6562 | UCHAR ucEncoderID; |
5915 | UCHAR ucEncoderConfig; |
6563 | UCHAR ucEncoderConfig; |
5916 | USHORT usEncoderCmdTblId; |
6564 | USHORT usEncoderCmdTblId; |
5917 | }ASIC_ENCODER_INFO; |
6565 | }ASIC_ENCODER_INFO; |
5918 | 6566 | ||
5919 | typedef struct _ATOM_DISP_OUT_INFO |
6567 | typedef struct _ATOM_DISP_OUT_INFO |
5920 | { |
6568 | { |
5921 | ATOM_COMMON_TABLE_HEADER sHeader; |
6569 | ATOM_COMMON_TABLE_HEADER sHeader; |
5922 | USHORT ptrTransmitterInfo; |
6570 | USHORT ptrTransmitterInfo; |
5923 | USHORT ptrEncoderInfo; |
6571 | USHORT ptrEncoderInfo; |
5924 | ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; |
6572 | ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; |
5925 | ASIC_ENCODER_INFO asEncoderInfo[1]; |
6573 | ASIC_ENCODER_INFO asEncoderInfo[1]; |
5926 | }ATOM_DISP_OUT_INFO; |
6574 | }ATOM_DISP_OUT_INFO; |
5927 | 6575 | ||
5928 | typedef struct _ATOM_DISP_OUT_INFO_V2 |
6576 | typedef struct _ATOM_DISP_OUT_INFO_V2 |
5929 | { |
6577 | { |
5930 | ATOM_COMMON_TABLE_HEADER sHeader; |
6578 | ATOM_COMMON_TABLE_HEADER sHeader; |
5931 | USHORT ptrTransmitterInfo; |
6579 | USHORT ptrTransmitterInfo; |
5932 | USHORT ptrEncoderInfo; |
6580 | USHORT ptrEncoderInfo; |
5933 | USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. |
6581 | USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. |
5934 | ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; |
6582 | ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; |
5935 | ASIC_ENCODER_INFO asEncoderInfo[1]; |
6583 | ASIC_ENCODER_INFO asEncoderInfo[1]; |
5936 | }ATOM_DISP_OUT_INFO_V2; |
6584 | }ATOM_DISP_OUT_INFO_V2; |
- | 6585 | ||
- | 6586 | ||
- | 6587 | typedef struct _ATOM_DISP_CLOCK_ID { |
|
- | 6588 | UCHAR ucPpllId; |
|
- | 6589 | UCHAR ucPpllAttribute; |
|
- | 6590 | }ATOM_DISP_CLOCK_ID; |
|
- | 6591 | ||
- | 6592 | // ucPpllAttribute |
|
- | 6593 | #define CLOCK_SOURCE_SHAREABLE 0x01 |
|
- | 6594 | #define CLOCK_SOURCE_DP_MODE 0x02 |
|
- | 6595 | #define CLOCK_SOURCE_NONE_DP_MODE 0x04 |
|
- | 6596 | ||
- | 6597 | //DispOutInfoTable |
|
- | 6598 | typedef struct _ASIC_TRANSMITTER_INFO_V2 |
|
- | 6599 | { |
|
- | 6600 | USHORT usTransmitterObjId; |
|
- | 6601 | USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object |
|
- | 6602 | UCHAR ucTransmitterCmdTblId; |
|
- | 6603 | UCHAR ucConfig; |
|
- | 6604 | UCHAR ucEncoderID; // available 1st encoder ( default ) |
|
- | 6605 | UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) |
|
- | 6606 | UCHAR uc2ndEncoderID; |
|
- | 6607 | UCHAR ucReserved; |
|
- | 6608 | }ASIC_TRANSMITTER_INFO_V2; |
|
- | 6609 | ||
- | 6610 | typedef struct _ATOM_DISP_OUT_INFO_V3 |
|
- | 6611 | { |
|
- | 6612 | ATOM_COMMON_TABLE_HEADER sHeader; |
|
- | 6613 | USHORT ptrTransmitterInfo; |
|
- | 6614 | USHORT ptrEncoderInfo; |
|
- | 6615 | USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. |
|
- | 6616 | USHORT usReserved; |
|
- | 6617 | UCHAR ucDCERevision; |
|
- | 6618 | UCHAR ucMaxDispEngineNum; |
|
- | 6619 | UCHAR ucMaxActiveDispEngineNum; |
|
- | 6620 | UCHAR ucMaxPPLLNum; |
|
- | 6621 | UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE |
|
- | 6622 | UCHAR ucReserved[3]; |
|
- | 6623 | ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only |
|
- | 6624 | }ATOM_DISP_OUT_INFO_V3; |
|
- | 6625 | ||
- | 6626 | typedef enum CORE_REF_CLK_SOURCE{ |
|
- | 6627 | CLOCK_SRC_XTALIN=0, |
|
- | 6628 | CLOCK_SRC_XO_IN=1, |
|
- | 6629 | CLOCK_SRC_XO_IN2=2, |
|
- | 6630 | }CORE_REF_CLK_SOURCE; |
|
5937 | 6631 | ||
5938 | // DispDevicePriorityInfo |
6632 | // DispDevicePriorityInfo |
5939 | typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO |
6633 | typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO |
5940 | { |
6634 | { |
5941 | ATOM_COMMON_TABLE_HEADER sHeader; |
6635 | ATOM_COMMON_TABLE_HEADER sHeader; |
5942 | USHORT asDevicePriority[16]; |
6636 | USHORT asDevicePriority[16]; |
5943 | }ATOM_DISPLAY_DEVICE_PRIORITY_INFO; |
6637 | }ATOM_DISPLAY_DEVICE_PRIORITY_INFO; |
5944 | 6638 | ||
5945 | //ProcessAuxChannelTransactionTable |
6639 | //ProcessAuxChannelTransactionTable |
5946 | typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS |
6640 | typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS |
5947 | { |
6641 | { |
5948 | USHORT lpAuxRequest; |
6642 | USHORT lpAuxRequest; |
5949 | USHORT lpDataOut; |
6643 | USHORT lpDataOut; |
5950 | UCHAR ucChannelID; |
6644 | UCHAR ucChannelID; |
5951 | union |
6645 | union |
5952 | { |
6646 | { |
5953 | UCHAR ucReplyStatus; |
6647 | UCHAR ucReplyStatus; |
5954 | UCHAR ucDelay; |
6648 | UCHAR ucDelay; |
5955 | }; |
6649 | }; |
5956 | UCHAR ucDataOutLen; |
6650 | UCHAR ucDataOutLen; |
5957 | UCHAR ucReserved; |
6651 | UCHAR ucReserved; |
5958 | }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; |
6652 | }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; |
5959 | 6653 | ||
5960 | //ProcessAuxChannelTransactionTable |
6654 | //ProcessAuxChannelTransactionTable |
5961 | typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 |
6655 | typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 |
5962 | { |
6656 | { |
5963 | USHORT lpAuxRequest; |
6657 | USHORT lpAuxRequest; |
5964 | USHORT lpDataOut; |
6658 | USHORT lpDataOut; |
5965 | UCHAR ucChannelID; |
6659 | UCHAR ucChannelID; |
5966 | union |
6660 | union |
5967 | { |
6661 | { |
5968 | UCHAR ucReplyStatus; |
6662 | UCHAR ucReplyStatus; |
5969 | UCHAR ucDelay; |
6663 | UCHAR ucDelay; |
5970 | }; |
6664 | }; |
5971 | UCHAR ucDataOutLen; |
6665 | UCHAR ucDataOutLen; |
5972 | UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 |
6666 | UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 |
5973 | }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; |
6667 | }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; |
5974 | 6668 | ||
5975 | #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS |
6669 | #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS |
5976 | 6670 | ||
5977 | //GetSinkType |
6671 | //GetSinkType |
5978 | 6672 | ||
5979 | typedef struct _DP_ENCODER_SERVICE_PARAMETERS |
6673 | typedef struct _DP_ENCODER_SERVICE_PARAMETERS |
5980 | { |
6674 | { |
5981 | USHORT ucLinkClock; |
6675 | USHORT ucLinkClock; |
5982 | union |
6676 | union |
5983 | { |
6677 | { |
5984 | UCHAR ucConfig; // for DP training command |
6678 | UCHAR ucConfig; // for DP training command |
5985 | UCHAR ucI2cId; // use for GET_SINK_TYPE command |
6679 | UCHAR ucI2cId; // use for GET_SINK_TYPE command |
5986 | }; |
6680 | }; |
5987 | UCHAR ucAction; |
6681 | UCHAR ucAction; |
5988 | UCHAR ucStatus; |
6682 | UCHAR ucStatus; |
5989 | UCHAR ucLaneNum; |
6683 | UCHAR ucLaneNum; |
5990 | UCHAR ucReserved[2]; |
6684 | UCHAR ucReserved[2]; |
5991 | }DP_ENCODER_SERVICE_PARAMETERS; |
6685 | }DP_ENCODER_SERVICE_PARAMETERS; |
5992 | 6686 | ||
5993 | // ucAction |
6687 | // ucAction |
5994 | #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 |
6688 | #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 |
5995 | /* obselete */ |
6689 | /* obselete */ |
5996 | #define ATOM_DP_ACTION_TRAINING_START 0x02 |
6690 | #define ATOM_DP_ACTION_TRAINING_START 0x02 |
5997 | #define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 |
6691 | #define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 |
5998 | #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 |
6692 | #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 |
5999 | #define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 |
6693 | #define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 |
6000 | #define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 |
6694 | #define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 |
6001 | #define ATOM_DP_ACTION_BLANKING 0x07 |
6695 | #define ATOM_DP_ACTION_BLANKING 0x07 |
6002 | 6696 | ||
6003 | // ucConfig |
6697 | // ucConfig |
6004 | #define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 |
6698 | #define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 |
6005 | #define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 |
6699 | #define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 |
6006 | #define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 |
6700 | #define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 |
6007 | #define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 |
6701 | #define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 |
6008 | #define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 |
6702 | #define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 |
6009 | #define ATOM_DP_CONFIG_LINK_A 0x00 |
6703 | #define ATOM_DP_CONFIG_LINK_A 0x00 |
6010 | #define ATOM_DP_CONFIG_LINK_B 0x04 |
6704 | #define ATOM_DP_CONFIG_LINK_B 0x04 |
6011 | /* /obselete */ |
6705 | /* /obselete */ |
6012 | #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
6706 | #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
6013 | 6707 | ||
6014 | 6708 | ||
6015 | typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 |
6709 | typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 |
6016 | { |
6710 | { |
6017 | USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION |
6711 | USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION |
6018 | UCHAR ucAuxId; |
6712 | UCHAR ucAuxId; |
6019 | UCHAR ucAction; |
6713 | UCHAR ucAction; |
6020 | UCHAR ucSinkType; // Iput and Output parameters. |
6714 | UCHAR ucSinkType; // Iput and Output parameters. |
6021 | UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION |
6715 | UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION |
6022 | UCHAR ucReserved[2]; |
6716 | UCHAR ucReserved[2]; |
6023 | }DP_ENCODER_SERVICE_PARAMETERS_V2; |
6717 | }DP_ENCODER_SERVICE_PARAMETERS_V2; |
6024 | 6718 | ||
6025 | typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 |
6719 | typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 |
6026 | { |
6720 | { |
6027 | DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; |
6721 | DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; |
6028 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; |
6722 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; |
6029 | }DP_ENCODER_SERVICE_PS_ALLOCATION_V2; |
6723 | }DP_ENCODER_SERVICE_PS_ALLOCATION_V2; |
6030 | 6724 | ||
6031 | // ucAction |
6725 | // ucAction |
6032 | #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 |
6726 | #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 |
6033 | #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 |
6727 | #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 |
6034 | 6728 | ||
6035 | 6729 | ||
6036 | // DP_TRAINING_TABLE |
6730 | // DP_TRAINING_TABLE |
6037 | #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR |
6731 | #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR |
6038 | #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) |
6732 | #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) |
6039 | #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) |
6733 | #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) |
6040 | #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) |
6734 | #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) |
6041 | #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) |
6735 | #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) |
6042 | #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) |
6736 | #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) |
6043 | #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) |
6737 | #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) |
6044 | #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) |
6738 | #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) |
6045 | #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) |
6739 | #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) |
6046 | #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) |
6740 | #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) |
6047 | #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) |
6741 | #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) |
6048 | #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) |
6742 | #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) |
6049 | #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) |
6743 | #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) |
6050 | 6744 | ||
6051 | typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS |
6745 | typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS |
6052 | { |
6746 | { |
6053 | UCHAR ucI2CSpeed; |
6747 | UCHAR ucI2CSpeed; |
6054 | union |
6748 | union |
6055 | { |
6749 | { |
6056 | UCHAR ucRegIndex; |
6750 | UCHAR ucRegIndex; |
6057 | UCHAR ucStatus; |
6751 | UCHAR ucStatus; |
6058 | }; |
6752 | }; |
6059 | USHORT lpI2CDataOut; |
6753 | USHORT lpI2CDataOut; |
6060 | UCHAR ucFlag; |
6754 | UCHAR ucFlag; |
6061 | UCHAR ucTransBytes; |
6755 | UCHAR ucTransBytes; |
6062 | UCHAR ucSlaveAddr; |
6756 | UCHAR ucSlaveAddr; |
6063 | UCHAR ucLineNumber; |
6757 | UCHAR ucLineNumber; |
6064 | }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; |
6758 | }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; |
6065 | 6759 | ||
6066 | #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS |
6760 | #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS |
6067 | 6761 | ||
6068 | //ucFlag |
6762 | //ucFlag |
6069 | #define HW_I2C_WRITE 1 |
6763 | #define HW_I2C_WRITE 1 |
6070 | #define HW_I2C_READ 0 |
6764 | #define HW_I2C_READ 0 |
6071 | #define I2C_2BYTE_ADDR 0x02 |
6765 | #define I2C_2BYTE_ADDR 0x02 |
- | 6766 | ||
- | 6767 | /****************************************************************************/ |
|
- | 6768 | // Structures used by HW_Misc_OperationTable |
|
- | 6769 | /****************************************************************************/ |
|
- | 6770 | typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 |
|
- | 6771 | { |
|
- | 6772 | UCHAR ucCmd; // Input: To tell which action to take |
|
- | 6773 | UCHAR ucReserved[3]; |
|
- | 6774 | ULONG ulReserved; |
|
- | 6775 | }ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; |
|
- | 6776 | ||
- | 6777 | typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 |
|
- | 6778 | { |
|
- | 6779 | UCHAR ucReturnCode; // Output: Return value base on action was taken |
|
- | 6780 | UCHAR ucReserved[3]; |
|
- | 6781 | ULONG ulReserved; |
|
- | 6782 | }ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; |
|
- | 6783 | ||
- | 6784 | // Actions code |
|
- | 6785 | #define ATOM_GET_SDI_SUPPORT 0xF0 |
|
- | 6786 | ||
- | 6787 | // Return code |
|
- | 6788 | #define ATOM_UNKNOWN_CMD 0 |
|
- | 6789 | #define ATOM_FEATURE_NOT_SUPPORTED 1 |
|
- | 6790 | #define ATOM_FEATURE_SUPPORTED 2 |
|
- | 6791 | ||
- | 6792 | typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION |
|
- | 6793 | { |
|
- | 6794 | ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; |
|
- | 6795 | PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; |
|
- | 6796 | }ATOM_HW_MISC_OPERATION_PS_ALLOCATION; |
|
- | 6797 | ||
- | 6798 | /****************************************************************************/ |
|
6072 | 6799 | ||
6073 | typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 |
6800 | typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 |
6074 | { |
6801 | { |
6075 | UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... |
6802 | UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... |
6076 | UCHAR ucReserved[3]; |
6803 | UCHAR ucReserved[3]; |
6077 | }SET_HWBLOCK_INSTANCE_PARAMETER_V2; |
6804 | }SET_HWBLOCK_INSTANCE_PARAMETER_V2; |
6078 | 6805 | ||
6079 | #define HWBLKINST_INSTANCE_MASK 0x07 |
6806 | #define HWBLKINST_INSTANCE_MASK 0x07 |
6080 | #define HWBLKINST_HWBLK_MASK 0xF0 |
6807 | #define HWBLKINST_HWBLK_MASK 0xF0 |
6081 | #define HWBLKINST_HWBLK_SHIFT 0x04 |
6808 | #define HWBLKINST_HWBLK_SHIFT 0x04 |
6082 | 6809 | ||
6083 | //ucHWBlock |
6810 | //ucHWBlock |
6084 | #define SELECT_DISP_ENGINE 0 |
6811 | #define SELECT_DISP_ENGINE 0 |
6085 | #define SELECT_DISP_PLL 1 |
6812 | #define SELECT_DISP_PLL 1 |
6086 | #define SELECT_DCIO_UNIPHY_LINK0 2 |
6813 | #define SELECT_DCIO_UNIPHY_LINK0 2 |
6087 | #define SELECT_DCIO_UNIPHY_LINK1 3 |
6814 | #define SELECT_DCIO_UNIPHY_LINK1 3 |
6088 | #define SELECT_DCIO_IMPCAL 4 |
6815 | #define SELECT_DCIO_IMPCAL 4 |
6089 | #define SELECT_DCIO_DIG 6 |
6816 | #define SELECT_DCIO_DIG 6 |
6090 | #define SELECT_CRTC_PIXEL_RATE 7 |
6817 | #define SELECT_CRTC_PIXEL_RATE 7 |
6091 | #define SELECT_VGA_BLK 8 |
6818 | #define SELECT_VGA_BLK 8 |
- | 6819 | ||
- | 6820 | // DIGTransmitterInfoTable structure used to program UNIPHY settings |
|
- | 6821 | typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ |
|
- | 6822 | ATOM_COMMON_TABLE_HEADER sHeader; |
|
- | 6823 | USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock |
|
- | 6824 | USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info |
|
- | 6825 | USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range |
|
- | 6826 | USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info |
|
- | 6827 | USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings |
|
- | 6828 | }DIG_TRANSMITTER_INFO_HEADER_V3_1; |
|
- | 6829 | ||
- | 6830 | typedef struct _CLOCK_CONDITION_REGESTER_INFO{ |
|
- | 6831 | USHORT usRegisterIndex; |
|
- | 6832 | UCHAR ucStartBit; |
|
- | 6833 | UCHAR ucEndBit; |
|
- | 6834 | }CLOCK_CONDITION_REGESTER_INFO; |
|
- | 6835 | ||
- | 6836 | typedef struct _CLOCK_CONDITION_SETTING_ENTRY{ |
|
- | 6837 | USHORT usMaxClockFreq; |
|
- | 6838 | UCHAR ucEncodeMode; |
|
- | 6839 | UCHAR ucPhySel; |
|
- | 6840 | ULONG ulAnalogSetting[1]; |
|
- | 6841 | }CLOCK_CONDITION_SETTING_ENTRY; |
|
- | 6842 | ||
- | 6843 | typedef struct _CLOCK_CONDITION_SETTING_INFO{ |
|
- | 6844 | USHORT usEntrySize; |
|
- | 6845 | CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1]; |
|
- | 6846 | }CLOCK_CONDITION_SETTING_INFO; |
|
- | 6847 | ||
- | 6848 | typedef struct _PHY_CONDITION_REG_VAL{ |
|
- | 6849 | ULONG ulCondition; |
|
- | 6850 | ULONG ulRegVal; |
|
- | 6851 | }PHY_CONDITION_REG_VAL; |
|
- | 6852 | ||
- | 6853 | typedef struct _PHY_CONDITION_REG_INFO{ |
|
- | 6854 | USHORT usRegIndex; |
|
- | 6855 | USHORT usSize; |
|
- | 6856 | PHY_CONDITION_REG_VAL asRegVal[1]; |
|
- | 6857 | }PHY_CONDITION_REG_INFO; |
|
- | 6858 | ||
- | 6859 | typedef struct _PHY_ANALOG_SETTING_INFO{ |
|
- | 6860 | UCHAR ucEncodeMode; |
|
- | 6861 | UCHAR ucPhySel; |
|
- | 6862 | USHORT usSize; |
|
- | 6863 | PHY_CONDITION_REG_INFO asAnalogSetting[1]; |
|
- | 6864 | }PHY_ANALOG_SETTING_INFO; |
|
6092 | 6865 | ||
6093 | /****************************************************************************/ |
6866 | /****************************************************************************/ |
6094 | //Portion VI: Definitinos for vbios MC scratch registers that driver used |
6867 | //Portion VI: Definitinos for vbios MC scratch registers that driver used |
6095 | /****************************************************************************/ |
6868 | /****************************************************************************/ |
6096 | 6869 | ||
6097 | #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 |
6870 | #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 |
6098 | #define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 |
6871 | #define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 |
6099 | #define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 |
6872 | #define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 |
6100 | #define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 |
6873 | #define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 |
6101 | #define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 |
6874 | #define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 |
6102 | #define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 |
6875 | #define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 |
6103 | #define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 |
6876 | #define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 |
6104 | 6877 | ||
6105 | /****************************************************************************/ |
6878 | /****************************************************************************/ |
6106 | //Portion VI: Definitinos being oboselete |
6879 | //Portion VI: Definitinos being oboselete |
6107 | /****************************************************************************/ |
6880 | /****************************************************************************/ |
6108 | 6881 | ||
6109 | //========================================================================================== |
6882 | //========================================================================================== |
6110 | //Remove the definitions below when driver is ready! |
6883 | //Remove the definitions below when driver is ready! |
6111 | typedef struct _ATOM_DAC_INFO |
6884 | typedef struct _ATOM_DAC_INFO |
6112 | { |
6885 | { |
6113 | ATOM_COMMON_TABLE_HEADER sHeader; |
6886 | ATOM_COMMON_TABLE_HEADER sHeader; |
6114 | USHORT usMaxFrequency; // in 10kHz unit |
6887 | USHORT usMaxFrequency; // in 10kHz unit |
6115 | USHORT usReserved; |
6888 | USHORT usReserved; |
6116 | }ATOM_DAC_INFO; |
6889 | }ATOM_DAC_INFO; |
6117 | 6890 | ||
6118 | 6891 | ||
6119 | typedef struct _COMPASSIONATE_DATA |
6892 | typedef struct _COMPASSIONATE_DATA |
6120 | { |
6893 | { |
6121 | ATOM_COMMON_TABLE_HEADER sHeader; |
6894 | ATOM_COMMON_TABLE_HEADER sHeader; |
6122 | 6895 | ||
6123 | //============================== DAC1 portion |
6896 | //============================== DAC1 portion |
6124 | UCHAR ucDAC1_BG_Adjustment; |
6897 | UCHAR ucDAC1_BG_Adjustment; |
6125 | UCHAR ucDAC1_DAC_Adjustment; |
6898 | UCHAR ucDAC1_DAC_Adjustment; |
6126 | USHORT usDAC1_FORCE_Data; |
6899 | USHORT usDAC1_FORCE_Data; |
6127 | //============================== DAC2 portion |
6900 | //============================== DAC2 portion |
6128 | UCHAR ucDAC2_CRT2_BG_Adjustment; |
6901 | UCHAR ucDAC2_CRT2_BG_Adjustment; |
6129 | UCHAR ucDAC2_CRT2_DAC_Adjustment; |
6902 | UCHAR ucDAC2_CRT2_DAC_Adjustment; |
6130 | USHORT usDAC2_CRT2_FORCE_Data; |
6903 | USHORT usDAC2_CRT2_FORCE_Data; |
6131 | USHORT usDAC2_CRT2_MUX_RegisterIndex; |
6904 | USHORT usDAC2_CRT2_MUX_RegisterIndex; |
6132 | UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low |
6905 | UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low |
6133 | UCHAR ucDAC2_NTSC_BG_Adjustment; |
6906 | UCHAR ucDAC2_NTSC_BG_Adjustment; |
6134 | UCHAR ucDAC2_NTSC_DAC_Adjustment; |
6907 | UCHAR ucDAC2_NTSC_DAC_Adjustment; |
6135 | USHORT usDAC2_TV1_FORCE_Data; |
6908 | USHORT usDAC2_TV1_FORCE_Data; |
6136 | USHORT usDAC2_TV1_MUX_RegisterIndex; |
6909 | USHORT usDAC2_TV1_MUX_RegisterIndex; |
6137 | UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low |
6910 | UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low |
6138 | UCHAR ucDAC2_CV_BG_Adjustment; |
6911 | UCHAR ucDAC2_CV_BG_Adjustment; |
6139 | UCHAR ucDAC2_CV_DAC_Adjustment; |
6912 | UCHAR ucDAC2_CV_DAC_Adjustment; |
6140 | USHORT usDAC2_CV_FORCE_Data; |
6913 | USHORT usDAC2_CV_FORCE_Data; |
6141 | USHORT usDAC2_CV_MUX_RegisterIndex; |
6914 | USHORT usDAC2_CV_MUX_RegisterIndex; |
6142 | UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low |
6915 | UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low |
6143 | UCHAR ucDAC2_PAL_BG_Adjustment; |
6916 | UCHAR ucDAC2_PAL_BG_Adjustment; |
6144 | UCHAR ucDAC2_PAL_DAC_Adjustment; |
6917 | UCHAR ucDAC2_PAL_DAC_Adjustment; |
6145 | USHORT usDAC2_TV2_FORCE_Data; |
6918 | USHORT usDAC2_TV2_FORCE_Data; |
6146 | }COMPASSIONATE_DATA; |
6919 | }COMPASSIONATE_DATA; |
6147 | 6920 | ||
6148 | /****************************Supported Device Info Table Definitions**********************/ |
6921 | /****************************Supported Device Info Table Definitions**********************/ |
6149 | // ucConnectInfo: |
6922 | // ucConnectInfo: |
6150 | // [7:4] - connector type |
6923 | // [7:4] - connector type |
6151 | // = 1 - VGA connector |
6924 | // = 1 - VGA connector |
6152 | // = 2 - DVI-I |
6925 | // = 2 - DVI-I |
6153 | // = 3 - DVI-D |
6926 | // = 3 - DVI-D |
6154 | // = 4 - DVI-A |
6927 | // = 4 - DVI-A |
6155 | // = 5 - SVIDEO |
6928 | // = 5 - SVIDEO |
6156 | // = 6 - COMPOSITE |
6929 | // = 6 - COMPOSITE |
6157 | // = 7 - LVDS |
6930 | // = 7 - LVDS |
6158 | // = 8 - DIGITAL LINK |
6931 | // = 8 - DIGITAL LINK |
6159 | // = 9 - SCART |
6932 | // = 9 - SCART |
6160 | // = 0xA - HDMI_type A |
6933 | // = 0xA - HDMI_type A |
6161 | // = 0xB - HDMI_type B |
6934 | // = 0xB - HDMI_type B |
6162 | // = 0xE - Special case1 (DVI+DIN) |
6935 | // = 0xE - Special case1 (DVI+DIN) |
6163 | // Others=TBD |
6936 | // Others=TBD |
6164 | // [3:0] - DAC Associated |
6937 | // [3:0] - DAC Associated |
6165 | // = 0 - no DAC |
6938 | // = 0 - no DAC |
6166 | // = 1 - DACA |
6939 | // = 1 - DACA |
6167 | // = 2 - DACB |
6940 | // = 2 - DACB |
6168 | // = 3 - External DAC |
6941 | // = 3 - External DAC |
6169 | // Others=TBD |
6942 | // Others=TBD |
6170 | // |
6943 | // |
6171 | 6944 | ||
6172 | typedef struct _ATOM_CONNECTOR_INFO |
6945 | typedef struct _ATOM_CONNECTOR_INFO |
6173 | { |
6946 | { |
6174 | #if ATOM_BIG_ENDIAN |
6947 | #if ATOM_BIG_ENDIAN |
6175 | UCHAR bfConnectorType:4; |
6948 | UCHAR bfConnectorType:4; |
6176 | UCHAR bfAssociatedDAC:4; |
6949 | UCHAR bfAssociatedDAC:4; |
6177 | #else |
6950 | #else |
6178 | UCHAR bfAssociatedDAC:4; |
6951 | UCHAR bfAssociatedDAC:4; |
6179 | UCHAR bfConnectorType:4; |
6952 | UCHAR bfConnectorType:4; |
6180 | #endif |
6953 | #endif |
6181 | }ATOM_CONNECTOR_INFO; |
6954 | }ATOM_CONNECTOR_INFO; |
6182 | 6955 | ||
6183 | typedef union _ATOM_CONNECTOR_INFO_ACCESS |
6956 | typedef union _ATOM_CONNECTOR_INFO_ACCESS |
6184 | { |
6957 | { |
6185 | ATOM_CONNECTOR_INFO sbfAccess; |
6958 | ATOM_CONNECTOR_INFO sbfAccess; |
6186 | UCHAR ucAccess; |
6959 | UCHAR ucAccess; |
6187 | }ATOM_CONNECTOR_INFO_ACCESS; |
6960 | }ATOM_CONNECTOR_INFO_ACCESS; |
6188 | 6961 | ||
6189 | typedef struct _ATOM_CONNECTOR_INFO_I2C |
6962 | typedef struct _ATOM_CONNECTOR_INFO_I2C |
6190 | { |
6963 | { |
6191 | ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; |
6964 | ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; |
6192 | ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; |
6965 | ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; |
6193 | }ATOM_CONNECTOR_INFO_I2C; |
6966 | }ATOM_CONNECTOR_INFO_I2C; |
6194 | 6967 | ||
6195 | 6968 | ||
6196 | typedef struct _ATOM_SUPPORTED_DEVICES_INFO |
6969 | typedef struct _ATOM_SUPPORTED_DEVICES_INFO |
6197 | { |
6970 | { |
6198 | ATOM_COMMON_TABLE_HEADER sHeader; |
6971 | ATOM_COMMON_TABLE_HEADER sHeader; |
6199 | USHORT usDeviceSupport; |
6972 | USHORT usDeviceSupport; |
6200 | ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; |
6973 | ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; |
6201 | }ATOM_SUPPORTED_DEVICES_INFO; |
6974 | }ATOM_SUPPORTED_DEVICES_INFO; |
6202 | 6975 | ||
6203 | #define NO_INT_SRC_MAPPED 0xFF |
6976 | #define NO_INT_SRC_MAPPED 0xFF |
6204 | 6977 | ||
6205 | typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP |
6978 | typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP |
6206 | { |
6979 | { |
6207 | UCHAR ucIntSrcBitmap; |
6980 | UCHAR ucIntSrcBitmap; |
6208 | }ATOM_CONNECTOR_INC_SRC_BITMAP; |
6981 | }ATOM_CONNECTOR_INC_SRC_BITMAP; |
6209 | 6982 | ||
6210 | typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 |
6983 | typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 |
6211 | { |
6984 | { |
6212 | ATOM_COMMON_TABLE_HEADER sHeader; |
6985 | ATOM_COMMON_TABLE_HEADER sHeader; |
6213 | USHORT usDeviceSupport; |
6986 | USHORT usDeviceSupport; |
6214 | ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; |
6987 | ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; |
6215 | ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; |
6988 | ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; |
6216 | }ATOM_SUPPORTED_DEVICES_INFO_2; |
6989 | }ATOM_SUPPORTED_DEVICES_INFO_2; |
6217 | 6990 | ||
6218 | typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 |
6991 | typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 |
6219 | { |
6992 | { |
6220 | ATOM_COMMON_TABLE_HEADER sHeader; |
6993 | ATOM_COMMON_TABLE_HEADER sHeader; |
6221 | USHORT usDeviceSupport; |
6994 | USHORT usDeviceSupport; |
6222 | ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; |
6995 | ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; |
6223 | ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; |
6996 | ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; |
6224 | }ATOM_SUPPORTED_DEVICES_INFO_2d1; |
6997 | }ATOM_SUPPORTED_DEVICES_INFO_2d1; |
6225 | 6998 | ||
6226 | #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 |
6999 | #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 |
6227 | 7000 | ||
6228 | 7001 | ||
6229 | 7002 | ||
6230 | typedef struct _ATOM_MISC_CONTROL_INFO |
7003 | typedef struct _ATOM_MISC_CONTROL_INFO |
6231 | { |
7004 | { |
6232 | USHORT usFrequency; |
7005 | USHORT usFrequency; |
6233 | UCHAR ucPLL_ChargePump; // PLL charge-pump gain control |
7006 | UCHAR ucPLL_ChargePump; // PLL charge-pump gain control |
6234 | UCHAR ucPLL_DutyCycle; // PLL duty cycle control |
7007 | UCHAR ucPLL_DutyCycle; // PLL duty cycle control |
6235 | UCHAR ucPLL_VCO_Gain; // PLL VCO gain control |
7008 | UCHAR ucPLL_VCO_Gain; // PLL VCO gain control |
6236 | UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control |
7009 | UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control |
6237 | }ATOM_MISC_CONTROL_INFO; |
7010 | }ATOM_MISC_CONTROL_INFO; |
6238 | 7011 | ||
6239 | 7012 | ||
6240 | #define ATOM_MAX_MISC_INFO 4 |
7013 | #define ATOM_MAX_MISC_INFO 4 |
6241 | 7014 | ||
6242 | typedef struct _ATOM_TMDS_INFO |
7015 | typedef struct _ATOM_TMDS_INFO |
6243 | { |
7016 | { |
6244 | ATOM_COMMON_TABLE_HEADER sHeader; |
7017 | ATOM_COMMON_TABLE_HEADER sHeader; |
6245 | USHORT usMaxFrequency; // in 10Khz |
7018 | USHORT usMaxFrequency; // in 10Khz |
6246 | ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; |
7019 | ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; |
6247 | }ATOM_TMDS_INFO; |
7020 | }ATOM_TMDS_INFO; |
6248 | 7021 | ||
6249 | 7022 | ||
6250 | typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE |
7023 | typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE |
6251 | { |
7024 | { |
6252 | UCHAR ucTVStandard; //Same as TV standards defined above, |
7025 | UCHAR ucTVStandard; //Same as TV standards defined above, |
6253 | UCHAR ucPadding[1]; |
7026 | UCHAR ucPadding[1]; |
6254 | }ATOM_ENCODER_ANALOG_ATTRIBUTE; |
7027 | }ATOM_ENCODER_ANALOG_ATTRIBUTE; |
6255 | 7028 | ||
6256 | typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE |
7029 | typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE |
6257 | { |
7030 | { |
6258 | UCHAR ucAttribute; //Same as other digital encoder attributes defined above |
7031 | UCHAR ucAttribute; //Same as other digital encoder attributes defined above |
6259 | UCHAR ucPadding[1]; |
7032 | UCHAR ucPadding[1]; |
6260 | }ATOM_ENCODER_DIGITAL_ATTRIBUTE; |
7033 | }ATOM_ENCODER_DIGITAL_ATTRIBUTE; |
6261 | 7034 | ||
6262 | typedef union _ATOM_ENCODER_ATTRIBUTE |
7035 | typedef union _ATOM_ENCODER_ATTRIBUTE |
6263 | { |
7036 | { |
6264 | ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; |
7037 | ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; |
6265 | ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; |
7038 | ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; |
6266 | }ATOM_ENCODER_ATTRIBUTE; |
7039 | }ATOM_ENCODER_ATTRIBUTE; |
6267 | 7040 | ||
6268 | 7041 | ||
6269 | typedef struct _DVO_ENCODER_CONTROL_PARAMETERS |
7042 | typedef struct _DVO_ENCODER_CONTROL_PARAMETERS |
6270 | { |
7043 | { |
6271 | USHORT usPixelClock; |
7044 | USHORT usPixelClock; |
6272 | USHORT usEncoderID; |
7045 | USHORT usEncoderID; |
6273 | UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. |
7046 | UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. |
6274 | UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT |
7047 | UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT |
6275 | ATOM_ENCODER_ATTRIBUTE usDevAttr; |
7048 | ATOM_ENCODER_ATTRIBUTE usDevAttr; |
6276 | }DVO_ENCODER_CONTROL_PARAMETERS; |
7049 | }DVO_ENCODER_CONTROL_PARAMETERS; |
6277 | 7050 | ||
6278 | typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION |
7051 | typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION |
6279 | { |
7052 | { |
6280 | DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; |
7053 | DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; |
6281 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion |
7054 | WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion |
6282 | }DVO_ENCODER_CONTROL_PS_ALLOCATION; |
7055 | }DVO_ENCODER_CONTROL_PS_ALLOCATION; |
6283 | 7056 | ||
6284 | 7057 | ||
6285 | #define ATOM_XTMDS_ASIC_SI164_ID 1 |
7058 | #define ATOM_XTMDS_ASIC_SI164_ID 1 |
6286 | #define ATOM_XTMDS_ASIC_SI178_ID 2 |
7059 | #define ATOM_XTMDS_ASIC_SI178_ID 2 |
6287 | #define ATOM_XTMDS_ASIC_TFP513_ID 3 |
7060 | #define ATOM_XTMDS_ASIC_TFP513_ID 3 |
6288 | #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 |
7061 | #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 |
6289 | #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 |
7062 | #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 |
6290 | #define ATOM_XTMDS_MVPU_FPGA 0x00000004 |
7063 | #define ATOM_XTMDS_MVPU_FPGA 0x00000004 |
6291 | 7064 | ||
6292 | 7065 | ||
6293 | typedef struct _ATOM_XTMDS_INFO |
7066 | typedef struct _ATOM_XTMDS_INFO |
6294 | { |
7067 | { |
6295 | ATOM_COMMON_TABLE_HEADER sHeader; |
7068 | ATOM_COMMON_TABLE_HEADER sHeader; |
6296 | USHORT usSingleLinkMaxFrequency; |
7069 | USHORT usSingleLinkMaxFrequency; |
6297 | ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip |
7070 | ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip |
6298 | UCHAR ucXtransimitterID; |
7071 | UCHAR ucXtransimitterID; |
6299 | UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported |
7072 | UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported |
6300 | UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters |
7073 | UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters |
6301 | // due to design. This ID is used to alert driver that the sequence is not "standard"! |
7074 | // due to design. This ID is used to alert driver that the sequence is not "standard"! |
6302 | UCHAR ucMasterAddress; // Address to control Master xTMDS Chip |
7075 | UCHAR ucMasterAddress; // Address to control Master xTMDS Chip |
6303 | UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip |
7076 | UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip |
6304 | }ATOM_XTMDS_INFO; |
7077 | }ATOM_XTMDS_INFO; |
6305 | 7078 | ||
6306 | typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS |
7079 | typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS |
6307 | { |
7080 | { |
6308 | UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off |
7081 | UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off |
6309 | UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... |
7082 | UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... |
6310 | UCHAR ucPadding[2]; |
7083 | UCHAR ucPadding[2]; |
6311 | }DFP_DPMS_STATUS_CHANGE_PARAMETERS; |
7084 | }DFP_DPMS_STATUS_CHANGE_PARAMETERS; |
6312 | 7085 | ||
6313 | /****************************Legacy Power Play Table Definitions **********************/ |
7086 | /****************************Legacy Power Play Table Definitions **********************/ |
6314 | 7087 | ||
6315 | //Definitions for ulPowerPlayMiscInfo |
7088 | //Definitions for ulPowerPlayMiscInfo |
6316 | #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L |
7089 | #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L |
6317 | #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L |
7090 | #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L |
6318 | #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L |
7091 | #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L |
6319 | 7092 | ||
6320 | #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L |
7093 | #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L |
6321 | #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L |
7094 | #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L |
6322 | 7095 | ||
6323 | #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L |
7096 | #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L |
6324 | 7097 | ||
6325 | #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L |
7098 | #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L |
6326 | #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L |
7099 | #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L |
6327 | #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program |
7100 | #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program |
6328 | 7101 | ||
6329 | #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L |
7102 | #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L |
6330 | #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L |
7103 | #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L |
6331 | #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L |
7104 | #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L |
6332 | #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L |
7105 | #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L |
6333 | #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L |
7106 | #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L |
6334 | #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L |
7107 | #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L |
6335 | #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L |
7108 | #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L |
6336 | 7109 | ||
6337 | #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L |
7110 | #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L |
6338 | #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L |
7111 | #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L |
6339 | #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L |
7112 | #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L |
6340 | #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L |
7113 | #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L |
6341 | #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L |
7114 | #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L |
6342 | 7115 | ||
6343 | #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved |
7116 | #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved |
6344 | #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 |
7117 | #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 |
6345 | 7118 | ||
6346 | #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L |
7119 | #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L |
6347 | #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L |
7120 | #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L |
6348 | #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L |
7121 | #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L |
6349 | #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic |
7122 | #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic |
6350 | #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic |
7123 | #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic |
6351 | #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode |
7124 | #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode |
6352 | 7125 | ||
6353 | #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) |
7126 | #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) |
6354 | #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 |
7127 | #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 |
6355 | #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L |
7128 | #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L |
6356 | 7129 | ||
6357 | #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L |
7130 | #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L |
6358 | #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L |
7131 | #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L |
6359 | #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L |
7132 | #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L |
6360 | #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L |
7133 | #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L |
6361 | #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L |
7134 | #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L |
6362 | #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L |
7135 | #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L |
6363 | #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. |
7136 | #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. |
6364 | //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback |
7137 | //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback |
6365 | #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L |
7138 | #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L |
6366 | #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L |
7139 | #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L |
6367 | #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L |
7140 | #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L |
6368 | 7141 | ||
6369 | //ucTableFormatRevision=1 |
7142 | //ucTableFormatRevision=1 |
6370 | //ucTableContentRevision=1 |
7143 | //ucTableContentRevision=1 |
6371 | typedef struct _ATOM_POWERMODE_INFO |
7144 | typedef struct _ATOM_POWERMODE_INFO |
6372 | { |
7145 | { |
6373 | ULONG ulMiscInfo; //The power level should be arranged in ascending order |
7146 | ULONG ulMiscInfo; //The power level should be arranged in ascending order |
6374 | ULONG ulReserved1; // must set to 0 |
7147 | ULONG ulReserved1; // must set to 0 |
6375 | ULONG ulReserved2; // must set to 0 |
7148 | ULONG ulReserved2; // must set to 0 |
6376 | USHORT usEngineClock; |
7149 | USHORT usEngineClock; |
6377 | USHORT usMemoryClock; |
7150 | USHORT usMemoryClock; |
6378 | UCHAR ucVoltageDropIndex; // index to GPIO table |
7151 | UCHAR ucVoltageDropIndex; // index to GPIO table |
6379 | UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate |
7152 | UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate |
6380 | UCHAR ucMinTemperature; |
7153 | UCHAR ucMinTemperature; |
6381 | UCHAR ucMaxTemperature; |
7154 | UCHAR ucMaxTemperature; |
6382 | UCHAR ucNumPciELanes; // number of PCIE lanes |
7155 | UCHAR ucNumPciELanes; // number of PCIE lanes |
6383 | }ATOM_POWERMODE_INFO; |
7156 | }ATOM_POWERMODE_INFO; |
6384 | 7157 | ||
6385 | //ucTableFormatRevision=2 |
7158 | //ucTableFormatRevision=2 |
6386 | //ucTableContentRevision=1 |
7159 | //ucTableContentRevision=1 |
6387 | typedef struct _ATOM_POWERMODE_INFO_V2 |
7160 | typedef struct _ATOM_POWERMODE_INFO_V2 |
6388 | { |
7161 | { |
6389 | ULONG ulMiscInfo; //The power level should be arranged in ascending order |
7162 | ULONG ulMiscInfo; //The power level should be arranged in ascending order |
6390 | ULONG ulMiscInfo2; |
7163 | ULONG ulMiscInfo2; |
6391 | ULONG ulEngineClock; |
7164 | ULONG ulEngineClock; |
6392 | ULONG ulMemoryClock; |
7165 | ULONG ulMemoryClock; |
6393 | UCHAR ucVoltageDropIndex; // index to GPIO table |
7166 | UCHAR ucVoltageDropIndex; // index to GPIO table |
6394 | UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate |
7167 | UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate |
6395 | UCHAR ucMinTemperature; |
7168 | UCHAR ucMinTemperature; |
6396 | UCHAR ucMaxTemperature; |
7169 | UCHAR ucMaxTemperature; |
6397 | UCHAR ucNumPciELanes; // number of PCIE lanes |
7170 | UCHAR ucNumPciELanes; // number of PCIE lanes |
6398 | }ATOM_POWERMODE_INFO_V2; |
7171 | }ATOM_POWERMODE_INFO_V2; |
6399 | 7172 | ||
6400 | //ucTableFormatRevision=2 |
7173 | //ucTableFormatRevision=2 |
6401 | //ucTableContentRevision=2 |
7174 | //ucTableContentRevision=2 |
6402 | typedef struct _ATOM_POWERMODE_INFO_V3 |
7175 | typedef struct _ATOM_POWERMODE_INFO_V3 |
6403 | { |
7176 | { |
6404 | ULONG ulMiscInfo; //The power level should be arranged in ascending order |
7177 | ULONG ulMiscInfo; //The power level should be arranged in ascending order |
6405 | ULONG ulMiscInfo2; |
7178 | ULONG ulMiscInfo2; |
6406 | ULONG ulEngineClock; |
7179 | ULONG ulEngineClock; |
6407 | ULONG ulMemoryClock; |
7180 | ULONG ulMemoryClock; |
6408 | UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table |
7181 | UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table |
6409 | UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate |
7182 | UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate |
6410 | UCHAR ucMinTemperature; |
7183 | UCHAR ucMinTemperature; |
6411 | UCHAR ucMaxTemperature; |
7184 | UCHAR ucMaxTemperature; |
6412 | UCHAR ucNumPciELanes; // number of PCIE lanes |
7185 | UCHAR ucNumPciELanes; // number of PCIE lanes |
6413 | UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table |
7186 | UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table |
6414 | }ATOM_POWERMODE_INFO_V3; |
7187 | }ATOM_POWERMODE_INFO_V3; |
6415 | 7188 | ||
6416 | 7189 | ||
6417 | #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 |
7190 | #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 |
6418 | 7191 | ||
6419 | #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 |
7192 | #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 |
6420 | #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 |
7193 | #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 |
6421 | 7194 | ||
6422 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 |
7195 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 |
6423 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 |
7196 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 |
6424 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 |
7197 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 |
6425 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 |
7198 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 |
6426 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 |
7199 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 |
6427 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 |
7200 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 |
6428 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog |
7201 | #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog |
6429 | 7202 | ||
6430 | 7203 | ||
6431 | typedef struct _ATOM_POWERPLAY_INFO |
7204 | typedef struct _ATOM_POWERPLAY_INFO |
6432 | { |
7205 | { |
6433 | ATOM_COMMON_TABLE_HEADER sHeader; |
7206 | ATOM_COMMON_TABLE_HEADER sHeader; |
6434 | UCHAR ucOverdriveThermalController; |
7207 | UCHAR ucOverdriveThermalController; |
6435 | UCHAR ucOverdriveI2cLine; |
7208 | UCHAR ucOverdriveI2cLine; |
6436 | UCHAR ucOverdriveIntBitmap; |
7209 | UCHAR ucOverdriveIntBitmap; |
6437 | UCHAR ucOverdriveControllerAddress; |
7210 | UCHAR ucOverdriveControllerAddress; |
6438 | UCHAR ucSizeOfPowerModeEntry; |
7211 | UCHAR ucSizeOfPowerModeEntry; |
6439 | UCHAR ucNumOfPowerModeEntries; |
7212 | UCHAR ucNumOfPowerModeEntries; |
6440 | ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; |
7213 | ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; |
6441 | }ATOM_POWERPLAY_INFO; |
7214 | }ATOM_POWERPLAY_INFO; |
6442 | 7215 | ||
6443 | typedef struct _ATOM_POWERPLAY_INFO_V2 |
7216 | typedef struct _ATOM_POWERPLAY_INFO_V2 |
6444 | { |
7217 | { |
6445 | ATOM_COMMON_TABLE_HEADER sHeader; |
7218 | ATOM_COMMON_TABLE_HEADER sHeader; |
6446 | UCHAR ucOverdriveThermalController; |
7219 | UCHAR ucOverdriveThermalController; |
6447 | UCHAR ucOverdriveI2cLine; |
7220 | UCHAR ucOverdriveI2cLine; |
6448 | UCHAR ucOverdriveIntBitmap; |
7221 | UCHAR ucOverdriveIntBitmap; |
6449 | UCHAR ucOverdriveControllerAddress; |
7222 | UCHAR ucOverdriveControllerAddress; |
6450 | UCHAR ucSizeOfPowerModeEntry; |
7223 | UCHAR ucSizeOfPowerModeEntry; |
6451 | UCHAR ucNumOfPowerModeEntries; |
7224 | UCHAR ucNumOfPowerModeEntries; |
6452 | ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; |
7225 | ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; |
6453 | }ATOM_POWERPLAY_INFO_V2; |
7226 | }ATOM_POWERPLAY_INFO_V2; |
6454 | 7227 | ||
6455 | typedef struct _ATOM_POWERPLAY_INFO_V3 |
7228 | typedef struct _ATOM_POWERPLAY_INFO_V3 |
6456 | { |
7229 | { |
6457 | ATOM_COMMON_TABLE_HEADER sHeader; |
7230 | ATOM_COMMON_TABLE_HEADER sHeader; |
6458 | UCHAR ucOverdriveThermalController; |
7231 | UCHAR ucOverdriveThermalController; |
6459 | UCHAR ucOverdriveI2cLine; |
7232 | UCHAR ucOverdriveI2cLine; |
6460 | UCHAR ucOverdriveIntBitmap; |
7233 | UCHAR ucOverdriveIntBitmap; |
6461 | UCHAR ucOverdriveControllerAddress; |
7234 | UCHAR ucOverdriveControllerAddress; |
6462 | UCHAR ucSizeOfPowerModeEntry; |
7235 | UCHAR ucSizeOfPowerModeEntry; |
6463 | UCHAR ucNumOfPowerModeEntries; |
7236 | UCHAR ucNumOfPowerModeEntries; |
6464 | ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; |
7237 | ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; |
6465 | }ATOM_POWERPLAY_INFO_V3; |
7238 | }ATOM_POWERPLAY_INFO_V3; |
6466 | 7239 | ||
6467 | /* New PPlib */ |
7240 | /* New PPlib */ |
6468 | /**************************************************************************/ |
7241 | /**************************************************************************/ |
6469 | typedef struct _ATOM_PPLIB_THERMALCONTROLLER |
7242 | typedef struct _ATOM_PPLIB_THERMALCONTROLLER |
6470 | 7243 | ||
6471 | { |
7244 | { |
6472 | UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* |
7245 | UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* |
6473 | UCHAR ucI2cLine; // as interpreted by DAL I2C |
7246 | UCHAR ucI2cLine; // as interpreted by DAL I2C |
6474 | UCHAR ucI2cAddress; |
7247 | UCHAR ucI2cAddress; |
6475 | UCHAR ucFanParameters; // Fan Control Parameters. |
7248 | UCHAR ucFanParameters; // Fan Control Parameters. |
6476 | UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. |
7249 | UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. |
6477 | UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. |
7250 | UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. |
6478 | UCHAR ucReserved; // ---- |
7251 | UCHAR ucReserved; // ---- |
6479 | UCHAR ucFlags; // to be defined |
7252 | UCHAR ucFlags; // to be defined |
6480 | } ATOM_PPLIB_THERMALCONTROLLER; |
7253 | } ATOM_PPLIB_THERMALCONTROLLER; |
6481 | 7254 | ||
6482 | #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f |
7255 | #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f |
6483 | #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. |
7256 | #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. |
6484 | 7257 | ||
6485 | #define ATOM_PP_THERMALCONTROLLER_NONE 0 |
7258 | #define ATOM_PP_THERMALCONTROLLER_NONE 0 |
6486 | #define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib |
7259 | #define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib |
6487 | #define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib |
7260 | #define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib |
6488 | #define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib |
7261 | #define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib |
6489 | #define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib |
7262 | #define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib |
6490 | #define ATOM_PP_THERMALCONTROLLER_LM64 5 |
7263 | #define ATOM_PP_THERMALCONTROLLER_LM64 5 |
6491 | #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib |
7264 | #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib |
6492 | #define ATOM_PP_THERMALCONTROLLER_RV6xx 7 |
7265 | #define ATOM_PP_THERMALCONTROLLER_RV6xx 7 |
6493 | #define ATOM_PP_THERMALCONTROLLER_RV770 8 |
7266 | #define ATOM_PP_THERMALCONTROLLER_RV770 8 |
6494 | #define ATOM_PP_THERMALCONTROLLER_ADT7473 9 |
7267 | #define ATOM_PP_THERMALCONTROLLER_ADT7473 9 |
6495 | #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 |
7268 | #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 |
6496 | #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 |
7269 | #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 |
6497 | #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. |
7270 | #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. |
6498 | #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally |
7271 | #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally |
6499 | #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 |
7272 | #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 |
- | 7273 | #define ATOM_PP_THERMALCONTROLLER_SISLANDS 16 |
|
- | 7274 | #define ATOM_PP_THERMALCONTROLLER_LM96163 17 |
|
6500 | 7275 | ||
6501 | // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. |
7276 | // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. |
6502 | // We probably should reserve the bit 0x80 for this use. |
7277 | // We probably should reserve the bit 0x80 for this use. |
6503 | // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). |
7278 | // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). |
6504 | // The driver can pick the correct internal controller based on the ASIC. |
7279 | // The driver can pick the correct internal controller based on the ASIC. |
6505 | 7280 | ||
6506 | #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller |
7281 | #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller |
6507 | #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller |
7282 | #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller |
6508 | 7283 | ||
6509 | typedef struct _ATOM_PPLIB_STATE |
7284 | typedef struct _ATOM_PPLIB_STATE |
6510 | { |
7285 | { |
6511 | UCHAR ucNonClockStateIndex; |
7286 | UCHAR ucNonClockStateIndex; |
6512 | UCHAR ucClockStateIndices[1]; // variable-sized |
7287 | UCHAR ucClockStateIndices[1]; // variable-sized |
6513 | } ATOM_PPLIB_STATE; |
7288 | } ATOM_PPLIB_STATE; |
- | 7289 | ||
6514 | 7290 | ||
6515 | typedef struct _ATOM_PPLIB_FANTABLE |
7291 | typedef struct _ATOM_PPLIB_FANTABLE |
6516 | { |
7292 | { |
6517 | UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. |
7293 | UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. |
6518 | UCHAR ucTHyst; // Temperature hysteresis. Integer. |
7294 | UCHAR ucTHyst; // Temperature hysteresis. Integer. |
6519 | USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. |
7295 | USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. |
6520 | USHORT usTMed; // The middle temperature where we change slopes. |
7296 | USHORT usTMed; // The middle temperature where we change slopes. |
6521 | USHORT usTHigh; // The high point above TMed for adjusting the second slope. |
7297 | USHORT usTHigh; // The high point above TMed for adjusting the second slope. |
6522 | USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). |
7298 | USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). |
6523 | USHORT usPWMMed; // The PWM value (in percent) at TMed. |
7299 | USHORT usPWMMed; // The PWM value (in percent) at TMed. |
6524 | USHORT usPWMHigh; // The PWM value at THigh. |
7300 | USHORT usPWMHigh; // The PWM value at THigh. |
6525 | } ATOM_PPLIB_FANTABLE; |
7301 | } ATOM_PPLIB_FANTABLE; |
- | 7302 | ||
- | 7303 | typedef struct _ATOM_PPLIB_FANTABLE2 |
|
- | 7304 | { |
|
- | 7305 | ATOM_PPLIB_FANTABLE basicTable; |
|
- | 7306 | USHORT usTMax; // The max temperature |
|
- | 7307 | } ATOM_PPLIB_FANTABLE2; |
|
6526 | 7308 | ||
6527 | typedef struct _ATOM_PPLIB_EXTENDEDHEADER |
7309 | typedef struct _ATOM_PPLIB_EXTENDEDHEADER |
6528 | { |
7310 | { |
6529 | USHORT usSize; |
7311 | USHORT usSize; |
6530 | ULONG ulMaxEngineClock; // For Overdrive. |
7312 | ULONG ulMaxEngineClock; // For Overdrive. |
6531 | ULONG ulMaxMemoryClock; // For Overdrive. |
7313 | ULONG ulMaxMemoryClock; // For Overdrive. |
6532 | // Add extra system parameters here, always adjust size to include all fields. |
7314 | // Add extra system parameters here, always adjust size to include all fields. |
- | 7315 | USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table |
|
- | 7316 | USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table |
|
6533 | } ATOM_PPLIB_EXTENDEDHEADER; |
7317 | } ATOM_PPLIB_EXTENDEDHEADER; |
6534 | 7318 | ||
6535 | //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps |
7319 | //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps |
6536 | #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 |
7320 | #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 |
6537 | #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 |
7321 | #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 |
6538 | #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 |
7322 | #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 |
6539 | #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 |
7323 | #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 |
6540 | #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 |
7324 | #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 |
6541 | #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 |
7325 | #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 |
6542 | #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 |
7326 | #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 |
6543 | #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 |
7327 | #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 |
6544 | #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 |
7328 | #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 |
6545 | #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 |
7329 | #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 |
6546 | #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 |
7330 | #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 |
6547 | #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 |
7331 | #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 |
6548 | #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 |
7332 | #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 |
6549 | #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. |
7333 | #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. |
6550 | #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). |
7334 | #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). |
6551 | #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. |
7335 | #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. |
6552 | #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. |
7336 | #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. |
6553 | #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. |
7337 | #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. |
- | 7338 | ||
6554 | 7339 | ||
6555 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE |
7340 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE |
6556 | { |
7341 | { |
6557 | ATOM_COMMON_TABLE_HEADER sHeader; |
7342 | ATOM_COMMON_TABLE_HEADER sHeader; |
6558 | 7343 | ||
6559 | UCHAR ucDataRevision; |
7344 | UCHAR ucDataRevision; |
6560 | 7345 | ||
6561 | UCHAR ucNumStates; |
7346 | UCHAR ucNumStates; |
6562 | UCHAR ucStateEntrySize; |
7347 | UCHAR ucStateEntrySize; |
6563 | UCHAR ucClockInfoSize; |
7348 | UCHAR ucClockInfoSize; |
6564 | UCHAR ucNonClockSize; |
7349 | UCHAR ucNonClockSize; |
6565 | 7350 | ||
6566 | // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures |
7351 | // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures |
6567 | USHORT usStateArrayOffset; |
7352 | USHORT usStateArrayOffset; |
6568 | 7353 | ||
6569 | // offset from start of this table to array of ASIC-specific structures, |
7354 | // offset from start of this table to array of ASIC-specific structures, |
6570 | // currently ATOM_PPLIB_CLOCK_INFO. |
7355 | // currently ATOM_PPLIB_CLOCK_INFO. |
6571 | USHORT usClockInfoArrayOffset; |
7356 | USHORT usClockInfoArrayOffset; |
6572 | 7357 | ||
6573 | // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO |
7358 | // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO |
6574 | USHORT usNonClockInfoArrayOffset; |
7359 | USHORT usNonClockInfoArrayOffset; |
6575 | 7360 | ||
6576 | USHORT usBackbiasTime; // in microseconds |
7361 | USHORT usBackbiasTime; // in microseconds |
6577 | USHORT usVoltageTime; // in microseconds |
7362 | USHORT usVoltageTime; // in microseconds |
6578 | USHORT usTableSize; //the size of this structure, or the extended structure |
7363 | USHORT usTableSize; //the size of this structure, or the extended structure |
6579 | 7364 | ||
6580 | ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* |
7365 | ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* |
6581 | 7366 | ||
6582 | ATOM_PPLIB_THERMALCONTROLLER sThermalController; |
7367 | ATOM_PPLIB_THERMALCONTROLLER sThermalController; |
6583 | 7368 | ||
6584 | USHORT usBootClockInfoOffset; |
7369 | USHORT usBootClockInfoOffset; |
6585 | USHORT usBootNonClockInfoOffset; |
7370 | USHORT usBootNonClockInfoOffset; |
6586 | 7371 | ||
6587 | } ATOM_PPLIB_POWERPLAYTABLE; |
7372 | } ATOM_PPLIB_POWERPLAYTABLE; |
6588 | 7373 | ||
6589 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 |
7374 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 |
6590 | { |
7375 | { |
6591 | ATOM_PPLIB_POWERPLAYTABLE basicTable; |
7376 | ATOM_PPLIB_POWERPLAYTABLE basicTable; |
6592 | UCHAR ucNumCustomThermalPolicy; |
7377 | UCHAR ucNumCustomThermalPolicy; |
6593 | USHORT usCustomThermalPolicyArrayOffset; |
7378 | USHORT usCustomThermalPolicyArrayOffset; |
6594 | }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; |
7379 | }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; |
6595 | 7380 | ||
6596 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 |
7381 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 |
6597 | { |
7382 | { |
6598 | ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; |
7383 | ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; |
6599 | USHORT usFormatID; // To be used ONLY by PPGen. |
7384 | USHORT usFormatID; // To be used ONLY by PPGen. |
6600 | USHORT usFanTableOffset; |
7385 | USHORT usFanTableOffset; |
6601 | USHORT usExtendendedHeaderOffset; |
7386 | USHORT usExtendendedHeaderOffset; |
6602 | } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; |
7387 | } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; |
6603 | 7388 | ||
6604 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 |
7389 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 |
6605 | { |
7390 | { |
6606 | ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; |
7391 | ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; |
6607 | ULONG ulGoldenPPID; // PPGen use only |
7392 | ULONG ulGoldenPPID; // PPGen use only |
6608 | ULONG ulGoldenRevision; // PPGen use only |
7393 | ULONG ulGoldenRevision; // PPGen use only |
6609 | USHORT usVddcDependencyOnSCLKOffset; |
7394 | USHORT usVddcDependencyOnSCLKOffset; |
6610 | USHORT usVddciDependencyOnMCLKOffset; |
7395 | USHORT usVddciDependencyOnMCLKOffset; |
6611 | USHORT usVddcDependencyOnMCLKOffset; |
7396 | USHORT usVddcDependencyOnMCLKOffset; |
6612 | USHORT usMaxClockVoltageOnDCOffset; |
7397 | USHORT usMaxClockVoltageOnDCOffset; |
- | 7398 | USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table |
|
6613 | USHORT usReserved[2]; |
7399 | USHORT usReserved; |
6614 | } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; |
7400 | } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; |
6615 | 7401 | ||
6616 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 |
7402 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 |
6617 | { |
7403 | { |
6618 | ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; |
7404 | ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; |
6619 | ULONG ulTDPLimit; |
7405 | ULONG ulTDPLimit; |
6620 | ULONG ulNearTDPLimit; |
7406 | ULONG ulNearTDPLimit; |
6621 | ULONG ulSQRampingThreshold; |
7407 | ULONG ulSQRampingThreshold; |
6622 | USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table |
7408 | USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table |
6623 | ULONG ulCACLeakage; // TBD, this parameter is still under discussion. Change to ulReserved if not needed. |
7409 | ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table |
6624 | ULONG ulReserved; |
7410 | USHORT usTDPODLimit; |
- | 7411 | USHORT usLoadLineSlope; // in milliOhms * 100 |
|
6625 | } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; |
7412 | } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; |
6626 | 7413 | ||
6627 | //// ATOM_PPLIB_NONCLOCK_INFO::usClassification |
7414 | //// ATOM_PPLIB_NONCLOCK_INFO::usClassification |
6628 | #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 |
7415 | #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 |
6629 | #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 |
7416 | #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 |
6630 | #define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 |
7417 | #define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 |
6631 | #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 |
7418 | #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 |
6632 | #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 |
7419 | #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 |
6633 | #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 |
7420 | #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 |
6634 | // 2, 4, 6, 7 are reserved |
7421 | // 2, 4, 6, 7 are reserved |
6635 | 7422 | ||
6636 | #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 |
7423 | #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 |
6637 | #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 |
7424 | #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 |
6638 | #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 |
7425 | #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 |
6639 | #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 |
7426 | #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 |
6640 | #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 |
7427 | #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 |
6641 | #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 |
7428 | #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 |
6642 | #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 |
7429 | #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 |
6643 | #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 |
7430 | #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 |
6644 | #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 |
7431 | #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 |
6645 | #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 |
7432 | #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 |
6646 | #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 |
7433 | #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 |
6647 | #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 |
7434 | #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 |
6648 | #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 |
7435 | #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 |
6649 | 7436 | ||
6650 | //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 |
7437 | //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 |
6651 | #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 |
7438 | #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 |
6652 | #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 |
7439 | #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 |
- | 7440 | #define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D) |
|
6653 | 7441 | ||
6654 | //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings |
7442 | //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings |
6655 | #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 |
7443 | #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 |
6656 | #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 |
7444 | #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 |
6657 | 7445 | ||
6658 | // 0 is 2.5Gb/s, 1 is 5Gb/s |
7446 | // 0 is 2.5Gb/s, 1 is 5Gb/s |
6659 | #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 |
7447 | #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 |
6660 | #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 |
7448 | #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 |
6661 | 7449 | ||
6662 | // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec |
7450 | // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec |
6663 | #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 |
7451 | #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 |
6664 | #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 |
7452 | #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 |
6665 | 7453 | ||
6666 | // lookup into reduced refresh-rate table |
7454 | // lookup into reduced refresh-rate table |
6667 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 |
7455 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 |
6668 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 |
7456 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 |
6669 | 7457 | ||
6670 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 |
7458 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 |
6671 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 |
7459 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 |
6672 | // 2-15 TBD as needed. |
7460 | // 2-15 TBD as needed. |
6673 | 7461 | ||
6674 | #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 |
7462 | #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 |
6675 | #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 |
7463 | #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 |
- | 7464 | ||
6676 | #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 |
7465 | #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 |
- | 7466 | ||
6677 | #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 |
7467 | #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 |
6678 | 7468 | ||
6679 | //memory related flags |
7469 | //memory related flags |
6680 | #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 |
7470 | #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 |
6681 | 7471 | ||
6682 | //M3 Arb //2bits, current 3 sets of parameters in total |
7472 | //M3 Arb //2bits, current 3 sets of parameters in total |
6683 | #define ATOM_PPLIB_M3ARB_MASK 0x00060000 |
7473 | #define ATOM_PPLIB_M3ARB_MASK 0x00060000 |
6684 | #define ATOM_PPLIB_M3ARB_SHIFT 17 |
7474 | #define ATOM_PPLIB_M3ARB_SHIFT 17 |
6685 | 7475 | ||
6686 | #define ATOM_PPLIB_ENABLE_DRR 0x00080000 |
7476 | #define ATOM_PPLIB_ENABLE_DRR 0x00080000 |
6687 | 7477 | ||
6688 | // remaining 16 bits are reserved |
7478 | // remaining 16 bits are reserved |
6689 | typedef struct _ATOM_PPLIB_THERMAL_STATE |
7479 | typedef struct _ATOM_PPLIB_THERMAL_STATE |
6690 | { |
7480 | { |
6691 | UCHAR ucMinTemperature; |
7481 | UCHAR ucMinTemperature; |
6692 | UCHAR ucMaxTemperature; |
7482 | UCHAR ucMaxTemperature; |
6693 | UCHAR ucThermalAction; |
7483 | UCHAR ucThermalAction; |
6694 | }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; |
7484 | }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; |
6695 | 7485 | ||
6696 | // Contained in an array starting at the offset |
7486 | // Contained in an array starting at the offset |
6697 | // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. |
7487 | // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. |
6698 | // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex |
7488 | // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex |
6699 | #define ATOM_PPLIB_NONCLOCKINFO_VER1 12 |
7489 | #define ATOM_PPLIB_NONCLOCKINFO_VER1 12 |
6700 | #define ATOM_PPLIB_NONCLOCKINFO_VER2 24 |
7490 | #define ATOM_PPLIB_NONCLOCKINFO_VER2 24 |
6701 | typedef struct _ATOM_PPLIB_NONCLOCK_INFO |
7491 | typedef struct _ATOM_PPLIB_NONCLOCK_INFO |
6702 | { |
7492 | { |
6703 | USHORT usClassification; |
7493 | USHORT usClassification; |
6704 | UCHAR ucMinTemperature; |
7494 | UCHAR ucMinTemperature; |
6705 | UCHAR ucMaxTemperature; |
7495 | UCHAR ucMaxTemperature; |
6706 | ULONG ulCapsAndSettings; |
7496 | ULONG ulCapsAndSettings; |
6707 | UCHAR ucRequiredPower; |
7497 | UCHAR ucRequiredPower; |
6708 | USHORT usClassification2; |
7498 | USHORT usClassification2; |
6709 | ULONG ulVCLK; |
7499 | ULONG ulVCLK; |
6710 | ULONG ulDCLK; |
7500 | ULONG ulDCLK; |
6711 | UCHAR ucUnused[5]; |
7501 | UCHAR ucUnused[5]; |
6712 | } ATOM_PPLIB_NONCLOCK_INFO; |
7502 | } ATOM_PPLIB_NONCLOCK_INFO; |
6713 | 7503 | ||
6714 | // Contained in an array starting at the offset |
7504 | // Contained in an array starting at the offset |
6715 | // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. |
7505 | // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. |
6716 | // referenced from ATOM_PPLIB_STATE::ucClockStateIndices |
7506 | // referenced from ATOM_PPLIB_STATE::ucClockStateIndices |
6717 | typedef struct _ATOM_PPLIB_R600_CLOCK_INFO |
7507 | typedef struct _ATOM_PPLIB_R600_CLOCK_INFO |
6718 | { |
7508 | { |
6719 | USHORT usEngineClockLow; |
7509 | USHORT usEngineClockLow; |
6720 | UCHAR ucEngineClockHigh; |
7510 | UCHAR ucEngineClockHigh; |
6721 | 7511 | ||
6722 | USHORT usMemoryClockLow; |
7512 | USHORT usMemoryClockLow; |
6723 | UCHAR ucMemoryClockHigh; |
7513 | UCHAR ucMemoryClockHigh; |
6724 | 7514 | ||
6725 | USHORT usVDDC; |
7515 | USHORT usVDDC; |
6726 | USHORT usUnused1; |
7516 | USHORT usUnused1; |
6727 | USHORT usUnused2; |
7517 | USHORT usUnused2; |
6728 | 7518 | ||
6729 | ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* |
7519 | ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* |
6730 | 7520 | ||
6731 | } ATOM_PPLIB_R600_CLOCK_INFO; |
7521 | } ATOM_PPLIB_R600_CLOCK_INFO; |
6732 | 7522 | ||
6733 | // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO |
7523 | // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO |
6734 | #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 |
7524 | #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 |
6735 | #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 |
7525 | #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 |
6736 | #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 |
7526 | #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 |
6737 | #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 |
7527 | #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 |
6738 | #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 |
7528 | #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 |
6739 | #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). |
7529 | #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). |
6740 | 7530 | ||
6741 | typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO |
7531 | typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO |
6742 | { |
7532 | { |
6743 | USHORT usEngineClockLow; |
7533 | USHORT usEngineClockLow; |
6744 | UCHAR ucEngineClockHigh; |
7534 | UCHAR ucEngineClockHigh; |
6745 | 7535 | ||
6746 | USHORT usMemoryClockLow; |
7536 | USHORT usMemoryClockLow; |
6747 | UCHAR ucMemoryClockHigh; |
7537 | UCHAR ucMemoryClockHigh; |
6748 | 7538 | ||
6749 | USHORT usVDDC; |
7539 | USHORT usVDDC; |
6750 | USHORT usVDDCI; |
7540 | USHORT usVDDCI; |
6751 | USHORT usUnused; |
7541 | USHORT usUnused; |
6752 | 7542 | ||
6753 | ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* |
7543 | ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* |
6754 | 7544 | ||
6755 | } ATOM_PPLIB_EVERGREEN_CLOCK_INFO; |
7545 | } ATOM_PPLIB_EVERGREEN_CLOCK_INFO; |
- | 7546 | ||
- | 7547 | typedef struct _ATOM_PPLIB_SI_CLOCK_INFO |
|
- | 7548 | { |
|
- | 7549 | USHORT usEngineClockLow; |
|
- | 7550 | UCHAR ucEngineClockHigh; |
|
- | 7551 | ||
- | 7552 | USHORT usMemoryClockLow; |
|
- | 7553 | UCHAR ucMemoryClockHigh; |
|
- | 7554 | ||
- | 7555 | USHORT usVDDC; |
|
- | 7556 | USHORT usVDDCI; |
|
- | 7557 | UCHAR ucPCIEGen; |
|
- | 7558 | UCHAR ucUnused1; |
|
- | 7559 | ||
- | 7560 | ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now |
|
- | 7561 | ||
- | 7562 | } ATOM_PPLIB_SI_CLOCK_INFO; |
|
- | 7563 | ||
6756 | 7564 | ||
6757 | typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO |
7565 | typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO |
6758 | 7566 | ||
6759 | { |
7567 | { |
6760 | USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). |
7568 | USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). |
6761 | UCHAR ucLowEngineClockHigh; |
7569 | UCHAR ucLowEngineClockHigh; |
6762 | USHORT usHighEngineClockLow; // High Engine clock in MHz. |
7570 | USHORT usHighEngineClockLow; // High Engine clock in MHz. |
6763 | UCHAR ucHighEngineClockHigh; |
7571 | UCHAR ucHighEngineClockHigh; |
6764 | USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. |
7572 | USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. |
6765 | UCHAR ucMemoryClockHigh; // Currentyl unused. |
7573 | UCHAR ucMemoryClockHigh; // Currentyl unused. |
6766 | UCHAR ucPadding; // For proper alignment and size. |
7574 | UCHAR ucPadding; // For proper alignment and size. |
6767 | USHORT usVDDC; // For the 780, use: None, Low, High, Variable |
7575 | USHORT usVDDC; // For the 780, use: None, Low, High, Variable |
6768 | UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} |
7576 | UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} |
6769 | UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requirement. |
7577 | UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement. |
6770 | USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). |
7578 | USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). |
6771 | ULONG ulFlags; |
7579 | ULONG ulFlags; |
6772 | } ATOM_PPLIB_RS780_CLOCK_INFO; |
7580 | } ATOM_PPLIB_RS780_CLOCK_INFO; |
6773 | 7581 | ||
6774 | #define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 |
7582 | #define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 |
6775 | #define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 |
7583 | #define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 |
6776 | #define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 |
7584 | #define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 |
6777 | #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 |
7585 | #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 |
6778 | 7586 | ||
6779 | #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. |
7587 | #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. |
6780 | #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 |
7588 | #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 |
6781 | #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 |
7589 | #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 |
6782 | 7590 | ||
6783 | #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 |
7591 | #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 |
6784 | #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 |
7592 | #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 |
6785 | #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 |
7593 | #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 |
6786 | 7594 | ||
6787 | typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ |
7595 | typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ |
6788 | USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz |
7596 | USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz |
6789 | UCHAR ucEngineClockHigh; //clockfrequency >> 16. |
7597 | UCHAR ucEngineClockHigh; //clockfrequency >> 16. |
6790 | UCHAR vddcIndex; //2-bit vddc index; |
7598 | UCHAR vddcIndex; //2-bit vddc index; |
6791 | UCHAR leakage; //please use 8-bit absolute value, not the 6-bit % value |
- | |
6792 | //please initalize to 0 |
- | |
6793 | UCHAR rsv; |
7599 | USHORT tdpLimit; |
6794 | //please initalize to 0 |
7600 | //please initalize to 0 |
6795 | USHORT rsv1; |
7601 | USHORT rsv1; |
6796 | //please initialize to 0s |
7602 | //please initialize to 0s |
6797 | ULONG rsv2[2]; |
7603 | ULONG rsv2[2]; |
6798 | }ATOM_PPLIB_SUMO_CLOCK_INFO; |
7604 | }ATOM_PPLIB_SUMO_CLOCK_INFO; |
6799 | 7605 | ||
6800 | 7606 | ||
6801 | 7607 | ||
6802 | typedef struct _ATOM_PPLIB_STATE_V2 |
7608 | typedef struct _ATOM_PPLIB_STATE_V2 |
6803 | { |
7609 | { |
6804 | //number of valid dpm levels in this state; Driver uses it to calculate the whole |
7610 | //number of valid dpm levels in this state; Driver uses it to calculate the whole |
6805 | //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) |
7611 | //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) |
6806 | UCHAR ucNumDPMLevels; |
7612 | UCHAR ucNumDPMLevels; |
6807 | 7613 | ||
6808 | //a index to the array of nonClockInfos |
7614 | //a index to the array of nonClockInfos |
6809 | UCHAR nonClockInfoIndex; |
7615 | UCHAR nonClockInfoIndex; |
6810 | /** |
7616 | /** |
6811 | * Driver will read the first ucNumDPMLevels in this array |
7617 | * Driver will read the first ucNumDPMLevels in this array |
6812 | */ |
7618 | */ |
6813 | UCHAR clockInfoIndex[1]; |
7619 | UCHAR clockInfoIndex[1]; |
6814 | } ATOM_PPLIB_STATE_V2; |
7620 | } ATOM_PPLIB_STATE_V2; |
6815 | 7621 | ||
6816 | typedef struct StateArray{ |
7622 | typedef struct _StateArray{ |
6817 | //how many states we have |
7623 | //how many states we have |
6818 | UCHAR ucNumEntries; |
7624 | UCHAR ucNumEntries; |
6819 | 7625 | ||
6820 | ATOM_PPLIB_STATE_V2 states[1]; |
7626 | ATOM_PPLIB_STATE_V2 states[1]; |
6821 | }StateArray; |
7627 | }StateArray; |
6822 | 7628 | ||
6823 | 7629 | ||
6824 | typedef struct ClockInfoArray{ |
7630 | typedef struct _ClockInfoArray{ |
6825 | //how many clock levels we have |
7631 | //how many clock levels we have |
6826 | UCHAR ucNumEntries; |
7632 | UCHAR ucNumEntries; |
6827 | 7633 | ||
6828 | //sizeof(ATOM_PPLIB_SUMO_CLOCK_INFO) |
7634 | //sizeof(ATOM_PPLIB_CLOCK_INFO) |
6829 | UCHAR ucEntrySize; |
- | |
6830 | 7635 | UCHAR ucEntrySize; |
|
6831 | //this is for Sumo |
7636 | |
6832 | ATOM_PPLIB_SUMO_CLOCK_INFO clockInfo[1]; |
7637 | UCHAR clockInfo[1]; |
6833 | }ClockInfoArray; |
7638 | }ClockInfoArray; |
6834 | 7639 | ||
6835 | typedef struct NonClockInfoArray{ |
7640 | typedef struct _NonClockInfoArray{ |
6836 | 7641 | ||
6837 | //how many non-clock levels we have. normally should be same as number of states |
7642 | //how many non-clock levels we have. normally should be same as number of states |
6838 | UCHAR ucNumEntries; |
7643 | UCHAR ucNumEntries; |
6839 | //sizeof(ATOM_PPLIB_NONCLOCK_INFO) |
7644 | //sizeof(ATOM_PPLIB_NONCLOCK_INFO) |
6840 | UCHAR ucEntrySize; |
7645 | UCHAR ucEntrySize; |
6841 | 7646 | ||
6842 | ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; |
7647 | ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; |
6843 | }NonClockInfoArray; |
7648 | }NonClockInfoArray; |
6844 | 7649 | ||
6845 | typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record |
7650 | typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record |
6846 | { |
7651 | { |
6847 | USHORT usClockLow; |
7652 | USHORT usClockLow; |
6848 | UCHAR ucClockHigh; |
7653 | UCHAR ucClockHigh; |
6849 | USHORT usVoltage; |
7654 | USHORT usVoltage; |
6850 | }ATOM_PPLIB_Clock_Voltage_Dependency_Record; |
7655 | }ATOM_PPLIB_Clock_Voltage_Dependency_Record; |
6851 | 7656 | ||
6852 | typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table |
7657 | typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table |
6853 | { |
7658 | { |
6854 | UCHAR ucNumEntries; // Number of entries. |
7659 | UCHAR ucNumEntries; // Number of entries. |
6855 | ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. |
7660 | ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. |
6856 | }ATOM_PPLIB_Clock_Voltage_Dependency_Table; |
7661 | }ATOM_PPLIB_Clock_Voltage_Dependency_Table; |
6857 | 7662 | ||
6858 | typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record |
7663 | typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record |
6859 | { |
7664 | { |
6860 | USHORT usSclkLow; |
7665 | USHORT usSclkLow; |
6861 | UCHAR ucSclkHigh; |
7666 | UCHAR ucSclkHigh; |
6862 | USHORT usMclkLow; |
7667 | USHORT usMclkLow; |
6863 | UCHAR ucMclkHigh; |
7668 | UCHAR ucMclkHigh; |
6864 | USHORT usVddc; |
7669 | USHORT usVddc; |
6865 | USHORT usVddci; |
7670 | USHORT usVddci; |
6866 | }ATOM_PPLIB_Clock_Voltage_Limit_Record; |
7671 | }ATOM_PPLIB_Clock_Voltage_Limit_Record; |
6867 | 7672 | ||
6868 | typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table |
7673 | typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table |
6869 | { |
7674 | { |
6870 | UCHAR ucNumEntries; // Number of entries. |
7675 | UCHAR ucNumEntries; // Number of entries. |
6871 | ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. |
7676 | ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. |
6872 | }ATOM_PPLIB_Clock_Voltage_Limit_Table; |
7677 | }ATOM_PPLIB_Clock_Voltage_Limit_Table; |
- | 7678 | ||
- | 7679 | typedef struct _ATOM_PPLIB_CAC_Leakage_Record |
|
- | 7680 | { |
|
- | 7681 | USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations |
|
- | 7682 | ULONG ulLeakageValue; |
|
- | 7683 | }ATOM_PPLIB_CAC_Leakage_Record; |
|
- | 7684 | ||
- | 7685 | typedef struct _ATOM_PPLIB_CAC_Leakage_Table |
|
- | 7686 | { |
|
- | 7687 | UCHAR ucNumEntries; // Number of entries. |
|
- | 7688 | ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries. |
|
- | 7689 | }ATOM_PPLIB_CAC_Leakage_Table; |
|
- | 7690 | ||
- | 7691 | typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record |
|
- | 7692 | { |
|
- | 7693 | USHORT usVoltage; |
|
- | 7694 | USHORT usSclkLow; |
|
- | 7695 | UCHAR ucSclkHigh; |
|
- | 7696 | USHORT usMclkLow; |
|
- | 7697 | UCHAR ucMclkHigh; |
|
- | 7698 | }ATOM_PPLIB_PhaseSheddingLimits_Record; |
|
- | 7699 | ||
- | 7700 | typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table |
|
- | 7701 | { |
|
- | 7702 | UCHAR ucNumEntries; // Number of entries. |
|
- | 7703 | ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries. |
|
- | 7704 | }ATOM_PPLIB_PhaseSheddingLimits_Table; |
|
- | 7705 | ||
- | 7706 | typedef struct _VCEClockInfo{ |
|
- | 7707 | USHORT usEVClkLow; |
|
- | 7708 | UCHAR ucEVClkHigh; |
|
- | 7709 | USHORT usECClkLow; |
|
- | 7710 | UCHAR ucECClkHigh; |
|
- | 7711 | }VCEClockInfo; |
|
- | 7712 | ||
- | 7713 | typedef struct _VCEClockInfoArray{ |
|
- | 7714 | UCHAR ucNumEntries; |
|
- | 7715 | VCEClockInfo entries[1]; |
|
- | 7716 | }VCEClockInfoArray; |
|
- | 7717 | ||
- | 7718 | typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record |
|
- | 7719 | { |
|
- | 7720 | USHORT usVoltage; |
|
- | 7721 | UCHAR ucVCEClockInfoIndex; |
|
- | 7722 | }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record; |
|
- | 7723 | ||
- | 7724 | typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table |
|
- | 7725 | { |
|
- | 7726 | UCHAR numEntries; |
|
- | 7727 | ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1]; |
|
- | 7728 | }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table; |
|
- | 7729 | ||
- | 7730 | typedef struct _ATOM_PPLIB_VCE_State_Record |
|
- | 7731 | { |
|
- | 7732 | UCHAR ucVCEClockInfoIndex; |
|
- | 7733 | UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary |
|
- | 7734 | }ATOM_PPLIB_VCE_State_Record; |
|
- | 7735 | ||
- | 7736 | typedef struct _ATOM_PPLIB_VCE_State_Table |
|
- | 7737 | { |
|
- | 7738 | UCHAR numEntries; |
|
- | 7739 | ATOM_PPLIB_VCE_State_Record entries[1]; |
|
- | 7740 | }ATOM_PPLIB_VCE_State_Table; |
|
- | 7741 | ||
- | 7742 | ||
- | 7743 | typedef struct _ATOM_PPLIB_VCE_Table |
|
- | 7744 | { |
|
- | 7745 | UCHAR revid; |
|
- | 7746 | // VCEClockInfoArray array; |
|
- | 7747 | // ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits; |
|
- | 7748 | // ATOM_PPLIB_VCE_State_Table states; |
|
- | 7749 | }ATOM_PPLIB_VCE_Table; |
|
- | 7750 | ||
- | 7751 | ||
- | 7752 | typedef struct _UVDClockInfo{ |
|
- | 7753 | USHORT usVClkLow; |
|
- | 7754 | UCHAR ucVClkHigh; |
|
- | 7755 | USHORT usDClkLow; |
|
- | 7756 | UCHAR ucDClkHigh; |
|
- | 7757 | }UVDClockInfo; |
|
- | 7758 | ||
- | 7759 | typedef struct _UVDClockInfoArray{ |
|
- | 7760 | UCHAR ucNumEntries; |
|
- | 7761 | UVDClockInfo entries[1]; |
|
- | 7762 | }UVDClockInfoArray; |
|
- | 7763 | ||
- | 7764 | typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record |
|
- | 7765 | { |
|
- | 7766 | USHORT usVoltage; |
|
- | 7767 | UCHAR ucUVDClockInfoIndex; |
|
- | 7768 | }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record; |
|
- | 7769 | ||
- | 7770 | typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table |
|
- | 7771 | { |
|
- | 7772 | UCHAR numEntries; |
|
- | 7773 | ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1]; |
|
- | 7774 | }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table; |
|
- | 7775 | ||
- | 7776 | typedef struct _ATOM_PPLIB_UVD_State_Record |
|
- | 7777 | { |
|
- | 7778 | UCHAR ucUVDClockInfoIndex; |
|
- | 7779 | UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary |
|
- | 7780 | }ATOM_PPLIB_UVD_State_Record; |
|
- | 7781 | ||
- | 7782 | typedef struct _ATOM_PPLIB_UVD_State_Table |
|
- | 7783 | { |
|
- | 7784 | UCHAR numEntries; |
|
- | 7785 | ATOM_PPLIB_UVD_State_Record entries[1]; |
|
- | 7786 | }ATOM_PPLIB_UVD_State_Table; |
|
- | 7787 | ||
- | 7788 | ||
- | 7789 | typedef struct _ATOM_PPLIB_UVD_Table |
|
- | 7790 | { |
|
- | 7791 | UCHAR revid; |
|
- | 7792 | // UVDClockInfoArray array; |
|
- | 7793 | // ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits; |
|
- | 7794 | // ATOM_PPLIB_UVD_State_Table states; |
|
- | 7795 | }ATOM_PPLIB_UVD_Table; |
|
6873 | 7796 | ||
6874 | /**************************************************************************/ |
7797 | /**************************************************************************/ |
6875 | 7798 | ||
6876 | 7799 | ||
6877 | // Following definitions are for compatibility issue in different SW components. |
7800 | // Following definitions are for compatibility issue in different SW components. |
6878 | #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 |
7801 | #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 |
6879 | #define Object_Info Object_Header |
7802 | #define Object_Info Object_Header |
6880 | #define AdjustARB_SEQ MC_InitParameter |
7803 | #define AdjustARB_SEQ MC_InitParameter |
6881 | #define VRAM_GPIO_DetectionInfo VoltageObjectInfo |
7804 | #define VRAM_GPIO_DetectionInfo VoltageObjectInfo |
6882 | #define ASIC_VDDCI_Info ASIC_ProfilingInfo |
7805 | #define ASIC_VDDCI_Info ASIC_ProfilingInfo |
6883 | #define ASIC_MVDDQ_Info MemoryTrainingInfo |
7806 | #define ASIC_MVDDQ_Info MemoryTrainingInfo |
6884 | #define SS_Info PPLL_SS_Info |
7807 | #define SS_Info PPLL_SS_Info |
6885 | #define ASIC_MVDDC_Info ASIC_InternalSS_Info |
7808 | #define ASIC_MVDDC_Info ASIC_InternalSS_Info |
6886 | #define DispDevicePriorityInfo SaveRestoreInfo |
7809 | #define DispDevicePriorityInfo SaveRestoreInfo |
6887 | #define DispOutInfo TV_VideoMode |
7810 | #define DispOutInfo TV_VideoMode |
6888 | 7811 | ||
6889 | 7812 | ||
6890 | #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE |
7813 | #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE |
6891 | #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE |
7814 | #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE |
6892 | 7815 | ||
6893 | //New device naming, remove them when both DAL/VBIOS is ready |
7816 | //New device naming, remove them when both DAL/VBIOS is ready |
6894 | #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS |
7817 | #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS |
6895 | #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS |
7818 | #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS |
6896 | 7819 | ||
6897 | #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS |
7820 | #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS |
6898 | #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS |
7821 | #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS |
6899 | 7822 | ||
6900 | #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS |
7823 | #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS |
6901 | #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION |
7824 | #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION |
6902 | 7825 | ||
6903 | #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT |
7826 | #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT |
6904 | #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT |
7827 | #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT |
6905 | 7828 | ||
6906 | #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX |
7829 | #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX |
6907 | #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX |
7830 | #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX |
6908 | 7831 | ||
6909 | #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 |
7832 | #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 |
6910 | #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) |
7833 | #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) |
6911 | 7834 | ||
6912 | #define ATOM_S0_DFP1I ATOM_S0_DFP1 |
7835 | #define ATOM_S0_DFP1I ATOM_S0_DFP1 |
6913 | #define ATOM_S0_DFP1X ATOM_S0_DFP2 |
7836 | #define ATOM_S0_DFP1X ATOM_S0_DFP2 |
6914 | 7837 | ||
6915 | #define ATOM_S0_DFP2I 0x00200000L |
7838 | #define ATOM_S0_DFP2I 0x00200000L |
6916 | #define ATOM_S0_DFP2Ib2 0x20 |
7839 | #define ATOM_S0_DFP2Ib2 0x20 |
6917 | 7840 | ||
6918 | #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE |
7841 | #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE |
6919 | #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE |
7842 | #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE |
6920 | 7843 | ||
6921 | #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L |
7844 | #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L |
6922 | #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 |
7845 | #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 |
6923 | 7846 | ||
6924 | #define ATOM_S3_DFP2I_ACTIVEb1 0x02 |
7847 | #define ATOM_S3_DFP2I_ACTIVEb1 0x02 |
6925 | 7848 | ||
6926 | #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE |
7849 | #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE |
6927 | #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE |
7850 | #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE |
6928 | 7851 | ||
6929 | #define ATOM_S3_DFP2I_ACTIVE 0x00000200L |
7852 | #define ATOM_S3_DFP2I_ACTIVE 0x00000200L |
6930 | 7853 | ||
6931 | #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE |
7854 | #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE |
6932 | #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE |
7855 | #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE |
6933 | #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L |
7856 | #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L |
6934 | 7857 | ||
6935 | #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 |
7858 | #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 |
6936 | #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 |
7859 | #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 |
6937 | 7860 | ||
6938 | #define ATOM_S5_DOS_REQ_DFP2I 0x0200 |
7861 | #define ATOM_S5_DOS_REQ_DFP2I 0x0200 |
6939 | #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 |
7862 | #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 |
6940 | #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 |
7863 | #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 |
6941 | 7864 | ||
6942 | #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 |
7865 | #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 |
6943 | #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L |
7866 | #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L |
6944 | 7867 | ||
6945 | #define TMDS1XEncoderControl DVOEncoderControl |
7868 | #define TMDS1XEncoderControl DVOEncoderControl |
6946 | #define DFP1XOutputControl DVOOutputControl |
7869 | #define DFP1XOutputControl DVOOutputControl |
6947 | 7870 | ||
6948 | #define ExternalDFPOutputControl DFP1XOutputControl |
7871 | #define ExternalDFPOutputControl DFP1XOutputControl |
6949 | #define EnableExternalTMDS_Encoder TMDS1XEncoderControl |
7872 | #define EnableExternalTMDS_Encoder TMDS1XEncoderControl |
6950 | 7873 | ||
6951 | #define DFP1IOutputControl TMDSAOutputControl |
7874 | #define DFP1IOutputControl TMDSAOutputControl |
6952 | #define DFP2IOutputControl LVTMAOutputControl |
7875 | #define DFP2IOutputControl LVTMAOutputControl |
6953 | 7876 | ||
6954 | #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS |
7877 | #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS |
6955 | #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION |
7878 | #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION |
6956 | 7879 | ||
6957 | #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS |
7880 | #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS |
6958 | #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION |
7881 | #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION |
6959 | 7882 | ||
6960 | #define ucDac1Standard ucDacStandard |
7883 | #define ucDac1Standard ucDacStandard |
6961 | #define ucDac2Standard ucDacStandard |
7884 | #define ucDac2Standard ucDacStandard |
6962 | 7885 | ||
6963 | #define TMDS1EncoderControl TMDSAEncoderControl |
7886 | #define TMDS1EncoderControl TMDSAEncoderControl |
6964 | #define TMDS2EncoderControl LVTMAEncoderControl |
7887 | #define TMDS2EncoderControl LVTMAEncoderControl |
6965 | 7888 | ||
6966 | #define DFP1OutputControl TMDSAOutputControl |
7889 | #define DFP1OutputControl TMDSAOutputControl |
6967 | #define DFP2OutputControl LVTMAOutputControl |
7890 | #define DFP2OutputControl LVTMAOutputControl |
6968 | #define CRT1OutputControl DAC1OutputControl |
7891 | #define CRT1OutputControl DAC1OutputControl |
6969 | #define CRT2OutputControl DAC2OutputControl |
7892 | #define CRT2OutputControl DAC2OutputControl |
6970 | 7893 | ||
6971 | //These two lines will be removed for sure in a few days, will follow up with Michael V. |
7894 | //These two lines will be removed for sure in a few days, will follow up with Michael V. |
6972 | #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL |
7895 | #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL |
6973 | #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL |
7896 | #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL |
6974 | 7897 | ||
6975 | //#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L |
7898 | //#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L |
6976 | //#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE |
7899 | //#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE |
6977 | //#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE |
7900 | //#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE |
6978 | //#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE |
7901 | //#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE |
6979 | //#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE |
7902 | //#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE |
6980 | 7903 | ||
6981 | #define ATOM_S6_ACC_REQ_TV2 0x00400000L |
7904 | #define ATOM_S6_ACC_REQ_TV2 0x00400000L |
6982 | #define ATOM_DEVICE_TV2_INDEX 0x00000006 |
7905 | #define ATOM_DEVICE_TV2_INDEX 0x00000006 |
6983 | #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) |
7906 | #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) |
6984 | #define ATOM_S0_TV2 0x00100000L |
7907 | #define ATOM_S0_TV2 0x00100000L |
6985 | #define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE |
7908 | #define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE |
6986 | #define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE |
7909 | #define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE |
6987 | 7910 | ||
6988 | // |
7911 | // |
6989 | #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L |
7912 | #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L |
6990 | #define ATOM_S2_LCD1_DPMS_STATE 0x00020000L |
7913 | #define ATOM_S2_LCD1_DPMS_STATE 0x00020000L |
6991 | #define ATOM_S2_TV1_DPMS_STATE 0x00040000L |
7914 | #define ATOM_S2_TV1_DPMS_STATE 0x00040000L |
6992 | #define ATOM_S2_DFP1_DPMS_STATE 0x00080000L |
7915 | #define ATOM_S2_DFP1_DPMS_STATE 0x00080000L |
6993 | #define ATOM_S2_CRT2_DPMS_STATE 0x00100000L |
7916 | #define ATOM_S2_CRT2_DPMS_STATE 0x00100000L |
6994 | #define ATOM_S2_LCD2_DPMS_STATE 0x00200000L |
7917 | #define ATOM_S2_LCD2_DPMS_STATE 0x00200000L |
6995 | #define ATOM_S2_TV2_DPMS_STATE 0x00400000L |
7918 | #define ATOM_S2_TV2_DPMS_STATE 0x00400000L |
6996 | #define ATOM_S2_DFP2_DPMS_STATE 0x00800000L |
7919 | #define ATOM_S2_DFP2_DPMS_STATE 0x00800000L |
6997 | #define ATOM_S2_CV_DPMS_STATE 0x01000000L |
7920 | #define ATOM_S2_CV_DPMS_STATE 0x01000000L |
6998 | #define ATOM_S2_DFP3_DPMS_STATE 0x02000000L |
7921 | #define ATOM_S2_DFP3_DPMS_STATE 0x02000000L |
6999 | #define ATOM_S2_DFP4_DPMS_STATE 0x04000000L |
7922 | #define ATOM_S2_DFP4_DPMS_STATE 0x04000000L |
7000 | #define ATOM_S2_DFP5_DPMS_STATE 0x08000000L |
7923 | #define ATOM_S2_DFP5_DPMS_STATE 0x08000000L |
7001 | 7924 | ||
7002 | #define ATOM_S2_CRT1_DPMS_STATEb2 0x01 |
7925 | #define ATOM_S2_CRT1_DPMS_STATEb2 0x01 |
7003 | #define ATOM_S2_LCD1_DPMS_STATEb2 0x02 |
7926 | #define ATOM_S2_LCD1_DPMS_STATEb2 0x02 |
7004 | #define ATOM_S2_TV1_DPMS_STATEb2 0x04 |
7927 | #define ATOM_S2_TV1_DPMS_STATEb2 0x04 |
7005 | #define ATOM_S2_DFP1_DPMS_STATEb2 0x08 |
7928 | #define ATOM_S2_DFP1_DPMS_STATEb2 0x08 |
7006 | #define ATOM_S2_CRT2_DPMS_STATEb2 0x10 |
7929 | #define ATOM_S2_CRT2_DPMS_STATEb2 0x10 |
7007 | #define ATOM_S2_LCD2_DPMS_STATEb2 0x20 |
7930 | #define ATOM_S2_LCD2_DPMS_STATEb2 0x20 |
7008 | #define ATOM_S2_TV2_DPMS_STATEb2 0x40 |
7931 | #define ATOM_S2_TV2_DPMS_STATEb2 0x40 |
7009 | #define ATOM_S2_DFP2_DPMS_STATEb2 0x80 |
7932 | #define ATOM_S2_DFP2_DPMS_STATEb2 0x80 |
7010 | #define ATOM_S2_CV_DPMS_STATEb3 0x01 |
7933 | #define ATOM_S2_CV_DPMS_STATEb3 0x01 |
7011 | #define ATOM_S2_DFP3_DPMS_STATEb3 0x02 |
7934 | #define ATOM_S2_DFP3_DPMS_STATEb3 0x02 |
7012 | #define ATOM_S2_DFP4_DPMS_STATEb3 0x04 |
7935 | #define ATOM_S2_DFP4_DPMS_STATEb3 0x04 |
7013 | #define ATOM_S2_DFP5_DPMS_STATEb3 0x08 |
7936 | #define ATOM_S2_DFP5_DPMS_STATEb3 0x08 |
7014 | 7937 | ||
7015 | #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 |
7938 | #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 |
7016 | #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 |
7939 | #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 |
7017 | #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 |
7940 | #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 |
7018 | 7941 | ||
7019 | /*********************************************************************************/ |
7942 | /*********************************************************************************/ |
7020 | 7943 | ||
7021 | #pragma pack() // BIOS data must use byte aligment |
7944 | #pragma pack() // BIOS data must use byte aligment |
- | 7945 | ||
- | 7946 | // |
|
- | 7947 | // AMD ACPI Table |
|
- | 7948 | // |
|
- | 7949 | #pragma pack(1) |
|
- | 7950 | ||
- | 7951 | typedef struct { |
|
- | 7952 | ULONG Signature; |
|
- | 7953 | ULONG TableLength; //Length |
|
- | 7954 | UCHAR Revision; |
|
- | 7955 | UCHAR Checksum; |
|
- | 7956 | UCHAR OemId[6]; |
|
- | 7957 | UCHAR OemTableId[8]; //UINT64 OemTableId; |
|
- | 7958 | ULONG OemRevision; |
|
- | 7959 | ULONG CreatorId; |
|
- | 7960 | ULONG CreatorRevision; |
|
- | 7961 | } AMD_ACPI_DESCRIPTION_HEADER; |
|
- | 7962 | /* |
|
- | 7963 | //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h |
|
- | 7964 | typedef struct { |
|
- | 7965 | UINT32 Signature; //0x0 |
|
- | 7966 | UINT32 Length; //0x4 |
|
- | 7967 | UINT8 Revision; //0x8 |
|
- | 7968 | UINT8 Checksum; //0x9 |
|
- | 7969 | UINT8 OemId[6]; //0xA |
|
- | 7970 | UINT64 OemTableId; //0x10 |
|
- | 7971 | UINT32 OemRevision; //0x18 |
|
- | 7972 | UINT32 CreatorId; //0x1C |
|
- | 7973 | UINT32 CreatorRevision; //0x20 |
|
- | 7974 | }EFI_ACPI_DESCRIPTION_HEADER; |
|
- | 7975 | */ |
|
- | 7976 | typedef struct { |
|
- | 7977 | AMD_ACPI_DESCRIPTION_HEADER SHeader; |
|
- | 7978 | UCHAR TableUUID[16]; //0x24 |
|
- | 7979 | ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. |
|
- | 7980 | ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. |
|
- | 7981 | ULONG Reserved[4]; //0x3C |
|
- | 7982 | }UEFI_ACPI_VFCT; |
|
- | 7983 | ||
- | 7984 | typedef struct { |
|
- | 7985 | ULONG PCIBus; //0x4C |
|
- | 7986 | ULONG PCIDevice; //0x50 |
|
- | 7987 | ULONG PCIFunction; //0x54 |
|
- | 7988 | USHORT VendorID; //0x58 |
|
- | 7989 | USHORT DeviceID; //0x5A |
|
- | 7990 | USHORT SSVID; //0x5C |
|
- | 7991 | USHORT SSID; //0x5E |
|
- | 7992 | ULONG Revision; //0x60 |
|
- | 7993 | ULONG ImageLength; //0x64 |
|
- | 7994 | }VFCT_IMAGE_HEADER; |
|
- | 7995 | ||
- | 7996 | ||
- | 7997 | typedef struct { |
|
- | 7998 | VFCT_IMAGE_HEADER VbiosHeader; |
|
- | 7999 | UCHAR VbiosContent[1]; |
|
- | 8000 | }GOP_VBIOS_CONTENT; |
|
- | 8001 | ||
- | 8002 | typedef struct { |
|
- | 8003 | VFCT_IMAGE_HEADER Lib1Header; |
|
- | 8004 | UCHAR Lib1Content[1]; |
|
- | 8005 | }GOP_LIB1_CONTENT; |
|
- | 8006 | ||
- | 8007 | #pragma pack() |
|
- | 8008 | ||
7022 | 8009 | ||
7023 | #endif /* _ATOMBIOS_H */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>8)) |
8010 | #endif /* _ATOMBIOS_H */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>8)) |
7024 | 8011 | ||
7025 | //><8)) |
8012 | //><8)) |
7026 | 8013 | ||
7027 | //>=2Gb) |
8014 | //>=2Gb) |
7028 | >><>><>><>><>><>><>><>><>><>><>><>><>=Max>=InterNBVoltageHigh.>=>=>=>=>3 |
8015 | >><>><>><>><>><>><>><>><>><>><>><>><>=Max>=InterNBVoltageHigh.>=>=>=>=>3 |
7029 | >3 |
8016 | >3 |
7030 | >=>=>3 |
8017 | >=>=>3 |
7031 | >3 |
8018 | >3 |
7032 | > |
8019 | > |