Rev 1268 | Rev 1321 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 1268 | Rev 1313 | ||
|---|---|---|---|
| Line 1139... | Line 1139... | ||
| 1139 | #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS |
1139 | #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS |
| Line 1140... | Line 1140... | ||
| 1140 | 1140 | ||
| 1141 | /* ucTableFormatRevision=1,ucTableContentRevision=2 */ |
1141 | /* ucTableFormatRevision=1,ucTableContentRevision=2 */ |
| 1142 | typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 { |
1142 | typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 { |
| 1143 | USHORT usPixelClock; /* in 10KHz; for bios convenient */ |
1143 | USHORT usPixelClock; /* in 10KHz; for bios convenient */ |
| 1144 | UCHAR ucMisc; /* see PANEL_ENCODER_MISC_xx defintions below */ |
1144 | UCHAR ucMisc; /* see PANEL_ENCODER_MISC_xx definitions below */ |
| 1145 | UCHAR ucAction; /* 0: turn off encoder */ |
1145 | UCHAR ucAction; /* 0: turn off encoder */ |
| 1146 | /* 1: setup and turn on encoder */ |
1146 | /* 1: setup and turn on encoder */ |
| 1147 | UCHAR ucTruncate; /* bit0=0: Disable truncate */ |
1147 | UCHAR ucTruncate; /* bit0=0: Disable truncate */ |
| 1148 | /* =1: Enable truncate */ |
1148 | /* =1: Enable truncate */ |
| Line 1422... | Line 1422... | ||
| 1422 | 1422 | ||
| 1423 | /****************************************************************************/ |
1423 | /****************************************************************************/ |
| 1424 | /* Structures used in FirmwareInfoTable */ |
1424 | /* Structures used in FirmwareInfoTable */ |
| Line 1425... | Line 1425... | ||
| 1425 | /****************************************************************************/ |
1425 | /****************************************************************************/ |
| 1426 | 1426 | ||
| 1427 | /* usBIOSCapability Defintion: */ |
1427 | /* usBIOSCapability Definition: */ |
| 1428 | /* Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; */ |
1428 | /* Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; */ |
| 1429 | /* Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; */ |
1429 | /* Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; */ |
| 1430 | /* Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; */ |
1430 | /* Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; */ |
| Line 2384... | Line 2384... | ||
| 2384 | UCHAR ucExt_TV_ASIC_SlaveAddr; |
2384 | UCHAR ucExt_TV_ASIC_SlaveAddr; |
| 2385 | ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; |
2385 | ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; |
| 2386 | } ATOM_ANALOG_TV_INFO_V1_2; |
2386 | } ATOM_ANALOG_TV_INFO_V1_2; |
| Line 2387... | Line 2387... | ||
| 2387 | 2387 | ||
| 2388 | /**************************************************************************/ |
2388 | /**************************************************************************/ |
| Line 2389... | Line 2389... | ||
| 2389 | /* VRAM usage and their defintions */ |
2389 | /* VRAM usage and their definitions */ |
| 2390 | 2390 | ||
| 2391 | /* One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. */ |
2391 | /* One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. */ |
| 2392 | /* Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. */ |
2392 | /* Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. */ |
| Line 3044... | Line 3044... | ||
| 3044 | 3044 | ||
| 3045 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 |
3045 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 |
| 3046 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 |
3046 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 |
| Line 3047... | Line 3047... | ||
| 3047 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 |
3047 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 |
| 3048 | 3048 | ||
| 3049 | /* Byte aligned defintion for BIOS usage */ |
3049 | /* Byte aligned definition for BIOS usage */ |
| 3050 | #define ATOM_S0_CRT1_MONOb0 0x01 |
3050 | #define ATOM_S0_CRT1_MONOb0 0x01 |
| Line 3051... | Line 3051... | ||
| 3051 | #define ATOM_S0_CRT1_COLORb0 0x02 |
3051 | #define ATOM_S0_CRT1_COLORb0 0x02 |
| Line 3129... | Line 3129... | ||
| 3129 | #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 |
3129 | #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 |
| 3130 | #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 |
3130 | #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 |
| 3131 | #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 |
3131 | #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 |
| 3132 | #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L |
3132 | #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L |
| Line 3133... | Line 3133... | ||
| 3133 | 3133 | ||
| 3134 | /* Byte aligned defintion for BIOS usage */ |
3134 | /* Byte aligned definition for BIOS usage */ |
| 3135 | #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F |
3135 | #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F |
| 3136 | #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF |
3136 | #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF |
| 3137 | #define ATOM_S2_CRT1_DPMS_STATEb2 0x01 |
3137 | #define ATOM_S2_CRT1_DPMS_STATEb2 0x01 |
| 3138 | #define ATOM_S2_LCD1_DPMS_STATEb2 0x02 |
3138 | #define ATOM_S2_LCD1_DPMS_STATEb2 0x02 |
| Line 3188... | Line 3188... | ||
| 3188 | #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L |
3188 | #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L |
| 3189 | #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L |
3189 | #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L |
| 3190 | #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L |
3190 | #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L |
| 3191 | #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L |
3191 | #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L |
| Line 3192... | Line 3192... | ||
| 3192 | 3192 | ||
| 3193 | /* Byte aligned defintion for BIOS usage */ |
3193 | /* Byte aligned definition for BIOS usage */ |
| 3194 | #define ATOM_S3_CRT1_ACTIVEb0 0x01 |
3194 | #define ATOM_S3_CRT1_ACTIVEb0 0x01 |
| 3195 | #define ATOM_S3_LCD1_ACTIVEb0 0x02 |
3195 | #define ATOM_S3_LCD1_ACTIVEb0 0x02 |
| 3196 | #define ATOM_S3_TV1_ACTIVEb0 0x04 |
3196 | #define ATOM_S3_TV1_ACTIVEb0 0x04 |
| 3197 | #define ATOM_S3_DFP1_ACTIVEb0 0x08 |
3197 | #define ATOM_S3_DFP1_ACTIVEb0 0x08 |
| Line 3228... | Line 3228... | ||
| 3228 | /* BIOS_4_SCRATCH Definition */ |
3228 | /* BIOS_4_SCRATCH Definition */ |
| 3229 | #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL |
3229 | #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL |
| 3230 | #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L |
3230 | #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L |
| 3231 | #define ATOM_S4_LCD1_REFRESH_SHIFT 8 |
3231 | #define ATOM_S4_LCD1_REFRESH_SHIFT 8 |
| Line 3232... | Line 3232... | ||
| 3232 | 3232 | ||
| 3233 | /* Byte aligned defintion for BIOS usage */ |
3233 | /* Byte aligned definition for BIOS usage */ |
| 3234 | #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF |
3234 | #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF |
| 3235 | #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
3235 | #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
| Line 3236... | Line 3236... | ||
| 3236 | #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
3236 | #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
| Line 3308... | Line 3308... | ||
| 3308 | #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L |
3308 | #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L |
| 3309 | #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L |
3309 | #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L |
| 3310 | #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L |
3310 | #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L |
| 3311 | #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L |
3311 | #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L |
| Line 3312... | Line 3312... | ||
| 3312 | 3312 | ||
| 3313 | /* Byte aligned defintion for BIOS usage */ |
3313 | /* Byte aligned definition for BIOS usage */ |
| 3314 | #define ATOM_S6_DEVICE_CHANGEb0 0x01 |
3314 | #define ATOM_S6_DEVICE_CHANGEb0 0x01 |
| 3315 | #define ATOM_S6_SCALER_CHANGEb0 0x02 |
3315 | #define ATOM_S6_SCALER_CHANGEb0 0x02 |
| 3316 | #define ATOM_S6_LID_CHANGEb0 0x04 |
3316 | #define ATOM_S6_LID_CHANGEb0 0x04 |
| 3317 | #define ATOM_S6_DOCKING_CHANGEb0 0x08 |
3317 | #define ATOM_S6_DOCKING_CHANGEb0 0x08 |