WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/atom.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Author: Stanislaw Skowronek
 */
 
#include 
#include 
#include 
#include 
 
#define ATOM_DEBUG
 
#include "atom.h"
#include "atom-names.h"
#include "atom-bits.h"
#include "radeon.h"
 
#define ATOM_COND_ABOVE		0
#define ATOM_COND_ABOVEOREQUAL	1
#define ATOM_COND_ALWAYS	2
#define ATOM_COND_BELOW		3
#define ATOM_COND_BELOWOREQUAL	4
#define ATOM_COND_EQUAL		5
#define ATOM_COND_NOTEQUAL	6
 
#define ATOM_PORT_ATI	0
#define ATOM_PORT_PCI	1
#define ATOM_PORT_SYSIO	2
 
#define ATOM_UNIT_MICROSEC	0
#define ATOM_UNIT_MILLISEC	1
 
#define PLL_INDEX	2
#define PLL_DATA	3
 
typedef struct {
	struct atom_context *ctx;
	uint32_t *ps, *ws;
	int ps_shift;
	uint16_t start;
	unsigned last_jump;
	unsigned long last_jump_jiffies;
	bool abort;
} atom_exec_context;
 
int atom_debug = 0;
static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
 
static uint32_t atom_arg_mask[8] =
    { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
0xFF000000 };
static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
 
static int atom_dst_to_src[8][4] = {
	/* translate destination alignment field to the source alignment encoding */
	{0, 0, 0, 0},
	{1, 2, 3, 0},
	{1, 2, 3, 0},
	{1, 2, 3, 0},
	{4, 5, 6, 7},
	{4, 5, 6, 7},
	{4, 5, 6, 7},
	{4, 5, 6, 7},
};
static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
 
static int debug_depth = 0;
#ifdef ATOM_DEBUG
static void debug_print_spaces(int n)
{
	while (n--)
		printk("   ");
}
 
#define DEBUG(...) do if (atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)
#define SDEBUG(...) do if (atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)
#else
#define DEBUG(...) do { } while (0)
#define SDEBUG(...) do { } while (0)
#endif
 
static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
				 uint32_t index, uint32_t data)
{
	struct radeon_device *rdev = ctx->card->dev->dev_private;
	uint32_t temp = 0xCDCDCDCD;
 
	while (1)
		switch (CU8(base)) {
		case ATOM_IIO_NOP:
			base++;
			break;
		case ATOM_IIO_READ:
			temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1));
			base += 3;
			break;
		case ATOM_IIO_WRITE:
			if (rdev->family == CHIP_RV515)
			(void)ctx->card->ioreg_read(ctx->card, CU16(base + 1));
			ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp);
			base += 3;
			break;
		case ATOM_IIO_CLEAR:
			temp &=
			    ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
			      CU8(base + 2));
			base += 3;
			break;
		case ATOM_IIO_SET:
			temp |=
			    (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +
									2);
			base += 3;
			break;
		case ATOM_IIO_MOVE_INDEX:
			temp &=
			    ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
			      CU8(base + 3));
			temp |=
			    ((index >> CU8(base + 2)) &
			     (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
									  3);
			base += 4;
			break;
		case ATOM_IIO_MOVE_DATA:
			temp &=
			    ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
			      CU8(base + 3));
			temp |=
			    ((data >> CU8(base + 2)) &
			     (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
									  3);
			base += 4;
			break;
		case ATOM_IIO_MOVE_ATTR:
			temp &=
			    ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
			      CU8(base + 3));
			temp |=
			    ((ctx->
			      io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -
									  CU8
									  (base
									   +
									   1))))
			    << CU8(base + 3);
			base += 4;
			break;
		case ATOM_IIO_END:
			return temp;
		default:
			printk(KERN_INFO "Unknown IIO opcode.\n");
			return 0;
		}
}
 
static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
				 int *ptr, uint32_t *saved, int print)
{
	uint32_t idx, val = 0xCDCDCDCD, align, arg;
	struct atom_context *gctx = ctx->ctx;
	arg = attr & 7;
	align = (attr >> 3) & 7;
	switch (arg) {
	case ATOM_ARG_REG:
		idx = U16(*ptr);
		(*ptr) += 2;
		if (print)
			DEBUG("REG[0x%04X]", idx);
		idx += gctx->reg_block;
		switch (gctx->io_mode) {
		case ATOM_IO_MM:
			val = gctx->card->reg_read(gctx->card, idx);
			break;
		case ATOM_IO_PCI:
			printk(KERN_INFO
			       "PCI registers are not implemented.\n");
			return 0;
		case ATOM_IO_SYSIO:
			printk(KERN_INFO
			       "SYSIO registers are not implemented.\n");
			return 0;
		default:
			if (!(gctx->io_mode & 0x80)) {
				printk(KERN_INFO "Bad IO mode.\n");
				return 0;
			}
			if (!gctx->iio[gctx->io_mode & 0x7F]) {
				printk(KERN_INFO
				       "Undefined indirect IO read method %d.\n",
				       gctx->io_mode & 0x7F);
				return 0;
			}
			val =
			    atom_iio_execute(gctx,
					     gctx->iio[gctx->io_mode & 0x7F],
					     idx, 0);
		}
		break;
	case ATOM_ARG_PS:
		idx = U8(*ptr);
		(*ptr)++;
		/* get_unaligned_le32 avoids unaligned accesses from atombios
		 * tables, noticed on a DEC Alpha. */
		val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
		if (print)
			DEBUG("PS[0x%02X,0x%04X]", idx, val);
		break;
	case ATOM_ARG_WS:
		idx = U8(*ptr);
		(*ptr)++;
		if (print)
			DEBUG("WS[0x%02X]", idx);
		switch (idx) {
		case ATOM_WS_QUOTIENT:
			val = gctx->divmul[0];
			break;
		case ATOM_WS_REMAINDER:
			val = gctx->divmul[1];
			break;
		case ATOM_WS_DATAPTR:
			val = gctx->data_block;
			break;
		case ATOM_WS_SHIFT:
			val = gctx->shift;
			break;
		case ATOM_WS_OR_MASK:
			val = 1 << gctx->shift;
			break;
		case ATOM_WS_AND_MASK:
			val = ~(1 << gctx->shift);
			break;
		case ATOM_WS_FB_WINDOW:
			val = gctx->fb_base;
			break;
		case ATOM_WS_ATTRIBUTES:
			val = gctx->io_attr;
			break;
		case ATOM_WS_REGPTR:
			val = gctx->reg_block;
			break;
		default:
			val = ctx->ws[idx];
		}
		break;
	case ATOM_ARG_ID:
		idx = U16(*ptr);
		(*ptr) += 2;
		if (print) {
			if (gctx->data_block)
				DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);
			else
				DEBUG("ID[0x%04X]", idx);
		}
		val = U32(idx + gctx->data_block);
		break;
	case ATOM_ARG_FB:
		idx = U8(*ptr);
		(*ptr)++;
		if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
			DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n",
				  gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
			val = 0;
		} else
			val = gctx->scratch[(gctx->fb_base / 4) + idx];
		if (print)
			DEBUG("FB[0x%02X]", idx);
		break;
	case ATOM_ARG_IMM:
		switch (align) {
		case ATOM_SRC_DWORD:
			val = U32(*ptr);
			(*ptr) += 4;
			if (print)
				DEBUG("IMM 0x%08X\n", val);
			return val;
		case ATOM_SRC_WORD0:
		case ATOM_SRC_WORD8:
		case ATOM_SRC_WORD16:
			val = U16(*ptr);
			(*ptr) += 2;
			if (print)
				DEBUG("IMM 0x%04X\n", val);
			return val;
		case ATOM_SRC_BYTE0:
		case ATOM_SRC_BYTE8:
		case ATOM_SRC_BYTE16:
		case ATOM_SRC_BYTE24:
			val = U8(*ptr);
			(*ptr)++;
			if (print)
				DEBUG("IMM 0x%02X\n", val);
			return val;
		}
		return 0;
	case ATOM_ARG_PLL:
		idx = U8(*ptr);
		(*ptr)++;
		if (print)
			DEBUG("PLL[0x%02X]", idx);
		val = gctx->card->pll_read(gctx->card, idx);
		break;
	case ATOM_ARG_MC:
		idx = U8(*ptr);
		(*ptr)++;
		if (print)
			DEBUG("MC[0x%02X]", idx);
		val = gctx->card->mc_read(gctx->card, idx);
		break;
	}
	if (saved)
		*saved = val;
	val &= atom_arg_mask[align];
	val >>= atom_arg_shift[align];
	if (print)
		switch (align) {
		case ATOM_SRC_DWORD:
			DEBUG(".[31:0] -> 0x%08X\n", val);
			break;
		case ATOM_SRC_WORD0:
			DEBUG(".[15:0] -> 0x%04X\n", val);
			break;
		case ATOM_SRC_WORD8:
			DEBUG(".[23:8] -> 0x%04X\n", val);
			break;
		case ATOM_SRC_WORD16:
			DEBUG(".[31:16] -> 0x%04X\n", val);
			break;
		case ATOM_SRC_BYTE0:
			DEBUG(".[7:0] -> 0x%02X\n", val);
			break;
		case ATOM_SRC_BYTE8:
			DEBUG(".[15:8] -> 0x%02X\n", val);
			break;
		case ATOM_SRC_BYTE16:
			DEBUG(".[23:16] -> 0x%02X\n", val);
			break;
		case ATOM_SRC_BYTE24:
			DEBUG(".[31:24] -> 0x%02X\n", val);
			break;
		}
	return val;
}
 
static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)
{
	uint32_t align = (attr >> 3) & 7, arg = attr & 7;
	switch (arg) {
	case ATOM_ARG_REG:
	case ATOM_ARG_ID:
		(*ptr) += 2;
		break;
	case ATOM_ARG_PLL:
	case ATOM_ARG_MC:
	case ATOM_ARG_PS:
	case ATOM_ARG_WS:
	case ATOM_ARG_FB:
		(*ptr)++;
		break;
	case ATOM_ARG_IMM:
		switch (align) {
		case ATOM_SRC_DWORD:
			(*ptr) += 4;
			return;
		case ATOM_SRC_WORD0:
		case ATOM_SRC_WORD8:
		case ATOM_SRC_WORD16:
			(*ptr) += 2;
			return;
		case ATOM_SRC_BYTE0:
		case ATOM_SRC_BYTE8:
		case ATOM_SRC_BYTE16:
		case ATOM_SRC_BYTE24:
			(*ptr)++;
			return;
		}
		return;
	}
}
 
static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
{
	return atom_get_src_int(ctx, attr, ptr, NULL, 1);
}
 
static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
{
	uint32_t val = 0xCDCDCDCD;
 
	switch (align) {
	case ATOM_SRC_DWORD:
		val = U32(*ptr);
		(*ptr) += 4;
		break;
	case ATOM_SRC_WORD0:
	case ATOM_SRC_WORD8:
	case ATOM_SRC_WORD16:
		val = U16(*ptr);
		(*ptr) += 2;
		break;
	case ATOM_SRC_BYTE0:
	case ATOM_SRC_BYTE8:
	case ATOM_SRC_BYTE16:
	case ATOM_SRC_BYTE24:
		val = U8(*ptr);
		(*ptr)++;
		break;
	}
	return val;
}
 
static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
			     int *ptr, uint32_t *saved, int print)
{
	return atom_get_src_int(ctx,
				arg | atom_dst_to_src[(attr >> 3) &
						      7][(attr >> 6) & 3] << 3,
				ptr, saved, print);
}
 
static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)
{
	atom_skip_src_int(ctx,
			  arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &
								 3] << 3, ptr);
}
 
static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
			 int *ptr, uint32_t val, uint32_t saved)
{
	uint32_t align =
	    atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =
	    val, idx;
	struct atom_context *gctx = ctx->ctx;
	old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
	val <<= atom_arg_shift[align];
	val &= atom_arg_mask[align];
	saved &= ~atom_arg_mask[align];
	val |= saved;
	switch (arg) {
	case ATOM_ARG_REG:
		idx = U16(*ptr);
		(*ptr) += 2;
		DEBUG("REG[0x%04X]", idx);
		idx += gctx->reg_block;
		switch (gctx->io_mode) {
		case ATOM_IO_MM:
			if (idx == 0)
				gctx->card->reg_write(gctx->card, idx,
						      val << 2);
			else
				gctx->card->reg_write(gctx->card, idx, val);
			break;
		case ATOM_IO_PCI:
			printk(KERN_INFO
			       "PCI registers are not implemented.\n");
			return;
		case ATOM_IO_SYSIO:
			printk(KERN_INFO
			       "SYSIO registers are not implemented.\n");
			return;
		default:
			if (!(gctx->io_mode & 0x80)) {
				printk(KERN_INFO "Bad IO mode.\n");
				return;
			}
			if (!gctx->iio[gctx->io_mode & 0xFF]) {
				printk(KERN_INFO
				       "Undefined indirect IO write method %d.\n",
				       gctx->io_mode & 0x7F);
				return;
			}
			atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],
					 idx, val);
		}
		break;
	case ATOM_ARG_PS:
		idx = U8(*ptr);
		(*ptr)++;
		DEBUG("PS[0x%02X]", idx);
		ctx->ps[idx] = cpu_to_le32(val);
		break;
	case ATOM_ARG_WS:
		idx = U8(*ptr);
		(*ptr)++;
		DEBUG("WS[0x%02X]", idx);
		switch (idx) {
		case ATOM_WS_QUOTIENT:
			gctx->divmul[0] = val;
			break;
		case ATOM_WS_REMAINDER:
			gctx->divmul[1] = val;
			break;
		case ATOM_WS_DATAPTR:
			gctx->data_block = val;
			break;
		case ATOM_WS_SHIFT:
			gctx->shift = val;
			break;
		case ATOM_WS_OR_MASK:
		case ATOM_WS_AND_MASK:
			break;
		case ATOM_WS_FB_WINDOW:
			gctx->fb_base = val;
			break;
		case ATOM_WS_ATTRIBUTES:
			gctx->io_attr = val;
			break;
		case ATOM_WS_REGPTR:
			gctx->reg_block = val;
			break;
		default:
			ctx->ws[idx] = val;
		}
		break;
	case ATOM_ARG_FB:
		idx = U8(*ptr);
		(*ptr)++;
		if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
			DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n",
				  gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
		} else
			gctx->scratch[(gctx->fb_base / 4) + idx] = val;
		DEBUG("FB[0x%02X]", idx);
		break;
	case ATOM_ARG_PLL:
		idx = U8(*ptr);
		(*ptr)++;
		DEBUG("PLL[0x%02X]", idx);
		gctx->card->pll_write(gctx->card, idx, val);
		break;
	case ATOM_ARG_MC:
		idx = U8(*ptr);
		(*ptr)++;
		DEBUG("MC[0x%02X]", idx);
		gctx->card->mc_write(gctx->card, idx, val);
		return;
	}
	switch (align) {
	case ATOM_SRC_DWORD:
		DEBUG(".[31:0] <- 0x%08X\n", old_val);
		break;
	case ATOM_SRC_WORD0:
		DEBUG(".[15:0] <- 0x%04X\n", old_val);
		break;
	case ATOM_SRC_WORD8:
		DEBUG(".[23:8] <- 0x%04X\n", old_val);
		break;
	case ATOM_SRC_WORD16:
		DEBUG(".[31:16] <- 0x%04X\n", old_val);
		break;
	case ATOM_SRC_BYTE0:
		DEBUG(".[7:0] <- 0x%02X\n", old_val);
		break;
	case ATOM_SRC_BYTE8:
		DEBUG(".[15:8] <- 0x%02X\n", old_val);
		break;
	case ATOM_SRC_BYTE16:
		DEBUG(".[23:16] <- 0x%02X\n", old_val);
		break;
	case ATOM_SRC_BYTE24:
		DEBUG(".[31:24] <- 0x%02X\n", old_val);
		break;
	}
}
 
static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src, saved;
	int dptr = *ptr;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	SDEBUG("   src: ");
	src = atom_get_src(ctx, attr, ptr);
	dst += src;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src, saved;
	int dptr = *ptr;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	SDEBUG("   src: ");
	src = atom_get_src(ctx, attr, ptr);
	dst &= src;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg)
{
	printk("ATOM BIOS beeped!\n");
}
 
static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
{
	int idx = U8((*ptr)++);
	int r = 0;
 
	if (idx < ATOM_TABLE_NAMES_CNT)
		SDEBUG("   table: %d (%s)\n", idx, atom_table_names[idx]);
	else
		SDEBUG("   table: %d\n", idx);
	if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
		r = atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
	if (r) {
		ctx->abort = true;
	}
}
 
static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t saved;
	int dptr = *ptr;
	attr &= 0x38;
	attr |= atom_def_dst[attr >> 3] << 6;
	atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, 0, saved);
}
 
static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src;
	SDEBUG("   src1: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
	SDEBUG("   src2: ");
	src = atom_get_src(ctx, attr, ptr);
	ctx->ctx->cs_equal = (dst == src);
	ctx->ctx->cs_above = (dst > src);
	SDEBUG("   result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE",
	       ctx->ctx->cs_above ? "GT" : "LE");
}
 
static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
{
	unsigned count = U8((*ptr)++);
	SDEBUG("   count: %d\n", count);
    if (arg == ATOM_UNIT_MICROSEC)
       udelay(count);
    else
		msleep(count);
}
 
static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src;
	SDEBUG("   src1: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
	SDEBUG("   src2: ");
	src = atom_get_src(ctx, attr, ptr);
	if (src != 0) {
		ctx->ctx->divmul[0] = dst / src;
		ctx->ctx->divmul[1] = dst % src;
	} else {
		ctx->ctx->divmul[0] = 0;
		ctx->ctx->divmul[1] = 0;
	}
}
 
static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
{
	/* functionally, a nop */
}
 
static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
{
	int execute = 0, target = U16(*ptr);
	unsigned long cjiffies;
 
	(*ptr) += 2;
	switch (arg) {
	case ATOM_COND_ABOVE:
		execute = ctx->ctx->cs_above;
		break;
	case ATOM_COND_ABOVEOREQUAL:
		execute = ctx->ctx->cs_above || ctx->ctx->cs_equal;
		break;
	case ATOM_COND_ALWAYS:
		execute = 1;
		break;
	case ATOM_COND_BELOW:
		execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal);
		break;
	case ATOM_COND_BELOWOREQUAL:
		execute = !ctx->ctx->cs_above;
		break;
	case ATOM_COND_EQUAL:
		execute = ctx->ctx->cs_equal;
		break;
	case ATOM_COND_NOTEQUAL:
		execute = !ctx->ctx->cs_equal;
		break;
	}
	if (arg != ATOM_COND_ALWAYS)
		SDEBUG("   taken: %s\n", execute ? "yes" : "no");
	SDEBUG("   target: 0x%04X\n", target);
	if (execute) {
		if (ctx->last_jump == (ctx->start + target)) {
			cjiffies = jiffies;
			if (time_after(cjiffies, ctx->last_jump_jiffies)) {
				cjiffies -= ctx->last_jump_jiffies;
				if ((jiffies_to_msecs(cjiffies) > 5000)) {
					DRM_ERROR("atombios stuck in loop for more than 5secs aborting\n");
					ctx->abort = true;
				}
			} else {
				/* jiffies wrap around we will just wait a little longer */
				ctx->last_jump_jiffies = jiffies;
			}
		} else {
			ctx->last_jump = ctx->start + target;
			ctx->last_jump_jiffies = jiffies;
		}
		*ptr = ctx->start + target;
	}
}
 
static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, mask, src, saved;
	int dptr = *ptr;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
	SDEBUG("   mask: 0x%08x", mask);
	SDEBUG("   src: ");
	src = atom_get_src(ctx, attr, ptr);
	dst &= mask;
	dst |= src;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t src, saved;
	int dptr = *ptr;
	if (((attr >> 3) & 7) != ATOM_SRC_DWORD)
		atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
	else {
		atom_skip_dst(ctx, arg, attr, ptr);
		saved = 0xCDCDCDCD;
	}
	SDEBUG("   src: ");
	src = atom_get_src(ctx, attr, ptr);
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, src, saved);
}
 
static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src;
	SDEBUG("   src1: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
	SDEBUG("   src2: ");
	src = atom_get_src(ctx, attr, ptr);
	ctx->ctx->divmul[0] = dst * src;
}
 
static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg)
{
	/* nothing */
}
 
static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src, saved;
	int dptr = *ptr;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	SDEBUG("   src: ");
	src = atom_get_src(ctx, attr, ptr);
	dst |= src;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t val = U8((*ptr)++);
	SDEBUG("POST card output: 0x%02X\n", val);
}
 
static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg)
{
	printk(KERN_INFO "unimplemented!\n");
}
 
static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg)
{
	printk(KERN_INFO "unimplemented!\n");
}
 
static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg)
{
	printk(KERN_INFO "unimplemented!\n");
}
 
static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg)
{
	int idx = U8(*ptr);
	(*ptr)++;
	SDEBUG("   block: %d\n", idx);
	if (!idx)
		ctx->ctx->data_block = 0;
	else if (idx == 255)
		ctx->ctx->data_block = ctx->start;
	else
		ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx);
	SDEBUG("   base: 0x%04X\n", ctx->ctx->data_block);
}
 
static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	SDEBUG("   fb_base: ");
	ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr);
}
 
static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg)
{
	int port;
	switch (arg) {
	case ATOM_PORT_ATI:
		port = U16(*ptr);
		if (port < ATOM_IO_NAMES_CNT)
			SDEBUG("   port: %d (%s)\n", port, atom_io_names[port]);
		else
			SDEBUG("   port: %d\n", port);
		if (!port)
			ctx->ctx->io_mode = ATOM_IO_MM;
		else
			ctx->ctx->io_mode = ATOM_IO_IIO | port;
		(*ptr) += 2;
		break;
	case ATOM_PORT_PCI:
		ctx->ctx->io_mode = ATOM_IO_PCI;
		(*ptr)++;
		break;
	case ATOM_PORT_SYSIO:
		ctx->ctx->io_mode = ATOM_IO_SYSIO;
		(*ptr)++;
		break;
	}
}
 
static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
{
	ctx->ctx->reg_block = U16(*ptr);
	(*ptr) += 2;
	SDEBUG("   base: 0x%04X\n", ctx->ctx->reg_block);
}
 
static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++), shift;
	uint32_t saved, dst;
	int dptr = *ptr;
	attr &= 0x38;
	attr |= atom_def_dst[attr >> 3] << 6;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
	SDEBUG("   shift: %d\n", shift);
	dst <<= shift;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++), shift;
	uint32_t saved, dst;
	int dptr = *ptr;
	attr &= 0x38;
	attr |= atom_def_dst[attr >> 3] << 6;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
	SDEBUG("   shift: %d\n", shift);
	dst >>= shift;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++), shift;
	uint32_t saved, dst;
	int dptr = *ptr;
	uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	/* op needs to full dst value */
	dst = saved;
	shift = atom_get_src(ctx, attr, ptr);
	SDEBUG("   shift: %d\n", shift);
	dst <<= shift;
	dst &= atom_arg_mask[dst_align];
	dst >>= atom_arg_shift[dst_align];
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++), shift;
	uint32_t saved, dst;
	int dptr = *ptr;
	uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	/* op needs to full dst value */
	dst = saved;
	shift = atom_get_src(ctx, attr, ptr);
	SDEBUG("   shift: %d\n", shift);
	dst >>= shift;
	dst &= atom_arg_mask[dst_align];
	dst >>= atom_arg_shift[dst_align];
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src, saved;
	int dptr = *ptr;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	SDEBUG("   src: ");
	src = atom_get_src(ctx, attr, ptr);
	dst -= src;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t src, val, target;
	SDEBUG("   switch: ");
	src = atom_get_src(ctx, attr, ptr);
	while (U16(*ptr) != ATOM_CASE_END)
		if (U8(*ptr) == ATOM_CASE_MAGIC) {
			(*ptr)++;
			SDEBUG("   case: ");
			val =
			    atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM,
					 ptr);
			target = U16(*ptr);
			if (val == src) {
				SDEBUG("   target: %04X\n", target);
				*ptr = ctx->start + target;
				return;
			}
			(*ptr) += 2;
		} else {
			printk(KERN_INFO "Bad case.\n");
			return;
		}
	(*ptr) += 2;
}
 
static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src;
	SDEBUG("   src1: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
	SDEBUG("   src2: ");
	src = atom_get_src(ctx, attr, ptr);
	ctx->ctx->cs_equal = ((dst & src) == 0);
	SDEBUG("   result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE");
}
 
static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src, saved;
	int dptr = *ptr;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	SDEBUG("   src: ");
	src = atom_get_src(ctx, attr, ptr);
	dst ^= src;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg)
{
	printk(KERN_INFO "unimplemented!\n");
}
 
static struct {
	void (*func) (atom_exec_context *, int *, int);
	int arg;
} opcode_table[ATOM_OP_CNT] = {
	{
	NULL, 0}, {
	atom_op_move, ATOM_ARG_REG}, {
	atom_op_move, ATOM_ARG_PS}, {
	atom_op_move, ATOM_ARG_WS}, {
	atom_op_move, ATOM_ARG_FB}, {
	atom_op_move, ATOM_ARG_PLL}, {
	atom_op_move, ATOM_ARG_MC}, {
	atom_op_and, ATOM_ARG_REG}, {
	atom_op_and, ATOM_ARG_PS}, {
	atom_op_and, ATOM_ARG_WS}, {
	atom_op_and, ATOM_ARG_FB}, {
	atom_op_and, ATOM_ARG_PLL}, {
	atom_op_and, ATOM_ARG_MC}, {
	atom_op_or, ATOM_ARG_REG}, {
	atom_op_or, ATOM_ARG_PS}, {
	atom_op_or, ATOM_ARG_WS}, {
	atom_op_or, ATOM_ARG_FB}, {
	atom_op_or, ATOM_ARG_PLL}, {
	atom_op_or, ATOM_ARG_MC}, {
	atom_op_shift_left, ATOM_ARG_REG}, {
	atom_op_shift_left, ATOM_ARG_PS}, {
	atom_op_shift_left, ATOM_ARG_WS}, {
	atom_op_shift_left, ATOM_ARG_FB}, {
	atom_op_shift_left, ATOM_ARG_PLL}, {
	atom_op_shift_left, ATOM_ARG_MC}, {
	atom_op_shift_right, ATOM_ARG_REG}, {
	atom_op_shift_right, ATOM_ARG_PS}, {
	atom_op_shift_right, ATOM_ARG_WS}, {
	atom_op_shift_right, ATOM_ARG_FB}, {
	atom_op_shift_right, ATOM_ARG_PLL}, {
	atom_op_shift_right, ATOM_ARG_MC}, {
	atom_op_mul, ATOM_ARG_REG}, {
	atom_op_mul, ATOM_ARG_PS}, {
	atom_op_mul, ATOM_ARG_WS}, {
	atom_op_mul, ATOM_ARG_FB}, {
	atom_op_mul, ATOM_ARG_PLL}, {
	atom_op_mul, ATOM_ARG_MC}, {
	atom_op_div, ATOM_ARG_REG}, {
	atom_op_div, ATOM_ARG_PS}, {
	atom_op_div, ATOM_ARG_WS}, {
	atom_op_div, ATOM_ARG_FB}, {
	atom_op_div, ATOM_ARG_PLL}, {
	atom_op_div, ATOM_ARG_MC}, {
	atom_op_add, ATOM_ARG_REG}, {
	atom_op_add, ATOM_ARG_PS}, {
	atom_op_add, ATOM_ARG_WS}, {
	atom_op_add, ATOM_ARG_FB}, {
	atom_op_add, ATOM_ARG_PLL}, {
	atom_op_add, ATOM_ARG_MC}, {
	atom_op_sub, ATOM_ARG_REG}, {
	atom_op_sub, ATOM_ARG_PS}, {
	atom_op_sub, ATOM_ARG_WS}, {
	atom_op_sub, ATOM_ARG_FB}, {
	atom_op_sub, ATOM_ARG_PLL}, {
	atom_op_sub, ATOM_ARG_MC}, {
	atom_op_setport, ATOM_PORT_ATI}, {
	atom_op_setport, ATOM_PORT_PCI}, {
	atom_op_setport, ATOM_PORT_SYSIO}, {
	atom_op_setregblock, 0}, {
	atom_op_setfbbase, 0}, {
	atom_op_compare, ATOM_ARG_REG}, {
	atom_op_compare, ATOM_ARG_PS}, {
	atom_op_compare, ATOM_ARG_WS}, {
	atom_op_compare, ATOM_ARG_FB}, {
	atom_op_compare, ATOM_ARG_PLL}, {
	atom_op_compare, ATOM_ARG_MC}, {
	atom_op_switch, 0}, {
	atom_op_jump, ATOM_COND_ALWAYS}, {
	atom_op_jump, ATOM_COND_EQUAL}, {
	atom_op_jump, ATOM_COND_BELOW}, {
	atom_op_jump, ATOM_COND_ABOVE}, {
	atom_op_jump, ATOM_COND_BELOWOREQUAL}, {
	atom_op_jump, ATOM_COND_ABOVEOREQUAL}, {
	atom_op_jump, ATOM_COND_NOTEQUAL}, {
	atom_op_test, ATOM_ARG_REG}, {
	atom_op_test, ATOM_ARG_PS}, {
	atom_op_test, ATOM_ARG_WS}, {
	atom_op_test, ATOM_ARG_FB}, {
	atom_op_test, ATOM_ARG_PLL}, {
	atom_op_test, ATOM_ARG_MC}, {
	atom_op_delay, ATOM_UNIT_MILLISEC}, {
	atom_op_delay, ATOM_UNIT_MICROSEC}, {
	atom_op_calltable, 0}, {
	atom_op_repeat, 0}, {
	atom_op_clear, ATOM_ARG_REG}, {
	atom_op_clear, ATOM_ARG_PS}, {
	atom_op_clear, ATOM_ARG_WS}, {
	atom_op_clear, ATOM_ARG_FB}, {
	atom_op_clear, ATOM_ARG_PLL}, {
	atom_op_clear, ATOM_ARG_MC}, {
	atom_op_nop, 0}, {
	atom_op_eot, 0}, {
	atom_op_mask, ATOM_ARG_REG}, {
	atom_op_mask, ATOM_ARG_PS}, {
	atom_op_mask, ATOM_ARG_WS}, {
	atom_op_mask, ATOM_ARG_FB}, {
	atom_op_mask, ATOM_ARG_PLL}, {
	atom_op_mask, ATOM_ARG_MC}, {
	atom_op_postcard, 0}, {
	atom_op_beep, 0}, {
	atom_op_savereg, 0}, {
	atom_op_restorereg, 0}, {
	atom_op_setdatablock, 0}, {
	atom_op_xor, ATOM_ARG_REG}, {
	atom_op_xor, ATOM_ARG_PS}, {
	atom_op_xor, ATOM_ARG_WS}, {
	atom_op_xor, ATOM_ARG_FB}, {
	atom_op_xor, ATOM_ARG_PLL}, {
	atom_op_xor, ATOM_ARG_MC}, {
	atom_op_shl, ATOM_ARG_REG}, {
	atom_op_shl, ATOM_ARG_PS}, {
	atom_op_shl, ATOM_ARG_WS}, {
	atom_op_shl, ATOM_ARG_FB}, {
	atom_op_shl, ATOM_ARG_PLL}, {
	atom_op_shl, ATOM_ARG_MC}, {
	atom_op_shr, ATOM_ARG_REG}, {
	atom_op_shr, ATOM_ARG_PS}, {
	atom_op_shr, ATOM_ARG_WS}, {
	atom_op_shr, ATOM_ARG_FB}, {
	atom_op_shr, ATOM_ARG_PLL}, {
	atom_op_shr, ATOM_ARG_MC}, {
atom_op_debug, 0},};
 
static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
{
	int base = CU16(ctx->cmd_table + 4 + 2 * index);
	int len, ws, ps, ptr;
	unsigned char op;
	atom_exec_context ectx;
	int ret = 0;
 
	if (!base)
		return -EINVAL;
 
	len = CU16(base + ATOM_CT_SIZE_PTR);
	ws = CU8(base + ATOM_CT_WS_PTR);
	ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK;
	ptr = base + ATOM_CT_CODE_PTR;
 
	SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
 
	ectx.ctx = ctx;
	ectx.ps_shift = ps / 4;
	ectx.start = base;
	ectx.ps = params;
	ectx.abort = false;
	ectx.last_jump = 0;
	if (ws)
		ectx.ws = kzalloc(4 * ws, GFP_KERNEL);
	else
		ectx.ws = NULL;
 
	debug_depth++;
	while (1) {
		op = CU8(ptr++);
		if (op < ATOM_OP_NAMES_CNT)
			SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1);
		else
			SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1);
		if (ectx.abort) {
			DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n",
				base, len, ws, ps, ptr - 1);
			ret = -EINVAL;
			goto free;
		}
 
		if (op < ATOM_OP_CNT && op > 0)
			opcode_table[op].func(&ectx, &ptr,
					      opcode_table[op].arg);
		else
			break;
 
		if (op == ATOM_OP_EOT)
			break;
	}
	debug_depth--;
	SDEBUG("<<\n");
 
free:
	if (ws)
		kfree(ectx.ws);
	return ret;
}
 
int atom_execute_table_scratch_unlocked(struct atom_context *ctx, int index, uint32_t * params)
{
	int r;
 
	mutex_lock(&ctx->mutex);
	/* reset data block */
	ctx->data_block = 0;
	/* reset reg block */
	ctx->reg_block = 0;
	/* reset fb window */
	ctx->fb_base = 0;
	/* reset io mode */
	ctx->io_mode = ATOM_IO_MM;
	/* reset divmul */
	ctx->divmul[0] = 0;
	ctx->divmul[1] = 0;
	r = atom_execute_table_locked(ctx, index, params);
	mutex_unlock(&ctx->mutex);
	return r;
}
 
int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
{
	int r;
	mutex_lock(&ctx->scratch_mutex);
	r = atom_execute_table_scratch_unlocked(ctx, index, params);
	mutex_unlock(&ctx->scratch_mutex);
	return r;
}
 
static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
 
static void atom_index_iio(struct atom_context *ctx, int base)
{
	ctx->iio = kzalloc(2 * 256, GFP_KERNEL);
	if (!ctx->iio)
		return;
	while (CU8(base) == ATOM_IIO_START) {
		ctx->iio[CU8(base + 1)] = base + 2;
		base += 2;
		while (CU8(base) != ATOM_IIO_END)
			base += atom_iio_len[CU8(base)];
		base += 3;
	}
}
 
struct atom_context *atom_parse(struct card_info *card, void *bios)
{
	int base;
	struct atom_context *ctx =
	    kzalloc(sizeof(struct atom_context), GFP_KERNEL);
	char *str;
	char name[512];
	int i;
 
	if (!ctx)
		return NULL;
 
	ctx->card = card;
	ctx->bios = bios;
 
	if (CU16(0) != ATOM_BIOS_MAGIC) {
		printk(KERN_INFO "Invalid BIOS magic.\n");
		kfree(ctx);
		return NULL;
	}
	if (strncmp
	    (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC,
	     strlen(ATOM_ATI_MAGIC))) {
		printk(KERN_INFO "Invalid ATI magic.\n");
		kfree(ctx);
		return NULL;
	}
 
	base = CU16(ATOM_ROM_TABLE_PTR);
	if (strncmp
	    (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC,
	     strlen(ATOM_ROM_MAGIC))) {
		printk(KERN_INFO "Invalid ATOM magic.\n");
		kfree(ctx);
		return NULL;
	}
 
	ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR);
	ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR);
	atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4);
	if (!ctx->iio) {
		atom_destroy(ctx);
		return NULL;
	}
 
	str = CSTR(CU16(base + ATOM_ROM_MSG_PTR));
	while (*str && ((*str == '\n') || (*str == '\r')))
		str++;
	/* name string isn't always 0 terminated */
	for (i = 0; i < 511; i++) {
		name[i] = str[i];
		if (name[i] < '.' || name[i] > 'z') {
			name[i] = 0;
			break;
		}
	}
	printk(KERN_INFO "ATOM BIOS: %s\n", name);
 
	return ctx;
}
 
int atom_asic_init(struct atom_context *ctx)
{
	struct radeon_device *rdev = ctx->card->dev->dev_private;
	int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR);
	uint32_t ps[16];
	int ret;
 
	memset(ps, 0, 64);
 
	ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR));
	ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR));
	if (!ps[0] || !ps[1])
		return 1;
 
	if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT))
		return 1;
	ret = atom_execute_table(ctx, ATOM_CMD_INIT, ps);
	if (ret)
		return ret;
 
	memset(ps, 0, 64);
 
	if (rdev->family < CHIP_R600) {
		if (CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_SPDFANCNTL))
			atom_execute_table(ctx, ATOM_CMD_SPDFANCNTL, ps);
	}
	return ret;
}
 
void atom_destroy(struct atom_context *ctx)
{
	kfree(ctx->iio);
	kfree(ctx);
}
 
bool atom_parse_data_header(struct atom_context *ctx, int index,
			    uint16_t * size, uint8_t * frev, uint8_t * crev,
			    uint16_t * data_start)
{
	int offset = index * 2 + 4;
	int idx = CU16(ctx->data_table + offset);
	u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4);
 
	if (!mdt[index])
		return false;
 
	if (size)
		*size = CU16(idx);
	if (frev)
		*frev = CU8(idx + 2);
	if (crev)
		*crev = CU8(idx + 3);
	*data_start = idx;
	return true;
}
 
bool atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev,
			   uint8_t * crev)
{
	int offset = index * 2 + 4;
	int idx = CU16(ctx->cmd_table + offset);
	u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4);
 
	if (!mct[index])
		return false;
 
	if (frev)
		*frev = CU8(idx + 2);
	if (crev)
		*crev = CU8(idx + 3);
	return true;
}
 
int atom_allocate_fb_scratch(struct atom_context *ctx)
{
	int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
	uint16_t data_offset;
	int usage_bytes = 0;
	struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
 
	if (atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
	firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
 
	DRM_DEBUG("atom firmware requested %08x %dkb\n",
			  le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
			  le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
 
		usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
	}
	ctx->scratch_size_bytes = 0;
	if (usage_bytes == 0)
		usage_bytes = 20 * 1024;
	/* allocate some scratch memory */
	ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
	if (!ctx->scratch)
		return -ENOMEM;
	ctx->scratch_size_bytes = usage_bytes;
	return 0;
}
 
free:
>
 
free:
>
>
>
>
>
>
>
>
>

Rev 5078	Rev 5271
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice shall be included in	11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.	12	* all copies or substantial portions of the Software.
13	*	13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.	20	* OTHER DEALINGS IN THE SOFTWARE.
21	*	21	*
22	* Author: Stanislaw Skowronek	22	* Author: Stanislaw Skowronek
23	*/	23	*/
24		24
25	#include	25	#include
26	#include	26	#include
27	#include	27	#include
28	#include	28	#include
29		29
30	#define ATOM_DEBUG	30	#define ATOM_DEBUG
31		31
32	#include "atom.h"	32	#include "atom.h"
33	#include "atom-names.h"	33	#include "atom-names.h"
34	#include "atom-bits.h"	34	#include "atom-bits.h"
35	#include "radeon.h"	35	#include "radeon.h"
36		36
37	#define ATOM_COND_ABOVE 0	37	#define ATOM_COND_ABOVE 0
38	#define ATOM_COND_ABOVEOREQUAL 1	38	#define ATOM_COND_ABOVEOREQUAL 1
39	#define ATOM_COND_ALWAYS 2	39	#define ATOM_COND_ALWAYS 2
40	#define ATOM_COND_BELOW 3	40	#define ATOM_COND_BELOW 3
41	#define ATOM_COND_BELOWOREQUAL 4	41	#define ATOM_COND_BELOWOREQUAL 4
42	#define ATOM_COND_EQUAL 5	42	#define ATOM_COND_EQUAL 5
43	#define ATOM_COND_NOTEQUAL 6	43	#define ATOM_COND_NOTEQUAL 6
44		44
45	#define ATOM_PORT_ATI 0	45	#define ATOM_PORT_ATI 0
46	#define ATOM_PORT_PCI 1	46	#define ATOM_PORT_PCI 1
47	#define ATOM_PORT_SYSIO 2	47	#define ATOM_PORT_SYSIO 2
48		48
49	#define ATOM_UNIT_MICROSEC 0	49	#define ATOM_UNIT_MICROSEC 0
50	#define ATOM_UNIT_MILLISEC 1	50	#define ATOM_UNIT_MILLISEC 1
51		51
52	#define PLL_INDEX 2	52	#define PLL_INDEX 2
53	#define PLL_DATA 3	53	#define PLL_DATA 3
54		54
55	typedef struct {	55	typedef struct {
56	struct atom_context *ctx;	56	struct atom_context *ctx;
57	uint32_t ps, ws;	57	uint32_t ps, ws;
58	int ps_shift;	58	int ps_shift;
59	uint16_t start;	59	uint16_t start;
60	unsigned last_jump;	60	unsigned last_jump;
61	unsigned long last_jump_jiffies;	61	unsigned long last_jump_jiffies;
62	bool abort;	62	bool abort;
63	} atom_exec_context;	63	} atom_exec_context;
64		64
65	int atom_debug = 0;	65	int atom_debug = 0;
66	static int atom_execute_table_locked(struct atom_context ctx, int index, uint32_t params);	66	static int atom_execute_table_locked(struct atom_context ctx, int index, uint32_t params);
67	int atom_execute_table(struct atom_context ctx, int index, uint32_t params);	67	int atom_execute_table(struct atom_context ctx, int index, uint32_t params);
68		68
69	static uint32_t atom_arg_mask[8] =	69	static uint32_t atom_arg_mask[8] =
70	{ 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,	70	{ 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
71	0xFF000000 };	71	0xFF000000 };
72	static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };	72	static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
73		73
74	static int atom_dst_to_src[8][4] = {	74	static int atom_dst_to_src[8][4] = {
75	/* translate destination alignment field to the source alignment encoding */	75	/* translate destination alignment field to the source alignment encoding */
76	{0, 0, 0, 0},	76	{0, 0, 0, 0},
77	{1, 2, 3, 0},	77	{1, 2, 3, 0},
78	{1, 2, 3, 0},	78	{1, 2, 3, 0},
79	{1, 2, 3, 0},	79	{1, 2, 3, 0},
80	{4, 5, 6, 7},	80	{4, 5, 6, 7},
81	{4, 5, 6, 7},	81	{4, 5, 6, 7},
82	{4, 5, 6, 7},	82	{4, 5, 6, 7},
83	{4, 5, 6, 7},	83	{4, 5, 6, 7},
84	};	84	};
85	static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };	85	static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
86		86
87	static int debug_depth = 0;	87	static int debug_depth = 0;
88	#ifdef ATOM_DEBUG	88	#ifdef ATOM_DEBUG
89	static void debug_print_spaces(int n)	89	static void debug_print_spaces(int n)
90	{	90	{
91	while (n--)	91	while (n--)
92	printk(" ");	92	printk(" ");
93	}	93	}
94		94
95	#define DEBUG(...) do if (atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)	95	#define DEBUG(...) do if (atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)
96	#define SDEBUG(...) do if (atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)	96	#define SDEBUG(...) do if (atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)
97	#else	97	#else
98	#define DEBUG(...) do { } while (0)	98	#define DEBUG(...) do { } while (0)
99	#define SDEBUG(...) do { } while (0)	99	#define SDEBUG(...) do { } while (0)
100	#endif	100	#endif
101		101
102	static uint32_t atom_iio_execute(struct atom_context *ctx, int base,	102	static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
103	uint32_t index, uint32_t data)	103	uint32_t index, uint32_t data)
104	{	104	{
105	struct radeon_device *rdev = ctx->card->dev->dev_private;	105	struct radeon_device *rdev = ctx->card->dev->dev_private;
106	uint32_t temp = 0xCDCDCDCD;	106	uint32_t temp = 0xCDCDCDCD;
107		107
108	while (1)	108	while (1)
109	switch (CU8(base)) {	109	switch (CU8(base)) {
110	case ATOM_IIO_NOP:	110	case ATOM_IIO_NOP:
111	base++;	111	base++;
112	break;	112	break;
113	case ATOM_IIO_READ:	113	case ATOM_IIO_READ:
114	temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1));	114	temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1));
115	base += 3;	115	base += 3;
116	break;	116	break;
117	case ATOM_IIO_WRITE:	117	case ATOM_IIO_WRITE:
118	if (rdev->family == CHIP_RV515)	118	if (rdev->family == CHIP_RV515)
119	(void)ctx->card->ioreg_read(ctx->card, CU16(base + 1));	119	(void)ctx->card->ioreg_read(ctx->card, CU16(base + 1));
120	ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp);	120	ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp);
121	base += 3;	121	base += 3;
122	break;	122	break;
123	case ATOM_IIO_CLEAR:	123	case ATOM_IIO_CLEAR:
124	temp &=	124	temp &=
125	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<	125	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
126	CU8(base + 2));	126	CU8(base + 2));
127	base += 3;	127	base += 3;
128	break;	128	break;
129	case ATOM_IIO_SET:	129	case ATOM_IIO_SET:
130	temp \|=	130	temp \|=
131	(0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +	131	(0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +
132	2);	132	2);
133	base += 3;	133	base += 3;
134	break;	134	break;
135	case ATOM_IIO_MOVE_INDEX:	135	case ATOM_IIO_MOVE_INDEX:
136	temp &=	136	temp &=
137	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<	137	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
138	CU8(base + 3));	138	CU8(base + 3));
139	temp \|=	139	temp \|=
140	((index >> CU8(base + 2)) &	140	((index >> CU8(base + 2)) &
141	(0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +	141	(0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
142	3);	142	3);
143	base += 4;	143	base += 4;
144	break;	144	break;
145	case ATOM_IIO_MOVE_DATA:	145	case ATOM_IIO_MOVE_DATA:
146	temp &=	146	temp &=
147	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<	147	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
148	CU8(base + 3));	148	CU8(base + 3));
149	temp \|=	149	temp \|=
150	((data >> CU8(base + 2)) &	150	((data >> CU8(base + 2)) &
151	(0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +	151	(0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
152	3);	152	3);
153	base += 4;	153	base += 4;
154	break;	154	break;
155	case ATOM_IIO_MOVE_ATTR:	155	case ATOM_IIO_MOVE_ATTR:
156	temp &=	156	temp &=
157	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<	157	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
158	CU8(base + 3));	158	CU8(base + 3));
159	temp \|=	159	temp \|=
160	((ctx->	160	((ctx->
161	io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -	161	io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -
162	CU8	162	CU8
163	(base	163	(base
164	+	164	+
165	1))))	165	1))))
166	<< CU8(base + 3);	166	<< CU8(base + 3);
167	base += 4;	167	base += 4;
168	break;	168	break;
169	case ATOM_IIO_END:	169	case ATOM_IIO_END:
170	return temp;	170	return temp;
171	default:	171	default:
172	printk(KERN_INFO "Unknown IIO opcode.\n");	172	printk(KERN_INFO "Unknown IIO opcode.\n");
173	return 0;	173	return 0;
174	}	174	}
175	}	175	}
176		176
177	static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,	177	static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
178	int ptr, uint32_t saved, int print)	178	int ptr, uint32_t saved, int print)
179	{	179	{
180	uint32_t idx, val = 0xCDCDCDCD, align, arg;	180	uint32_t idx, val = 0xCDCDCDCD, align, arg;
181	struct atom_context *gctx = ctx->ctx;	181	struct atom_context *gctx = ctx->ctx;
182	arg = attr & 7;	182	arg = attr & 7;
183	align = (attr >> 3) & 7;	183	align = (attr >> 3) & 7;
184	switch (arg) {	184	switch (arg) {
185	case ATOM_ARG_REG:	185	case ATOM_ARG_REG:
186	idx = U16(*ptr);	186	idx = U16(*ptr);
187	(*ptr) += 2;	187	(*ptr) += 2;
188	if (print)	188	if (print)
189	DEBUG("REG[0x%04X]", idx);	189	DEBUG("REG[0x%04X]", idx);
190	idx += gctx->reg_block;	190	idx += gctx->reg_block;
191	switch (gctx->io_mode) {	191	switch (gctx->io_mode) {
192	case ATOM_IO_MM:	192	case ATOM_IO_MM:
193	val = gctx->card->reg_read(gctx->card, idx);	193	val = gctx->card->reg_read(gctx->card, idx);
194	break;	194	break;
195	case ATOM_IO_PCI:	195	case ATOM_IO_PCI:
196	printk(KERN_INFO	196	printk(KERN_INFO
197	"PCI registers are not implemented.\n");	197	"PCI registers are not implemented.\n");
198	return 0;	198	return 0;
199	case ATOM_IO_SYSIO:	199	case ATOM_IO_SYSIO:
200	printk(KERN_INFO	200	printk(KERN_INFO
201	"SYSIO registers are not implemented.\n");	201	"SYSIO registers are not implemented.\n");
202	return 0;	202	return 0;
203	default:	203	default:
204	if (!(gctx->io_mode & 0x80)) {	204	if (!(gctx->io_mode & 0x80)) {
205	printk(KERN_INFO "Bad IO mode.\n");	205	printk(KERN_INFO "Bad IO mode.\n");
206	return 0;	206	return 0;
207	}	207	}
208	if (!gctx->iio[gctx->io_mode & 0x7F]) {	208	if (!gctx->iio[gctx->io_mode & 0x7F]) {
209	printk(KERN_INFO	209	printk(KERN_INFO
210	"Undefined indirect IO read method %d.\n",	210	"Undefined indirect IO read method %d.\n",
211	gctx->io_mode & 0x7F);	211	gctx->io_mode & 0x7F);
212	return 0;	212	return 0;
213	}	213	}
214	val =	214	val =
215	atom_iio_execute(gctx,	215	atom_iio_execute(gctx,
216	gctx->iio[gctx->io_mode & 0x7F],	216	gctx->iio[gctx->io_mode & 0x7F],
217	idx, 0);	217	idx, 0);
218	}	218	}
219	break;	219	break;
220	case ATOM_ARG_PS:	220	case ATOM_ARG_PS:
221	idx = U8(*ptr);	221	idx = U8(*ptr);
222	(*ptr)++;	222	(*ptr)++;
223	/* get_unaligned_le32 avoids unaligned accesses from atombios	223	/* get_unaligned_le32 avoids unaligned accesses from atombios
224	* tables, noticed on a DEC Alpha. */	224	* tables, noticed on a DEC Alpha. */
225	val = get_unaligned_le32((u32 *)&ctx->ps[idx]);	225	val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
226	if (print)	226	if (print)
227	DEBUG("PS[0x%02X,0x%04X]", idx, val);	227	DEBUG("PS[0x%02X,0x%04X]", idx, val);
228	break;	228	break;
229	case ATOM_ARG_WS:	229	case ATOM_ARG_WS:
230	idx = U8(*ptr);	230	idx = U8(*ptr);
231	(*ptr)++;	231	(*ptr)++;
232	if (print)	232	if (print)
233	DEBUG("WS[0x%02X]", idx);	233	DEBUG("WS[0x%02X]", idx);
234	switch (idx) {	234	switch (idx) {
235	case ATOM_WS_QUOTIENT:	235	case ATOM_WS_QUOTIENT:
236	val = gctx->divmul[0];	236	val = gctx->divmul[0];
237	break;	237	break;
238	case ATOM_WS_REMAINDER:	238	case ATOM_WS_REMAINDER:
239	val = gctx->divmul[1];	239	val = gctx->divmul[1];
240	break;	240	break;
241	case ATOM_WS_DATAPTR:	241	case ATOM_WS_DATAPTR:
242	val = gctx->data_block;	242	val = gctx->data_block;
243	break;	243	break;
244	case ATOM_WS_SHIFT:	244	case ATOM_WS_SHIFT:
245	val = gctx->shift;	245	val = gctx->shift;
246	break;	246	break;
247	case ATOM_WS_OR_MASK:	247	case ATOM_WS_OR_MASK:
248	val = 1 << gctx->shift;	248	val = 1 << gctx->shift;
249	break;	249	break;
250	case ATOM_WS_AND_MASK:	250	case ATOM_WS_AND_MASK:
251	val = ~(1 << gctx->shift);	251	val = ~(1 << gctx->shift);
252	break;	252	break;
253	case ATOM_WS_FB_WINDOW:	253	case ATOM_WS_FB_WINDOW:
254	val = gctx->fb_base;	254	val = gctx->fb_base;
255	break;	255	break;
256	case ATOM_WS_ATTRIBUTES:	256	case ATOM_WS_ATTRIBUTES:
257	val = gctx->io_attr;	257	val = gctx->io_attr;
258	break;	258	break;
259	case ATOM_WS_REGPTR:	259	case ATOM_WS_REGPTR:
260	val = gctx->reg_block;	260	val = gctx->reg_block;
261	break;	261	break;
262	default:	262	default:
263	val = ctx->ws[idx];	263	val = ctx->ws[idx];
264	}	264	}
265	break;	265	break;
266	case ATOM_ARG_ID:	266	case ATOM_ARG_ID:
267	idx = U16(*ptr);	267	idx = U16(*ptr);
268	(*ptr) += 2;	268	(*ptr) += 2;
269	if (print) {	269	if (print) {
270	if (gctx->data_block)	270	if (gctx->data_block)
271	DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);	271	DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);
272	else	272	else
273	DEBUG("ID[0x%04X]", idx);	273	DEBUG("ID[0x%04X]", idx);
274	}	274	}
275	val = U32(idx + gctx->data_block);	275	val = U32(idx + gctx->data_block);
276	break;	276	break;
277	case ATOM_ARG_FB:	277	case ATOM_ARG_FB:
278	idx = U8(*ptr);	278	idx = U8(*ptr);
279	(*ptr)++;	279	(*ptr)++;
280	if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {	280	if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
281	DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n",	281	DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n",
282	gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);	282	gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
283	val = 0;	283	val = 0;
284	} else	284	} else
285	val = gctx->scratch[(gctx->fb_base / 4) + idx];	285	val = gctx->scratch[(gctx->fb_base / 4) + idx];
286	if (print)	286	if (print)
287	DEBUG("FB[0x%02X]", idx);	287	DEBUG("FB[0x%02X]", idx);
288	break;	288	break;
289	case ATOM_ARG_IMM:	289	case ATOM_ARG_IMM:
290	switch (align) {	290	switch (align) {
291	case ATOM_SRC_DWORD:	291	case ATOM_SRC_DWORD:
292	val = U32(*ptr);	292	val = U32(*ptr);
293	(*ptr) += 4;	293	(*ptr) += 4;
294	if (print)	294	if (print)
295	DEBUG("IMM 0x%08X\n", val);	295	DEBUG("IMM 0x%08X\n", val);
296	return val;	296	return val;
297	case ATOM_SRC_WORD0:	297	case ATOM_SRC_WORD0:
298	case ATOM_SRC_WORD8:	298	case ATOM_SRC_WORD8:
299	case ATOM_SRC_WORD16:	299	case ATOM_SRC_WORD16:
300	val = U16(*ptr);	300	val = U16(*ptr);
301	(*ptr) += 2;	301	(*ptr) += 2;
302	if (print)	302	if (print)
303	DEBUG("IMM 0x%04X\n", val);	303	DEBUG("IMM 0x%04X\n", val);
304	return val;	304	return val;
305	case ATOM_SRC_BYTE0:	305	case ATOM_SRC_BYTE0:
306	case ATOM_SRC_BYTE8:	306	case ATOM_SRC_BYTE8:
307	case ATOM_SRC_BYTE16:	307	case ATOM_SRC_BYTE16:
308	case ATOM_SRC_BYTE24:	308	case ATOM_SRC_BYTE24:
309	val = U8(*ptr);	309	val = U8(*ptr);
310	(*ptr)++;	310	(*ptr)++;
311	if (print)	311	if (print)
312	DEBUG("IMM 0x%02X\n", val);	312	DEBUG("IMM 0x%02X\n", val);
313	return val;	313	return val;
314	}	314	}
315	return 0;	315	return 0;
316	case ATOM_ARG_PLL:	316	case ATOM_ARG_PLL:
317	idx = U8(*ptr);	317	idx = U8(*ptr);
318	(*ptr)++;	318	(*ptr)++;
319	if (print)	319	if (print)
320	DEBUG("PLL[0x%02X]", idx);	320	DEBUG("PLL[0x%02X]", idx);
321	val = gctx->card->pll_read(gctx->card, idx);	321	val = gctx->card->pll_read(gctx->card, idx);
322	break;	322	break;
323	case ATOM_ARG_MC:	323	case ATOM_ARG_MC:
324	idx = U8(*ptr);	324	idx = U8(*ptr);
325	(*ptr)++;	325	(*ptr)++;
326	if (print)	326	if (print)
327	DEBUG("MC[0x%02X]", idx);	327	DEBUG("MC[0x%02X]", idx);
328	val = gctx->card->mc_read(gctx->card, idx);	328	val = gctx->card->mc_read(gctx->card, idx);
329	break;	329	break;
330	}	330	}
331	if (saved)	331	if (saved)
332	*saved = val;	332	*saved = val;
333	val &= atom_arg_mask[align];	333	val &= atom_arg_mask[align];
334	val >>= atom_arg_shift[align];	334	val >>= atom_arg_shift[align];
335	if (print)	335	if (print)
336	switch (align) {	336	switch (align) {
337	case ATOM_SRC_DWORD:	337	case ATOM_SRC_DWORD:
338	DEBUG(".[31:0] -> 0x%08X\n", val);	338	DEBUG(".[31:0] -> 0x%08X\n", val);
339	break;	339	break;
340	case ATOM_SRC_WORD0:	340	case ATOM_SRC_WORD0:
341	DEBUG(".[15:0] -> 0x%04X\n", val);	341	DEBUG(".[15:0] -> 0x%04X\n", val);
342	break;	342	break;
343	case ATOM_SRC_WORD8:	343	case ATOM_SRC_WORD8:
344	DEBUG(".[23:8] -> 0x%04X\n", val);	344	DEBUG(".[23:8] -> 0x%04X\n", val);
345	break;	345	break;
346	case ATOM_SRC_WORD16:	346	case ATOM_SRC_WORD16:
347	DEBUG(".[31:16] -> 0x%04X\n", val);	347	DEBUG(".[31:16] -> 0x%04X\n", val);
348	break;	348	break;
349	case ATOM_SRC_BYTE0:	349	case ATOM_SRC_BYTE0:
350	DEBUG(".[7:0] -> 0x%02X\n", val);	350	DEBUG(".[7:0] -> 0x%02X\n", val);
351	break;	351	break;
352	case ATOM_SRC_BYTE8:	352	case ATOM_SRC_BYTE8:
353	DEBUG(".[15:8] -> 0x%02X\n", val);	353	DEBUG(".[15:8] -> 0x%02X\n", val);
354	break;	354	break;
355	case ATOM_SRC_BYTE16:	355	case ATOM_SRC_BYTE16:
356	DEBUG(".[23:16] -> 0x%02X\n", val);	356	DEBUG(".[23:16] -> 0x%02X\n", val);
357	break;	357	break;
358	case ATOM_SRC_BYTE24:	358	case ATOM_SRC_BYTE24:
359	DEBUG(".[31:24] -> 0x%02X\n", val);	359	DEBUG(".[31:24] -> 0x%02X\n", val);
360	break;	360	break;
361	}	361	}
362	return val;	362	return val;
363	}	363	}
364		364
365	static void atom_skip_src_int(atom_exec_context ctx, uint8_t attr, int ptr)	365	static void atom_skip_src_int(atom_exec_context ctx, uint8_t attr, int ptr)
366	{	366	{
367	uint32_t align = (attr >> 3) & 7, arg = attr & 7;	367	uint32_t align = (attr >> 3) & 7, arg = attr & 7;
368	switch (arg) {	368	switch (arg) {
369	case ATOM_ARG_REG:	369	case ATOM_ARG_REG:
370	case ATOM_ARG_ID:	370	case ATOM_ARG_ID:
371	(*ptr) += 2;	371	(*ptr) += 2;
372	break;	372	break;
373	case ATOM_ARG_PLL:	373	case ATOM_ARG_PLL:
374	case ATOM_ARG_MC:	374	case ATOM_ARG_MC:
375	case ATOM_ARG_PS:	375	case ATOM_ARG_PS:
376	case ATOM_ARG_WS:	376	case ATOM_ARG_WS:
377	case ATOM_ARG_FB:	377	case ATOM_ARG_FB:
378	(*ptr)++;	378	(*ptr)++;
379	break;	379	break;
380	case ATOM_ARG_IMM:	380	case ATOM_ARG_IMM:
381	switch (align) {	381	switch (align) {
382	case ATOM_SRC_DWORD:	382	case ATOM_SRC_DWORD:
383	(*ptr) += 4;	383	(*ptr) += 4;
384	return;	384	return;
385	case ATOM_SRC_WORD0:	385	case ATOM_SRC_WORD0:
386	case ATOM_SRC_WORD8:	386	case ATOM_SRC_WORD8:
387	case ATOM_SRC_WORD16:	387	case ATOM_SRC_WORD16:
388	(*ptr) += 2;	388	(*ptr) += 2;
389	return;	389	return;
390	case ATOM_SRC_BYTE0:	390	case ATOM_SRC_BYTE0:
391	case ATOM_SRC_BYTE8:	391	case ATOM_SRC_BYTE8:
392	case ATOM_SRC_BYTE16:	392	case ATOM_SRC_BYTE16:
393	case ATOM_SRC_BYTE24:	393	case ATOM_SRC_BYTE24:
394	(*ptr)++;	394	(*ptr)++;
395	return;	395	return;
396	}	396	}
397	return;	397	return;
398	}	398	}
399	}	399	}
400		400
401	static uint32_t atom_get_src(atom_exec_context ctx, uint8_t attr, int ptr)	401	static uint32_t atom_get_src(atom_exec_context ctx, uint8_t attr, int ptr)
402	{	402	{
403	return atom_get_src_int(ctx, attr, ptr, NULL, 1);	403	return atom_get_src_int(ctx, attr, ptr, NULL, 1);
404	}	404	}
405		405
406	static uint32_t atom_get_src_direct(atom_exec_context ctx, uint8_t align, int ptr)	406	static uint32_t atom_get_src_direct(atom_exec_context ctx, uint8_t align, int ptr)
407	{	407	{
408	uint32_t val = 0xCDCDCDCD;	408	uint32_t val = 0xCDCDCDCD;
409		409
410	switch (align) {	410	switch (align) {
411	case ATOM_SRC_DWORD:	411	case ATOM_SRC_DWORD:
412	val = U32(*ptr);	412	val = U32(*ptr);
413	(*ptr) += 4;	413	(*ptr) += 4;
414	break;	414	break;
415	case ATOM_SRC_WORD0:	415	case ATOM_SRC_WORD0:
416	case ATOM_SRC_WORD8:	416	case ATOM_SRC_WORD8:
417	case ATOM_SRC_WORD16:	417	case ATOM_SRC_WORD16:
418	val = U16(*ptr);	418	val = U16(*ptr);
419	(*ptr) += 2;	419	(*ptr) += 2;
420	break;	420	break;
421	case ATOM_SRC_BYTE0:	421	case ATOM_SRC_BYTE0:
422	case ATOM_SRC_BYTE8:	422	case ATOM_SRC_BYTE8:
423	case ATOM_SRC_BYTE16:	423	case ATOM_SRC_BYTE16:
424	case ATOM_SRC_BYTE24:	424	case ATOM_SRC_BYTE24:
425	val = U8(*ptr);	425	val = U8(*ptr);
426	(*ptr)++;	426	(*ptr)++;
427	break;	427	break;
428	}	428	}
429	return val;	429	return val;
430	}	430	}
431		431
432	static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,	432	static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
433	int ptr, uint32_t saved, int print)	433	int ptr, uint32_t saved, int print)
434	{	434	{
435	return atom_get_src_int(ctx,	435	return atom_get_src_int(ctx,
436	arg \| atom_dst_to_src[(attr >> 3) &	436	arg \| atom_dst_to_src[(attr >> 3) &
437	7][(attr >> 6) & 3] << 3,	437	7][(attr >> 6) & 3] << 3,
438	ptr, saved, print);	438	ptr, saved, print);
439	}	439	}
440		440
441	static void atom_skip_dst(atom_exec_context ctx, int arg, uint8_t attr, int ptr)	441	static void atom_skip_dst(atom_exec_context ctx, int arg, uint8_t attr, int ptr)
442	{	442	{
443	atom_skip_src_int(ctx,	443	atom_skip_src_int(ctx,
444	arg \| atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &	444	arg \| atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &
445	3] << 3, ptr);	445	3] << 3, ptr);
446	}	446	}
447		447
448	static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,	448	static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
449	int *ptr, uint32_t val, uint32_t saved)	449	int *ptr, uint32_t val, uint32_t saved)
450	{	450	{
451	uint32_t align =	451	uint32_t align =
452	atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =	452	atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =
453	val, idx;	453	val, idx;
454	struct atom_context *gctx = ctx->ctx;	454	struct atom_context *gctx = ctx->ctx;
455	old_val &= atom_arg_mask[align] >> atom_arg_shift[align];	455	old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
456	val <<= atom_arg_shift[align];	456	val <<= atom_arg_shift[align];
457	val &= atom_arg_mask[align];	457	val &= atom_arg_mask[align];
458	saved &= ~atom_arg_mask[align];	458	saved &= ~atom_arg_mask[align];
459	val \|= saved;	459	val \|= saved;
460	switch (arg) {	460	switch (arg) {
461	case ATOM_ARG_REG:	461	case ATOM_ARG_REG:
462	idx = U16(*ptr);	462	idx = U16(*ptr);
463	(*ptr) += 2;	463	(*ptr) += 2;
464	DEBUG("REG[0x%04X]", idx);	464	DEBUG("REG[0x%04X]", idx);
465	idx += gctx->reg_block;	465	idx += gctx->reg_block;
466	switch (gctx->io_mode) {	466	switch (gctx->io_mode) {
467	case ATOM_IO_MM:	467	case ATOM_IO_MM:
468	if (idx == 0)	468	if (idx == 0)
469	gctx->card->reg_write(gctx->card, idx,	469	gctx->card->reg_write(gctx->card, idx,
470	val << 2);	470	val << 2);
471	else	471	else
472	gctx->card->reg_write(gctx->card, idx, val);	472	gctx->card->reg_write(gctx->card, idx, val);
473	break;	473	break;
474	case ATOM_IO_PCI:	474	case ATOM_IO_PCI:
475	printk(KERN_INFO	475	printk(KERN_INFO
476	"PCI registers are not implemented.\n");	476	"PCI registers are not implemented.\n");
477	return;	477	return;
478	case ATOM_IO_SYSIO:	478	case ATOM_IO_SYSIO:
479	printk(KERN_INFO	479	printk(KERN_INFO
480	"SYSIO registers are not implemented.\n");	480	"SYSIO registers are not implemented.\n");
481	return;	481	return;
482	default:	482	default:
483	if (!(gctx->io_mode & 0x80)) {	483	if (!(gctx->io_mode & 0x80)) {
484	printk(KERN_INFO "Bad IO mode.\n");	484	printk(KERN_INFO "Bad IO mode.\n");
485	return;	485	return;
486	}	486	}
487	if (!gctx->iio[gctx->io_mode & 0xFF]) {	487	if (!gctx->iio[gctx->io_mode & 0xFF]) {
488	printk(KERN_INFO	488	printk(KERN_INFO
489	"Undefined indirect IO write method %d.\n",	489	"Undefined indirect IO write method %d.\n",
490	gctx->io_mode & 0x7F);	490	gctx->io_mode & 0x7F);
491	return;	491	return;
492	}	492	}
493	atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],	493	atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],
494	idx, val);	494	idx, val);
495	}	495	}
496	break;	496	break;
497	case ATOM_ARG_PS:	497	case ATOM_ARG_PS:
498	idx = U8(*ptr);	498	idx = U8(*ptr);
499	(*ptr)++;	499	(*ptr)++;
500	DEBUG("PS[0x%02X]", idx);	500	DEBUG("PS[0x%02X]", idx);

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(root)/drivers/video/drm/radeon/atom.c – Rev 5078 → 5271