WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/atom.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Author: Stanislaw Skowronek
 */
 
#include 
#include 
 
#define ATOM_DEBUG
 
#include "atom.h"
#include "atom-names.h"
#include "atom-bits.h"
 
#define ATOM_COND_ABOVE		0
#define ATOM_COND_ABOVEOREQUAL	1
#define ATOM_COND_ALWAYS	2
#define ATOM_COND_BELOW		3
#define ATOM_COND_BELOWOREQUAL	4
#define ATOM_COND_EQUAL		5
#define ATOM_COND_NOTEQUAL	6
 
#define ATOM_PORT_ATI	0
#define ATOM_PORT_PCI	1
#define ATOM_PORT_SYSIO	2
 
#define ATOM_UNIT_MICROSEC	0
#define ATOM_UNIT_MILLISEC	1
 
#define PLL_INDEX	2
#define PLL_DATA	3
 
typedef struct {
	struct atom_context *ctx;
 
	uint32_t *ps, *ws;
	int ps_shift;
	uint16_t start;
} atom_exec_context;
 
int atom_debug = 0;
static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
 
static uint32_t atom_arg_mask[8] =
    { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
0xFF000000 };
static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
 
static int atom_dst_to_src[8][4] = {
	/* translate destination alignment field to the source alignment encoding */
	{0, 0, 0, 0},
	{1, 2, 3, 0},
	{1, 2, 3, 0},
	{1, 2, 3, 0},
	{4, 5, 6, 7},
	{4, 5, 6, 7},
	{4, 5, 6, 7},
	{4, 5, 6, 7},
};
static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
 
static int debug_depth = 0;
#ifdef ATOM_DEBUG
static void debug_print_spaces(int n)
{
	while (n--)
		printk("   ");
}
 
#define DEBUG(...) do if (atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)
#define SDEBUG(...) do if (atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)
#else
#define DEBUG(...) do { } while (0)
#define SDEBUG(...) do { } while (0)
#endif
 
static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
				 uint32_t index, uint32_t data)
{
	uint32_t temp = 0xCDCDCDCD;
	while (1)
		switch (CU8(base)) {
		case ATOM_IIO_NOP:
			base++;
			break;
		case ATOM_IIO_READ:
			temp = ctx->card->reg_read(ctx->card, CU16(base + 1));
			base += 3;
			break;
		case ATOM_IIO_WRITE:
			(void)ctx->card->reg_read(ctx->card, CU16(base + 1));
			ctx->card->reg_write(ctx->card, CU16(base + 1), temp);
			base += 3;
			break;
		case ATOM_IIO_CLEAR:
			temp &=
			    ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
			      CU8(base + 2));
			base += 3;
			break;
		case ATOM_IIO_SET:
			temp |=
			    (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +
									2);
			base += 3;
			break;
		case ATOM_IIO_MOVE_INDEX:
			temp &=
			    ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
			      CU8(base + 2));
			temp |=
			    ((index >> CU8(base + 2)) &
			     (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
									  3);
			base += 4;
			break;
		case ATOM_IIO_MOVE_DATA:
			temp &=
			    ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
			      CU8(base + 2));
			temp |=
			    ((data >> CU8(base + 2)) &
			     (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
									  3);
			base += 4;
			break;
		case ATOM_IIO_MOVE_ATTR:
			temp &=
			    ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
			      CU8(base + 2));
			temp |=
			    ((ctx->
			      io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -
									  CU8
									  (base
									   +
									   1))))
			    << CU8(base + 3);
			base += 4;
			break;
		case ATOM_IIO_END:
			return temp;
		default:
			printk(KERN_INFO "Unknown IIO opcode.\n");
			return 0;
		}
}
 
static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
				 int *ptr, uint32_t *saved, int print)
{
	uint32_t idx, val = 0xCDCDCDCD, align, arg;
	struct atom_context *gctx = ctx->ctx;
	arg = attr & 7;
	align = (attr >> 3) & 7;
	switch (arg) {
	case ATOM_ARG_REG:
		idx = U16(*ptr);
		(*ptr) += 2;
		if (print)
			DEBUG("REG[0x%04X]", idx);
		idx += gctx->reg_block;
		switch (gctx->io_mode) {
		case ATOM_IO_MM:
			val = gctx->card->reg_read(gctx->card, idx);
			break;
		case ATOM_IO_PCI:
			printk(KERN_INFO
			       "PCI registers are not implemented.\n");
			return 0;
		case ATOM_IO_SYSIO:
			printk(KERN_INFO
			       "SYSIO registers are not implemented.\n");
			return 0;
		default:
			if (!(gctx->io_mode & 0x80)) {
				printk(KERN_INFO "Bad IO mode.\n");
				return 0;
			}
			if (!gctx->iio[gctx->io_mode & 0x7F]) {
				printk(KERN_INFO
				       "Undefined indirect IO read method %d.\n",
				       gctx->io_mode & 0x7F);
				return 0;
			}
			val =
			    atom_iio_execute(gctx,
					     gctx->iio[gctx->io_mode & 0x7F],
					     idx, 0);
		}
		break;
	case ATOM_ARG_PS:
		idx = U8(*ptr);
		(*ptr)++;
		val = le32_to_cpu(ctx->ps[idx]);
		if (print)
			DEBUG("PS[0x%02X,0x%04X]", idx, val);
		break;
	case ATOM_ARG_WS:
		idx = U8(*ptr);
		(*ptr)++;
		if (print)
			DEBUG("WS[0x%02X]", idx);
		switch (idx) {
		case ATOM_WS_QUOTIENT:
			val = gctx->divmul[0];
			break;
		case ATOM_WS_REMAINDER:
			val = gctx->divmul[1];
			break;
		case ATOM_WS_DATAPTR:
			val = gctx->data_block;
			break;
		case ATOM_WS_SHIFT:
			val = gctx->shift;
			break;
		case ATOM_WS_OR_MASK:
			val = 1 << gctx->shift;
			break;
		case ATOM_WS_AND_MASK:
			val = ~(1 << gctx->shift);
			break;
		case ATOM_WS_FB_WINDOW:
			val = gctx->fb_base;
			break;
		case ATOM_WS_ATTRIBUTES:
			val = gctx->io_attr;
			break;
		case ATOM_WS_REGPTR:
			val = gctx->reg_block;
			break;
		default:
			val = ctx->ws[idx];
		}
		break;
	case ATOM_ARG_ID:
		idx = U16(*ptr);
		(*ptr) += 2;
		if (print) {
			if (gctx->data_block)
				DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);
			else
				DEBUG("ID[0x%04X]", idx);
		}
		val = U32(idx + gctx->data_block);
		break;
	case ATOM_ARG_FB:
		idx = U8(*ptr);
		(*ptr)++;
		val = gctx->scratch[((gctx->fb_base + idx) / 4)];
		if (print)
			DEBUG("FB[0x%02X]", idx);
		break;
	case ATOM_ARG_IMM:
		switch (align) {
		case ATOM_SRC_DWORD:
			val = U32(*ptr);
			(*ptr) += 4;
			if (print)
				DEBUG("IMM 0x%08X\n", val);
			return val;
		case ATOM_SRC_WORD0:
		case ATOM_SRC_WORD8:
		case ATOM_SRC_WORD16:
			val = U16(*ptr);
			(*ptr) += 2;
			if (print)
				DEBUG("IMM 0x%04X\n", val);
			return val;
		case ATOM_SRC_BYTE0:
		case ATOM_SRC_BYTE8:
		case ATOM_SRC_BYTE16:
		case ATOM_SRC_BYTE24:
			val = U8(*ptr);
			(*ptr)++;
			if (print)
				DEBUG("IMM 0x%02X\n", val);
			return val;
		}
		return 0;
	case ATOM_ARG_PLL:
		idx = U8(*ptr);
		(*ptr)++;
		if (print)
			DEBUG("PLL[0x%02X]", idx);
		val = gctx->card->pll_read(gctx->card, idx);
		break;
	case ATOM_ARG_MC:
		idx = U8(*ptr);
		(*ptr)++;
		if (print)
			DEBUG("MC[0x%02X]", idx);
		val = gctx->card->mc_read(gctx->card, idx);
		break;
	}
	if (saved)
		*saved = val;
	val &= atom_arg_mask[align];
	val >>= atom_arg_shift[align];
	if (print)
		switch (align) {
		case ATOM_SRC_DWORD:
			DEBUG(".[31:0] -> 0x%08X\n", val);
			break;
		case ATOM_SRC_WORD0:
			DEBUG(".[15:0] -> 0x%04X\n", val);
			break;
		case ATOM_SRC_WORD8:
			DEBUG(".[23:8] -> 0x%04X\n", val);
			break;
		case ATOM_SRC_WORD16:
			DEBUG(".[31:16] -> 0x%04X\n", val);
			break;
		case ATOM_SRC_BYTE0:
			DEBUG(".[7:0] -> 0x%02X\n", val);
			break;
		case ATOM_SRC_BYTE8:
			DEBUG(".[15:8] -> 0x%02X\n", val);
			break;
		case ATOM_SRC_BYTE16:
			DEBUG(".[23:16] -> 0x%02X\n", val);
			break;
		case ATOM_SRC_BYTE24:
			DEBUG(".[31:24] -> 0x%02X\n", val);
			break;
		}
	return val;
}
 
static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)
{
	uint32_t align = (attr >> 3) & 7, arg = attr & 7;
	switch (arg) {
	case ATOM_ARG_REG:
	case ATOM_ARG_ID:
		(*ptr) += 2;
		break;
	case ATOM_ARG_PLL:
	case ATOM_ARG_MC:
	case ATOM_ARG_PS:
	case ATOM_ARG_WS:
	case ATOM_ARG_FB:
		(*ptr)++;
		break;
	case ATOM_ARG_IMM:
		switch (align) {
		case ATOM_SRC_DWORD:
			(*ptr) += 4;
			return;
		case ATOM_SRC_WORD0:
		case ATOM_SRC_WORD8:
		case ATOM_SRC_WORD16:
			(*ptr) += 2;
			return;
		case ATOM_SRC_BYTE0:
		case ATOM_SRC_BYTE8:
		case ATOM_SRC_BYTE16:
		case ATOM_SRC_BYTE24:
			(*ptr)++;
			return;
		}
		return;
	}
}
 
static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
{
	return atom_get_src_int(ctx, attr, ptr, NULL, 1);
}
 
static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
{
	uint32_t val = 0xCDCDCDCD;
 
	switch (align) {
	case ATOM_SRC_DWORD:
		val = U32(*ptr);
		(*ptr) += 4;
		break;
	case ATOM_SRC_WORD0:
	case ATOM_SRC_WORD8:
	case ATOM_SRC_WORD16:
		val = U16(*ptr);
		(*ptr) += 2;
		break;
	case ATOM_SRC_BYTE0:
	case ATOM_SRC_BYTE8:
	case ATOM_SRC_BYTE16:
	case ATOM_SRC_BYTE24:
		val = U8(*ptr);
		(*ptr)++;
		break;
	}
	return val;
}
 
static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
			     int *ptr, uint32_t *saved, int print)
{
	return atom_get_src_int(ctx,
				arg | atom_dst_to_src[(attr >> 3) &
						      7][(attr >> 6) & 3] << 3,
				ptr, saved, print);
}
 
static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)
{
	atom_skip_src_int(ctx,
			  arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &
								 3] << 3, ptr);
}
 
static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
			 int *ptr, uint32_t val, uint32_t saved)
{
	uint32_t align =
	    atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =
	    val, idx;
	struct atom_context *gctx = ctx->ctx;
	old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
	val <<= atom_arg_shift[align];
	val &= atom_arg_mask[align];
	saved &= ~atom_arg_mask[align];
	val |= saved;
	switch (arg) {
	case ATOM_ARG_REG:
		idx = U16(*ptr);
		(*ptr) += 2;
		DEBUG("REG[0x%04X]", idx);
		idx += gctx->reg_block;
		switch (gctx->io_mode) {
		case ATOM_IO_MM:
			if (idx == 0)
				gctx->card->reg_write(gctx->card, idx,
						      val << 2);
			else
				gctx->card->reg_write(gctx->card, idx, val);
			break;
		case ATOM_IO_PCI:
			printk(KERN_INFO
			       "PCI registers are not implemented.\n");
			return;
		case ATOM_IO_SYSIO:
			printk(KERN_INFO
			       "SYSIO registers are not implemented.\n");
			return;
		default:
			if (!(gctx->io_mode & 0x80)) {
				printk(KERN_INFO "Bad IO mode.\n");
				return;
			}
			if (!gctx->iio[gctx->io_mode & 0xFF]) {
				printk(KERN_INFO
				       "Undefined indirect IO write method %d.\n",
				       gctx->io_mode & 0x7F);
				return;
			}
			atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],
					 idx, val);
		}
		break;
	case ATOM_ARG_PS:
		idx = U8(*ptr);
		(*ptr)++;
		DEBUG("PS[0x%02X]", idx);
		ctx->ps[idx] = cpu_to_le32(val);
		break;
	case ATOM_ARG_WS:
		idx = U8(*ptr);
		(*ptr)++;
		DEBUG("WS[0x%02X]", idx);
		switch (idx) {
		case ATOM_WS_QUOTIENT:
			gctx->divmul[0] = val;
			break;
		case ATOM_WS_REMAINDER:
			gctx->divmul[1] = val;
			break;
		case ATOM_WS_DATAPTR:
			gctx->data_block = val;
			break;
		case ATOM_WS_SHIFT:
			gctx->shift = val;
			break;
		case ATOM_WS_OR_MASK:
		case ATOM_WS_AND_MASK:
			break;
		case ATOM_WS_FB_WINDOW:
			gctx->fb_base = val;
			break;
		case ATOM_WS_ATTRIBUTES:
			gctx->io_attr = val;
			break;
		case ATOM_WS_REGPTR:
			gctx->reg_block = val;
			break;
		default:
			ctx->ws[idx] = val;
		}
		break;
	case ATOM_ARG_FB:
		idx = U8(*ptr);
		(*ptr)++;
		gctx->scratch[((gctx->fb_base + idx) / 4)] = val;
		DEBUG("FB[0x%02X]", idx);
		break;
	case ATOM_ARG_PLL:
		idx = U8(*ptr);
		(*ptr)++;
		DEBUG("PLL[0x%02X]", idx);
		gctx->card->pll_write(gctx->card, idx, val);
		break;
	case ATOM_ARG_MC:
		idx = U8(*ptr);
		(*ptr)++;
		DEBUG("MC[0x%02X]", idx);
		gctx->card->mc_write(gctx->card, idx, val);
		return;
	}
	switch (align) {
	case ATOM_SRC_DWORD:
		DEBUG(".[31:0] <- 0x%08X\n", old_val);
		break;
	case ATOM_SRC_WORD0:
		DEBUG(".[15:0] <- 0x%04X\n", old_val);
		break;
	case ATOM_SRC_WORD8:
		DEBUG(".[23:8] <- 0x%04X\n", old_val);
		break;
	case ATOM_SRC_WORD16:
		DEBUG(".[31:16] <- 0x%04X\n", old_val);
		break;
	case ATOM_SRC_BYTE0:
		DEBUG(".[7:0] <- 0x%02X\n", old_val);
		break;
	case ATOM_SRC_BYTE8:
		DEBUG(".[15:8] <- 0x%02X\n", old_val);
		break;
	case ATOM_SRC_BYTE16:
		DEBUG(".[23:16] <- 0x%02X\n", old_val);
		break;
	case ATOM_SRC_BYTE24:
		DEBUG(".[31:24] <- 0x%02X\n", old_val);
		break;
	}
}
 
static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src, saved;
	int dptr = *ptr;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	SDEBUG("   src: ");
	src = atom_get_src(ctx, attr, ptr);
	dst += src;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src, saved;
	int dptr = *ptr;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	SDEBUG("   src: ");
	src = atom_get_src(ctx, attr, ptr);
	dst &= src;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg)
{
	printk("ATOM BIOS beeped!\n");
}
 
static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
{
	int idx = U8((*ptr)++);
	if (idx < ATOM_TABLE_NAMES_CNT)
		SDEBUG("   table: %d (%s)\n", idx, atom_table_names[idx]);
	else
		SDEBUG("   table: %d\n", idx);
	if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
		atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
}
 
static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t saved;
	int dptr = *ptr;
	attr &= 0x38;
	attr |= atom_def_dst[attr >> 3] << 6;
	atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, 0, saved);
}
 
static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src;
	SDEBUG("   src1: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
	SDEBUG("   src2: ");
	src = atom_get_src(ctx, attr, ptr);
	ctx->ctx->cs_equal = (dst == src);
	ctx->ctx->cs_above = (dst > src);
	SDEBUG("   result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE",
	       ctx->ctx->cs_above ? "GT" : "LE");
}
 
static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t count = U8((*ptr)++);
	SDEBUG("   count: %d\n", count);
    if (arg == ATOM_UNIT_MICROSEC)
       udelay(count);
    else
       mdelay(count);
}
 
static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src;
	SDEBUG("   src1: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
	SDEBUG("   src2: ");
	src = atom_get_src(ctx, attr, ptr);
	if (src != 0) {
		ctx->ctx->divmul[0] = dst / src;
		ctx->ctx->divmul[1] = dst % src;
	} else {
		ctx->ctx->divmul[0] = 0;
		ctx->ctx->divmul[1] = 0;
	}
}
 
static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
{
	/* functionally, a nop */
}
 
static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
{
	int execute = 0, target = U16(*ptr);
	(*ptr) += 2;
	switch (arg) {
	case ATOM_COND_ABOVE:
		execute = ctx->ctx->cs_above;
		break;
	case ATOM_COND_ABOVEOREQUAL:
		execute = ctx->ctx->cs_above || ctx->ctx->cs_equal;
		break;
	case ATOM_COND_ALWAYS:
		execute = 1;
		break;
	case ATOM_COND_BELOW:
		execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal);
		break;
	case ATOM_COND_BELOWOREQUAL:
		execute = !ctx->ctx->cs_above;
		break;
	case ATOM_COND_EQUAL:
		execute = ctx->ctx->cs_equal;
		break;
	case ATOM_COND_NOTEQUAL:
		execute = !ctx->ctx->cs_equal;
		break;
	}
	if (arg != ATOM_COND_ALWAYS)
		SDEBUG("   taken: %s\n", execute ? "yes" : "no");
	SDEBUG("   target: 0x%04X\n", target);
	if (execute)
		*ptr = ctx->start + target;
}
 
static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src1, src2, saved;
	int dptr = *ptr;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	SDEBUG("   src1: ");
	src1 = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
	SDEBUG("   src2: ");
	src2 = atom_get_src(ctx, attr, ptr);
	dst &= src1;
	dst |= src2;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t src, saved;
	int dptr = *ptr;
	if (((attr >> 3) & 7) != ATOM_SRC_DWORD)
		atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
	else {
		atom_skip_dst(ctx, arg, attr, ptr);
		saved = 0xCDCDCDCD;
	}
	SDEBUG("   src: ");
	src = atom_get_src(ctx, attr, ptr);
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, src, saved);
}
 
static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src;
	SDEBUG("   src1: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
	SDEBUG("   src2: ");
	src = atom_get_src(ctx, attr, ptr);
	ctx->ctx->divmul[0] = dst * src;
}
 
static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg)
{
	/* nothing */
}
 
static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src, saved;
	int dptr = *ptr;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	SDEBUG("   src: ");
	src = atom_get_src(ctx, attr, ptr);
	dst |= src;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t val = U8((*ptr)++);
	SDEBUG("POST card output: 0x%02X\n", val);
}
 
static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg)
{
	printk(KERN_INFO "unimplemented!\n");
}
 
static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg)
{
	printk(KERN_INFO "unimplemented!\n");
}
 
static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg)
{
	printk(KERN_INFO "unimplemented!\n");
}
 
static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg)
{
	int idx = U8(*ptr);
	(*ptr)++;
	SDEBUG("   block: %d\n", idx);
	if (!idx)
		ctx->ctx->data_block = 0;
	else if (idx == 255)
		ctx->ctx->data_block = ctx->start;
	else
		ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx);
	SDEBUG("   base: 0x%04X\n", ctx->ctx->data_block);
}
 
static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	SDEBUG("   fb_base: ");
	ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr);
}
 
static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg)
{
	int port;
	switch (arg) {
	case ATOM_PORT_ATI:
		port = U16(*ptr);
		if (port < ATOM_IO_NAMES_CNT)
			SDEBUG("   port: %d (%s)\n", port, atom_io_names[port]);
		else
			SDEBUG("   port: %d\n", port);
		if (!port)
			ctx->ctx->io_mode = ATOM_IO_MM;
		else
			ctx->ctx->io_mode = ATOM_IO_IIO | port;
		(*ptr) += 2;
		break;
	case ATOM_PORT_PCI:
		ctx->ctx->io_mode = ATOM_IO_PCI;
		(*ptr)++;
		break;
	case ATOM_PORT_SYSIO:
		ctx->ctx->io_mode = ATOM_IO_SYSIO;
		(*ptr)++;
		break;
	}
}
 
static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
{
	ctx->ctx->reg_block = U16(*ptr);
	(*ptr) += 2;
	SDEBUG("   base: 0x%04X\n", ctx->ctx->reg_block);
}
 
static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++), shift;
	uint32_t saved, dst;
	int dptr = *ptr;
	attr &= 0x38;
	attr |= atom_def_dst[attr >> 3] << 6;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
	SDEBUG("   shift: %d\n", shift);
	dst <<= shift;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++), shift;
	uint32_t saved, dst;
	int dptr = *ptr;
	attr &= 0x38;
	attr |= atom_def_dst[attr >> 3] << 6;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
	SDEBUG("   shift: %d\n", shift);
	dst >>= shift;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++), shift;
	uint32_t saved, dst;
	int dptr = *ptr;
	attr &= 0x38;
	attr |= atom_def_dst[attr >> 3] << 6;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	shift = atom_get_src(ctx, attr, ptr);
	SDEBUG("   shift: %d\n", shift);
	dst <<= shift;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++), shift;
	uint32_t saved, dst;
	int dptr = *ptr;
	attr &= 0x38;
	attr |= atom_def_dst[attr >> 3] << 6;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	shift = atom_get_src(ctx, attr, ptr);
	SDEBUG("   shift: %d\n", shift);
	dst >>= shift;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src, saved;
	int dptr = *ptr;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	SDEBUG("   src: ");
	src = atom_get_src(ctx, attr, ptr);
	dst -= src;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t src, val, target;
	SDEBUG("   switch: ");
	src = atom_get_src(ctx, attr, ptr);
	while (U16(*ptr) != ATOM_CASE_END)
		if (U8(*ptr) == ATOM_CASE_MAGIC) {
			(*ptr)++;
			SDEBUG("   case: ");
			val =
			    atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM,
					 ptr);
			target = U16(*ptr);
			if (val == src) {
				SDEBUG("   target: %04X\n", target);
				*ptr = ctx->start + target;
				return;
			}
			(*ptr) += 2;
		} else {
			printk(KERN_INFO "Bad case.\n");
			return;
		}
	(*ptr) += 2;
}
 
static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src;
	SDEBUG("   src1: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
	SDEBUG("   src2: ");
	src = atom_get_src(ctx, attr, ptr);
	ctx->ctx->cs_equal = ((dst & src) == 0);
	SDEBUG("   result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE");
}
 
static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg)
{
	uint8_t attr = U8((*ptr)++);
	uint32_t dst, src, saved;
	int dptr = *ptr;
	SDEBUG("   dst: ");
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
	SDEBUG("   src: ");
	src = atom_get_src(ctx, attr, ptr);
	dst ^= src;
	SDEBUG("   dst: ");
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}
 
static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg)
{
	printk(KERN_INFO "unimplemented!\n");
}
 
static struct {
	void (*func) (atom_exec_context *, int *, int);
	int arg;
} opcode_table[ATOM_OP_CNT] = {
	{
	NULL, 0}, {
	atom_op_move, ATOM_ARG_REG}, {
	atom_op_move, ATOM_ARG_PS}, {
	atom_op_move, ATOM_ARG_WS}, {
	atom_op_move, ATOM_ARG_FB}, {
	atom_op_move, ATOM_ARG_PLL}, {
	atom_op_move, ATOM_ARG_MC}, {
	atom_op_and, ATOM_ARG_REG}, {
	atom_op_and, ATOM_ARG_PS}, {
	atom_op_and, ATOM_ARG_WS}, {
	atom_op_and, ATOM_ARG_FB}, {
	atom_op_and, ATOM_ARG_PLL}, {
	atom_op_and, ATOM_ARG_MC}, {
	atom_op_or, ATOM_ARG_REG}, {
	atom_op_or, ATOM_ARG_PS}, {
	atom_op_or, ATOM_ARG_WS}, {
	atom_op_or, ATOM_ARG_FB}, {
	atom_op_or, ATOM_ARG_PLL}, {
	atom_op_or, ATOM_ARG_MC}, {
	atom_op_shift_left, ATOM_ARG_REG}, {
	atom_op_shift_left, ATOM_ARG_PS}, {
	atom_op_shift_left, ATOM_ARG_WS}, {
	atom_op_shift_left, ATOM_ARG_FB}, {
	atom_op_shift_left, ATOM_ARG_PLL}, {
	atom_op_shift_left, ATOM_ARG_MC}, {
	atom_op_shift_right, ATOM_ARG_REG}, {
	atom_op_shift_right, ATOM_ARG_PS}, {
	atom_op_shift_right, ATOM_ARG_WS}, {
	atom_op_shift_right, ATOM_ARG_FB}, {
	atom_op_shift_right, ATOM_ARG_PLL}, {
	atom_op_shift_right, ATOM_ARG_MC}, {
	atom_op_mul, ATOM_ARG_REG}, {
	atom_op_mul, ATOM_ARG_PS}, {
	atom_op_mul, ATOM_ARG_WS}, {
	atom_op_mul, ATOM_ARG_FB}, {
	atom_op_mul, ATOM_ARG_PLL}, {
	atom_op_mul, ATOM_ARG_MC}, {
	atom_op_div, ATOM_ARG_REG}, {
	atom_op_div, ATOM_ARG_PS}, {
	atom_op_div, ATOM_ARG_WS}, {
	atom_op_div, ATOM_ARG_FB}, {
	atom_op_div, ATOM_ARG_PLL}, {
	atom_op_div, ATOM_ARG_MC}, {
	atom_op_add, ATOM_ARG_REG}, {
	atom_op_add, ATOM_ARG_PS}, {
	atom_op_add, ATOM_ARG_WS}, {
	atom_op_add, ATOM_ARG_FB}, {
	atom_op_add, ATOM_ARG_PLL}, {
	atom_op_add, ATOM_ARG_MC}, {
	atom_op_sub, ATOM_ARG_REG}, {
	atom_op_sub, ATOM_ARG_PS}, {
	atom_op_sub, ATOM_ARG_WS}, {
	atom_op_sub, ATOM_ARG_FB}, {
	atom_op_sub, ATOM_ARG_PLL}, {
	atom_op_sub, ATOM_ARG_MC}, {
	atom_op_setport, ATOM_PORT_ATI}, {
	atom_op_setport, ATOM_PORT_PCI}, {
	atom_op_setport, ATOM_PORT_SYSIO}, {
	atom_op_setregblock, 0}, {
	atom_op_setfbbase, 0}, {
	atom_op_compare, ATOM_ARG_REG}, {
	atom_op_compare, ATOM_ARG_PS}, {
	atom_op_compare, ATOM_ARG_WS}, {
	atom_op_compare, ATOM_ARG_FB}, {
	atom_op_compare, ATOM_ARG_PLL}, {
	atom_op_compare, ATOM_ARG_MC}, {
	atom_op_switch, 0}, {
	atom_op_jump, ATOM_COND_ALWAYS}, {
	atom_op_jump, ATOM_COND_EQUAL}, {
	atom_op_jump, ATOM_COND_BELOW}, {
	atom_op_jump, ATOM_COND_ABOVE}, {
	atom_op_jump, ATOM_COND_BELOWOREQUAL}, {
	atom_op_jump, ATOM_COND_ABOVEOREQUAL}, {
	atom_op_jump, ATOM_COND_NOTEQUAL}, {
	atom_op_test, ATOM_ARG_REG}, {
	atom_op_test, ATOM_ARG_PS}, {
	atom_op_test, ATOM_ARG_WS}, {
	atom_op_test, ATOM_ARG_FB}, {
	atom_op_test, ATOM_ARG_PLL}, {
	atom_op_test, ATOM_ARG_MC}, {
	atom_op_delay, ATOM_UNIT_MILLISEC}, {
	atom_op_delay, ATOM_UNIT_MICROSEC}, {
	atom_op_calltable, 0}, {
	atom_op_repeat, 0}, {
	atom_op_clear, ATOM_ARG_REG}, {
	atom_op_clear, ATOM_ARG_PS}, {
	atom_op_clear, ATOM_ARG_WS}, {
	atom_op_clear, ATOM_ARG_FB}, {
	atom_op_clear, ATOM_ARG_PLL}, {
	atom_op_clear, ATOM_ARG_MC}, {
	atom_op_nop, 0}, {
	atom_op_eot, 0}, {
	atom_op_mask, ATOM_ARG_REG}, {
	atom_op_mask, ATOM_ARG_PS}, {
	atom_op_mask, ATOM_ARG_WS}, {
	atom_op_mask, ATOM_ARG_FB}, {
	atom_op_mask, ATOM_ARG_PLL}, {
	atom_op_mask, ATOM_ARG_MC}, {
	atom_op_postcard, 0}, {
	atom_op_beep, 0}, {
	atom_op_savereg, 0}, {
	atom_op_restorereg, 0}, {
	atom_op_setdatablock, 0}, {
	atom_op_xor, ATOM_ARG_REG}, {
	atom_op_xor, ATOM_ARG_PS}, {
	atom_op_xor, ATOM_ARG_WS}, {
	atom_op_xor, ATOM_ARG_FB}, {
	atom_op_xor, ATOM_ARG_PLL}, {
	atom_op_xor, ATOM_ARG_MC}, {
	atom_op_shl, ATOM_ARG_REG}, {
	atom_op_shl, ATOM_ARG_PS}, {
	atom_op_shl, ATOM_ARG_WS}, {
	atom_op_shl, ATOM_ARG_FB}, {
	atom_op_shl, ATOM_ARG_PLL}, {
	atom_op_shl, ATOM_ARG_MC}, {
	atom_op_shr, ATOM_ARG_REG}, {
	atom_op_shr, ATOM_ARG_PS}, {
	atom_op_shr, ATOM_ARG_WS}, {
	atom_op_shr, ATOM_ARG_FB}, {
	atom_op_shr, ATOM_ARG_PLL}, {
	atom_op_shr, ATOM_ARG_MC}, {
atom_op_debug, 0},};
 
static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
{
	int base = CU16(ctx->cmd_table + 4 + 2 * index);
	int len, ws, ps, ptr;
	unsigned char op;
	atom_exec_context ectx;
 
	if (!base)
		return;
 
	len = CU16(base + ATOM_CT_SIZE_PTR);
	ws = CU8(base + ATOM_CT_WS_PTR);
	ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK;
	ptr = base + ATOM_CT_CODE_PTR;
 
	SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
 
 
 
	ectx.ctx = ctx;
	ectx.ps_shift = ps / 4;
	ectx.start = base;
	ectx.ps = params;
	if (ws)
		ectx.ws = kzalloc(4 * ws, GFP_KERNEL);
	else
		ectx.ws = NULL;
 
	debug_depth++;
	while (1) {
		op = CU8(ptr++);
		if (op < ATOM_OP_NAMES_CNT)
			SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1);
		else
			SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1);
 
		if (op < ATOM_OP_CNT && op > 0)
			opcode_table[op].func(&ectx, &ptr,
					      opcode_table[op].arg);
		else
			break;
 
		if (op == ATOM_OP_EOT)
			break;
	}
	debug_depth--;
	SDEBUG("<<\n");
 
	if (ws)
		kfree(ectx.ws);
}
 
void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
{
	mutex_lock(&ctx->mutex);
	/* reset reg block */
	ctx->reg_block = 0;
	/* reset fb window */
	ctx->fb_base = 0;
	/* reset io mode */
	ctx->io_mode = ATOM_IO_MM;
	atom_execute_table_locked(ctx, index, params);
	mutex_unlock(&ctx->mutex);
}
 
static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
 
static void atom_index_iio(struct atom_context *ctx, int base)
{
	ctx->iio = kzalloc(2 * 256, GFP_KERNEL);
	while (CU8(base) == ATOM_IIO_START) {
		ctx->iio[CU8(base + 1)] = base + 2;
		base += 2;
		while (CU8(base) != ATOM_IIO_END)
			base += atom_iio_len[CU8(base)];
		base += 3;
	}
}
 
struct atom_context *atom_parse(struct card_info *card, void *bios)
{
	int base;
	struct atom_context *ctx =
	    kzalloc(sizeof(struct atom_context), GFP_KERNEL);
	char *str;
	char name[512];
	int i;
 
	ctx->card = card;
	ctx->bios = bios;
 
	if (CU16(0) != ATOM_BIOS_MAGIC) {
		printk(KERN_INFO "Invalid BIOS magic.\n");
		kfree(ctx);
		return NULL;
	}
	if (strncmp
	    (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC,
	     strlen(ATOM_ATI_MAGIC))) {
		printk(KERN_INFO "Invalid ATI magic.\n");
		kfree(ctx);
		return NULL;
	}
 
	base = CU16(ATOM_ROM_TABLE_PTR);
	if (strncmp
	    (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC,
	     strlen(ATOM_ROM_MAGIC))) {
		printk(KERN_INFO "Invalid ATOM magic.\n");
		kfree(ctx);
		return NULL;
	}
 
	ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR);
	ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR);
	atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4);
 
	str = CSTR(CU16(base + ATOM_ROM_MSG_PTR));
	while (*str && ((*str == '\n') || (*str == '\r')))
		str++;
	/* name string isn't always 0 terminated */
	for (i = 0; i < 511; i++) {
		name[i] = str[i];
		if (name[i] < '.' || name[i] > 'z') {
			name[i] = 0;
			break;
		}
	}
	printk(KERN_INFO "ATOM BIOS: %s\n", name);
 
	return ctx;
}
 
int atom_asic_init(struct atom_context *ctx)
{
	int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR);
	uint32_t ps[16];
	memset(ps, 0, 64);
 
	ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR));
	ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR));
	if (!ps[0] || !ps[1])
		return 1;
 
	if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT))
		return 1;
	atom_execute_table(ctx, ATOM_CMD_INIT, ps);
 
	return 0;
}
 
void atom_destroy(struct atom_context *ctx)
{
	if (ctx->iio)
		kfree(ctx->iio);
	kfree(ctx);
}
 
void atom_parse_data_header(struct atom_context *ctx, int index,
			    uint16_t * size, uint8_t * frev, uint8_t * crev,
			    uint16_t * data_start)
{
	int offset = index * 2 + 4;
	int idx = CU16(ctx->data_table + offset);
 
	if (size)
		*size = CU16(idx);
	if (frev)
		*frev = CU8(idx + 2);
	if (crev)
		*crev = CU8(idx + 3);
	*data_start = idx;
	return;
}
 
void atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev,
			   uint8_t * crev)
{
	int offset = index * 2 + 4;
	int idx = CU16(ctx->cmd_table + offset);
 
	if (frev)
		*frev = CU8(idx + 2);
	if (crev)
		*crev = CU8(idx + 3);
	return;
}
 
int atom_allocate_fb_scratch(struct atom_context *ctx)
{
	int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
	uint16_t data_offset;
	int usage_bytes;
	struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
 
	atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
 
	firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
 
	DRM_DEBUG("atom firmware requested %08x %dkb\n",
		  firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware,
		  firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb);
 
	usage_bytes = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb * 1024;
	if (usage_bytes == 0)
		usage_bytes = 20 * 1024;
	/* allocate some scratch memory */
	ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
	if (!ctx->scratch)
		return -ENOMEM;
	return 0;
}
 
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Rev 1321	Rev 1403
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice shall be included in	11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.	12	* all copies or substantial portions of the Software.
13	*	13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.	20	* OTHER DEALINGS IN THE SOFTWARE.
21	*	21	*
22	* Author: Stanislaw Skowronek	22	* Author: Stanislaw Skowronek
23	*/	23	*/
24		24
25	#include	25	#include
26	#include	26	#include
27		27
28	#define ATOM_DEBUG	28	#define ATOM_DEBUG
29		29
30	#include "atom.h"	30	#include "atom.h"
31	#include "atom-names.h"	31	#include "atom-names.h"
32	#include "atom-bits.h"	32	#include "atom-bits.h"
33		33
34	#define ATOM_COND_ABOVE 0	34	#define ATOM_COND_ABOVE 0
35	#define ATOM_COND_ABOVEOREQUAL 1	35	#define ATOM_COND_ABOVEOREQUAL 1
36	#define ATOM_COND_ALWAYS 2	36	#define ATOM_COND_ALWAYS 2
37	#define ATOM_COND_BELOW 3	37	#define ATOM_COND_BELOW 3
38	#define ATOM_COND_BELOWOREQUAL 4	38	#define ATOM_COND_BELOWOREQUAL 4
39	#define ATOM_COND_EQUAL 5	39	#define ATOM_COND_EQUAL 5
40	#define ATOM_COND_NOTEQUAL 6	40	#define ATOM_COND_NOTEQUAL 6
41		41
42	#define ATOM_PORT_ATI 0	42	#define ATOM_PORT_ATI 0
43	#define ATOM_PORT_PCI 1	43	#define ATOM_PORT_PCI 1
44	#define ATOM_PORT_SYSIO 2	44	#define ATOM_PORT_SYSIO 2
45		45
46	#define ATOM_UNIT_MICROSEC 0	46	#define ATOM_UNIT_MICROSEC 0
47	#define ATOM_UNIT_MILLISEC 1	47	#define ATOM_UNIT_MILLISEC 1
48		48
49	#define PLL_INDEX 2	49	#define PLL_INDEX 2
50	#define PLL_DATA 3	50	#define PLL_DATA 3
51		51
52	typedef struct {	52	typedef struct {
53	struct atom_context *ctx;	53	struct atom_context *ctx;
54		54
55	uint32_t ps, ws;	55	uint32_t ps, ws;
56	int ps_shift;	56	int ps_shift;
57	uint16_t start;	57	uint16_t start;
58	} atom_exec_context;	58	} atom_exec_context;
59		59
60	int atom_debug = 0;	60	int atom_debug = 0;
-		61	static void atom_execute_table_locked(struct atom_context ctx, int index, uint32_t params);
61	void atom_execute_table(struct atom_context ctx, int index, uint32_t params);	62	void atom_execute_table(struct atom_context ctx, int index, uint32_t params);
62		63
63	static uint32_t atom_arg_mask[8] =	64	static uint32_t atom_arg_mask[8] =
64	{ 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,	65	{ 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
65	0xFF000000 };	66	0xFF000000 };
66	static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };	67	static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
67		68
68	static int atom_dst_to_src[8][4] = {	69	static int atom_dst_to_src[8][4] = {
69	/* translate destination alignment field to the source alignment encoding */	70	/* translate destination alignment field to the source alignment encoding */
70	{0, 0, 0, 0},	71	{0, 0, 0, 0},
71	{1, 2, 3, 0},	72	{1, 2, 3, 0},
72	{1, 2, 3, 0},	73	{1, 2, 3, 0},
73	{1, 2, 3, 0},	74	{1, 2, 3, 0},
74	{4, 5, 6, 7},	75	{4, 5, 6, 7},
75	{4, 5, 6, 7},	76	{4, 5, 6, 7},
76	{4, 5, 6, 7},	77	{4, 5, 6, 7},
77	{4, 5, 6, 7},	78	{4, 5, 6, 7},
78	};	79	};
79	static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };	80	static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
80		81
81	static int debug_depth = 0;	82	static int debug_depth = 0;
82	#ifdef ATOM_DEBUG	83	#ifdef ATOM_DEBUG
83	static void debug_print_spaces(int n)	84	static void debug_print_spaces(int n)
84	{	85	{
85	while (n--)	86	while (n--)
86	printk(" ");	87	printk(" ");
87	}	88	}
88		89
89	#define DEBUG(...) do if (atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)	90	#define DEBUG(...) do if (atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)
90	#define SDEBUG(...) do if (atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)	91	#define SDEBUG(...) do if (atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)
91	#else	92	#else
92	#define DEBUG(...) do { } while (0)	93	#define DEBUG(...) do { } while (0)
93	#define SDEBUG(...) do { } while (0)	94	#define SDEBUG(...) do { } while (0)
94	#endif	95	#endif
95		96
96	static uint32_t atom_iio_execute(struct atom_context *ctx, int base,	97	static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
97	uint32_t index, uint32_t data)	98	uint32_t index, uint32_t data)
98	{	99	{
99	uint32_t temp = 0xCDCDCDCD;	100	uint32_t temp = 0xCDCDCDCD;
100	while (1)	101	while (1)
101	switch (CU8(base)) {	102	switch (CU8(base)) {
102	case ATOM_IIO_NOP:	103	case ATOM_IIO_NOP:
103	base++;	104	base++;
104	break;	105	break;
105	case ATOM_IIO_READ:	106	case ATOM_IIO_READ:
106	temp = ctx->card->reg_read(ctx->card, CU16(base + 1));	107	temp = ctx->card->reg_read(ctx->card, CU16(base + 1));
107	base += 3;	108	base += 3;
108	break;	109	break;
109	case ATOM_IIO_WRITE:	110	case ATOM_IIO_WRITE:
110	(void)ctx->card->reg_read(ctx->card, CU16(base + 1));	111	(void)ctx->card->reg_read(ctx->card, CU16(base + 1));
111	ctx->card->reg_write(ctx->card, CU16(base + 1), temp);	112	ctx->card->reg_write(ctx->card, CU16(base + 1), temp);
112	base += 3;	113	base += 3;
113	break;	114	break;
114	case ATOM_IIO_CLEAR:	115	case ATOM_IIO_CLEAR:
115	temp &=	116	temp &=
116	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<	117	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
117	CU8(base + 2));	118	CU8(base + 2));
118	base += 3;	119	base += 3;
119	break;	120	break;
120	case ATOM_IIO_SET:	121	case ATOM_IIO_SET:
121	temp \|=	122	temp \|=
122	(0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +	123	(0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +
123	2);	124	2);
124	base += 3;	125	base += 3;
125	break;	126	break;
126	case ATOM_IIO_MOVE_INDEX:	127	case ATOM_IIO_MOVE_INDEX:
127	temp &=	128	temp &=
128	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<	129	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
129	CU8(base + 2));	130	CU8(base + 2));
130	temp \|=	131	temp \|=
131	((index >> CU8(base + 2)) &	132	((index >> CU8(base + 2)) &
132	(0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +	133	(0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
133	3);	134	3);
134	base += 4;	135	base += 4;
135	break;	136	break;
136	case ATOM_IIO_MOVE_DATA:	137	case ATOM_IIO_MOVE_DATA:
137	temp &=	138	temp &=
138	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<	139	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
139	CU8(base + 2));	140	CU8(base + 2));
140	temp \|=	141	temp \|=
141	((data >> CU8(base + 2)) &	142	((data >> CU8(base + 2)) &
142	(0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +	143	(0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
143	3);	144	3);
144	base += 4;	145	base += 4;
145	break;	146	break;
146	case ATOM_IIO_MOVE_ATTR:	147	case ATOM_IIO_MOVE_ATTR:
147	temp &=	148	temp &=
148	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<	149	~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
149	CU8(base + 2));	150	CU8(base + 2));
150	temp \|=	151	temp \|=
151	((ctx->	152	((ctx->
152	io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -	153	io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -
153	CU8	154	CU8
154	(base	155	(base
155	+	156	+
156	1))))	157	1))))
157	<< CU8(base + 3);	158	<< CU8(base + 3);
158	base += 4;	159	base += 4;
159	break;	160	break;
160	case ATOM_IIO_END:	161	case ATOM_IIO_END:
161	return temp;	162	return temp;
162	default:	163	default:
163	printk(KERN_INFO "Unknown IIO opcode.\n");	164	printk(KERN_INFO "Unknown IIO opcode.\n");
164	return 0;	165	return 0;
165	}	166	}
166	}	167	}
167		168
168	static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,	169	static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
169	int ptr, uint32_t saved, int print)	170	int ptr, uint32_t saved, int print)
170	{	171	{
171	uint32_t idx, val = 0xCDCDCDCD, align, arg;	172	uint32_t idx, val = 0xCDCDCDCD, align, arg;
172	struct atom_context *gctx = ctx->ctx;	173	struct atom_context *gctx = ctx->ctx;
173	arg = attr & 7;	174	arg = attr & 7;
174	align = (attr >> 3) & 7;	175	align = (attr >> 3) & 7;
175	switch (arg) {	176	switch (arg) {
176	case ATOM_ARG_REG:	177	case ATOM_ARG_REG:
177	idx = U16(*ptr);	178	idx = U16(*ptr);
178	(*ptr) += 2;	179	(*ptr) += 2;
179	if (print)	180	if (print)
180	DEBUG("REG[0x%04X]", idx);	181	DEBUG("REG[0x%04X]", idx);
181	idx += gctx->reg_block;	182	idx += gctx->reg_block;
182	switch (gctx->io_mode) {	183	switch (gctx->io_mode) {
183	case ATOM_IO_MM:	184	case ATOM_IO_MM:
184	val = gctx->card->reg_read(gctx->card, idx);	185	val = gctx->card->reg_read(gctx->card, idx);
185	break;	186	break;
186	case ATOM_IO_PCI:	187	case ATOM_IO_PCI:
187	printk(KERN_INFO	188	printk(KERN_INFO
188	"PCI registers are not implemented.\n");	189	"PCI registers are not implemented.\n");
189	return 0;	190	return 0;
190	case ATOM_IO_SYSIO:	191	case ATOM_IO_SYSIO:
191	printk(KERN_INFO	192	printk(KERN_INFO
192	"SYSIO registers are not implemented.\n");	193	"SYSIO registers are not implemented.\n");
193	return 0;	194	return 0;
194	default:	195	default:
195	if (!(gctx->io_mode & 0x80)) {	196	if (!(gctx->io_mode & 0x80)) {
196	printk(KERN_INFO "Bad IO mode.\n");	197	printk(KERN_INFO "Bad IO mode.\n");
197	return 0;	198	return 0;
198	}	199	}
199	if (!gctx->iio[gctx->io_mode & 0x7F]) {	200	if (!gctx->iio[gctx->io_mode & 0x7F]) {
200	printk(KERN_INFO	201	printk(KERN_INFO
201	"Undefined indirect IO read method %d.\n",	202	"Undefined indirect IO read method %d.\n",
202	gctx->io_mode & 0x7F);	203	gctx->io_mode & 0x7F);
203	return 0;	204	return 0;
204	}	205	}
205	val =	206	val =
206	atom_iio_execute(gctx,	207	atom_iio_execute(gctx,
207	gctx->iio[gctx->io_mode & 0x7F],	208	gctx->iio[gctx->io_mode & 0x7F],
208	idx, 0);	209	idx, 0);
209	}	210	}
210	break;	211	break;
211	case ATOM_ARG_PS:	212	case ATOM_ARG_PS:
212	idx = U8(*ptr);	213	idx = U8(*ptr);
213	(*ptr)++;	214	(*ptr)++;
214	val = le32_to_cpu(ctx->ps[idx]);	215	val = le32_to_cpu(ctx->ps[idx]);
215	if (print)	216	if (print)
216	DEBUG("PS[0x%02X,0x%04X]", idx, val);	217	DEBUG("PS[0x%02X,0x%04X]", idx, val);
217	break;	218	break;
218	case ATOM_ARG_WS:	219	case ATOM_ARG_WS:
219	idx = U8(*ptr);	220	idx = U8(*ptr);
220	(*ptr)++;	221	(*ptr)++;
221	if (print)	222	if (print)
222	DEBUG("WS[0x%02X]", idx);	223	DEBUG("WS[0x%02X]", idx);
223	switch (idx) {	224	switch (idx) {
224	case ATOM_WS_QUOTIENT:	225	case ATOM_WS_QUOTIENT:
225	val = gctx->divmul[0];	226	val = gctx->divmul[0];
226	break;	227	break;
227	case ATOM_WS_REMAINDER:	228	case ATOM_WS_REMAINDER:
228	val = gctx->divmul[1];	229	val = gctx->divmul[1];
229	break;	230	break;
230	case ATOM_WS_DATAPTR:	231	case ATOM_WS_DATAPTR:
231	val = gctx->data_block;	232	val = gctx->data_block;
232	break;	233	break;
233	case ATOM_WS_SHIFT:	234	case ATOM_WS_SHIFT:
234	val = gctx->shift;	235	val = gctx->shift;
235	break;	236	break;
236	case ATOM_WS_OR_MASK:	237	case ATOM_WS_OR_MASK:
237	val = 1 << gctx->shift;	238	val = 1 << gctx->shift;
238	break;	239	break;
239	case ATOM_WS_AND_MASK:	240	case ATOM_WS_AND_MASK:
240	val = ~(1 << gctx->shift);	241	val = ~(1 << gctx->shift);
241	break;	242	break;
242	case ATOM_WS_FB_WINDOW:	243	case ATOM_WS_FB_WINDOW:
243	val = gctx->fb_base;	244	val = gctx->fb_base;
244	break;	245	break;
245	case ATOM_WS_ATTRIBUTES:	246	case ATOM_WS_ATTRIBUTES:
246	val = gctx->io_attr;	247	val = gctx->io_attr;
247	break;	248	break;
-		249	case ATOM_WS_REGPTR:
-		250	val = gctx->reg_block;
-		251	break;
248	default:	252	default:
249	val = ctx->ws[idx];	253	val = ctx->ws[idx];
250	}	254	}
251	break;	255	break;
252	case ATOM_ARG_ID:	256	case ATOM_ARG_ID:
253	idx = U16(*ptr);	257	idx = U16(*ptr);
254	(*ptr) += 2;	258	(*ptr) += 2;
255	if (print) {	259	if (print) {
256	if (gctx->data_block)	260	if (gctx->data_block)
257	DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);	261	DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);
258	else	262	else
259	DEBUG("ID[0x%04X]", idx);	263	DEBUG("ID[0x%04X]", idx);
260	}	264	}
261	val = U32(idx + gctx->data_block);	265	val = U32(idx + gctx->data_block);
262	break;	266	break;
263	case ATOM_ARG_FB:	267	case ATOM_ARG_FB:
264	idx = U8(*ptr);	268	idx = U8(*ptr);
265	(*ptr)++;	269	(*ptr)++;
266	val = gctx->scratch[((gctx->fb_base + idx) / 4)];	270	val = gctx->scratch[((gctx->fb_base + idx) / 4)];
267	if (print)	271	if (print)
268	DEBUG("FB[0x%02X]", idx);	272	DEBUG("FB[0x%02X]", idx);
269	break;	273	break;
270	case ATOM_ARG_IMM:	274	case ATOM_ARG_IMM:
271	switch (align) {	275	switch (align) {
272	case ATOM_SRC_DWORD:	276	case ATOM_SRC_DWORD:
273	val = U32(*ptr);	277	val = U32(*ptr);
274	(*ptr) += 4;	278	(*ptr) += 4;
275	if (print)	279	if (print)
276	DEBUG("IMM 0x%08X\n", val);	280	DEBUG("IMM 0x%08X\n", val);
277	return val;	281	return val;
278	case ATOM_SRC_WORD0:	282	case ATOM_SRC_WORD0:
279	case ATOM_SRC_WORD8:	283	case ATOM_SRC_WORD8:
280	case ATOM_SRC_WORD16:	284	case ATOM_SRC_WORD16:
281	val = U16(*ptr);	285	val = U16(*ptr);
282	(*ptr) += 2;	286	(*ptr) += 2;
283	if (print)	287	if (print)
284	DEBUG("IMM 0x%04X\n", val);	288	DEBUG("IMM 0x%04X\n", val);
285	return val;	289	return val;
286	case ATOM_SRC_BYTE0:	290	case ATOM_SRC_BYTE0:
287	case ATOM_SRC_BYTE8:	291	case ATOM_SRC_BYTE8:
288	case ATOM_SRC_BYTE16:	292	case ATOM_SRC_BYTE16:
289	case ATOM_SRC_BYTE24:	293	case ATOM_SRC_BYTE24:
290	val = U8(*ptr);	294	val = U8(*ptr);
291	(*ptr)++;	295	(*ptr)++;
292	if (print)	296	if (print)
293	DEBUG("IMM 0x%02X\n", val);	297	DEBUG("IMM 0x%02X\n", val);
294	return val;	298	return val;
295	}	299	}
296	return 0;	300	return 0;
297	case ATOM_ARG_PLL:	301	case ATOM_ARG_PLL:
298	idx = U8(*ptr);	302	idx = U8(*ptr);
299	(*ptr)++;	303	(*ptr)++;
300	if (print)	304	if (print)
301	DEBUG("PLL[0x%02X]", idx);	305	DEBUG("PLL[0x%02X]", idx);
302	val = gctx->card->pll_read(gctx->card, idx);	306	val = gctx->card->pll_read(gctx->card, idx);
303	break;	307	break;
304	case ATOM_ARG_MC:	308	case ATOM_ARG_MC:
305	idx = U8(*ptr);	309	idx = U8(*ptr);
306	(*ptr)++;	310	(*ptr)++;
307	if (print)	311	if (print)
308	DEBUG("MC[0x%02X]", idx);	312	DEBUG("MC[0x%02X]", idx);
309	val = gctx->card->mc_read(gctx->card, idx);	313	val = gctx->card->mc_read(gctx->card, idx);
310	break;	314	break;
311	}	315	}
312	if (saved)	316	if (saved)
313	*saved = val;	317	*saved = val;
314	val &= atom_arg_mask[align];	318	val &= atom_arg_mask[align];
315	val >>= atom_arg_shift[align];	319	val >>= atom_arg_shift[align];
316	if (print)	320	if (print)
317	switch (align) {	321	switch (align) {
318	case ATOM_SRC_DWORD:	322	case ATOM_SRC_DWORD:
319	DEBUG(".[31:0] -> 0x%08X\n", val);	323	DEBUG(".[31:0] -> 0x%08X\n", val);
320	break;	324	break;
321	case ATOM_SRC_WORD0:	325	case ATOM_SRC_WORD0:
322	DEBUG(".[15:0] -> 0x%04X\n", val);	326	DEBUG(".[15:0] -> 0x%04X\n", val);
323	break;	327	break;
324	case ATOM_SRC_WORD8:	328	case ATOM_SRC_WORD8:
325	DEBUG(".[23:8] -> 0x%04X\n", val);	329	DEBUG(".[23:8] -> 0x%04X\n", val);
326	break;	330	break;
327	case ATOM_SRC_WORD16:	331	case ATOM_SRC_WORD16:
328	DEBUG(".[31:16] -> 0x%04X\n", val);	332	DEBUG(".[31:16] -> 0x%04X\n", val);
329	break;	333	break;
330	case ATOM_SRC_BYTE0:	334	case ATOM_SRC_BYTE0:
331	DEBUG(".[7:0] -> 0x%02X\n", val);	335	DEBUG(".[7:0] -> 0x%02X\n", val);
332	break;	336	break;
333	case ATOM_SRC_BYTE8:	337	case ATOM_SRC_BYTE8:
334	DEBUG(".[15:8] -> 0x%02X\n", val);	338	DEBUG(".[15:8] -> 0x%02X\n", val);
335	break;	339	break;
336	case ATOM_SRC_BYTE16:	340	case ATOM_SRC_BYTE16:
337	DEBUG(".[23:16] -> 0x%02X\n", val);	341	DEBUG(".[23:16] -> 0x%02X\n", val);
338	break;	342	break;
339	case ATOM_SRC_BYTE24:	343	case ATOM_SRC_BYTE24:
340	DEBUG(".[31:24] -> 0x%02X\n", val);	344	DEBUG(".[31:24] -> 0x%02X\n", val);
341	break;	345	break;
342	}	346	}
343	return val;	347	return val;
344	}	348	}
345		349
346	static void atom_skip_src_int(atom_exec_context ctx, uint8_t attr, int ptr)	350	static void atom_skip_src_int(atom_exec_context ctx, uint8_t attr, int ptr)
347	{	351	{
348	uint32_t align = (attr >> 3) & 7, arg = attr & 7;	352	uint32_t align = (attr >> 3) & 7, arg = attr & 7;
349	switch (arg) {	353	switch (arg) {
350	case ATOM_ARG_REG:	354	case ATOM_ARG_REG:
351	case ATOM_ARG_ID:	355	case ATOM_ARG_ID:
352	(*ptr) += 2;	356	(*ptr) += 2;
353	break;	357	break;
354	case ATOM_ARG_PLL:	358	case ATOM_ARG_PLL:
355	case ATOM_ARG_MC:	359	case ATOM_ARG_MC:
356	case ATOM_ARG_PS:	360	case ATOM_ARG_PS:
357	case ATOM_ARG_WS:	361	case ATOM_ARG_WS:
358	case ATOM_ARG_FB:	362	case ATOM_ARG_FB:
359	(*ptr)++;	363	(*ptr)++;
360	break;	364	break;
361	case ATOM_ARG_IMM:	365	case ATOM_ARG_IMM:
362	switch (align) {	366	switch (align) {
363	case ATOM_SRC_DWORD:	367	case ATOM_SRC_DWORD:
364	(*ptr) += 4;	368	(*ptr) += 4;
365	return;	369	return;
366	case ATOM_SRC_WORD0:	370	case ATOM_SRC_WORD0:
367	case ATOM_SRC_WORD8:	371	case ATOM_SRC_WORD8:
368	case ATOM_SRC_WORD16:	372	case ATOM_SRC_WORD16:
369	(*ptr) += 2;	373	(*ptr) += 2;
370	return;	374	return;
371	case ATOM_SRC_BYTE0:	375	case ATOM_SRC_BYTE0:
372	case ATOM_SRC_BYTE8:	376	case ATOM_SRC_BYTE8:
373	case ATOM_SRC_BYTE16:	377	case ATOM_SRC_BYTE16:
374	case ATOM_SRC_BYTE24:	378	case ATOM_SRC_BYTE24:
375	(*ptr)++;	379	(*ptr)++;
376	return;	380	return;
377	}	381	}
378	return;	382	return;
379	}	383	}
380	}	384	}
381		385
382	static uint32_t atom_get_src(atom_exec_context ctx, uint8_t attr, int ptr)	386	static uint32_t atom_get_src(atom_exec_context ctx, uint8_t attr, int ptr)
383	{	387	{
384	return atom_get_src_int(ctx, attr, ptr, NULL, 1);	388	return atom_get_src_int(ctx, attr, ptr, NULL, 1);
385	}	389	}
-		390
-		391	static uint32_t atom_get_src_direct(atom_exec_context ctx, uint8_t align, int ptr)
-		392	{
-		393	uint32_t val = 0xCDCDCDCD;
-		394
-		395	switch (align) {
-		396	case ATOM_SRC_DWORD:
-		397	val = U32(*ptr);
-		398	(*ptr) += 4;
-		399	break;
-		400	case ATOM_SRC_WORD0:
-		401	case ATOM_SRC_WORD8:
-		402	case ATOM_SRC_WORD16:
-		403	val = U16(*ptr);
-		404	(*ptr) += 2;
-		405	break;
-		406	case ATOM_SRC_BYTE0:
-		407	case ATOM_SRC_BYTE8:
-		408	case ATOM_SRC_BYTE16:
-		409	case ATOM_SRC_BYTE24:
-		410	val = U8(*ptr);
-		411	(*ptr)++;
-		412	break;
-		413	}
-		414	return val;
-		415	}
386		416
387	static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,	417	static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
388	int ptr, uint32_t saved, int print)	418	int ptr, uint32_t saved, int print)
389	{	419	{
390	return atom_get_src_int(ctx,	420	return atom_get_src_int(ctx,
391	arg \| atom_dst_to_src[(attr >> 3) &	421	arg \| atom_dst_to_src[(attr >> 3) &
392	7][(attr >> 6) & 3] << 3,	422	7][(attr >> 6) & 3] << 3,
393	ptr, saved, print);	423	ptr, saved, print);
394	}	424	}
395		425
396	static void atom_skip_dst(atom_exec_context ctx, int arg, uint8_t attr, int ptr)	426	static void atom_skip_dst(atom_exec_context ctx, int arg, uint8_t attr, int ptr)
397	{	427	{
398	atom_skip_src_int(ctx,	428	atom_skip_src_int(ctx,
399	arg \| atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &	429	arg \| atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &
400	3] << 3, ptr);	430	3] << 3, ptr);
401	}	431	}
402		432
403	static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,	433	static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
404	int *ptr, uint32_t val, uint32_t saved)	434	int *ptr, uint32_t val, uint32_t saved)
405	{	435	{
406	uint32_t align =	436	uint32_t align =
407	atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =	437	atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =
408	val, idx;	438	val, idx;
409	struct atom_context *gctx = ctx->ctx;	439	struct atom_context *gctx = ctx->ctx;
410	old_val &= atom_arg_mask[align] >> atom_arg_shift[align];	440	old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
411	val <<= atom_arg_shift[align];	441	val <<= atom_arg_shift[align];
412	val &= atom_arg_mask[align];	442	val &= atom_arg_mask[align];
413	saved &= ~atom_arg_mask[align];	443	saved &= ~atom_arg_mask[align];
414	val \|= saved;	444	val \|= saved;
415	switch (arg) {	445	switch (arg) {
416	case ATOM_ARG_REG:	446	case ATOM_ARG_REG:
417	idx = U16(*ptr);	447	idx = U16(*ptr);
418	(*ptr) += 2;	448	(*ptr) += 2;
419	DEBUG("REG[0x%04X]", idx);	449	DEBUG("REG[0x%04X]", idx);
420	idx += gctx->reg_block;	450	idx += gctx->reg_block;
421	switch (gctx->io_mode) {	451	switch (gctx->io_mode) {
422	case ATOM_IO_MM:	452	case ATOM_IO_MM:
423	if (idx == 0)	453	if (idx == 0)
424	gctx->card->reg_write(gctx->card, idx,	454	gctx->card->reg_write(gctx->card, idx,
425	val << 2);	455	val << 2);
426	else	456	else
427	gctx->card->reg_write(gctx->card, idx, val);	457	gctx->card->reg_write(gctx->card, idx, val);
428	break;	458	break;
429	case ATOM_IO_PCI:	459	case ATOM_IO_PCI:
430	printk(KERN_INFO	460	printk(KERN_INFO
431	"PCI registers are not implemented.\n");	461	"PCI registers are not implemented.\n");
432	return;	462	return;
433	case ATOM_IO_SYSIO:	463	case ATOM_IO_SYSIO:
434	printk(KERN_INFO	464	printk(KERN_INFO
435	"SYSIO registers are not implemented.\n");	465	"SYSIO registers are not implemented.\n");
436	return;	466	return;
437	default:	467	default:
438	if (!(gctx->io_mode & 0x80)) {	468	if (!(gctx->io_mode & 0x80)) {
439	printk(KERN_INFO "Bad IO mode.\n");	469	printk(KERN_INFO "Bad IO mode.\n");
440	return;	470	return;
441	}	471	}
442	if (!gctx->iio[gctx->io_mode & 0xFF]) {	472	if (!gctx->iio[gctx->io_mode & 0xFF]) {
443	printk(KERN_INFO	473	printk(KERN_INFO
444	"Undefined indirect IO write method %d.\n",	474	"Undefined indirect IO write method %d.\n",
445	gctx->io_mode & 0x7F);	475	gctx->io_mode & 0x7F);
446	return;	476	return;
447	}	477	}
448	atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],	478	atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],
449	idx, val);	479	idx, val);
450	}	480	}
451	break;	481	break;
452	case ATOM_ARG_PS:	482	case ATOM_ARG_PS:
453	idx = U8(*ptr);	483	idx = U8(*ptr);
454	(*ptr)++;	484	(*ptr)++;
455	DEBUG("PS[0x%02X]", idx);	485	DEBUG("PS[0x%02X]", idx);
456	ctx->ps[idx] = cpu_to_le32(val);	486	ctx->ps[idx] = cpu_to_le32(val);
457	break;	487	break;
458	case ATOM_ARG_WS:	488	case ATOM_ARG_WS:
459	idx = U8(*ptr);	489	idx = U8(*ptr);
460	(*ptr)++;	490	(*ptr)++;
461	DEBUG("WS[0x%02X]", idx);	491	DEBUG("WS[0x%02X]", idx);
462	switch (idx) {	492	switch (idx) {
463	case ATOM_WS_QUOTIENT:	493	case ATOM_WS_QUOTIENT:
464	gctx->divmul[0] = val;	494	gctx->divmul[0] = val;
465	break;	495	break;
466	case ATOM_WS_REMAINDER:	496	case ATOM_WS_REMAINDER:
467	gctx->divmul[1] = val;	497	gctx->divmul[1] = val;
468	break;	498	break;
469	case ATOM_WS_DATAPTR:	499	case ATOM_WS_DATAPTR:
470	gctx->data_block = val;	500	gctx->data_block = val;

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(root)/drivers/video/drm/radeon/atom.c – Rev 1321 → 1403