WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/pci.c


#include 
 
#include 
#include 
#include 
#include 
#include 
 
#include 
 
extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn);
 
static LIST_HEAD(devices);
 
/* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
#define IORESOURCE_PCI_FIXED            (1<<4)  /* Do not move resource */
 
#define LEGACY_IO_RESOURCE      (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
 
#define IORESOURCE_ROM_COPY             (1<<2)  /* ROM is alloc'd copy, resource field overlaid */
#define IORESOURCE_ROM_BIOS_COPY        (1<<3)  /* ROM is BIOS copy, resource field overlaid */
 
/*
 * Translate the low bits of the PCI base
 * to the resource type
 */
static inline unsigned int pci_calc_resource_flags(unsigned int flags)
{
    if (flags & PCI_BASE_ADDRESS_SPACE_IO)
        return IORESOURCE_IO;
 
    if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
        return IORESOURCE_MEM | IORESOURCE_PREFETCH;
 
    return IORESOURCE_MEM;
}
 
 
static u32 pci_size(u32 base, u32 maxbase, u32 mask)
{
    u32 size = mask & maxbase;      /* Find the significant bits */
 
    if (!size)
        return 0;
 
    /* Get the lowest of them to find the decode size, and
       from that the extent.  */
    size = (size & ~(size-1)) - 1;
 
    /* base == maxbase can be valid only if the BAR has
       already been programmed with all 1s.  */
    if (base == maxbase && ((base | size) & mask) != mask)
        return 0;
 
    return size;
}
 
static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
{
    u64 size = mask & maxbase;      /* Find the significant bits */
 
    if (!size)
        return 0;
 
    /* Get the lowest of them to find the decode size, and
       from that the extent.  */
    size = (size & ~(size-1)) - 1;
 
    /* base == maxbase can be valid only if the BAR has
       already been programmed with all 1s.  */
    if (base == maxbase && ((base | size) & mask) != mask)
        return 0;
 
    return size;
}
 
static inline int is_64bit_memory(u32 mask)
{
    if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
        (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
        return 1;
    return 0;
}
 
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
{
    u32  pos, reg, next;
    u32  l, sz;
    struct resource *res;
 
    for(pos=0; pos < howmany; pos = next)
    {
        u64  l64;
        u64  sz64;
        u32  raw_sz;
 
        next = pos + 1;
 
        res  = &dev->resource[pos];
 
        reg = PCI_BASE_ADDRESS_0 + (pos << 2);
        l = PciRead32(dev->busnr, dev->devfn, reg);
        PciWrite32(dev->busnr, dev->devfn, reg, ~0);
        sz = PciRead32(dev->busnr, dev->devfn, reg);
        PciWrite32(dev->busnr, dev->devfn, reg, l);
 
        if (!sz || sz == 0xffffffff)
            continue;
 
        if (l == 0xffffffff)
            l = 0;
 
        raw_sz = sz;
        if ((l & PCI_BASE_ADDRESS_SPACE) ==
                        PCI_BASE_ADDRESS_SPACE_MEMORY)
        {
            sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
            /*
             * For 64bit prefetchable memory sz could be 0, if the
             * real size is bigger than 4G, so we need to check
             * szhi for that.
             */
            if (!is_64bit_memory(l) && !sz)
                    continue;
            res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
            res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
        }
        else {
            sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
            if (!sz)
                continue;
            res->start = l & PCI_BASE_ADDRESS_IO_MASK;
            res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
        }
        res->end = res->start + (unsigned long) sz;
        res->flags |= pci_calc_resource_flags(l);
        if (is_64bit_memory(l))
        {
            u32 szhi, lhi;
 
            lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
            PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
            szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
            PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
            sz64 = ((u64)szhi << 32) | raw_sz;
            l64 = ((u64)lhi << 32) | l;
            sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
            next++;
 
#if BITS_PER_LONG == 64
            if (!sz64) {
                res->start = 0;
                res->end = 0;
                res->flags = 0;
                continue;
            }
            res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
            res->end = res->start + sz64;
#else
            if (sz64 > 0x100000000ULL) {
                printk(KERN_ERR "PCI: Unable to handle 64-bit "
                                "BAR for device %s\n", pci_name(dev));
                res->start = 0;
                res->flags = 0;
            }
            else if (lhi)
            {
                /* 64-bit wide address, treat as disabled */
                PciWrite32(dev->busnr, dev->devfn, reg,
                        l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
                PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
                res->start = 0;
                res->end = sz;
            }
#endif
        }
    }
 
    if ( rom )
    {
        dev->rom_base_reg = rom;
        res = &dev->resource[PCI_ROM_RESOURCE];
 
        l = PciRead32(dev->busnr, dev->devfn, rom);
        PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
        sz = PciRead32(dev->busnr, dev->devfn, rom);
        PciWrite32(dev->busnr, dev->devfn, rom, l);
 
        if (l == 0xffffffff)
            l = 0;
 
        if (sz && sz != 0xffffffff)
        {
            sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
 
            if (sz)
            {
                res->flags = (l & IORESOURCE_ROM_ENABLE) |
                                  IORESOURCE_MEM | IORESOURCE_PREFETCH |
                                  IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
                res->start = l & PCI_ROM_ADDRESS_MASK;
                res->end = res->start + (unsigned long) sz;
            }
        }
    }
}
 
static void pci_read_irq(struct pci_dev *dev)
{
    u8 irq;
 
    irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
    dev->pin = irq;
    if (irq)
        irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);
    dev->irq = irq;
};
 
 
int pci_setup_device(struct pci_dev *dev)
{
    u32  class;
 
    class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
    dev->revision = class & 0xff;
    class >>= 8;                                /* upper 3 bytes */
    dev->class = class;
 
    /* "Unknown power state" */
//    dev->current_state = PCI_UNKNOWN;
 
    /* Early fixups, before probing the BARs */
 //   pci_fixup_device(pci_fixup_early, dev);
    class = dev->class >> 8;
 
    switch (dev->hdr_type)
    {
        case PCI_HEADER_TYPE_NORMAL:                /* standard header */
            if (class == PCI_CLASS_BRIDGE_PCI)
                goto bad;
            pci_read_irq(dev);
            pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
            dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
            dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);
 
            /*
             *      Do the ugly legacy mode stuff here rather than broken chip
             *      quirk code. Legacy mode ATA controllers have fixed
             *      addresses. These are not always echoed in BAR0-3, and
             *      BAR0-3 in a few cases contain junk!
             */
            if (class == PCI_CLASS_STORAGE_IDE)
            {
                u8 progif;
 
                progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
                if ((progif & 1) == 0)
                {
                    dev->resource[0].start = 0x1F0;
                    dev->resource[0].end = 0x1F7;
                    dev->resource[0].flags = LEGACY_IO_RESOURCE;
                    dev->resource[1].start = 0x3F6;
                    dev->resource[1].end = 0x3F6;
                    dev->resource[1].flags = LEGACY_IO_RESOURCE;
                }
                if ((progif & 4) == 0)
                {
                    dev->resource[2].start = 0x170;
                    dev->resource[2].end = 0x177;
                    dev->resource[2].flags = LEGACY_IO_RESOURCE;
                    dev->resource[3].start = 0x376;
                    dev->resource[3].end = 0x376;
                    dev->resource[3].flags = LEGACY_IO_RESOURCE;
                };
            }
            break;
 
        case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
                if (class != PCI_CLASS_BRIDGE_PCI)
                        goto bad;
                /* The PCI-to-PCI bridge spec requires that subtractive
                   decoding (i.e. transparent) bridge must have programming
                   interface code of 0x01. */
                pci_read_irq(dev);
                dev->transparent = ((dev->class & 0xff) == 1);
                pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
                break;
 
        case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
                if (class != PCI_CLASS_BRIDGE_CARDBUS)
                        goto bad;
                pci_read_irq(dev);
                pci_read_bases(dev, 1, 0);
                dev->subsystem_vendor = PciRead16(dev->busnr,
                                                  dev->devfn,
                                                  PCI_CB_SUBSYSTEM_VENDOR_ID);
 
                dev->subsystem_device = PciRead16(dev->busnr,
                                                  dev->devfn,
                                                  PCI_CB_SUBSYSTEM_ID);
                break;
 
        default:                                    /* unknown header */
                printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
                        pci_name(dev), dev->hdr_type);
                return -1;
 
        bad:
                printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
                       pci_name(dev), class, dev->hdr_type);
                dev->class = PCI_CLASS_NOT_DEFINED;
    }
 
    /* We found a fine healthy device, go go go... */
 
    return 0;
};
 
static pci_dev_t* pci_scan_device(u32 busnr, int devfn)
{
    pci_dev_t  *dev;
 
    u32   id;
    u8    hdr;
 
    int     timeout = 10;
 
    id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
 
    /* some broken boards return 0 or ~0 if a slot is empty: */
    if (id == 0xffffffff || id == 0x00000000 ||
        id == 0x0000ffff || id == 0xffff0000)
        return NULL;
 
    while (id == 0xffff0001)
    {
 
        delay(timeout/10);
        timeout *= 2;
 
        id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
 
        /* Card hasn't responded in 60 seconds?  Must be stuck. */
        if (timeout > 60 * 100)
        {
            printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
                   "responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));
            return NULL;
        }
    };
 
    if( pci_scan_filter(id, busnr, devfn) == 0)
        return NULL;
 
    hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);
 
    dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);
    if(unlikely(dev == NULL))
        return NULL;
 
    INIT_LIST_HEAD(&dev->link);
 
 
    dev->pci_dev.busnr    = busnr;
    dev->pci_dev.devfn    = devfn;
    dev->pci_dev.hdr_type = hdr & 0x7f;
    dev->pci_dev.multifunction    = !!(hdr & 0x80);
    dev->pci_dev.vendor   = id & 0xffff;
    dev->pci_dev.device   = (id >> 16) & 0xffff;
 
    pci_setup_device(&dev->pci_dev);
 
    return dev;
 
};
 
 
 
 
int _pci_scan_slot(u32 bus, int devfn)
{
    int  func, nr = 0;
 
    for (func = 0; func < 8; func++, devfn++)
    {
        pci_dev_t  *dev;
 
        dev = pci_scan_device(bus, devfn);
        if( dev )
        {
            list_add(&dev->link, &devices);
 
            nr++;
 
            /*
             * If this is a single function device,
             * don't scan past the first function.
             */
            if (!dev->pci_dev.multifunction)
            {
                if (func > 0) {
                    dev->pci_dev.multifunction = 1;
                }
                else {
                    break;
                }
             }
        }
        else {
            if (func == 0)
                break;
        }
    };
 
    return nr;
};
 
#define PCI_FIND_CAP_TTL    48
 
static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,
                   u8 pos, int cap, int *ttl)
{
    u8 id;
 
    while ((*ttl)--) {
        pos = PciRead8(bus, devfn, pos);
        if (pos < 0x40)
            break;
        pos &= ~3;
        id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);
        if (id == 0xff)
            break;
        if (id == cap)
            return pos;
        pos += PCI_CAP_LIST_NEXT;
    }
    return 0;
}
 
static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,
                   u8 pos, int cap)
{
    int ttl = PCI_FIND_CAP_TTL;
 
    return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
}
 
static int __pci_bus_find_cap_start(unsigned int bus,
                    unsigned int devfn, u8 hdr_type)
{
    u16 status;
 
    status = PciRead16(bus, devfn, PCI_STATUS);
    if (!(status & PCI_STATUS_CAP_LIST))
        return 0;
 
    switch (hdr_type) {
    case PCI_HEADER_TYPE_NORMAL:
    case PCI_HEADER_TYPE_BRIDGE:
        return PCI_CAPABILITY_LIST;
    case PCI_HEADER_TYPE_CARDBUS:
        return PCI_CB_CAPABILITY_LIST;
    default:
        return 0;
    }
 
    return 0;
}
 
 
int pci_find_capability(struct pci_dev *dev, int cap)
{
    int pos;
 
    pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);
    if (pos)
        pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);
 
    return pos;
}
 
 
 
 
int enum_pci_devices()
{
    pci_dev_t  *dev;
    u32       last_bus;
    u32       bus = 0 , devfn = 0;
 
 
    last_bus = PciApi(1);
 
 
    if( unlikely(last_bus == -1))
        return -1;
 
    for(;bus <= last_bus; bus++)
    {
        for (devfn = 0; devfn < 0x100; devfn += 8)
            _pci_scan_slot(bus, devfn);
 
 
    }
    for(dev = (pci_dev_t*)devices.next;
        &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        dbgprintf("PCI device %x:%x bus:%x devfn:%x\n",
                dev->pci_dev.vendor,
                dev->pci_dev.device,
                dev->pci_dev.busnr,
                dev->pci_dev.devfn);
 
    }
    return 0;
}
 
const struct pci_device_id* find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist)
{
    pci_dev_t *dev;
    const struct pci_device_id *ent;
 
    for(dev = (pci_dev_t*)devices.next;
        &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if( dev->pci_dev.vendor != idlist->vendor )
            continue;
 
        for(ent = idlist; ent->vendor != 0; ent++)
        {
            if(unlikely(ent->device == dev->pci_dev.device))
            {
                pdev->pci_dev = dev->pci_dev;
                return  ent;
            }
        };
    }
 
    return NULL;
};
 
struct pci_dev *
pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from)
{
    pci_dev_t *dev;
 
    dev = (pci_dev_t*)devices.next;
 
    if(from != NULL)
    {
        for(; &dev->link != &devices;
            dev = (pci_dev_t*)dev->link.next)
        {
            if( &dev->pci_dev == from)
            {
                dev = (pci_dev_t*)dev->link.next;
                break;
            };
        }
    };
 
    for(; &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if( dev->pci_dev.vendor != vendor )
                continue;
 
        if(dev->pci_dev.device == device)
        {
            return &dev->pci_dev;
        }
    }
    return NULL;
};
 
 
struct pci_dev * _pci_get_bus_and_slot(unsigned int bus, unsigned int devfn)
{
    pci_dev_t *dev;
 
    for(dev = (pci_dev_t*)devices.next;
        &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn)
            return &dev->pci_dev;
    }
    return NULL;
}
 
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
{
    pci_dev_t *dev;
 
    dev = (pci_dev_t*)devices.next;
 
    if(from != NULL)
    {
        for(; &dev->link != &devices;
            dev = (pci_dev_t*)dev->link.next)
        {
            if( &dev->pci_dev == from)
            {
                dev = (pci_dev_t*)dev->link.next;
                break;
            };
        }
    };
 
    for(; &dev->link != &devices;
        dev = (pci_dev_t*)dev->link.next)
    {
        if( dev->pci_dev.class == class)
        {
            return &dev->pci_dev;
        }
    }
 
   return NULL;
}
 
 
#define PIO_OFFSET      0x10000UL
#define PIO_MASK        0x0ffffUL
#define PIO_RESERVED    0x40000UL
 
#define IO_COND(addr, is_pio, is_mmio) do {            \
    unsigned long port = (unsigned long __force)addr;  \
    if (port >= PIO_RESERVED) {                        \
        is_mmio;                                       \
    } else if (port > PIO_OFFSET) {                    \
        port &= PIO_MASK;                              \
        is_pio;                                        \
    };                                                 \
} while (0)
 
/* Create a virtual mapping cookie for an IO port range */
void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
    if (port > PIO_MASK)
        return NULL;
    return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
}
 
void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
{
    resource_size_t start = pci_resource_start(dev, bar);
    resource_size_t len = pci_resource_len(dev, bar);
    unsigned long flags = pci_resource_flags(dev, bar);
 
    if (!len || !start)
        return NULL;
    if (maxlen && len > maxlen)
        len = maxlen;
    if (flags & IORESOURCE_IO)
        return ioport_map(start, len);
    if (flags & IORESOURCE_MEM) {
        return ioremap(start, len);
    }
    /* What? */
    return NULL;
}
 
void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
{
    IO_COND(addr, /* nothing */, iounmap(addr));
}
 
 
 
 
int pci_enable_rom(struct pci_dev *pdev)
{
    struct resource *res = pdev->resource + PCI_ROM_RESOURCE;
    struct pci_bus_region region;
    u32 rom_addr;
 
    if (!res->flags)
            return -1;
 
    _pcibios_resource_to_bus(pdev, ®ion, res);
    pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
    rom_addr &= ~PCI_ROM_ADDRESS_MASK;
    rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE;
    pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
    return 0;
}
 
void pci_disable_rom(struct pci_dev *pdev)
{
    u32 rom_addr;
    pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
    rom_addr &= ~PCI_ROM_ADDRESS_ENABLE;
    pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
}
 
/**
 * pci_get_rom_size - obtain the actual size of the ROM image
 * @pdev: target PCI device
 * @rom: kernel virtual pointer to image of ROM
 * @size: size of PCI window
 *  return: size of actual ROM image
 *
 * Determine the actual length of the ROM image.
 * The PCI window size could be much larger than the
 * actual image size.
 */
size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size)
{
        void __iomem *image;
        int last_image;
 
        image = rom;
        do {
                void __iomem *pds;
                /* Standard PCI ROMs start out with these bytes 55 AA */
                if (readb(image) != 0x55) {
                        dev_err(&pdev->dev, "Invalid ROM contents\n");
                        break;
                }
                if (readb(image + 1) != 0xAA)
                        break;
                /* get the PCI data structure and check its signature */
                pds = image + readw(image + 24);
                if (readb(pds) != 'P')
                        break;
                if (readb(pds + 1) != 'C')
                        break;
                if (readb(pds + 2) != 'I')
                        break;
                if (readb(pds + 3) != 'R')
                        break;
                last_image = readb(pds + 21) & 0x80;
                /* this length is reliable */
                image += readw(pds + 16) * 512;
        } while (!last_image);
 
        /* never return a size larger than the PCI resource window */
        /* there are known ROMs that get the size wrong */
        return min((size_t)(image - rom), size);
}
 
 
/**
 * pci_map_rom - map a PCI ROM to kernel space
 * @pdev: pointer to pci device struct
 * @size: pointer to receive size of pci window over ROM
 *
 * Return: kernel virtual pointer to image of ROM
 *
 * Map a PCI ROM into kernel space. If ROM is boot video ROM,
 * the shadow BIOS copy will be returned instead of the
 * actual ROM.
 */
void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
{
    struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
    loff_t start;
    void __iomem *rom;
 
    /*
     * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy
     * memory map if the VGA enable bit of the Bridge Control register is
     * set for embedded VGA.
     */
    if (res->flags & IORESOURCE_ROM_SHADOW) {
        /* primary video rom always starts here */
        start = (loff_t)0xC0000;
        *size = 0x20000; /* cover C000:0 through E000:0 */
    } else {
                if (res->flags &
                        (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) {
            *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
             return (void __iomem *)(unsigned long)
             pci_resource_start(pdev, PCI_ROM_RESOURCE);
        } else {
    				start = (loff_t)0xC0000;
    				*size = 0x20000; /* cover C000:0 through E000:0 */
 
        }
    }
 
    rom = ioremap(start, *size);
    if (!rom) {
            /* restore enable if ioremap fails */
            if (!(res->flags & (IORESOURCE_ROM_ENABLE |
                                IORESOURCE_ROM_SHADOW |
                                IORESOURCE_ROM_COPY)))
                    pci_disable_rom(pdev);
            return NULL;
    }
 
    /*
     * Try to find the true size of the ROM since sometimes the PCI window
     * size is much larger than the actual size of the ROM.
     * True size is important if the ROM is going to be copied.
     */
    *size = pci_get_rom_size(pdev, rom, *size);
    return rom;
}
 
void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
{
    struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
 
    if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY))
            return;
 
    iounmap(rom);
 
    /* Disable again before continuing, leave enabled if pci=rom */
    if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW)))
            pci_disable_rom(pdev);
}
 
static void __pci_set_master(struct pci_dev *dev, bool enable)
{
    u16 old_cmd, cmd;
 
    pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
    if (enable)
        cmd = old_cmd | PCI_COMMAND_MASTER;
    else
        cmd = old_cmd & ~PCI_COMMAND_MASTER;
    if (cmd != old_cmd) {
            dbgprintf("%s bus mastering\n",
                    enable ? "enabling" : "disabling");
        pci_write_config_word(dev, PCI_COMMAND, cmd);
        }
    dev->is_busmaster = enable;
}
 
 
/* pci_set_master - enables bus-mastering for device dev
 * @dev: the PCI device to enable
 *
 * Enables bus-mastering on the device and calls pcibios_set_master()
 * to do the needed arch specific settings.
 */
void pci_set_master(struct pci_dev *dev)
{
        __pci_set_master(dev, true);
//        pcibios_set_master(dev);
}
 
/**
 * pci_clear_master - disables bus-mastering for device dev
 * @dev: the PCI device to disable
 */
void pci_clear_master(struct pci_dev *dev)
{
        __pci_set_master(dev, false);
}
 
 
static inline int pcie_cap_version(const struct pci_dev *dev)
{
    return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS;
}
 
static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
{
    return true;
}
 
static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
{
    int type = pci_pcie_type(dev);
 
    return pcie_cap_version(dev) > 1 ||
           type == PCI_EXP_TYPE_ROOT_PORT ||
           type == PCI_EXP_TYPE_ENDPOINT ||
           type == PCI_EXP_TYPE_LEG_END;
}
 
static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
{
    int type = pci_pcie_type(dev);
 
    return pcie_cap_version(dev) > 1 ||
           type == PCI_EXP_TYPE_ROOT_PORT ||
           (type == PCI_EXP_TYPE_DOWNSTREAM &&
        dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT);
}
 
static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
{
    int type = pci_pcie_type(dev);
 
    return pcie_cap_version(dev) > 1 ||
           type == PCI_EXP_TYPE_ROOT_PORT ||
           type == PCI_EXP_TYPE_RC_EC;
}
 
static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
{
    if (!pci_is_pcie(dev))
        return false;
 
    switch (pos) {
    case PCI_EXP_FLAGS_TYPE:
        return true;
    case PCI_EXP_DEVCAP:
    case PCI_EXP_DEVCTL:
    case PCI_EXP_DEVSTA:
        return pcie_cap_has_devctl(dev);
    case PCI_EXP_LNKCAP:
    case PCI_EXP_LNKCTL:
    case PCI_EXP_LNKSTA:
        return pcie_cap_has_lnkctl(dev);
    case PCI_EXP_SLTCAP:
    case PCI_EXP_SLTCTL:
    case PCI_EXP_SLTSTA:
        return pcie_cap_has_sltctl(dev);
    case PCI_EXP_RTCTL:
    case PCI_EXP_RTCAP:
    case PCI_EXP_RTSTA:
        return pcie_cap_has_rtctl(dev);
    case PCI_EXP_DEVCAP2:
    case PCI_EXP_DEVCTL2:
    case PCI_EXP_LNKCAP2:
    case PCI_EXP_LNKCTL2:
    case PCI_EXP_LNKSTA2:
        return pcie_cap_version(dev) > 1;
    default:
        return false;
    }
}
 
/*
 * Note that these accessor functions are only for the "PCI Express
 * Capability" (see PCIe spec r3.0, sec 7.8).  They do not apply to the
 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
 */
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
{
    int ret;
 
    *val = 0;
    if (pos & 1)
        return -EINVAL;
 
    if (pcie_capability_reg_implemented(dev, pos)) {
        ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
        /*
         * Reset *val to 0 if pci_read_config_word() fails, it may
         * have been written as 0xFFFF if hardware error happens
         * during pci_read_config_word().
         */
        if (ret)
            *val = 0;
        return ret;
    }
 
    /*
     * For Functions that do not implement the Slot Capabilities,
     * Slot Status, and Slot Control registers, these spaces must
     * be hardwired to 0b, with the exception of the Presence Detect
     * State bit in the Slot Status register of Downstream Ports,
     * which must be hardwired to 1b.  (PCIe Base Spec 3.0, sec 7.8)
     */
    if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
         pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
        *val = PCI_EXP_SLTSTA_PDS;
    }
 
    return 0;
}
EXPORT_SYMBOL(pcie_capability_read_word);
 
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
{
    int ret;
 
    *val = 0;
    if (pos & 3)
        return -EINVAL;
 
    if (pcie_capability_reg_implemented(dev, pos)) {
        ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
        /*
         * Reset *val to 0 if pci_read_config_dword() fails, it may
         * have been written as 0xFFFFFFFF if hardware error happens
         * during pci_read_config_dword().
         */
        if (ret)
            *val = 0;
        return ret;
    }
 
    if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
         pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
        *val = PCI_EXP_SLTSTA_PDS;
    }
 
    return 0;
}
EXPORT_SYMBOL(pcie_capability_read_dword);
 
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
{
    if (pos & 1)
        return -EINVAL;
 
    if (!pcie_capability_reg_implemented(dev, pos))
        return 0;
 
    return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
}
EXPORT_SYMBOL(pcie_capability_write_word);
 
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
{
    if (pos & 3)
        return -EINVAL;
 
    if (!pcie_capability_reg_implemented(dev, pos))
        return 0;
 
    return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
}
EXPORT_SYMBOL(pcie_capability_write_dword);
 
int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
                                       u16 clear, u16 set)
{
        int ret;
        u16 val;
 
        ret = pcie_capability_read_word(dev, pos, &val);
        if (!ret) {
                val &= ~clear;
                val |= set;
                ret = pcie_capability_write_word(dev, pos, val);
        }
 
        return ret;
}
 
 
 
int pcie_get_readrq(struct pci_dev *dev)
{
        u16 ctl;
 
        pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
 
        return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
}
EXPORT_SYMBOL(pcie_get_readrq);
 
/**
 * pcie_set_readrq - set PCI Express maximum memory read request
 * @dev: PCI device to query
 * @rq: maximum memory read count in bytes
 *    valid values are 128, 256, 512, 1024, 2048, 4096
 *
 * If possible sets maximum memory read request in bytes
 */
int pcie_set_readrq(struct pci_dev *dev, int rq)
{
        u16 v;
 
        if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
                return -EINVAL;
 
        v = (ffs(rq) - 8) << 12;
 
        return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
                                                  PCI_EXP_DEVCTL_READRQ, v);
}

Rev 6131	Rev 7144
1	#include	1	#include
2		2
3	#include	3	#include
4	#include	4	#include
5	#include	5	#include
6	#include	6	#include
7	#include	7	#include
8		8
9	#include	9	#include
10		10
11	extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn);	11	extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn);
12		12
13	static LIST_HEAD(devices);	13	static LIST_HEAD(devices);
14		14
15	/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */	15	/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */
16	#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */	16	#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */
17		17
18	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)	18	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)
-		19
-		20	#define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */
-		21	#define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */
19		22
20	/*	23	/*
21	* Translate the low bits of the PCI base	24	* Translate the low bits of the PCI base
22	* to the resource type	25	* to the resource type
23	*/	26	*/
24	static inline unsigned int pci_calc_resource_flags(unsigned int flags)	27	static inline unsigned int pci_calc_resource_flags(unsigned int flags)
25	{	28	{
26	if (flags & PCI_BASE_ADDRESS_SPACE_IO)	29	if (flags & PCI_BASE_ADDRESS_SPACE_IO)
27	return IORESOURCE_IO;	30	return IORESOURCE_IO;
28		31
29	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)	32	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
30	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;	33	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;
31		34
32	return IORESOURCE_MEM;	35	return IORESOURCE_MEM;
33	}	36	}
34		37
35		38
36	static u32 pci_size(u32 base, u32 maxbase, u32 mask)	39	static u32 pci_size(u32 base, u32 maxbase, u32 mask)
37	{	40	{
38	u32 size = mask & maxbase; /* Find the significant bits */	41	u32 size = mask & maxbase; /* Find the significant bits */
39		42
40	if (!size)	43	if (!size)
41	return 0;	44	return 0;
42		45
43	/* Get the lowest of them to find the decode size, and	46	/* Get the lowest of them to find the decode size, and
44	from that the extent. */	47	from that the extent. */
45	size = (size & ~(size-1)) - 1;	48	size = (size & ~(size-1)) - 1;
46		49
47	/* base == maxbase can be valid only if the BAR has	50	/* base == maxbase can be valid only if the BAR has
48	already been programmed with all 1s. */	51	already been programmed with all 1s. */
49	if (base == maxbase && ((base \| size) & mask) != mask)	52	if (base == maxbase && ((base \| size) & mask) != mask)
50	return 0;	53	return 0;
51		54
52	return size;	55	return size;
53	}	56	}
54		57
55	static u64 pci_size64(u64 base, u64 maxbase, u64 mask)	58	static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
56	{	59	{
57	u64 size = mask & maxbase; /* Find the significant bits */	60	u64 size = mask & maxbase; /* Find the significant bits */
58		61
59	if (!size)	62	if (!size)
60	return 0;	63	return 0;
61		64
62	/* Get the lowest of them to find the decode size, and	65	/* Get the lowest of them to find the decode size, and
63	from that the extent. */	66	from that the extent. */
64	size = (size & ~(size-1)) - 1;	67	size = (size & ~(size-1)) - 1;
65		68
66	/* base == maxbase can be valid only if the BAR has	69	/* base == maxbase can be valid only if the BAR has
67	already been programmed with all 1s. */	70	already been programmed with all 1s. */
68	if (base == maxbase && ((base \| size) & mask) != mask)	71	if (base == maxbase && ((base \| size) & mask) != mask)
69	return 0;	72	return 0;
70		73
71	return size;	74	return size;
72	}	75	}
73		76
74	static inline int is_64bit_memory(u32 mask)	77	static inline int is_64bit_memory(u32 mask)
75	{	78	{
76	if ((mask & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==	79	if ((mask & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
77	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64))	80	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64))
78	return 1;	81	return 1;
79	return 0;	82	return 0;
80	}	83	}
81		84
82	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)	85	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
83	{	86	{
84	u32 pos, reg, next;	87	u32 pos, reg, next;
85	u32 l, sz;	88	u32 l, sz;
86	struct resource *res;	89	struct resource *res;
87		90
88	for(pos=0; pos < howmany; pos = next)	91	for(pos=0; pos < howmany; pos = next)
89	{	92	{
90	u64 l64;	93	u64 l64;
91	u64 sz64;	94	u64 sz64;
92	u32 raw_sz;	95	u32 raw_sz;
93		96
94	next = pos + 1;	97	next = pos + 1;
95		98
96	res = &dev->resource[pos];	99	res = &dev->resource[pos];
97		100
98	reg = PCI_BASE_ADDRESS_0 + (pos << 2);	101	reg = PCI_BASE_ADDRESS_0 + (pos << 2);
99	l = PciRead32(dev->busnr, dev->devfn, reg);	102	l = PciRead32(dev->busnr, dev->devfn, reg);
100	PciWrite32(dev->busnr, dev->devfn, reg, ~0);	103	PciWrite32(dev->busnr, dev->devfn, reg, ~0);
101	sz = PciRead32(dev->busnr, dev->devfn, reg);	104	sz = PciRead32(dev->busnr, dev->devfn, reg);
102	PciWrite32(dev->busnr, dev->devfn, reg, l);	105	PciWrite32(dev->busnr, dev->devfn, reg, l);
103		106
104	if (!sz \|\| sz == 0xffffffff)	107	if (!sz \|\| sz == 0xffffffff)
105	continue;	108	continue;
106		109
107	if (l == 0xffffffff)	110	if (l == 0xffffffff)
108	l = 0;	111	l = 0;
109		112
110	raw_sz = sz;	113	raw_sz = sz;
111	if ((l & PCI_BASE_ADDRESS_SPACE) ==	114	if ((l & PCI_BASE_ADDRESS_SPACE) ==
112	PCI_BASE_ADDRESS_SPACE_MEMORY)	115	PCI_BASE_ADDRESS_SPACE_MEMORY)
113	{	116	{
114	sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);	117	sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
115	/*	118	/*
116	* For 64bit prefetchable memory sz could be 0, if the	119	* For 64bit prefetchable memory sz could be 0, if the
117	* real size is bigger than 4G, so we need to check	120	* real size is bigger than 4G, so we need to check
118	* szhi for that.	121	* szhi for that.
119	*/	122	*/
120	if (!is_64bit_memory(l) && !sz)	123	if (!is_64bit_memory(l) && !sz)
121	continue;	124	continue;
122	res->start = l & PCI_BASE_ADDRESS_MEM_MASK;	125	res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
123	res->flags \|= l & ~PCI_BASE_ADDRESS_MEM_MASK;	126	res->flags \|= l & ~PCI_BASE_ADDRESS_MEM_MASK;
124	}	127	}
125	else {	128	else {
126	sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);	129	sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
127	if (!sz)	130	if (!sz)
128	continue;	131	continue;
129	res->start = l & PCI_BASE_ADDRESS_IO_MASK;	132	res->start = l & PCI_BASE_ADDRESS_IO_MASK;
130	res->flags \|= l & ~PCI_BASE_ADDRESS_IO_MASK;	133	res->flags \|= l & ~PCI_BASE_ADDRESS_IO_MASK;
131	}	134	}
132	res->end = res->start + (unsigned long) sz;	135	res->end = res->start + (unsigned long) sz;
133	res->flags \|= pci_calc_resource_flags(l);	136	res->flags \|= pci_calc_resource_flags(l);
134	if (is_64bit_memory(l))	137	if (is_64bit_memory(l))
135	{	138	{
136	u32 szhi, lhi;	139	u32 szhi, lhi;
137		140
138	lhi = PciRead32(dev->busnr, dev->devfn, reg+4);	141	lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
139	PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);	142	PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
140	szhi = PciRead32(dev->busnr, dev->devfn, reg+4);	143	szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
141	PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);	144	PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
142	sz64 = ((u64)szhi << 32) \| raw_sz;	145	sz64 = ((u64)szhi << 32) \| raw_sz;
143	l64 = ((u64)lhi << 32) \| l;	146	l64 = ((u64)lhi << 32) \| l;
144	sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);	147	sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
145	next++;	148	next++;
146		149
147	#if BITS_PER_LONG == 64	150	#if BITS_PER_LONG == 64
148	if (!sz64) {	151	if (!sz64) {
149	res->start = 0;	152	res->start = 0;
150	res->end = 0;	153	res->end = 0;
151	res->flags = 0;	154	res->flags = 0;
152	continue;	155	continue;
153	}	156	}
154	res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;	157	res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
155	res->end = res->start + sz64;	158	res->end = res->start + sz64;
156	#else	159	#else
157	if (sz64 > 0x100000000ULL) {	160	if (sz64 > 0x100000000ULL) {
158	printk(KERN_ERR "PCI: Unable to handle 64-bit "	161	printk(KERN_ERR "PCI: Unable to handle 64-bit "
159	"BAR for device %s\n", pci_name(dev));	162	"BAR for device %s\n", pci_name(dev));
160	res->start = 0;	163	res->start = 0;
161	res->flags = 0;	164	res->flags = 0;
162	}	165	}
163	else if (lhi)	166	else if (lhi)
164	{	167	{
165	/* 64-bit wide address, treat as disabled */	168	/* 64-bit wide address, treat as disabled */
166	PciWrite32(dev->busnr, dev->devfn, reg,	169	PciWrite32(dev->busnr, dev->devfn, reg,
167	l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);	170	l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
168	PciWrite32(dev->busnr, dev->devfn, reg+4, 0);	171	PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
169	res->start = 0;	172	res->start = 0;
170	res->end = sz;	173	res->end = sz;
171	}	174	}
172	#endif	175	#endif
173	}	176	}
174	}	177	}
175		178
176	if ( rom )	179	if ( rom )
177	{	180	{
178	dev->rom_base_reg = rom;	181	dev->rom_base_reg = rom;
179	res = &dev->resource[PCI_ROM_RESOURCE];	182	res = &dev->resource[PCI_ROM_RESOURCE];
180		183
181	l = PciRead32(dev->busnr, dev->devfn, rom);	184	l = PciRead32(dev->busnr, dev->devfn, rom);
182	PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);	185	PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
183	sz = PciRead32(dev->busnr, dev->devfn, rom);	186	sz = PciRead32(dev->busnr, dev->devfn, rom);
184	PciWrite32(dev->busnr, dev->devfn, rom, l);	187	PciWrite32(dev->busnr, dev->devfn, rom, l);
185		188
186	if (l == 0xffffffff)	189	if (l == 0xffffffff)
187	l = 0;	190	l = 0;
188		191
189	if (sz && sz != 0xffffffff)	192	if (sz && sz != 0xffffffff)
190	{	193	{
191	sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);	194	sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
192		195
193	if (sz)	196	if (sz)
194	{	197	{
195	res->flags = (l & IORESOURCE_ROM_ENABLE) \|	198	res->flags = (l & IORESOURCE_ROM_ENABLE) \|
196	IORESOURCE_MEM \| IORESOURCE_PREFETCH \|	199	IORESOURCE_MEM \| IORESOURCE_PREFETCH \|
197	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE;	200	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE;
198	res->start = l & PCI_ROM_ADDRESS_MASK;	201	res->start = l & PCI_ROM_ADDRESS_MASK;
199	res->end = res->start + (unsigned long) sz;	202	res->end = res->start + (unsigned long) sz;
200	}	203	}
201	}	204	}
202	}	205	}
203	}	206	}
204		207
205	static void pci_read_irq(struct pci_dev *dev)	208	static void pci_read_irq(struct pci_dev *dev)
206	{	209	{
207	u8 irq;	210	u8 irq;
208		211
209	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);	212	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
210	dev->pin = irq;	213	dev->pin = irq;
211	if (irq)	214	if (irq)
212	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);	215	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);
213	dev->irq = irq;	216	dev->irq = irq;
214	};	217	};
215		218
216		219
217	int pci_setup_device(struct pci_dev *dev)	220	int pci_setup_device(struct pci_dev *dev)
218	{	221	{
219	u32 class;	222	u32 class;
220		223
221	class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);	224	class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
222	dev->revision = class & 0xff;	225	dev->revision = class & 0xff;
223	class >>= 8; /* upper 3 bytes */	226	class >>= 8; /* upper 3 bytes */
224	dev->class = class;	227	dev->class = class;
225		228
226	/* "Unknown power state" */	229	/* "Unknown power state" */
227	// dev->current_state = PCI_UNKNOWN;	230	// dev->current_state = PCI_UNKNOWN;
228		231
229	/* Early fixups, before probing the BARs */	232	/* Early fixups, before probing the BARs */
230	// pci_fixup_device(pci_fixup_early, dev);	233	// pci_fixup_device(pci_fixup_early, dev);
231	class = dev->class >> 8;	234	class = dev->class >> 8;
232		235
233	switch (dev->hdr_type)	236	switch (dev->hdr_type)
234	{	237	{
235	case PCI_HEADER_TYPE_NORMAL: /* standard header */	238	case PCI_HEADER_TYPE_NORMAL: /* standard header */
236	if (class == PCI_CLASS_BRIDGE_PCI)	239	if (class == PCI_CLASS_BRIDGE_PCI)
237	goto bad;	240	goto bad;
238	pci_read_irq(dev);	241	pci_read_irq(dev);
239	pci_read_bases(dev, 6, PCI_ROM_ADDRESS);	242	pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
240	dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);	243	dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
241	dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);	244	dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);
242		245
243	/*	246	/*
244	* Do the ugly legacy mode stuff here rather than broken chip	247	* Do the ugly legacy mode stuff here rather than broken chip
245	* quirk code. Legacy mode ATA controllers have fixed	248	* quirk code. Legacy mode ATA controllers have fixed
246	* addresses. These are not always echoed in BAR0-3, and	249	* addresses. These are not always echoed in BAR0-3, and
247	* BAR0-3 in a few cases contain junk!	250	* BAR0-3 in a few cases contain junk!
248	*/	251	*/
249	if (class == PCI_CLASS_STORAGE_IDE)	252	if (class == PCI_CLASS_STORAGE_IDE)
250	{	253	{
251	u8 progif;	254	u8 progif;
252		255
253	progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);	256	progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
254	if ((progif & 1) == 0)	257	if ((progif & 1) == 0)
255	{	258	{
256	dev->resource[0].start = 0x1F0;	259	dev->resource[0].start = 0x1F0;
257	dev->resource[0].end = 0x1F7;	260	dev->resource[0].end = 0x1F7;
258	dev->resource[0].flags = LEGACY_IO_RESOURCE;	261	dev->resource[0].flags = LEGACY_IO_RESOURCE;
259	dev->resource[1].start = 0x3F6;	262	dev->resource[1].start = 0x3F6;
260	dev->resource[1].end = 0x3F6;	263	dev->resource[1].end = 0x3F6;
261	dev->resource[1].flags = LEGACY_IO_RESOURCE;	264	dev->resource[1].flags = LEGACY_IO_RESOURCE;
262	}	265	}
263	if ((progif & 4) == 0)	266	if ((progif & 4) == 0)
264	{	267	{
265	dev->resource[2].start = 0x170;	268	dev->resource[2].start = 0x170;
266	dev->resource[2].end = 0x177;	269	dev->resource[2].end = 0x177;
267	dev->resource[2].flags = LEGACY_IO_RESOURCE;	270	dev->resource[2].flags = LEGACY_IO_RESOURCE;
268	dev->resource[3].start = 0x376;	271	dev->resource[3].start = 0x376;
269	dev->resource[3].end = 0x376;	272	dev->resource[3].end = 0x376;
270	dev->resource[3].flags = LEGACY_IO_RESOURCE;	273	dev->resource[3].flags = LEGACY_IO_RESOURCE;
271	};	274	};
272	}	275	}
273	break;	276	break;
274		277
275	case PCI_HEADER_TYPE_BRIDGE: /* bridge header */	278	case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
276	if (class != PCI_CLASS_BRIDGE_PCI)	279	if (class != PCI_CLASS_BRIDGE_PCI)
277	goto bad;	280	goto bad;
278	/* The PCI-to-PCI bridge spec requires that subtractive	281	/* The PCI-to-PCI bridge spec requires that subtractive
279	decoding (i.e. transparent) bridge must have programming	282	decoding (i.e. transparent) bridge must have programming
280	interface code of 0x01. */	283	interface code of 0x01. */
281	pci_read_irq(dev);	284	pci_read_irq(dev);
282	dev->transparent = ((dev->class & 0xff) == 1);	285	dev->transparent = ((dev->class & 0xff) == 1);
283	pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);	286	pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
284	break;	287	break;
285		288
286	case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */	289	case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
287	if (class != PCI_CLASS_BRIDGE_CARDBUS)	290	if (class != PCI_CLASS_BRIDGE_CARDBUS)
288	goto bad;	291	goto bad;
289	pci_read_irq(dev);	292	pci_read_irq(dev);
290	pci_read_bases(dev, 1, 0);	293	pci_read_bases(dev, 1, 0);
291	dev->subsystem_vendor = PciRead16(dev->busnr,	294	dev->subsystem_vendor = PciRead16(dev->busnr,
292	dev->devfn,	295	dev->devfn,
293	PCI_CB_SUBSYSTEM_VENDOR_ID);	296	PCI_CB_SUBSYSTEM_VENDOR_ID);
294		297
295	dev->subsystem_device = PciRead16(dev->busnr,	298	dev->subsystem_device = PciRead16(dev->busnr,
296	dev->devfn,	299	dev->devfn,
297	PCI_CB_SUBSYSTEM_ID);	300	PCI_CB_SUBSYSTEM_ID);
298	break;	301	break;
299		302
300	default: /* unknown header */	303	default: /* unknown header */
301	printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",	304	printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
302	pci_name(dev), dev->hdr_type);	305	pci_name(dev), dev->hdr_type);
303	return -1;	306	return -1;
304		307
305	bad:	308	bad:
306	printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",	309	printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
307	pci_name(dev), class, dev->hdr_type);	310	pci_name(dev), class, dev->hdr_type);
308	dev->class = PCI_CLASS_NOT_DEFINED;	311	dev->class = PCI_CLASS_NOT_DEFINED;
309	}	312	}
310		313
311	/* We found a fine healthy device, go go go... */	314	/* We found a fine healthy device, go go go... */
312		315
313	return 0;	316	return 0;
314	};	317	};
315		318
316	static pci_dev_t* pci_scan_device(u32 busnr, int devfn)	319	static pci_dev_t* pci_scan_device(u32 busnr, int devfn)
317	{	320	{
318	pci_dev_t *dev;	321	pci_dev_t *dev;
319		322
320	u32 id;	323	u32 id;
321	u8 hdr;	324	u8 hdr;
322		325
323	int timeout = 10;	326	int timeout = 10;
324		327
325	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);	328	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
326		329
327	/* some broken boards return 0 or ~0 if a slot is empty: */	330	/* some broken boards return 0 or ~0 if a slot is empty: */
328	if (id == 0xffffffff \|\| id == 0x00000000 \|\|	331	if (id == 0xffffffff \|\| id == 0x00000000 \|\|
329	id == 0x0000ffff \|\| id == 0xffff0000)	332	id == 0x0000ffff \|\| id == 0xffff0000)
330	return NULL;	333	return NULL;
331		334
332	while (id == 0xffff0001)	335	while (id == 0xffff0001)
333	{	336	{
334		337
335	delay(timeout/10);	338	delay(timeout/10);
336	timeout *= 2;	339	timeout *= 2;
337		340
338	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);	341	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
339		342
340	/* Card hasn't responded in 60 seconds? Must be stuck. */	343	/* Card hasn't responded in 60 seconds? Must be stuck. */
341	if (timeout > 60 * 100)	344	if (timeout > 60 * 100)
342	{	345	{
343	printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "	346	printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
344	"responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));	347	"responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));
345	return NULL;	348	return NULL;
346	}	349	}
347	};	350	};
348		351
349	if( pci_scan_filter(id, busnr, devfn) == 0)	352	if( pci_scan_filter(id, busnr, devfn) == 0)
350	return NULL;	353	return NULL;
351		354
352	hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);	355	hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);
353		356
354	dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);	357	dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);
355	if(unlikely(dev == NULL))	358	if(unlikely(dev == NULL))
356	return NULL;	359	return NULL;
357		360
358	INIT_LIST_HEAD(&dev->link);	361	INIT_LIST_HEAD(&dev->link);
359		362
360		363
361	dev->pci_dev.busnr = busnr;	364	dev->pci_dev.busnr = busnr;
362	dev->pci_dev.devfn = devfn;	365	dev->pci_dev.devfn = devfn;
363	dev->pci_dev.hdr_type = hdr & 0x7f;	366	dev->pci_dev.hdr_type = hdr & 0x7f;
364	dev->pci_dev.multifunction = !!(hdr & 0x80);	367	dev->pci_dev.multifunction = !!(hdr & 0x80);
365	dev->pci_dev.vendor = id & 0xffff;	368	dev->pci_dev.vendor = id & 0xffff;
366	dev->pci_dev.device = (id >> 16) & 0xffff;	369	dev->pci_dev.device = (id >> 16) & 0xffff;
367		370
368	pci_setup_device(&dev->pci_dev);	371	pci_setup_device(&dev->pci_dev);
369		372
370	return dev;	373	return dev;
371		374
372	};	375	};
373		376
374		377
375		378
376		379
377	int _pci_scan_slot(u32 bus, int devfn)	380	int _pci_scan_slot(u32 bus, int devfn)
378	{	381	{
379	int func, nr = 0;	382	int func, nr = 0;
380		383
381	for (func = 0; func < 8; func++, devfn++)	384	for (func = 0; func < 8; func++, devfn++)
382	{	385	{
383	pci_dev_t *dev;	386	pci_dev_t *dev;
384		387
385	dev = pci_scan_device(bus, devfn);	388	dev = pci_scan_device(bus, devfn);
386	if( dev )	389	if( dev )
387	{	390	{
388	list_add(&dev->link, &devices);	391	list_add(&dev->link, &devices);
389		392
390	nr++;	393	nr++;
391		394
392	/*	395	/*
393	* If this is a single function device,	396	* If this is a single function device,
394	* don't scan past the first function.	397	* don't scan past the first function.
395	*/	398	*/
396	if (!dev->pci_dev.multifunction)	399	if (!dev->pci_dev.multifunction)
397	{	400	{
398	if (func > 0) {	401	if (func > 0) {
399	dev->pci_dev.multifunction = 1;	402	dev->pci_dev.multifunction = 1;
400	}	403	}
401	else {	404	else {
402	break;	405	break;
403	}	406	}
404	}	407	}
405	}	408	}
406	else {	409	else {
407	if (func == 0)	410	if (func == 0)
408	break;	411	break;
409	}	412	}
410	};	413	};
411		414
412	return nr;	415	return nr;
413	};	416	};
414		417
415	#define PCI_FIND_CAP_TTL 48	418	#define PCI_FIND_CAP_TTL 48
416		419
417	static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,	420	static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,
418	u8 pos, int cap, int *ttl)	421	u8 pos, int cap, int *ttl)
419	{	422	{
420	u8 id;	423	u8 id;
421		424
422	while ((*ttl)--) {	425	while ((*ttl)--) {
423	pos = PciRead8(bus, devfn, pos);	426	pos = PciRead8(bus, devfn, pos);
424	if (pos < 0x40)	427	if (pos < 0x40)
425	break;	428	break;
426	pos &= ~3;	429	pos &= ~3;
427	id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);	430	id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);
428	if (id == 0xff)	431	if (id == 0xff)
429	break;	432	break;
430	if (id == cap)	433	if (id == cap)
431	return pos;	434	return pos;
432	pos += PCI_CAP_LIST_NEXT;	435	pos += PCI_CAP_LIST_NEXT;
433	}	436	}
434	return 0;	437	return 0;
435	}	438	}
436		439
437	static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,	440	static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,
438	u8 pos, int cap)	441	u8 pos, int cap)
439	{	442	{
440	int ttl = PCI_FIND_CAP_TTL;	443	int ttl = PCI_FIND_CAP_TTL;
441		444
442	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);	445	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
443	}	446	}
444		447
445	static int __pci_bus_find_cap_start(unsigned int bus,	448	static int __pci_bus_find_cap_start(unsigned int bus,
446	unsigned int devfn, u8 hdr_type)	449	unsigned int devfn, u8 hdr_type)
447	{	450	{
448	u16 status;	451	u16 status;
449		452
450	status = PciRead16(bus, devfn, PCI_STATUS);	453	status = PciRead16(bus, devfn, PCI_STATUS);
451	if (!(status & PCI_STATUS_CAP_LIST))	454	if (!(status & PCI_STATUS_CAP_LIST))
452	return 0;	455	return 0;
453		456
454	switch (hdr_type) {	457	switch (hdr_type) {
455	case PCI_HEADER_TYPE_NORMAL:	458	case PCI_HEADER_TYPE_NORMAL:
456	case PCI_HEADER_TYPE_BRIDGE:	459	case PCI_HEADER_TYPE_BRIDGE:
457	return PCI_CAPABILITY_LIST;	460	return PCI_CAPABILITY_LIST;
458	case PCI_HEADER_TYPE_CARDBUS:	461	case PCI_HEADER_TYPE_CARDBUS:
459	return PCI_CB_CAPABILITY_LIST;	462	return PCI_CB_CAPABILITY_LIST;
460	default:	463	default:
461	return 0;	464	return 0;
462	}	465	}
463		466
464	return 0;	467	return 0;
465	}	468	}
466		469
467		470
468	int pci_find_capability(struct pci_dev *dev, int cap)	471	int pci_find_capability(struct pci_dev *dev, int cap)
469	{	472	{
470	int pos;	473	int pos;
471		474
472	pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);	475	pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);
473	if (pos)	476	if (pos)
474	pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);	477	pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);
475		478
476	return pos;	479	return pos;
477	}	480	}
478		481
479		482
480		483
481		484
482	int enum_pci_devices()	485	int enum_pci_devices()
483	{	486	{
484	pci_dev_t *dev;	487	pci_dev_t *dev;
485	u32 last_bus;	488	u32 last_bus;
486	u32 bus = 0 , devfn = 0;	489	u32 bus = 0 , devfn = 0;
487		490
488		491
489	last_bus = PciApi(1);	492	last_bus = PciApi(1);
490		493
491		494
492	if( unlikely(last_bus == -1))	495	if( unlikely(last_bus == -1))
493	return -1;	496	return -1;
494		497
495	for(;bus <= last_bus; bus++)	498	for(;bus <= last_bus; bus++)
496	{	499	{
497	for (devfn = 0; devfn < 0x100; devfn += 8)	500	for (devfn = 0; devfn < 0x100; devfn += 8)

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(root)/drivers/video/drm/i915/pci.c – Rev 6131 → 7144