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Rev 5128 | Rev 5354 | ||
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Line 3... | Line 3... | ||
3 | #include "i915_drv.h" |
3 | #include "i915_drv.h" |
Line 4... | Line 4... | ||
4 | 4 | ||
5 | #include |
5 | #include |
6 | #include |
6 | #include |
7 | #include |
- | |
8 | #include |
7 | #include |
9 | #include |
8 | #include |
Line 10... | Line 9... | ||
10 | #include |
9 | #include |
Line 31... | Line 30... | ||
31 | 30 | ||
32 | struct drm_device *main_device; |
31 | struct drm_device *main_device; |
33 | struct drm_file *drm_file_handlers[256]; |
32 | struct drm_file *drm_file_handlers[256]; |
Line 34... | Line 33... | ||
34 | videomode_t usermode; |
33 | videomode_t usermode; |
- | 34 | ||
Line 35... | Line 35... | ||
35 | 35 | void cpu_detect1(); |
|
36 | void cpu_detect(); |
36 | int kmap_init(); |
Line 37... | Line 37... | ||
37 | 37 | ||
Line 168... | Line 168... | ||
168 | }; |
168 | }; |
Line 169... | Line 169... | ||
169 | 169 | ||
170 | asm volatile ("int $0x40"::"a"(-1)); |
170 | asm volatile ("int $0x40"::"a"(-1)); |
Line 171... | Line 171... | ||
171 | } |
171 | } |
172 | 172 | ||
173 | u32_t __attribute__((externally_visible)) drvEntry(int action, char *cmdline) |
173 | u32 __attribute__((externally_visible)) drvEntry(int action, char *cmdline) |
174 | { |
174 | { |
Line 175... | Line 175... | ||
175 | static pci_dev_t device; |
175 | static pci_dev_t device; |
Line 184... | Line 184... | ||
184 | }; |
184 | }; |
Line 185... | Line 185... | ||
185 | 185 | ||
186 | if( GetService("DISPLAY") != 0 ) |
186 | if( GetService("DISPLAY") != 0 ) |
Line 187... | Line 187... | ||
187 | return 0; |
187 | return 0; |
188 | 188 | ||
189 | printf("\ni915 v3.17-rc5 build %s %s\nusage: i915 [options]\n" |
189 | printf("\ni915 v3.19-rc2 build %s %s\nusage: i915 [options]\n" |
190 | "-pm=<0,1> Enable powersavings, fbc, downclocking, etc. (default: 1 - true)\n", |
190 | "-pm=<0,1> Enable powersavings, fbc, downclocking, etc. (default: 1 - true)\n", |
191 | __DATE__, __TIME__); |
191 | __DATE__, __TIME__); |
192 | printf("-rc6=<-1,0-7> Enable power-saving render C-state 6.\n" |
192 | printf("-rc6=<-1,0-7> Enable power-saving render C-state 6.\n" |
Line 208... | Line 208... | ||
208 | { |
208 | { |
209 | printf("Can't open %s\nExit\n", log); |
209 | printf("Can't open %s\nExit\n", log); |
210 | return 0; |
210 | return 0; |
211 | } |
211 | } |
Line 212... | Line 212... | ||
212 | 212 | ||
213 | cpu_detect(); |
213 | cpu_detect1(); |
Line 214... | Line 214... | ||
214 | // dbgprintf("\ncache line size %d\n", x86_clflush_size); |
214 | // dbgprintf("\ncache line size %d\n", x86_clflush_size); |
215 | 215 | ||
216 | err = enum_pci_devices(); |
216 | err = enum_pci_devices(); |
217 | if( unlikely(err != 0) ) |
217 | if( unlikely(err != 0) ) |
218 | { |
218 | { |
219 | dbgprintf("Device enumeration failed\n"); |
219 | dbgprintf("Device enumeration failed\n"); |
Line -... | Line 220... | ||
- | 220 | return 0; |
|
- | 221 | } |
|
- | 222 | ||
- | 223 | err = kmap_init(); |
|
- | 224 | if( unlikely(err != 0) ) |
|
- | 225 | { |
|
- | 226 | dbgprintf("kmap initialization failed\n"); |
|
220 | return 0; |
227 | return 0; |
Line 221... | Line 228... | ||
221 | } |
228 | } |
222 | 229 | ||
Line 308... | Line 315... | ||
308 | int _stdcall display_handler(ioctl_t *io) |
315 | int _stdcall display_handler(ioctl_t *io) |
309 | { |
316 | { |
310 | struct drm_file *file; |
317 | struct drm_file *file; |
Line 311... | Line 318... | ||
311 | 318 | ||
312 | int retval = -1; |
319 | int retval = -1; |
313 | u32_t *inp; |
320 | u32 *inp; |
Line 314... | Line 321... | ||
314 | u32_t *outp; |
321 | u32 *outp; |
315 | 322 | ||
Line 316... | Line 323... | ||
316 | inp = io->input; |
323 | inp = io->input; |
Line 463... | Line 470... | ||
463 | #define PCI_CLASS_REVISION 0x08 |
470 | #define PCI_CLASS_REVISION 0x08 |
464 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
471 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
465 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
472 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
466 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
473 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
Line 467... | Line 474... | ||
467 | 474 | ||
468 | int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn) |
475 | int pci_scan_filter(u32 id, u32 busnr, u32 devfn) |
469 | { |
476 | { |
470 | u16_t vendor, device; |
477 | u16 vendor, device; |
471 | u32_t class; |
478 | u32 class; |
Line 472... | Line 479... | ||
472 | int ret = 0; |
479 | int ret = 0; |
473 | 480 | ||
Line 486... | Line 493... | ||
486 | } |
493 | } |
487 | return ret; |
494 | return ret; |
488 | }; |
495 | }; |
Line 489... | Line -... | ||
489 | - | ||
490 | - | ||
491 | - | ||
492 | - | ||
493 | static inline void __cpuid(unsigned int *eax, unsigned int *ebx, |
- | |
494 | unsigned int *ecx, unsigned int *edx) |
- | |
495 | { |
- | |
496 | /* ecx is often an input as well as an output. */ |
- | |
497 | asm volatile("cpuid" |
- | |
498 | : "=a" (*eax), |
- | |
499 | "=b" (*ebx), |
- | |
500 | "=c" (*ecx), |
- | |
501 | "=d" (*edx) |
- | |
502 | : "0" (*eax), "2" (*ecx) |
- | |
503 | : "memory"); |
- | |
504 | } |
- | |
505 | - | ||
506 | - | ||
507 | - | ||
508 | static inline void cpuid(unsigned int op, |
- | |
509 | unsigned int *eax, unsigned int *ebx, |
- | |
510 | unsigned int *ecx, unsigned int *edx) |
- | |
511 | { |
- | |
512 | *eax = op; |
- | |
513 | *ecx = 0; |
- | |
514 | __cpuid(eax, ebx, ecx, edx); |
- | |
515 | } |
496 | |
516 | 497 | ||
517 | struct mtrr |
498 | struct mtrr |
518 | { |
499 | { |
519 | u64_t base; |
500 | u64 base; |
Line 520... | Line 501... | ||
520 | u64_t mask; |
501 | u64 mask; |
521 | }; |
502 | }; |
522 | 503 | ||
523 | struct cpuinfo |
504 | struct cpuinfo |
524 | { |
505 | { |
525 | u64_t caps; |
506 | u64 caps; |
526 | u64_t def_mtrr; |
507 | u64 def_mtrr; |
527 | u64_t mtrr_cap; |
508 | u64 mtrr_cap; |
528 | int var_mtrr_count; |
509 | int var_mtrr_count; |
529 | int fix_mtrr_count; |
510 | int fix_mtrr_count; |
Line 547... | Line 528... | ||
547 | 528 | ||
548 | #define MTRR_UC 0 |
529 | #define MTRR_UC 0 |
549 | #define MTRR_WC 1 |
530 | #define MTRR_WC 1 |
Line 550... | Line 531... | ||
550 | #define MTRR_WB 6 |
531 | #define MTRR_WB 6 |
551 | 532 | ||
552 | static inline u64_t read_msr(u32_t msr) |
533 | static inline u64 read_msr(u32 msr) |
553 | { |
534 | { |
554 | union { |
535 | union { |
555 | u64_t val; |
536 | u64 val; |
556 | struct { |
537 | struct { |
557 | u32_t low; |
538 | u32 low; |
558 | u32_t high; |
539 | u32 high; |
Line 559... | Line 540... | ||
559 | }; |
540 | }; |
560 | }tmp; |
541 | }tmp; |
561 | 542 | ||
562 | asm volatile ( |
543 | asm volatile ( |
563 | "rdmsr" |
544 | "rdmsr" |
564 | : "=a" (tmp.low), "=d" (tmp.high) |
545 | : "=a" (tmp.low), "=d" (tmp.high) |
Line 565... | Line 546... | ||
565 | : "c" (msr)); |
546 | : "c" (msr)); |
566 | return tmp.val; |
547 | return tmp.val; |
567 | } |
548 | } |
568 | 549 | ||
569 | static inline void write_msr(u32_t msr, u64_t val) |
550 | static inline void write_msr(u32 msr, u64 val) |
570 | { |
551 | { |
571 | union { |
552 | union { |
572 | u64_t val; |
553 | u64 val; |
573 | struct { |
554 | struct { |
Line 574... | Line 555... | ||
574 | u32_t low; |
555 | u32 low; |
Line 575... | Line 556... | ||
575 | u32_t high; |
556 | u32 high; |
576 | }; |
557 | }; |
577 | }tmp; |
558 | }tmp; |
578 | 559 | ||
Line 579... | Line -... | ||
579 | tmp.val = val; |
- | |
580 | - | ||
581 | asm volatile ( |
- | |
582 | "wrmsr" |
- | |
583 | :: "a" (tmp.low), "d" (tmp.high), "c" (msr)); |
- | |
584 | } |
- | |
585 | - | ||
586 | #define rdmsr(msr, low, high) \ |
- | |
587 | do { \ |
- | |
588 | u64 __val = read_msr((msr)); \ |
- | |
589 | (void)((low) = (u32)__val); \ |
- | |
590 | (void)((high) = (u32)(__val >> 32)); \ |
- | |
591 | } while (0) |
- | |
592 | - | ||
593 | static inline void native_write_msr(unsigned int msr, |
- | |
594 | unsigned low, unsigned high) |
- | |
595 | { |
- | |
596 | asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); |
- | |
597 | } |
560 | tmp.val = val; |
Line 598... | Line 561... | ||
598 | 561 | ||
599 | static inline void wbinvd(void) |
562 | asm volatile ( |
600 | { |
563 | "wrmsr" |
Line 628... | Line 591... | ||
628 | native_write_msr(MTRRphysBase_MSR(reg), base_lo, base_hi); |
591 | native_write_msr(MTRRphysBase_MSR(reg), base_lo, base_hi); |
629 | native_write_msr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); |
592 | native_write_msr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); |
630 | }; |
593 | }; |
631 | } |
594 | } |
Line 632... | Line -... | ||
632 | - | ||
633 | static unsigned long __force_order; |
- | |
634 | - | ||
635 | static inline unsigned long read_cr0(void) |
- | |
636 | { |
- | |
637 | unsigned long val; |
- | |
638 | asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order)); |
- | |
639 | return val; |
- | |
640 | } |
- | |
641 | - | ||
642 | static inline void write_cr0(unsigned long val) |
- | |
643 | { |
- | |
644 | asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order)); |
- | |
645 | } |
- | |
646 | - | ||
647 | static inline unsigned long read_cr4(void) |
- | |
648 | { |
- | |
649 | unsigned long val; |
- | |
650 | asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order)); |
- | |
651 | return val; |
- | |
652 | } |
- | |
653 | - | ||
654 | static inline void write_cr4(unsigned long val) |
- | |
655 | { |
- | |
656 | asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order)); |
- | |
657 | } |
- | |
658 | - | ||
659 | static inline unsigned long read_cr3(void) |
- | |
660 | { |
- | |
661 | unsigned long val; |
- | |
662 | asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order)); |
- | |
663 | return val; |
- | |
664 | } |
- | |
665 | - | ||
666 | static inline void write_cr3(unsigned long val) |
- | |
667 | { |
- | |
668 | asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order)); |
- | |
Line 669... | Line 595... | ||
669 | } |
595 | |
Line 670... | Line 596... | ||
670 | 596 | ||
671 | static u32 deftype_lo, deftype_hi; |
597 | static u32 deftype_lo, deftype_hi; |
672 | 598 | ||
Line 673... | Line 599... | ||
673 | void cpu_detect() |
599 | void cpu_detect1() |
674 | { |
600 | { |
675 | struct cpuinfo cpuinfo; |
601 | struct cpuinfo cpuinfo; |
676 | 602 | ||
Line 677... | Line 603... | ||
677 | u32 junk, tfms, cap0, misc; |
603 | u32 junk, tfms, cap0, misc; |
678 | int i; |
604 | int i; |
679 | #if 0 |
605 | |
680 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
606 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
Line -... | Line 607... | ||
- | 607 | ||
681 | 608 | if (cap0 & (1<<19)) |
|
682 | if (cap0 & (1<<19)) |
609 | { |
683 | { |
610 | x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
684 | x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
611 | } |
685 | } |
612 | |
Line 953... | Line 880... | ||
953 | : "0" (0), "1" (0xffffffff), "2" (cs), "g" (ct) |
880 | : "0" (0), "1" (0xffffffff), "2" (cs), "g" (ct) |
954 | : "dx", "di"); |
881 | : "dx", "di"); |
955 | return __res; |
882 | return __res; |
956 | }>30)); |
883 | }>30)); |
Line 957... | Line -... | ||
957 | - |