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Line 1... | Line 1... | ||
1 | #include |
1 | #include |
2 | #include |
- | |
3 | #include |
2 | #include |
4 | #include "i915_drv.h" |
3 | #include "i915_drv.h" |
5 | //#include "intel_drv.h" |
- | |
Line 6... | Line 4... | ||
6 | 4 | ||
7 | #include |
5 | #include |
8 | #include |
6 | #include |
9 | #include |
7 | #include |
10 | #include |
8 | #include |
11 | #include |
9 | #include |
Line 12... | Line 10... | ||
12 | #include |
10 | #include |
Line -... | Line 11... | ||
- | 11 | ||
- | 12 | #include "bitmap.h" |
|
- | 13 | ||
- | 14 | #define I915_DEV_CLOSE 0 |
|
- | 15 | #define I915_DEV_INIT 1 |
|
13 | 16 | #define I915_DEV_READY 2 |
|
14 | #include "bitmap.h" |
17 | |
15 | 18 | ||
16 | struct pci_device { |
19 | struct pci_device { |
17 | uint16_t domain; |
20 | uint16_t domain; |
Line 50... | Line 53... | ||
50 | 53 | ||
51 | int i915_mask_update(struct drm_device *dev, void *data, |
54 | int i915_mask_update(struct drm_device *dev, void *data, |
Line 52... | Line 55... | ||
52 | struct drm_file *file); |
55 | struct drm_file *file); |
53 | 56 | ||
54 | struct cmdtable cmdtable[]= { |
57 | struct cmdtable cmdtable[]= { |
55 | CMDENTRY("-pm=", i915_powersave), |
58 | // CMDENTRY("-pm=", i915_powersave), |
56 | CMDENTRY("-rc6=", i915_enable_rc6), |
59 | // CMDENTRY("-rc6=", i915_enable_rc6), |
57 | CMDENTRY("-fbc=", i915_enable_fbc), |
60 | // CMDENTRY("-fbc=", i915_enable_fbc), |
58 | CMDENTRY("-ppgt=", i915_enable_ppgtt), |
61 | // CMDENTRY("-ppgt=", i915_enable_ppgtt), |
59 | CMDENTRY("-pc8=", i915_enable_pc8), |
62 | // CMDENTRY("-pc8=", i915_enable_pc8), |
Line 60... | Line 63... | ||
60 | {NULL, 0} |
63 | {NULL, 0} |
Line -... | Line 64... | ||
- | 64 | }; |
|
- | 65 | ||
61 | }; |
66 | |
62 | 67 | static char log[256]; |
|
Line 63... | Line 68... | ||
63 | 68 | ||
64 | static char log[256]; |
69 | unsigned long volatile jiffies; |
Line 91... | Line 96... | ||
91 | 96 | ||
Line 92... | Line 97... | ||
92 | void i915_dpms(struct drm_device *dev, int mode); |
97 | void i915_dpms(struct drm_device *dev, int mode); |
93 | 98 | ||
94 | void i915_driver_thread() |
99 | void i915_driver_thread() |
95 | { |
100 | { |
96 | struct drm_i915_private *dev_priv = main_device->dev_private; |
101 | struct drm_i915_private *dev_priv = NULL; |
97 | struct workqueue_struct *cwq = dev_priv->wq; |
102 | struct workqueue_struct *cwq = NULL; |
98 | static int dpms = 1; |
103 | static int dpms = 1; |
99 | static int dpms_lock = 0; |
104 | static int dpms_lock = 0; |
100 | oskey_t key; |
105 | oskey_t key; |
Line 101... | Line 106... | ||
101 | unsigned long irqflags; |
106 | unsigned long irqflags; |
Line -... | Line 107... | ||
- | 107 | int tmp; |
|
- | 108 | ||
- | 109 | printf("%s\n",__FUNCTION__); |
|
- | 110 | ||
- | 111 | while(driver_wq_state == I915_DEV_INIT) |
|
- | 112 | { |
|
- | 113 | jiffies = GetTimerTicks(); |
|
- | 114 | delay(1); |
|
- | 115 | }; |
|
102 | int tmp; |
116 | |
103 | 117 | dev_priv = main_device->dev_private; |
|
104 | printf("%s\n",__FUNCTION__); |
118 | cwq = dev_priv->wq; |
Line 105... | Line 119... | ||
105 | 119 | ||
106 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(1),"c"(1)); |
120 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(1),"c"(1)); |
- | 121 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0x46),"d"(0x330)); |
|
- | 122 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0xC6),"d"(0x330)); |
|
107 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0x46),"d"(0x330)); |
123 | |
Line 108... | Line 124... | ||
108 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0xC6),"d"(0x330)); |
124 | while(driver_wq_state != I915_DEV_CLOSE) |
109 | 125 | { |
|
110 | while(driver_wq_state != 0) |
126 | jiffies = GetTimerTicks(); |
Line 154... | Line 170... | ||
154 | asm volatile ("int $0x40"::"a"(-1)); |
170 | asm volatile ("int $0x40"::"a"(-1)); |
155 | } |
171 | } |
Line 156... | Line 172... | ||
156 | 172 | ||
157 | u32_t __attribute__((externally_visible)) drvEntry(int action, char *cmdline) |
173 | u32_t __attribute__((externally_visible)) drvEntry(int action, char *cmdline) |
- | 174 | { |
|
- | 175 | static pci_dev_t device; |
|
- | 176 | const struct pci_device_id *ent; |
|
158 | { |
177 | |
Line 159... | Line 178... | ||
159 | int err = 0; |
178 | int err = 0; |
160 | 179 | ||
161 | if(action != 1) |
180 | if(action != 1) |
162 | { |
181 | { |
163 | driver_wq_state = 0; |
182 | driver_wq_state = I915_DEV_CLOSE; |
Line 164... | Line 183... | ||
164 | return 0; |
183 | return 0; |
165 | }; |
184 | }; |
Line 166... | Line 185... | ||
166 | 185 | ||
167 | if( GetService("DISPLAY") != 0 ) |
186 | if( GetService("DISPLAY") != 0 ) |
168 | return 0; |
187 | return 0; |
169 | 188 | ||
170 | printf("\ni915 v3.14-rc1 build %s %s\nusage: i915 [options]\n" |
189 | printf("\ni915 v3.17-rc2 build %s %s\nusage: i915 [options]\n" |
171 | "-pm=<0,1> Enable powersavings, fbc, downclocking, etc. (default: 1 - true)\n", |
190 | "-pm=<0,1> Enable powersavings, fbc, downclocking, etc. (default: 1 - true)\n", |
Line 192... | Line 211... | ||
192 | } |
211 | } |
Line 193... | Line 212... | ||
193 | 212 | ||
194 | cpu_detect(); |
213 | cpu_detect(); |
Line 195... | Line 214... | ||
195 | // dbgprintf("\ncache line size %d\n", x86_clflush_size); |
214 | // dbgprintf("\ncache line size %d\n", x86_clflush_size); |
- | 215 | ||
- | 216 | err = enum_pci_devices(); |
|
- | 217 | if( unlikely(err != 0) ) |
|
- | 218 | { |
|
- | 219 | dbgprintf("Device enumeration failed\n"); |
|
- | 220 | return 0; |
|
- | 221 | } |
|
- | 222 | ||
Line 196... | Line 223... | ||
196 | 223 | driver_wq_state = I915_DEV_INIT; |
|
197 | enum_pci_devices(); |
224 | CreateKernelThread(i915_driver_thread); |
198 | 225 | ||
- | 226 | err = i915_init(); |
|
199 | err = i915_init(); |
227 | if(unlikely(err!= 0)) |
200 | if(err) |
228 | { |
201 | { |
229 | driver_wq_state = I915_DEV_CLOSE; |
Line -... | Line 230... | ||
- | 230 | dbgprintf("Epic Fail :(\n"); |
|
- | 231 | return 0; |
|
202 | dbgprintf("Epic Fail :(\n"); |
232 | }; |
Line 203... | Line 233... | ||
203 | return 0; |
233 | |
Line 204... | Line 234... | ||
204 | }; |
234 | driver_wq_state = I915_DEV_READY; |
205 | 235 | ||
Line 206... | Line -... | ||
206 | init_display_kms(main_device, &usermode); |
- | |
207 | - | ||
208 | err = RegService("DISPLAY", display_handler); |
- | |
Line 209... | Line 236... | ||
209 | 236 | init_display_kms(main_device, &usermode); |
|
210 | if( err != 0) |
237 | |
Line 316... | Line 343... | ||
316 | 343 | ||
317 | case SRV_GET_CAPS: |
344 | case SRV_GET_CAPS: |
318 | retval = get_driver_caps((hwcaps_t*)inp); |
345 | retval = get_driver_caps((hwcaps_t*)inp); |
Line 319... | Line -... | ||
319 | break; |
- | |
320 | - | ||
321 | case SRV_CREATE_SURFACE: |
- | |
322 | // check_input(8); |
- | |
323 | // retval = create_surface(main_device, (struct io_call_10*)inp); |
- | |
324 | break; |
- | |
325 | - | ||
326 | case SRV_LOCK_SURFACE: |
- | |
327 | // retval = lock_surface((struct io_call_12*)inp); |
- | |
328 | break; |
- | |
329 | - | ||
330 | case SRV_RESIZE_SURFACE: |
- | |
331 | // retval = resize_surface((struct io_call_14*)inp); |
- | |
332 | break; |
- | |
333 | - | ||
334 | case SRV_BLIT_BITMAP: |
- | |
335 | // srv_blit_bitmap( inp[0], inp[1], inp[2], |
- | |
336 | // inp[3], inp[4], inp[5], inp[6]); |
- | |
337 | - | ||
338 | // blit_tex( inp[0], inp[1], inp[2], |
- | |
339 | // inp[3], inp[4], inp[5], inp[6]); |
- | |
340 | - | ||
341 | break; |
346 | break; |
342 | 347 | ||
343 | case SRV_GET_PCI_INFO: |
348 | case SRV_GET_PCI_INFO: |
344 | get_pci_info((struct pci_device *)inp); |
349 | get_pci_info((struct pci_device *)inp); |
Line 505... | Line 510... | ||
505 | *eax = op; |
510 | *eax = op; |
506 | *ecx = 0; |
511 | *ecx = 0; |
507 | __cpuid(eax, ebx, ecx, edx); |
512 | __cpuid(eax, ebx, ecx, edx); |
508 | } |
513 | } |
Line -... | Line 514... | ||
- | 514 | ||
- | 515 | struct mtrr |
|
- | 516 | { |
|
- | 517 | u64_t base; |
|
- | 518 | u64_t mask; |
|
- | 519 | }; |
|
- | 520 | ||
- | 521 | struct cpuinfo |
|
- | 522 | { |
|
- | 523 | u64_t caps; |
|
- | 524 | u64_t def_mtrr; |
|
- | 525 | u64_t mtrr_cap; |
|
- | 526 | int var_mtrr_count; |
|
- | 527 | int fix_mtrr_count; |
|
- | 528 | struct mtrr var_mtrr[9]; |
|
- | 529 | char model_name[64]; |
|
- | 530 | }; |
|
- | 531 | ||
- | 532 | #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) |
|
- | 533 | #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) |
|
- | 534 | ||
- | 535 | #define MSR_MTRRdefType 0x000002ff |
|
- | 536 | ||
- | 537 | #define IA32_MTRRCAP 0xFE |
|
- | 538 | #define IA32_CR_PAT_MSR 0x277 |
|
- | 539 | ||
- | 540 | #define PAT_TYPE_UC 0 |
|
- | 541 | #define PAT_TYPE_WC 1 |
|
- | 542 | #define PAT_TYPE_WB 6 |
|
- | 543 | #define PAT_TYPE_UCM 7 |
|
- | 544 | ||
- | 545 | ||
- | 546 | #define MTRR_UC 0 |
|
- | 547 | #define MTRR_WC 1 |
|
- | 548 | #define MTRR_WB 6 |
|
- | 549 | ||
- | 550 | static inline u64_t read_msr(u32_t msr) |
|
- | 551 | { |
|
- | 552 | union { |
|
- | 553 | u64_t val; |
|
- | 554 | struct { |
|
- | 555 | u32_t low; |
|
- | 556 | u32_t high; |
|
- | 557 | }; |
|
- | 558 | }tmp; |
|
- | 559 | ||
- | 560 | asm volatile ( |
|
- | 561 | "rdmsr" |
|
- | 562 | : "=a" (tmp.low), "=d" (tmp.high) |
|
- | 563 | : "c" (msr)); |
|
- | 564 | return tmp.val; |
|
- | 565 | } |
|
- | 566 | ||
- | 567 | static inline void write_msr(u32_t msr, u64_t val) |
|
- | 568 | { |
|
- | 569 | union { |
|
- | 570 | u64_t val; |
|
- | 571 | struct { |
|
- | 572 | u32_t low; |
|
- | 573 | u32_t high; |
|
- | 574 | }; |
|
- | 575 | }tmp; |
|
- | 576 | ||
- | 577 | tmp.val = val; |
|
- | 578 | ||
- | 579 | asm volatile ( |
|
- | 580 | "wrmsr" |
|
- | 581 | :: "a" (tmp.low), "d" (tmp.high), "c" (msr)); |
|
- | 582 | } |
|
- | 583 | ||
- | 584 | #define rdmsr(msr, low, high) \ |
|
- | 585 | do { \ |
|
- | 586 | u64 __val = read_msr((msr)); \ |
|
- | 587 | (void)((low) = (u32)__val); \ |
|
- | 588 | (void)((high) = (u32)(__val >> 32)); \ |
|
- | 589 | } while (0) |
|
- | 590 | ||
- | 591 | static inline void native_write_msr(unsigned int msr, |
|
- | 592 | unsigned low, unsigned high) |
|
- | 593 | { |
|
- | 594 | asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); |
|
- | 595 | } |
|
- | 596 | ||
- | 597 | static inline void wbinvd(void) |
|
- | 598 | { |
|
- | 599 | asm volatile("wbinvd": : :"memory"); |
|
- | 600 | } |
|
- | 601 | ||
- | 602 | #define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) |
|
- | 603 | ||
- | 604 | static void set_mtrr(unsigned int reg, unsigned long base, |
|
- | 605 | unsigned long size, int type) |
|
- | 606 | { |
|
- | 607 | unsigned int base_lo, base_hi, mask_lo, mask_hi; |
|
- | 608 | u64 size_or_mask, size_and_mask; |
|
- | 609 | ||
- | 610 | size_or_mask = SIZE_OR_MASK_BITS(36); |
|
- | 611 | size_and_mask = 0x00f00000; |
|
- | 612 | ||
- | 613 | if (size == 0) { |
|
- | 614 | /* |
|
- | 615 | * The invalid bit is kept in the mask, so we simply |
|
- | 616 | * clear the relevant mask register to disable a range. |
|
- | 617 | */ |
|
- | 618 | native_write_msr(MTRRphysMask_MSR(reg), 0, 0); |
|
- | 619 | } |
|
- | 620 | else { |
|
- | 621 | base_lo = base << PAGE_SHIFT | type; |
|
- | 622 | base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT); |
|
- | 623 | mask_lo = -size << PAGE_SHIFT | 0x800; |
|
- | 624 | mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT); |
|
- | 625 | ||
- | 626 | native_write_msr(MTRRphysBase_MSR(reg), base_lo, base_hi); |
|
- | 627 | native_write_msr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); |
|
- | 628 | }; |
|
- | 629 | } |
|
- | 630 | ||
- | 631 | static unsigned long __force_order; |
|
- | 632 | ||
- | 633 | static inline unsigned long read_cr0(void) |
|
- | 634 | { |
|
- | 635 | unsigned long val; |
|
- | 636 | asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order)); |
|
- | 637 | return val; |
|
- | 638 | } |
|
- | 639 | ||
- | 640 | static inline void write_cr0(unsigned long val) |
|
- | 641 | { |
|
- | 642 | asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order)); |
|
- | 643 | } |
|
- | 644 | ||
- | 645 | static inline unsigned long read_cr4(void) |
|
- | 646 | { |
|
- | 647 | unsigned long val; |
|
- | 648 | asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order)); |
|
- | 649 | return val; |
|
- | 650 | } |
|
- | 651 | ||
- | 652 | static inline void write_cr4(unsigned long val) |
|
- | 653 | { |
|
- | 654 | asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order)); |
|
- | 655 | } |
|
- | 656 | ||
- | 657 | static inline unsigned long read_cr3(void) |
|
- | 658 | { |
|
- | 659 | unsigned long val; |
|
- | 660 | asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order)); |
|
- | 661 | return val; |
|
- | 662 | } |
|
- | 663 | ||
- | 664 | static inline void write_cr3(unsigned long val) |
|
- | 665 | { |
|
- | 666 | asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order)); |
|
- | 667 | } |
|
- | 668 | ||
- | 669 | static u32 deftype_lo, deftype_hi; |
|
509 | 670 | ||
510 | void cpu_detect() |
671 | void cpu_detect() |
511 | { |
672 | { |
Line -... | Line 673... | ||
- | 673 | struct cpuinfo cpuinfo; |
|
- | 674 | ||
- | 675 | u32 junk, tfms, cap0, misc; |
|
512 | u32 junk, tfms, cap0, misc; |
676 | int i; |
Line 513... | Line 677... | ||
513 | 677 | #if 0 |
|
514 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
678 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
515 | 679 | ||
516 | if (cap0 & (1<<19)) |
680 | if (cap0 & (1<<19)) |
Line -... | Line 681... | ||
- | 681 | { |
|
- | 682 | x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
|
- | 683 | } |
|
- | 684 | ||
- | 685 | cpuid(0x80000002, (unsigned int*)&cpuinfo.model_name[0], (unsigned int*)&cpuinfo.model_name[4], |
|
- | 686 | (unsigned int*)&cpuinfo.model_name[8], (unsigned int*)&cpuinfo.model_name[12]); |
|
- | 687 | cpuid(0x80000003, (unsigned int*)&cpuinfo.model_name[16], (unsigned int*)&cpuinfo.model_name[20], |
|
- | 688 | (unsigned int*)&cpuinfo.model_name[24], (unsigned int*)&cpuinfo.model_name[28]); |
|
- | 689 | cpuid(0x80000004, (unsigned int*)&cpuinfo.model_name[32], (unsigned int*)&cpuinfo.model_name[36], |
|
- | 690 | (unsigned int*)&cpuinfo.model_name[40], (unsigned int*)&cpuinfo.model_name[44]); |
|
- | 691 | ||
- | 692 | printf("\n%s\n\n",cpuinfo.model_name); |
|
- | 693 | ||
- | 694 | cpuinfo.def_mtrr = read_msr(MSR_MTRRdefType); |
|
- | 695 | cpuinfo.mtrr_cap = read_msr(IA32_MTRRCAP); |
|
- | 696 | ||
- | 697 | printf("MSR_MTRRdefType %016llx\n\n", cpuinfo.def_mtrr); |
|
- | 698 | ||
- | 699 | cpuinfo.var_mtrr_count = (u8_t)cpuinfo.mtrr_cap; |
|
- | 700 | ||
- | 701 | for(i = 0; i < cpuinfo.var_mtrr_count; i++) |
|
- | 702 | { |
|
- | 703 | u64_t mtrr_base; |
|
- | 704 | u64_t mtrr_mask; |
|
- | 705 | ||
- | 706 | cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i)); |
|
- | 707 | cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i)); |
|
- | 708 | ||
- | 709 | printf("MTRR_%d base: %016llx mask: %016llx\n", i, |
|
- | 710 | cpuinfo.var_mtrr[i].base, |
|
- | 711 | cpuinfo.var_mtrr[i].mask); |
|
- | 712 | }; |
|
- | 713 | ||
- | 714 | unsigned int cr0, cr3, cr4, eflags; |
|
- | 715 | ||
- | 716 | eflags = safe_cli(); |
|
- | 717 | ||
- | 718 | /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */ |
|
- | 719 | cr0 = read_cr0() | (1<<30); |
|
- | 720 | write_cr0(cr0); |
|
- | 721 | wbinvd(); |
|
- | 722 | ||
- | 723 | cr4 = read_cr4(); |
|
- | 724 | write_cr4(cr4 & ~(1<<7)); |
|
- | 725 | ||
- | 726 | cr3 = read_cr3(); |
|
- | 727 | write_cr3(cr3); |
|
- | 728 | ||
- | 729 | /* Save MTRR state */ |
|
- | 730 | rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); |
|
- | 731 | ||
- | 732 | /* Disable MTRRs, and set the default type to uncached */ |
|
- | 733 | native_write_msr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi); |
|
- | 734 | wbinvd(); |
|
- | 735 | ||
- | 736 | i = 0; |
|
- | 737 | set_mtrr(i++,0,0x80000000>>12,MTRR_WB); |
|
- | 738 | set_mtrr(i++,0x80000000>>12,0x40000000>>12,MTRR_WB); |
|
- | 739 | set_mtrr(i++,0xC0000000>>12,0x20000000>>12,MTRR_WB); |
|
- | 740 | set_mtrr(i++,0xdb800000>>12,0x00800000>>12,MTRR_UC); |
|
- | 741 | set_mtrr(i++,0xdc000000>>12,0x04000000>>12,MTRR_UC); |
|
- | 742 | set_mtrr(i++,0xE0000000>>12,0x10000000>>12,MTRR_WC); |
|
- | 743 | ||
- | 744 | for(; i < cpuinfo.var_mtrr_count; i++) |
|
- | 745 | set_mtrr(i,0,0,0); |
|
- | 746 | ||
- | 747 | write_cr3(cr3); |
|
- | 748 | ||
- | 749 | /* Intel (P6) standard MTRRs */ |
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- | 750 | native_write_msr(MSR_MTRRdefType, deftype_lo, deftype_hi); |
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- | 751 | ||
- | 752 | /* Enable caches */ |
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- | 753 | write_cr0(read_cr0() & ~(1<<30)); |
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- | 754 | ||
- | 755 | /* Restore value of CR4 */ |
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- | 756 | write_cr4(cr4); |
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- | 757 | ||
- | 758 | safe_sti(eflags); |
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- | 759 | ||
- | 760 | printf("\nnew MTRR map\n\n"); |
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- | 761 | ||
- | 762 | for(i = 0; i < cpuinfo.var_mtrr_count; i++) |
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- | 763 | { |
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- | 764 | u64_t mtrr_base; |
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- | 765 | u64_t mtrr_mask; |
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- | 766 | ||
- | 767 | cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i)); |
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- | 768 | cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i)); |
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- | 769 | ||
- | 770 | printf("MTRR_%d base: %016llx mask: %016llx\n", i, |
|
- | 771 | cpuinfo.var_mtrr[i].base, |
|
517 | { |
772 | cpuinfo.var_mtrr[i].mask); |
518 | x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
773 | }; |
Line 519... | Line 774... | ||
519 | } |
774 | #endif |